40th week of 2012 patent applcation highlights part 25 |
Patent application number | Title | Published |
20120249192 | CLOCK GENERATION CIRCUIT, PROCESSOR SYSTEM USING SAME, AND CLOCK FREQUENCY CONTROL METHOD - A clock generation circuit includes a system clock selection circuit that selects one of a first and a second clock signals with different frequencies from each other as a system clock signal according to a selection signal, a frequency division circuit that divides the system clock signal and generates a plurality of divided clock signals, and a communication clock selection circuit that selects a communication clock signal from the plurality of divided clock signals according to the selection signal and a division ratio setting signal, and switches to the selected communication clock signal in synchronization with a switching timing of the selection signal. | 2012-10-04 |
20120249193 | MEASUREMENT INITIALIZATION CIRCUITRY - Measurement initialization circuitry is described. Propagation of a start signal through a variable delay line may be stopped by either of two stop signals. One stop signal corresponds to a rising edge of a reference clock signal. A second stop signal corresponds to a falling edge of the reference clock signal. The start signal propagation is stopped responsive to the first to arrive of the first and second stop signals. Accordingly, in some examples, start signal propagation through a variable delay line may be stopped responsive to either a rising or falling edge of the reference clock signal. | 2012-10-04 |
20120249194 | ROBUST GLITCH-FREE CLOCK SWITCH WITH AN UNATE CLOCK NETWORK - A system, method, and computer program product are provided for the switching of clock signals. A clock network switching system includes a first re-synchronization circuit coupled to a first input clock, and a second re-synchronization circuit coupled to a second input clock. There is also an input select decoder coupled to the first and second re-synchronization circuit that can dynamically select either the first or the second input clock to be active. When an input clock is selected to be active, the re-synchronization circuit associated with the selected input clock generates an output clock synchronized with the selected input clock where both a high pulse width and a low pulse width of the output clock are not less than those of the selected input clock. | 2012-10-04 |
20120249195 | CLOCK GENERATING APPARATUS AND FREQUENCY CALIBRATING METHOD OF THE CLOCK GENERATING APPARATUS - A clock generating apparatus includes: a time-to-digital converter (TDC) arranged to convert a timing difference between a reference clock and a variable clock to generate a digital value; a calibrating device arranged to generate a control signal according to the digital value and the reference clock; a controllable oscillator arranged to generate an oscillating signal according to the control signal and the digital value; and a feedback device arranged to generate the variable clock to the TDC according to the oscillating signal, and the calibrating device calibrates the controllable oscillator to make the oscillating signal have a target oscillating frequency. | 2012-10-04 |
20120249196 | SIGNAL GENERATING DEVICE AND FREQUENCY SYNTHESIZER - A frequency synthesizer using a PLL has a simple structure and excellent spurious characteristics. A reference frequency signal inputted into a phase comparison unit is generated based on a clock when a zero cross point of a sawtooth wave composed of a digital signal is detected. However, in this case, since the digital values are skipped values, the digital value does not always become zero when its positive/negative sign is inverted. Hence, where the clock signals reading the digital value immediately before and the to digital value immediately after the zero cross time when the positive/negative sign is inverted in a region where the digital value gradually changes are P | 2012-10-04 |
20120249197 | Large signal VCO - An alternation voltage- or current generator comprises a first switch driving output network whose frequency can be tuned. The tuneable network comprises a first Inductor that is coupled with a first capacitor. A second inductor and/or at least a second capacitor and/or at least a series circuit of a third inductor and a third capacitor which is coupled via at a second switch to the network. The second switch is controlled by a controlled delay (PWM) which is synchronized by a sign change of current and/or voltage in the network. | 2012-10-04 |
20120249198 | DUAL LOOP PHASE LOCKED LOOP WITH LOW VOLTAGE-CONTROLLED OSCILLATOR GAIN - A dual loop PLL for generating an oscillator signal initially operates in a digital loop to achieve a frequency lock between an input reference signal and a feedback signal and then the PLL operates in an analog loop to achieve a phase lock. After attaining the phase lock, the analog loop is used to maintain the phase lock across frequency and phase variation due to changes in temperature and supply. | 2012-10-04 |
20120249199 | INTERNAL CLOCK GENERATOR AND OPERATING METHOD THEREOF - An internal clock signal generation circuit includes a variable delay line unit including an initial variable delayer having an initial delay amount controlled based on condition information and configured to delay an input clock signal by a time corresponding to a delay control signal to output a delay locked loop (DLL) clock signal, a delay replica modeling unit configured to delay the DLL clock signal by a time obtained by modeling a clock delay component and output a feedback clock signal, and a phase comparison unit configured to compare a phase of the input clock signal with a phase of the feedback clock signal and generate the delay control signal. | 2012-10-04 |
20120249200 | DIGITALLY CONTROLLED DELAY LINES WITH FINE GRAIN AND COARSE GRAIN DELAY ELEMENTS, AND METHODS AND SYSTEMS TO ADJUST IN FINE GRAIN INCREMENTS - Digitally controllable delay lines including fine grain and coarse grain delay elements, and methods and system to calibrate the delay lines in fine grain increments. Calibration may include calibrating a number of fine grain elements for which a combined delay is substantially equal to a delay of a coarse grain element, and calibrating numbers of fine grain and coarse grain elements which a combined delay corresponds to a period of a reference clock. A digitally controlled delay line may be implemented as part of a digital delay locked loop (DLL), and calibration parameters may be provided to a slave DLL having a similarly implemented delay line. A digitally controllable DLL may provide relatively low-power, high-resolution over a spectrum of process, voltage, and temperature variations, and may be implemented in relatively high-speed applications previously reserved for analog DLLs. | 2012-10-04 |
20120249201 | CLOCK SIGNAL GENERATION CIRCUIT - A clock signal generation circuit includes a clock delay control signal generation unit and a doubler clock generation unit. The clock delay control signal generation unit divides a clock signal to generate a divided clock signal, generates a plurality of periodic signals for a half period of the divided clock signal, and generates clock delay control signals from the plurality of periodic signals. The doubler clock generation unit delays the clock signal in response to the clock delay control signals to generate a delayed clock signal, and generates an output clock signal in response to the clock signal and the delayed clock signal. | 2012-10-04 |
20120249202 | Pulse Width Modulation for Switching Amplifier - A device and a method for implementing pulse width modulation for switching amplifiers ( | 2012-10-04 |
20120249203 | SIGNAL GENERATOR - There is provided a signal generator outputting an analog frequency signal based on a digital value according to a set frequency, which provides excellent noise characteristics, requires no ROM table corresponding to waveform data, and has a simple configuration. A digital signal having a digital value according to a set frequency is integrated to generate a waveform in a sawtooth shape, a waveform in a triangular wave shape is generated based on the waveform, and this waveform output is differentiated and then DIA converted and integrated. A comparator using, for example, the voltage at a midpoint of the triangular wave as a threshold value is used for the integrated output, and a frequency signal of an objective frequency is obtained from the comparator. | 2012-10-04 |
20120249204 | FLIP-FLOP CIRCUIT, SCAN TEST CIRCUIT, AND METHOD OF CONTROLLING SCAN TEST CIRCUIT - Provided is a flip-flop circuit which a small-sized test circuit with hold free and can perform test in an actual operating frequency. A Pos-type F/F includes a master latch (Low level latch) that selectively receives data or scan test data in synchronization with a rising edge of a clock signal, and a slave latch (High level latch) that receives the data from the master latch. In a scan shift operation, the master latch captures scan data signal input SIN in a Low period of a scan shift clock signal SCLK | 2012-10-04 |
20120249205 | Semiconductor Device, a Method of Improving a Distortion of an Output Waveform, and an Electronic Apparatus - Provided is a semiconductor device which inputs an input clock signal of predetermined frequency and outputs a plurality of clock signals of the same frequency, the semiconductor device including: an input unit configured to input the input clock signal of the predetermined frequency; and a delay unit configured to generate a plurality of clock signals of the same frequency by providing predetermined delay time period to the input clock signal to be delayed in order to reduce load applied to a power supply in common with the plurality of the clock signals. According to the semiconductor device, output waveform distortion of the clock signals can be improved even with simple structure. | 2012-10-04 |
20120249206 | VARIBLE DELAY CIRCUIT - A variable delay circuit includes delay units connected in series. Each delay unit includes first to third logic gates. The first logic gates are connected in series so that the output of the previous stage is input to one of inputs of the subsequent stage and first control data is input to the other of the inputs. In each stage, one of inputs of the second logic gate is connected to the one of the inputs of the first logic gate and second control data is input to the other of the inputs. The third logic gates are connected in series, the output of the second logic gate is input to third logic gate, and the delay time of a path from one of the inputs to the output and the delay time of a path from the other of the inputs to the output are substantially the same. | 2012-10-04 |
20120249207 | CLOCK SIGNAL GENERATION CIRCUIT - A clock signal generation circuit includes a first oscillation circuit for generating a first oscillation clock signal having a first frequency; a second oscillation circuit for generating a second oscillation clock signal having a second frequency; a frequency division circuit for generating a frequency division clock signal obtained through dividing the first oscillation clock signal; and a clock selection circuit for outputting the first oscillation clock signal as a high speed clock signal. The clock selection circuit is configured to output the second oscillation clock signal as the low speed clock signal when the second oscillation circuit transmits the second oscillation clock signal, and to output the frequency division clock signal as the low speed clock signal when the second oscillation circuit does not transmit the second oscillation clock signal. | 2012-10-04 |
20120249208 | CLAMP CIRCUIT, SEMICONDUCTOR DEVICE, SIGNAL PROCESSING SYSTEM, AND SIGNAL CLAMPING METHOD - The present invention provides a clamp circuit including, a switching section including first and second switching elements connected parallel between a current supply source and a clamp capacitor; a first control section that controls the first switching element to connect the current supply source and the clamp capacitor, when the voltage of an input signal input through the clamp capacitor is lower than a first reference voltage; and a second control section that stores voltage information based on the input signal when the voltage of the input signal is lower than a second reference voltage, and that controls the second switching element to connect the current supply source and the clamp capacitor for a period predetermined based on the voltage information, when the input signal is equal to or higher than the first reference voltage. | 2012-10-04 |
20120249209 | TRANSMISSION SYSTEM - Provided is a transmission system capable of improving the SN ratio for noise superimposed on a transmission line and extending the dynamic range. The transmission system transmits a signal between a transmitter ( | 2012-10-04 |
20120249210 | SWITCH CIRCUIT AND SEMICONDUCTOR CIRCUIT - A T/R switch applicable to an ultrasonograph and capable of transmitting a signal reflected from a living body over a wide band with low noise without causing erroneous operation of the switch or element destruction even when the potential of a transmission signal or reflected signal changes includes: a common source terminal commonly and serially coupling the source terminals of two MOS transistors; a common gate terminal commonly coupling the gate terminals of the two MOS transistors; a main switch, the drain terminals of which are connected to input/output terminals; and a floating voltage circuit which is connected to the common gate terminal and common source terminal, makes the common gate terminal potential follow, in phase, variation in the common source terminal potential, and sends a signal to turn the switch on or off to the common gate terminal. | 2012-10-04 |
20120249211 | SEMICONDUCTOR DEVICE - A semiconductor device including a first function block operating at a first operation voltage having a first range and for generating a data signal, a second function block operating at a second operation voltage having a second range, and a voltage level control unit for performing or not performing a level shifting operation on a voltage level of the data signal depending on the existence or non-existence of a difference between the first operation voltage and the second operation voltage, and for transmitting a level-shifted data signal or the data signal to the second function block. | 2012-10-04 |
20120249212 | EXTERNAL MOUNTED AMPLIFIERS WITH ACTIVE INTERFERENCE CANCELATION USING DIVERSITY ANTENNAS - A system includes a first external mounted amplifier (EMA) having a first low-noise amplifier (LNA) coupled to a first antenna, a second EMA having a second LNA coupled to a second antenna, a first splitter coupled between the first antenna and the first LNA, a first phase shifter coupled to the first splitter, and a second mixer coupled to the first phase shifter. The first LNA is operable to receive a first input signal from first antenna. The second LNA is operable to receive a second input signal from second antenna. The first splitter is operable to derive a first sampling signal from first signal. The first phase shifter is operable to shift the phase of first sampling signal to create a second cancelation signal. The second mixer is operable to mix a second input signal derived from second signal with second cancelation signal to create a second output signal. | 2012-10-04 |
20120249213 | ALTERNATE POWER GATING ENABLEMENT - Structures and methods for implementing alternating power gating in integrated circuits. A semiconductor structure includes a power gated circuit including a group of power gate switches and an alternating enable generator that generates enabling signals. Each respective one of the power gate switches is enabled by a respective one of the enabling signals. The alternating generator generates the enabling signals such that a first enabled power gate switch is alternated amongst the group of power gate switches. | 2012-10-04 |
20120249214 | DRIVER CIRCUIT OF SEMICONDUCTOR APPARATUS AND METHOD FOR CONTROLLING THE SAME - A driver circuit of a semiconductor apparatus includes a driver and a control unit configured to vary a voltage level of a power supply terminal of the driver in response to a standby mode signal. | 2012-10-04 |
20120249215 | SWITCH CIRCUIT - A switch circuit for switching between a first storage and a second storage. The switch circuit includes a switch, a control circuit, a switch control chip, and a processing chip. The control circuit is connected to the switch, the first storage, and the second storage. The control circuit either transmits power from a power supply to the first or second storage according to the switch. The switch control chip is connected to the control circuit. The processing chip is connected to the switch control chip. The control circuit controls the switch control chip to either transmit data between the processing chip and the first storage in response to the power supply powering the first storage, or transmit data between the processing chip and the second storage in response to the power supply powering the second storage. | 2012-10-04 |
20120249216 | HIGH VOLTAGE SWITCH CONFIGURATION - A High Voltage switch configuration having an input terminal which receives an input signal and an output terminal which issues an output signal to a load. The High Voltage switch configuration comprises at least a first and a second diode, being placed in antiseries between said input and output terminals and having a pair of corresponding terminals in common, in correspondence of a first internal circuit node. | 2012-10-04 |
20120249217 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A high-speed semiconductor integrated circuit device is achieved by adjusting an offset voltage. For example, dummy NMOS transistors MND | 2012-10-04 |
20120249218 | INDUCED THERMAL GRADIENTS - A temperature difference between a first thermal sensor and a second thermal sensor on a first die is determined. The temperature difference is transmitted from the first die to a circuit on a second die. A temperature from a thermal sensor on the second die is determined. The temperature difference and the temperature from the thermal sensor are utilized on the second die to modify operational characteristics of one or more circuits on the second die. | 2012-10-04 |
20120249219 | INDUCED THERMAL GRADIENTS - A temperature difference between a first thermal sensor and a second thermal sensor on a first die is determined. The temperature difference is transmitted from the first die to a circuit on a second die. A temperature from a thermal sensor on the second die is determined. The temperature difference and the temperature from the thermal sensor are utilized on the second die to modify operational characteristics of one or more circuits on the second die. | 2012-10-04 |
20120249220 | Trim Circuit for Power Supply Controller - A trim circuit for a power supply controller includes: a control circuit; at least a capacitance type programmable circuit connection; and a switching circuit, under control of the control circuit, the switching circuit selectively coupling the capacitance type programmable circuit connection to anyone of an operation voltage and a programming voltage, for determining a programming state of the capacitance type programmable circuit connection. | 2012-10-04 |
20120249221 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a fuse set; a terminal assigned to be applied with a first external signal in a normal operation; and a control unit configured to receive a second external signal through the terminal and apply the received second external signal to the fuse set in a fuse control operation. | 2012-10-04 |
20120249222 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a plurality of dies, wherein each of the dies is configured to enable a power circuit provided therein according to a power control signal, in a state in which the die was determined to be a good die or a fail die. | 2012-10-04 |
20120249223 | HIGH EFFICIENCY REGULATED CHARGE PUMP - Described herein are systems and methods for creating high efficiency regulated charge pumps. In an exemplary embodiment, a Dickson charge pump is combined with a low voltage amplifier to create an effective class G amplifier with high voltage outputs that achieves very high power efficiency. The charge pump capacitors are alternately driven by either the charge pump circuit or a low voltage amplifier which uses negative feedback from one or more high voltage outputs to give closed loop regulation. | 2012-10-04 |
20120249224 | DUAL MODE CHARGE PUMP - A dual mode charge pump is operable in a first mode or a second mode for providing positive and negative output voltages that can be stabilized by adjusting the charging time of two terminals of a flying capacitor or by adjusting the charging/discharging time of the positive and negative voltage output terminals. The dual mode charge pump can apply to a much wider input supply voltage range with less numbers of power switches, thus requiring less die area and lower costs. Moreover, the dual mode charge pump can precisely define a common mode voltage, thus making the common voltage drift smaller and less load dependent, especially when the output supply voltages are under different load conditions. | 2012-10-04 |
20120249225 | CHARGE PUMP CIRCUIT - There is provided a charge pump circuit which can prevent EMI noise of a frequency component independent of an operation clock frequency from occurring at the time of a change from a disable state to an enable state. The charge pump circuit includes a detection signal synchronization circuit which outputs a synchronization detection signal generated by synchronizing a detection signal outputted from a level detection circuit to a clock signal outputted from an oscillator circuit. The synchronization detection signal is used as a pump enable signal, and a first pump capacitance and a second pump capacitance in a pump circuit body are charged and discharged in response to the synchronization detection signal and the clock signal outputted from the oscillator circuit. | 2012-10-04 |
20120249226 | SEMICONDUCTOR DEVICE - A semiconductor device includes: first and second circuit cell arrays extending in first direction; first and second power supply lines each extending in first direction and arranged over first circuit cell array, first power supply line being supplied with first power source voltage; third power supply line extending in first direction separately from second power supply line, arranged over second circuit cell array, and supplied with second power source voltage; first transistor coupled between second and third power supply lines; and first circuit arranged on first circuit cell array and operating on first and second power source voltages supplied from first and second power supply lines, respectively. | 2012-10-04 |
20120249227 | VOLTAGE LEVEL GENERATOR CIRCUIT - A voltage level generator circuit comprised of a fixed voltage generator unit for generating a first electrical current in a fixed quantity from a first supply voltage; a first current mirror circuit unit including a first thin-film NMOSFET and a second thin-film NMOSFET and that outputs a second electrical current proportional to the first electrical current; a protective circuit including: a third thin-film NMOSFET and a first thick-film PMOSFET utilized as a grounded gate for protecting the second thin-film NMOSFET, a first diode for preventing inverse current flow to the first supply, and a second diode for preventing the gate-source voltage of the third thin-film NMOSFET from reaching a negative electrical potential; and a second current mirror circuit for outputting a third electrical current proportional to the second electrical current; and a first Zener diode unit for generating a first fixed voltage from a third electrical current. | 2012-10-04 |
20120249228 | POWER-UP SIGNAL GENERATION CIRCUIT OF SEMICONDUCTOR APPARATUS - A power-up signal generation circuit of a semiconductor apparatus includes a driver configured to generate a power-up signal in response to a first voltage. The power-up signal generation circuit may also comprise a power control unit configured to provide the first voltage or a second voltage as a power supply voltage to the driver in response to the power-up signal. | 2012-10-04 |
20120249229 | SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A semiconductor integrated circuit includes a plurality of semiconductor chips respectively selected in response to a plurality of chip selection signals, and a chip selection signal generator configured to generate the chip selection signals in response to one first control signal for deciding whether to drive the semiconductor chips and at least one second control signal for selecting at least one semiconductor chip from among the semiconductor chips. | 2012-10-04 |
20120249230 | INTEGRATED CIRCUIT POWER CONSUMPTION CALCULATING APPARATUS AND PROCESSING METHOD - An integrated circuit power consumption calculating apparatus obtains power consumption of an integrated circuit by outputting circuit component transistor connection information of each of circuit components after setting a group of transistors connected via a source terminal/drain terminal of a transistor within each cell of an integrated circuit, by outputting circuit component logic model information after extracting a logic for each of the circuit components from the circuit component transistor connection information information, by obtaining power information (circuit component power information) of each signal transition state of an input/output terminal for each of the circuit components based on the circuit component transistor connection information information, by generating signal terminal transition information with a logic simulation performed for each of the circuit components of the integrated circuit, and by obtaining power consumption in a signal transition of an input/output terminal of each of the circuit components. | 2012-10-04 |
20120249231 | FIELD DEVICE - To provide reliable notification of a fault state when a power supply to a calculation processing portion is in the OFF state when a power supply to a communication processing portion is in the ON state. An isolating circuit, an inverting circuit inverting a signal branch-outputted through an output tine of the isolating circuit, and a selecting circuit that uses the signal outputted from the output line of the isolating circuit as a first input and the inverted signal from the inverting circuit as a second input, to select either the first input or the second input, depending on a selection setting status thereof, to output the selected signal to the communication processing portion are provided. A +5 V voltage is applied through a resistor to the output line of the isolating circuit. This +5 V voltage is produced through the power supply supplied from the second double-wire transmission path. | 2012-10-04 |
20120249232 | TRAVELING WAVE AMPLIFIER WITH PRE-EMPHASIS FUNCTION - A traveling wave amplifier (TWA) primarily for driving a semiconductor optical device is disclosed. The TWA of an embodiment provides a plurality of differential amplifiers of the first type and an additional differential amplifier of the second type, where are they are connected between the input and the output of the TWA. The differential amplifiers of the first type provide a first delay from the input to the output, while, the differential amplifier of the second type provide a second delay longer than the first delay between the input and the output of the TWA. | 2012-10-04 |
20120249233 | ADAPTIVE DIGITAL PRE-DISTORTION METHOD AND DEVICE TO ENHANCE THE POWER UTILITY OF POWER AMPLIFIERS IN WIRELESS DIGITAL COMMUNICATION APPLICATIONS - The present invention concerns the field of power amplifiers and in particular the enhancement of the performance of the amplifier by a feedback loop acting on the input signal. It describes a method for linearizing a power amplifier circuit having a digital base-band input signal, a power output signal, a power amplifier and a linearizer module (LM), this method comprising the steps of: extracting a feedback signal from the power amplifier (PA) output signal, down-converting the feedback RF-signal to feedback IF-signal, filtering the feedback IF-signal with a band-pass filter, A/D converting the filtered feedback IF-signal into a feedback digital signal, converting the feedback digital signal into frequency-domain using fast-Fourier transform FFT on a block of n-samples to obtain a feedback FB-FFT block, converting the input base-band digital signal into frequency-domain using fast-Fourier transform FFT on a block of n-samples to obtain a input FF-FFT block, dividing the input FF-FFT block with the feedback FB-FFT block to obtain FFT correction samples blocks, averaging at least two blocks of FFT correction samples to obtain FFT correction coefficient values, applying the FFT correction coefficient values to a digital complex multiplier, converting the output of the multiplier from frequency domain into time domain with an inverse FFT module to obtain a corrected digital input signal, converting the corrected digital input signal to analog IF signal with a digital to analog converter to obtain a corrected IF input signal, applying the band-pass filter to the corrected IF input signal, up-converting the filtered corrected IF input signal to obtain a corrected RF input signal, applying the corrected RF input signal to the power amplifier. | 2012-10-04 |
20120249234 | RECEIVER - A receiver ( | 2012-10-04 |
20120249235 | LOW DISTORTION AMPLIFER - A variable gain amplifier circuit ( | 2012-10-04 |
20120249236 | Amplifier Circuit, Mobile Communication Device and Method for Adjusting a Bias of a Power Amplifier - An amplifier circuit includes a power amplifier configured to amplify an RF input signal to obtain an RF output signal, and a bias controller configured to control a bias of the power amplifier. The bias controller is configured to determine a measure of a load impedance of a load coupled to an output of the power amplifier and provide a bias control signal to adjust the bias of the power amplifier based on the determination of the measure of the load impedance. | 2012-10-04 |
20120249237 | CORRELATED-LEVEL-SHIFTING AND CORRELATED-DOUBLE-SAMPLING SWITCHED-CAPACITOR GAIN STAGES, SYSTEMS IMPLEMENTING THE GAIN STAGES, AND METHODS OF THEIR OPERATION - Embodiments of apparatus and methods for applying a gain to an input signal are provided. An embodiment of a switched-capacitor gain stage circuit includes an input node, an output node, an operational amplifier, a correlated-double-sampling portion, a correlated-level-shifting portion, and a switching configuration. The operational amplifier has a first amplifier input, a second amplifier input, and an amplifier output. The correlated-double-sampling portion includes a plurality of sampling capacitors arranged in parallel and selectively coupled between the input node and a central node, and an offset storage capacitor including a first terminal coupled to the first amplifier input. The correlated-level-shifting portion includes a correlated-level-shifting capacitor including a first terminal coupled to the output node. The switching configuration has multiple switches that are controllable sequentially to place the gain stage circuit in a sampling state, an approximate output voltage storage state, a level shifting and gain state, and an output state. | 2012-10-04 |
20120249238 | Envelope Path Processing for Envelope Tracking Amplification Stage - The invention relates to a method of calibrating an envelope path and an input path of an amplification stage of an envelope tracking power supply, the method comprising matching the envelope path to at least one characteristic of at least one element of the input path. | 2012-10-04 |
20120249239 | CORRELATED-DOUBLE-SAMPLING SWITCHED-CAPACITOR GAIN STAGES, SYSTEMS IMPLEMENTING THE GAIN STAGES, AND METHODS OF THEIR OPERATION - Embodiments of switched-capacitor gain stage circuits and methods of their operation are provided. The circuit includes an operational amplifier, parallel sampling capacitors, an offset storage capacitor coupled to an amplifier input, and multiple switches that are configurable to place the gain stage circuit in a sampling state, a gain state, and an output state. In the sampling state, the switches are configured so that a first charge component representing an input signal is stored on the sampling capacitors, and a second charge component representing an amplifier offset voltage is stored on the offset storage capacitor. In the gain state, the switches are configured so that a third charge component representing a finite gain of the amplifier is stored on the offset storage capacitor. In the output state, the switches are configured so that the first, second, and third charge components contribute to an output signal produced at the output node. | 2012-10-04 |
20120249240 | System and method for effectively implementing a front end for a transimpedance amplifier - An apparatus for implementing a front end circuit for a transimpedance amplifier includes a front end core that receives an input signal from a photo diode. The front end core responsively generates a balanced output signal to downstream devices. A power supply provides a supply voltage to the front end circuit. In accordance with the present invention, a current source is located between the supply voltage the front end core to thereby isolate the front end core from disturbances on the power supply. This biasing arrangement advantageously provides an improved power supply rejection ratio for the front end circuit. | 2012-10-04 |
20120249241 | LIGHT RECEIVING CIRCUIT WITH DIFFERENTIAL OUTPUT - A trans-impedance amplifier (TIA) for a light-receiving circuit is disclosed where the TIA reduces the power consumption as suppressing the degradation of the signal quality in high frequency regions. The TIA comprises a primary core, a dummy core, and a differential amplifier that receives each output of two cores in the differential mode. Two cores have an arrangement substantially same to each other except that the power consumption thereof is smaller in the dummy core. Because the output impedance of two cores becomes substantially equal, the scattering parameter of the common mode to the differential mode at the output of the primary core becomes small enough. | 2012-10-04 |
20120249242 | APPARATUS AND METHODS FOR ELECTRONIC AMPLIFICATION - Apparatus and methods for electronic amplification are provided. In one embodiment, a method includes providing a first differential amplification block, providing a second differential amplification block, electrically connecting the first and second differential amplification blocks in a stack between a first voltage reference and a second voltage reference, amplifying a first signal using the first differential amplification block, and amplifying a second signal using the second differential amplification block. A voltage difference between the first and second voltage references defines a power supply voltage, and the first differential amplification block operates over a first range of the power supply voltage and the second differential amplification block operates over a second range of the power supply voltage. | 2012-10-04 |
20120249243 | LOW SWITCHING ERROR, SMALL CAPACITORS, AUTO-ZERO OFFSET BUFFER AMPLIFIER - Switching error in an auto-zero offset amplifier is reduced by keeping a clock level to the auto-zero switches at an amplitude just enough to insure complete switching of the switches of the auto-zero offset buffer amplifier. A level shifting circuit provides the clock at the desired level control and a local voltage regulator provides a regulated voltage to the level shifting circuit. | 2012-10-04 |
20120249244 | OUTPUT BUFFER OF SOURCE DRIVER - An output buffer of a source driver is disclosed. The output buffer includes a buffer input, a buffer output, a differential input stage, a bias current source, an output stage, a compensation capacitor, and a comparator. The output stage and the comparator are both operated between an analog supply voltage (AVDD) and a half analog supply voltage (HAVDD), or both operated between the half analog supply voltage (HAVDD) and a ground voltage. The comparator compares an input signal with an output signal and outputs a control signal to the bias current source according to the compared result. | 2012-10-04 |
20120249245 | OUTPUT BUFFER OF SOURCE DRIVER - An output buffer of a source driver is disclosed. The output buffer includes a buffer input, a buffer output, a differential input stage, a bias current source, an output stage, a compensation capacitor, and a comparator. The output stage and the comparator are both operated between an analog supply voltage (AVDD) and a ground voltage (AGND). The comparator compares an input voltage and an output voltage and outputs a control signal to the bias current source according to the compared result to control a bias current outputted by the bias current source to enhance the slew rate of the output buffer. | 2012-10-04 |
20120249246 | OPERATIONAL AMPLIFIER - An operational amplifier includes an input stage, an output stage, an output enable switch, an internal capacitor, a coupling effect reduction circuit. The input stage provides an intermediate signal according to an input signal. The output stage, including an output node, provides a driving signal according to the intermediate signal. The output enable switch is turned on during an output enable period, having a start time point, to drive a load with the driving signal. The internal capacitor is coupled between the input stage and the output stage. The coupling effect reduction circuit, coupled between the internal capacitor and the output node or between the internal capacitor and the input stage, is turned off during an operational period starting from the start time point, to prevent coupling charge generated when the output enable switch is turned on from affecting operational voltage levels of the input stage. | 2012-10-04 |
20120249247 | Front-End Circuit of Low Supply-Voltage Memory Interface Receiver - A circuit includes a reference voltage generator configured to generate a first reference voltage and a second reference voltage, wherein the first reference voltage is higher than a half of a positive power supply voltage, and the second reference voltage is lower than the half of the positive power supply voltage. An n-type differential amplifier includes a first and a second NMOS transistor, wherein a gate of the first NMOS transistor is coupled to an input node, and a gate of the second NMOS transistor is configured to receive the first reference voltage. A p-type differential amplifier is operated by the positive supply voltage and includes a first and a second PMOS transistor. A gate of the first PMOS transistor is coupled to the input node, and a gate of the second PMOS transistor is configured to receive the second reference voltage. | 2012-10-04 |
20120249248 | PHASE-CONTROLLED OSCILLATOR - An adjustable-frequency oscillator, is formed by two looped systems, functioning at the same frequency but the signals are phase shifted by 90°. Each looped system includes a phase shift device, an active element providing the gain and a resonator having a fixed phase-frequency characteristic. As the phase shift in each loop is imperatively a whole multiple of 2π, the phase shift added in each loop by the phase shift device entails that each resonator introduces a complementary phase shift to comply with the oscillation criterion. This complementary phase shift is produced at a frequency defined by the resonator, this then defining the frequency of oscillation. The frequency is adjusted by two phase shift stages, which carry out the analogue multiplication of the signals coming from the two looped systems by control voltages and the summing of these products. | 2012-10-04 |
20120249249 | OSCILLATING SIGNAL GENERATOR UTILIZED IN PHASE-LOCKED LOOP AND METHOD FOR CONTROLLING THE OSCILLATING SIGNAL GENERATOR - An oscillating signal generator utilized in a phase-locked loop (PLL) includes: an oscillating circuit arranged to generate an oscillating signal according to at least a first control signal; and a control circuit, arranged to adjust the first control signal according to a temperature; and the first control signal is tuned between a first boundary and a second boundary, and when the temperature is closer to a first temperature boundary than a second temperature boundary, and the control circuit is arranged to make the first control signal to be closer to the first boundary than the second boundary such that the oscillating circuit outputs the oscillating signal of a predetermined frequency in a locked mode of the PLL. | 2012-10-04 |
20120249250 | Quadrature Voltage Controlled Oscillator - According to embodiments of the present invention, a quadrature voltage controlled oscillator is provided. The quadrature voltage controlled oscillator includes a first voltage controlled oscillator and a second voltage controlled oscillator respectively comprising an inductor having a first terminal and a second terminal, a first capacitor, a second capacitor, a third capacitor and a fourth capacitor respectively comprising a first terminal and a second terminal, a first transistor, a second transistor, a third transistor and a fourth transistor respectively comprising a source terminal, a drain terminal and a gate terminal, wherein the first terminal of the inductor is coupled to the first terminal of the first capacitor, and the second terminal of the inductor is coupled to the second terminal of the first capacitor, wherein the drain terminal of the first transistor is coupled to the first terminal of the inductor, the first terminal of the first capacitor, the first terminal of the second capacitor, and the gate terminal of the fourth transistor, wherein the drain terminal of the second transistor is coupled to the second terminal of the inductor, the second terminal of the first capacitor, the first terminal of the third capacitor, and the gate terminal of the third transistor, wherein the source terminal of the first transistor is coupled to the second terminal of the second capacitor, the drain terminal of the third transistor, and the first terminal of the fourth capacitor, wherein the source terminal of the second transistor is coupled to the second terminal of the third capacitor, the drain terminal of the fourth transistor, and the second terminal of the fourth capacitor, wherein the gate terminal of the first transistor of the first voltage controlled oscillator is directly coupled to the first terminal of the inductor of the second voltage controlled oscillator, wherein the gate terminal of the second transistor of the first voltage controlled oscillator is directly coupled to the second terminal of the inductor of the second voltage controlled oscillator, wherein the gate terminal of the first transistor of the second voltage controlled oscillator is directly coupled to the second terminal of the inductor of the first voltage controlled oscillator, wherein the gate terminal of the second transistor of the second voltage controlled oscillator is directly coupled to the first terminal of the inductor of the first voltage controlled oscillator. | 2012-10-04 |
20120249251 | GENERATION OF BEZIER CURVE AS CONTROL SIGNAL FOR OSCILLATING CIRCUIT - A function generating circuit for producing a control signal for an oscillating circuit that vibrates a crystal unit includes a temperature detecting circuit to detect an ambient temperature, and a Bezier-curve generating circuit to produce a Bezier curve as the control signal in response to the ambient temperature detected by the temperature detecting circuit. | 2012-10-04 |
20120249252 | OSCILLATOR CIRCUITRY HAVING NEGATIVE DIFFERENTIAL RESISTANCE - Circuitry is provided that closely emulates biological neural responses. Two astable multivibrator circuits (AMCs), each including a negative differential resistance device, are coupled in series-circuit relationship. Each AMC is characterized by a distinct voltage-dependant time constant. The circuitry exhibits oscillations in electrical current when subjected to a voltage equal to or greater than a threshold value. Various oscillating waveforms can be produced in accordance with voltages applied to the circuitry. | 2012-10-04 |
20120249253 | MEMS VIBRATOR AND OSCILLATOR - A MEMS vibrator according to the invention includes: a first electrode fixed to a surface of a substrate; and a second electrode having a beam portion including a second face facing a first face of the first electrode, and a supporting portion supporting the beam portion and fixed to the surface of the substrate. The beam portion has a first portion whose length in a normal direction of the first face of the beam portion monotonically decreases toward a tip of the beam portion. | 2012-10-04 |
20120249254 | MANUFACTURING METHOD OF PACKAGE - Provided is a manufacturing method of a package where a gas generated between a base substrate forming wafer and a lid substrate forming wafer at the time of bonding these two wafers to each other can be easily discharged to the outside. In the method, the base substrate forming wafer and the lid substrate forming wafer are laminated to each other by sandwiching the base substrate forming wafer and the lid substrate forming wafer from both sides in the laminating direction using a lower jig and an upper jig arranged in a vacuum chamber thus forming a wafer bonded body having a plurality of cavities in each of which a piezoelectric vibrating piece is sealed, and the wafer bonded body is cut for every one of plurality of cavities thus forming a plurality of packages. | 2012-10-04 |
20120249255 | CRYSTAL DEVICE AND MANUFACTURING METHOD THEREOF - A crystal device includes; a base, a framed crystal vibrating blank in which a mesa section is formed on an upper face end bonded to a seal path on an upper surface of the base via a low melting point glass layer or a resin adhesive layer, and a lid bonded to a seal path on an upper surface of the framed crystal vibrating blank via a low melting point glass layer or a resin adhesive layer. A pillow made of low melting point glass or a resin adhesive that suppresses vibration amplitude at the time of a drop impact of the framed crystal vibrating blank is formed on a rear surface of the lid simultaneously with the low melting point glass layer or the resin adhesive layer. | 2012-10-04 |
20120249256 | CALIBRATION CIRCUIT OF A FREQUENCY GENERATOR, frequency generator, AND COMPENSATION CIRCUIT THEREOF - A calibration circuit includes at least two compensation circuits and a comparator. The at least two compensation circuits are coupled to an input signal for outputting at least a first compensation signal and a second compensation signal respectively. The comparator is coupled to the first compensation signal and the second compensation signal for outputting a calibration signal, where the calibration signal is used for determining an oscillation frequency of a crystal oscillator to achieve a purpose of frequency compensation with a temperature. | 2012-10-04 |
20120249257 | CIRCUIT FOR IMPROVING THE IMMUNITY PERFORMANCE OF A VEHICLE NETWORK - In a vehicle network for controlling electronic devices of the type having a network driver with at least one output line connected to the network through a common mode choke. A circuit for improving the immunity of the network includes a resistor and a capacitor connected in series between the signal output line and ground. The series resistor and capacitor protect the network from communication errors. | 2012-10-04 |
20120249258 | ELECTRONIC COMPONENT - In an electronic component, a first resonator includes a first quarter-wave strip line disposed on a dielectric layer and a second quarter-wave strip line disposed on another dielectric layer, the first and second quarter-wave strip lines being interdigitally coupled to each other. A second resonator includes a third quarter-wave strip line disposed on a dielectric layer and a fourth quarter-wave strip line disposed on another dielectric layer, the third and fourth quarter-wave strip lines being interdigitally coupled to each other. The first quarter-wave strip line and the third quarter-wave strip line are electromagnetically coupled to each other and are disposed on different dielectric layers. The second quarter-wave strip line and the fourth quarter-wave strip line are electromagnetically coupled to each other. | 2012-10-04 |
20120249259 | RF impedance detection using two point voltage sampling - An adaptive impedance matching module having an adjustable impedance matching network with an input for receiving an RF power source and an output to be connected to an antenna, and first and second voltage measurement device configured to sense a voltage at respective first and second nodes on the impedance matching network. A network adjuster circuit is provided to switch the impedance matching network between a first state where first and second voltages are sensed on the respective first and second nodes and a second state where third and fourth voltages are sensed on the respective first and second nodes. Processing circuitry is provided which determines the matched load impedance based upon the first, second, third and fourth sensed voltages and including matching adjustment circuitry configured to adjust the matching impedance in the event the matched load impedance differs from a target load impedance by more that a predetermined amount. | 2012-10-04 |
20120249260 | METHOD FOR PERFORMING DYNAMIC IMPEDANCE MATCHING AND A COMMUNICATION APPARATUS THEREOF - Method for performing dynamic impedance matching and communication apparatus thereof are provided. With respect to an operating band of an impedance matching circuit of a communication device, a first number of times of tuning are performed on a first element of an impedance matching circuit, and a second number of times of tuning are performed on a second element of the impedance matching circuit, wherein the first number is different from the second number. | 2012-10-04 |
20120249261 | SYSTEMS AND METHODS FOR ENHANCING RELIABILITY OF MEMS DEVICES - A micro-electromechanical system (MEMS) device that in one embodiment includes at least two MEMS switches coupled to each other in a back-to-back configuration. The first and second suspended elements corresponding to first and second MEMS switches are electrically coupled. Further, first and second contacts corresponding to the first and second MEMS switches are configured such that a differential voltage between the second suspended element and the second contact is approximately equal to a differential voltage between the first suspended element and the first contact. The MEMS device includes at least one actuator coupled to one or more of the first and second suspended elements to actuate one or more of the first and the second suspended elements. In one example, the MEMS device includes one or more passive elements coupled to one or more of the first and second MEMS switches. | 2012-10-04 |
20120249262 | POWER COMBINER, POWER AMPLIFYING MODULE HAVING THE SAME, AND SIGNAL TRANSCEIVING MODULE - There are provided a power combiner implemented by a printed circuit board, a power amplifying module having the same, and a signal transceiving module. The power combiner includes: a primary wiring unit formed on one surface of a printed circuit board, receiving a plurality of balance signals having positive balance signals and negative balance signals, and including a plurality of positive primary wirings and a plurality of negative primary wirings, wherein the plurality of positive primary wirings are spaced apart from each other by a predetermined interval, the plurality of negative primary wirings are spaced apart from each other by a predetermined interval, one ends of the plurality of positive primary wirings are connected in common to thereby receive the plurality of positive balance signals, one ends of the plurality of negative primary wirings are connected in common to thereby receive the plurality of negative balance signals, and the other ends of the plurality of positive primary wirings and the other ends of the plurality of negative primary wirings are connected to each other to thereby form a loop; and a secondary wiring unit formed on the other surface of the printed circuit board, and including a secondary wiring combining powers of the plurality of balance signals from the primary wirings forming the loop to thereby output a single end signal. | 2012-10-04 |
20120249263 | SAME-BAND COMBINER USING DUAL-BANDPASS CHANNEL FILTERS - Various embodiments relate to an apparatus and related method for transmission and reception of a plurality of a carrier signals comprising one or more dual-band channels through a same-band combiner. A device such as a base station may include a same-band combiner that comprises a plurality of dual-bandpass filters and a combining element to transmit and receive the carrier signal. Each of the dual-bandpass filters may transmit and receive a channel, with each dual-bandpass filter including separate reception and transmission passbands for the separate frequencies in the dual-band channel. The combining element may separate and combine the one or more dual-band channels, with each of the dual-bandpass filters connected in parallel processing separate dual-band channels. | 2012-10-04 |
20120249264 | LAYERED BANDPASS FILTER - A bandpass filter includes a layered structure including a plurality of stacked dielectric layers, and first to third resonators provided within the layered structure. In terms of circuit configuration, the second resonator is located between the first and third resonators. The first resonator includes a first inductor and a first capacitor. The second resonator includes a second inductor and a second capacitor. The third resonator includes a third inductor and a third capacitor. The second inductor is disposed at a position different from that of each of the first and third inductors in the stacking direction of the dielectric layers. The second inductor is lower in inductance than the first and third inductors. The second capacitor is higher in capacitance than the first and third capacitors. | 2012-10-04 |
20120249265 | Resonator and Method of Controlling the Same - A resonator comprising a resonator body and actuation electrodes for driving the resonator into a resonant mode, in which the resonator body vibrates parallel to a first axis. The resonator comprises means to apply a voltage to the resonator in a direction perpendicular to the first axis direction. This serves to shift the frequency of resonant modes other than the principal resonant mode, and this allows increased amplitude of output signal from the resonator. | 2012-10-04 |
20120249266 | RF FILTER FOR ADJUSTING COUPLING AMOUNT OR TRANSMISSION ZERO - An RF filter, e.g. RF cavity filter for adjusting coupling amount or transmission zero is disclosed. The RF filter includes a housing member in which cavities are defined by walls, resonators located in the cavities, a cover combined with an upper surface of the housing member, a first tuning element inserted into a first cavity of the cavities through the cover, and a second tuning element inserted into a second cavity of the cavities through the cover. Here, the first tuning element and the second tuning element are connected electrically. | 2012-10-04 |
20120249267 | RADIO FREQUENCY FILTER STABILIZATION - An assembly and method relates to stabilizing a radio frequency (RF) filter with respect to a housing. The assembly can include a filter component; a housing having a groove to receive the filter component; a cover mounted to the housing to cover the groove; and an elastomeric element disposed between the cover and the filter. The elastomeric element may be one or more tubular pieces. | 2012-10-04 |
20120249268 | Industrial process terminated communication system - An industrial communication system, devices and termination standard which typically connect to a number of equipment workstations or process operations along the work flow or the conveyor line, and includes the work station data and power distribution lines running along side the cell, work flow or conveyor line. Individual data units are connected between the individual equipment and the data distribution and power distribution lines, wherein a selective flow of data is provided between and/or among the individual industrial equipment. A separate data distribution, or data trunk line is also present to provide a data path separate from data present on the power distribution line as described above, and a standardized termination and power connections are provided. | 2012-10-04 |
20120249269 | ATTENUATOR - An attenuator includes a first node, a second node, a first circuit coupled between the first and second nodes, a second circuit coupled between the first circuit and the second node, and coupled to the first circuit via a third node, a third circuit coupled to the third node, and a variable capacitor coupled to the third node and configured to regulate an attenuation characteristic of the attenuator such that a flat attenuation characteristic can be achieved within a predetermined frequency range. | 2012-10-04 |
20120249270 | Providing Multiple Inductors For A Radio Tuner - A method includes receiving a desired channel indication in a radio tuner, determining a band of operation in which the channel is located, and if the channel is within a first band coupling multiple inductors into a resonant tank, and if the desired channel is within a second band coupling a single inductor into the resonant tank. | 2012-10-04 |
20120249271 | ELECTROMAGNETIC CONTACTOR UNIT - There is provided an electromagnetic contactor unit capable of firmly connecting electromagnetic contactors without influencing outer dimensions when the electromagnetic contactors are connected to each other. The electromagnetic contactor unit connected at least two juxtaposed electromagnetic contactors ( | 2012-10-04 |
20120249272 | ROTARY SOLENOID - The invention provides a rotary solenoid, comprising a stator and rotor that can rotate around a rotational axis, wherein the rotor has a rotor shaft on which a rotor disc is arranged, and the rotor disc, seen in the direction of circumference, has alternating magnetically polarized magnetic poles. The stator carries at least one coil carrying windings for conducting electric current. Between the coil and the rotor disc is a pole face having at least of two partial pole faces for guiding the magnetic flux of the magnetic field generated by the windings when current is applied. Elements of the magnetic system (the magnetic poles, the partial pole faces and the air gap) are configured along the direction of circumference depending on the rotational angle changeable in such a way that a torque results that returns the rotor in the starting position, when the current is switched off | 2012-10-04 |
20120249273 | MAGNETIC-DIELECTRIC ASSEMBLY - A magnetic-dielectric disc assembly includes a magnetic ceramic disc coaxially secured within a dielectric ceramic ring by an adhesive that includes a powdered ceramic in an epoxy matrix. The powdered ceramic is selected from the group consisting of alumina, titania, silica, and zirconia. The magnetic-dielectric disc assembly can be used as a component of, for example, a circulator, isolator, or similar electrical assembly. | 2012-10-04 |
20120249274 | MAGNETIC SHIELD, PROGRAM, AND SELECTION METHOD - A magnetic shield including a first layer and a second layer and shielding an environmental magnetic field is obtained by manufacturing the first layer that is configured by a first material and that includes a hollow portion on the inside and the second layer that is configured by a second material that is different from the first material and which is a hollow member and placing the second layer in the hollow portion of the first layer. With the magnetic shield, in regions between the first layer and the second layer, a material in which the relative magnetic permeability at the strength of the magnetic field at a region that is next to the second layer is high compared to the relative magnetic permeability of the first material at the strength of the magnetic field is selected as the second material that configures the second layer. | 2012-10-04 |
20120249275 | Insulation for Power Transformers - A power transformer is provided that includes a first transformer component, a second transformer component, and a composite structure positioned between the first transformer component and the second transformer component. The composite structure includes a first composite fiber having at least one base fiber, a sheath of binder material, and nanoclay particles, and a second composite fiber, having at least one base fiber, bound to the first composite fiber by at least a portion of the sheath. | 2012-10-04 |
20120249276 | INTEGRATED INDUCTOR DEVICE WITH HIGH INDUCTANCE, FOR EXAMPLE FOR USE AS AN ANTENNA IN A RADIOFREQUENCY IDENTIFICATION SYSTEM - An embodiment of integrated inductor device, comprising a plurality of modules overlaid to each other, each module including at least one coil of conducting material. The directly overlaid pairs of coils are coiled in opposite directions. The directly overlaid modules are mechanically coupled through first adhesive conductive regions and the coils of the directly overlaid modules are electrically coupled to each other through second adhesive conductive regions. The first and the second adhesive conductive regions coupling directly overlaid modules are formed in the same step of the process, are of the same material and are arranged at a same level. | 2012-10-04 |
20120249277 | TAP CHANGER WITH A POLARITY SWITCH FOR A VARIABLE TRANSFORMER - The invention relates to a step switch provided with a pre-selector and a polarity circuit, a separate polarisation resistance being respectively provided at the beginning and the end of the stepped winding. Optionally, the two polarisation resistances can be connected continuously or via separate polarity switches. | 2012-10-04 |
20120249278 | SYSTEM AND METHOD FOR OPERATING A TAP CHANGER - A method of operating a tap changer of a transformer or a voltage regulator in a power grid includes obtaining a load forecast for a time period. An average voltage profile is determined for the time period based on the load forecast. The method further includes estimating tap positions of the tap changer for leveling the average voltage profile during the time period. Switching signal commands are provided to the tap changer based on the estimated tap positions. | 2012-10-04 |
20120249279 | TRANSFORMER - A transformer includes a pair of first coils and at least one second coil. The first and second coils are stacked so that the at least one second coil is interposed between the first coils in a common winding axial direction of the first and second coils. Each of the first coils is covered by insulating films and integrated with the insulating films into an integrated body, so that the first coils are electrically insulated from the at least one second coil. | 2012-10-04 |
20120249280 | POWER CONVERTER USING SOFT COMPOSITE MAGNETIC STRUCTURE - A power conversion device includes a magnetic core; and a plurality of windings surrounding portions of the magnetic core, including a first winding and a second winding magnetically coupled through the magnetic core. The magnetic core comprises a first part formed of a first material and a second part formed of a second material, the first material having a first stiffness and the second material having a second stiffness substantially less than the first stiffness. The first winding and the second winding are magnetically coupled through the first part of the magnetic core. | 2012-10-04 |
20120249281 | INDUCTOR AND EDDY CURRENT SENSOR INCLUDING AN INDUCTOR - An inductor and an eddy current sensor including an inductor are disclosed. The inductor includes a patterned metal layer arranged on an insulating substrate. The inductor is capable of sensing eddy current within a high temperature region. | 2012-10-04 |
20120249282 | LARGE INDUCTANCE INTEGRATED MAGNETIC INDUCTION DEVICES AND METHODS OF FABRICATING THE SAME - Methods and apparatus described herein are associated with integrated magnetic induction devices. A magnetic induction device can include a groove formed in a substrate, a magnetic core included in the groove and surrounded by a conductive winding that is adjacent to portion(s) of the substrate, and respective insulation layers included between the substrate and the conductive winding and between the magnetic core and the conductive winding. An inductor can further include conductive vias formed in the substrate and connected to respective portions of the conductive winding. Further, a transformer can include a groove formed in a substrate, a closed-loop/gapped magnetic core included in the groove and surrounded by first and second conductive windings that are adjacent to respective portions of the substrate, and respective insulation layers formed between the substrate and the first and second conductive windings, and between the closed-loop/gapped magnetic core and the first and second conductive windings. | 2012-10-04 |
20120249283 | FLEX-RIGID WIRING BOARD AND METHOD FOR MANUFACTURING THE SAME - A protection element is provided which is capable of stably retaining a flux on a soluble conductor at a predetermined position, enabling a speedy and precise blowout of the soluble conductor in the event of an abnormality. This protection element includes: a soluble conductor | 2012-10-04 |
20120249284 | SYSTEM FOR CONTROLLING BATTERY CONDITIONS - A system and method for controlling battery conditions. The system includes a network access device battery. The network access device battery powers a network access device. A heating element may be connected to the network access device battery. The heating element may be a resistive load for determining a status of the network access device battery or the heating element may be activated based on a heating schedule. | 2012-10-04 |
20120249285 | Highlighting in response to determining device transfer - A computationally implemented method includes, but is not limited to: determining that a computing device that was presenting an item has been transferred from a first user to a second user; and presenting, via the computing device, one or more highlighted portions of the item, the one or more highlighted portions being highlighted in response, at least in part, to said determining. In addition to the foregoing, other method aspects are described in the claims, drawings, and text forming a part of the present disclosure. | 2012-10-04 |
20120249286 | SYSTEM AND METHOD FOR ASSURING UTILITY NETWORK SECURITY AND RELIABILITY - A system and method for detecting a utility network threat based on the quality of communications received at devices in the utility network. The quality of a communication signal received by a device in the utility network is determined and a threat to the utility network is determined based on the signal quality. Threat information is output to devices on the utility network. | 2012-10-04 |
20120249287 | Presentation format selection based at least on device transfer determination - A computationally implemented method includes, but is not limited to: determining that a computing device that was in possession of a first user has been transferred from the first user to a second user, the determining including at least partially identifying the second user and the computing device being designed for presenting one or more items; and presenting, via the computing device, the one or more items in one or more particular formats, the one or more particular formats being selected based, at least in part, on said determining. In addition to the foregoing, other method aspects are described in the claims, drawings, and text forming a part of the present disclosure. | 2012-10-04 |
20120249288 | RF-ID TAG READING SYSTEM FOR USING PASSWORD AND METHOD THEREOF - Provided is a RFID tag with enhanced security. The tag includes a tag memory to store thereto pre-determined password information and tag data, an antenna to receive a tag data transmission request signal from an outer reader, and a tag controller to request the reader to transmit the password if the tag data transmission request signal is received, and then to transmit the tag data if the password received from the reader is identical with the pre-determined password. Accordingly, it can be prevented for a third-party, who does not know the password, to check the tag data. | 2012-10-04 |
20120249289 | Encrypted Communications for a Moveable Barrier Environment - An at least partially secure communication environment is provided in which accessory devices can be communicated with and controlled in the context of a movable barrier operator system. In one example approach, a gateway device can be configured to coordinate and control such communications in a secure manner. Three example approaches to such a communication environment include: a gateway device's receiving an accessory device control signal and sending a rolling code based accessory command signal to a target accessory device; receiving a rolling code based accessory device control signal and sending a command signal to an accessory device; and receiving a rolling code based accessory device control signal and sending a rolling code based accessory command signal to a target accessory device. Combinations are possible. An integrated system provides for automatic functioning of one device in response to status changes of one or more other devices. | 2012-10-04 |
20120249290 | Controller For A Door Entry System - Controller for retrofit connection to a pre-installed door entry system of an area having a communal entrance secured by a communal door having a first electrically operated lock and a non-communal internal region secured by an internal door having a second electrically operated lock, the door entry system comprising a door panel associated with the communal entrance and an entry phone located within the internal region; the controller being connectable to existing circuitry of the entry phone to be able to receive a request for entry into the internal region from the door panel; and transmit an electrical signal to the entry phone to unlock the first and second electrically operated locks. The controller comprises a detector; a verifier; and a lock controller arranged to generate the signals to control the entry phone to unlock the first and second electrically operated locks when the right of access has been verified. | 2012-10-04 |
20120249291 | SYSTEMS AND METHODS FOR VEHICLE PASSIVE ENTRY - A system for a vehicle includes a sensor and a control module. The sensor detects a gesture made by a user. The control module unlocks the vehicle when (i) a key fob is within a predetermined distance from the vehicle and (ii) the detected gesture matches a desired gesture. A method for a vehicle includes detecting a gesture made by a user using a sensor, and unlocking the vehicle when (i) a key fob is within a predetermined distance from the vehicle and (ii) the detected gesture matches a desired gesture. | 2012-10-04 |