40th week of 2017 patent applcation highlights part 74 |
Patent application number | Title | Published |
20170287931 | STACKED TYPE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a stacked body which is provided on a substrate and in which an insulating film and an electrode film are alternately stacked. The semiconductor memory device also includes an insulating member which penetrates the stacked body in a stacking direction of the insulating film and the electrode film to thereby separate the stacked body. The semiconductor memory device also includes a semiconductor pillar which penetrates the stacked body in the stacking direction. A maximum portion of the insulating member where a first distance from a side surface of the insulating member to a central plane of the insulating member becomes maximum and a maximum portion of the semiconductor pillar where a second distance from a side surface of the semiconductor pillar to a center line of the semiconductor pillar becomes maximum being provided in different positions in the stacking direction. | 2017-10-05 |
20170287932 | SEMICONDUCTOR DEVICE - Disclosed are a semiconductor device and a manufacturing method thereof. The semiconductor device includes source select lines, word lines, drain select lines, and a bit line stacked on a substrate in which a first cell string region and a second cell string region are defined; channel layers and memory layers vertically passing through the source select lines, the word lines, and the drain select lines in each of the first cell string region and the second cell string region; and a common source line vertically passing through the source select lines, the word lines, and the drain select lines at centers of the first cell string region and the second cell string region, and extended to a lower side of the source select lines. | 2017-10-05 |
20170287933 | METAL OXIDE SEMICONDUCTOR CELL DEVICE ARCHITECTURE WITH MIXED DIFFUSION BREAK ISOLATION TRENCHES - A standard cell IC includes pMOS transistors in a pMOS region of a MOS device. The pMOS region extends between a first cell edge and a second cell edge opposite the first cell edge. The standard cell IC further includes nMOS transistors in an nMOS region of the MOS device. The nMOS region extends between the first cell edge and the second cell edge. The standard cell IC further includes at least one single diffusion break located in an interior region between the first cell edge and the second cell edge that extends across the pMOS region and the nMOS region to separate the pMOS region into pMOS subregions and the nMOS region into nMOS subregions. The standard cell IC includes a first double diffusion break portion at the first cell edge. The standard cell IC further includes a second double diffusion break portion at the second cell edge. | 2017-10-05 |
20170287934 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An optical waveguide for optical signals is formed in a semiconductor layer of an SOI substrate, a heater for heating the optical waveguide is formed on a silicon oxide film which covers the optical waveguide, and wirings for supplying power to the heater are connected to both ends of the heater. Each of the wirings is constituted of a laminated film of a bottom barrier metal film, an aluminum-copper alloy film serving as a main conductive film and a top barrier metal film, and the heater is constituted integrally with the bottom barrier metal film constituting a part of each of the wirings. | 2017-10-05 |
20170287935 | VARIABLE BURIED OXIDE THICKNESS FOR SILICON-ON-INSULATOR DEVICES - Variable buried oxide thickness for silicon-on-insulator devices. In some embodiments, a radio-frequency device can include a silicon-on-insulator substrate having an insulator layer and a handle wafer. The radio-frequency device can further include a plurality of field-effect transistors implemented over the insulator layer. Each transistor can be separated from the handle wafer by a corresponding portion of the insulator layer. The corresponding portion of the insulator layer can have an average thickness value such that the average thickness values associated with the plurality of FETs transistors form a non-uniform distribution. | 2017-10-05 |
20170287936 | DISPLAY DEVICE - A display device includes a substrate including a pixel area and a peripheral area located outside the pixel area; pixels located in the pixel area; power supply lines configured to provide an operating power to the pixels; and a plurality of data fanout wires configured to provide data signals to the pixels, wherein, in at least a portion of the peripheral area, the power supply lines and the plurality of data fanout wires are arranged on a same layer. | 2017-10-05 |
20170287937 | DISPLAY DEVICE CAPABLE OF REDUCING RESISTANCE OF DRIVING VOLTAGE SUPPLY WIRES - A display device includes a display panel including a display area and a peripheral area, a plurality of data lines and a plurality of driving voltage lines provided in the display area, a plurality of data connection lines provided in the peripheral area and connected to the plurality of data lines, a first driving voltage transmission line provided in the peripheral area and overlapping the plurality of data connection lines, a second driving voltage transmission line provided in the peripheral area and disposed between the first driving voltage transmission line and the display area, and a plurality of driving voltage connection lines. The plurality of driving voltage connection lines are connected to the first driving voltage transmission line and the second driving voltage transmission line, and provided between the first driving voltage transmission line and the second driving voltage transmission line. | 2017-10-05 |
20170287938 | DISPLAY APPARATUS - A display apparatus includes a substrate, a circuit, and a pixel electrode. The substrate includes a display area and a peripheral area outside the display area. The circuit is disposed in the display area. The circuit includes a plurality of conductive layers, and each conductive layer contacts a corresponding inorganic layer arranged directly below the each conductive layer. The pixel electrode is arranged over the circuit and is electrically connected to at least one of the conductive layers. | 2017-10-05 |
20170287939 | DISPLAY DEVICE - According to an aspect, a display device includes: a substrate including a display region and a non-display region surrounding the display region; at least one driver IC including connecting terminals with a first surface fixed to face the non-display region; first wires supplying a signal to the display region; first bumps connected with the first wires; second wires transferring a signal to and from outside; second bumps connected with the second wires; and inspection wires. The connecting terminals of the driver IC include first connecting terminals overlapping the first or second bumps in plan view, and a second connecting terminal not overlapping the first or second bumps in plan view. At least one inspection wire includes a connecting conductor between itself and the second connecting terminal, and at least one fuse portion, a narrower width part of the inspection wire in plan view. | 2017-10-05 |
20170287940 | DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE - A wiring having excellent electrical characteristics is provided. A wiring having stable electrical characteristics is provided. A device is manufactured through the steps of forming a first insulating film over a substrate, forming a second insulating film over the first insulating film, removing part of the first insulating film and part of the second insulating film to form a first opening, forming a first conductor in the first opening and over a top surface of the second insulating film, and forming a second conductor by planarizing a surface of the first conductor so as to remove part of the first conductor. | 2017-10-05 |
20170287941 | ELECTRO-OPTICAL DEVICE AND ELECTRONIC APPARATUS - An electro-optical device includes one or more control lines that include a scanning line, a data line and a pixel circuit. The pixel circuit has a drive transistor, a write-in transistor with a gate which is electrically connected to the scanning line, a light-emitting element that emits light at a brightness that depends on the size of a current that is supplied through the drive transistor, and a control line which overlaps the gate of the drive transistor when viewed from a direction that is perpendicular to a surface of a substrate on which the pixel circuit is formed is included in the one or more control lines. | 2017-10-05 |
20170287942 | METHOD TO IMPROVE CRYSTALLINE REGROWTH - The migration of dislocations into pristine single crystal material during crystal growth of an adjacent conductive strap is inhibited by a conductive barrier formed at the interface between the layers. The conductive barrier may be formed by implanting carbon impurities or depositing Si:C layer that inhibits dislocation movement across the barrier layer, or by forming a passivation layer by annealing in vacuum prior to deposition of amorphous Si to prevent polycrystalline nucleation at the surface of single crystalline Si, or by implanting nucleation promoting species to enhance the nucleation of polycrystalline Si away from single crystalline Si. | 2017-10-05 |
20170287943 | HIGH APERTURE RATIO DISPLAY BY INTRODUCING TRANSPARENT STORAGE CAPACITOR AND VIA HOLE - This disclosure provides apparatuses and methods of manufacturing apparatuses including thin film transistors (TFTs) and storage capacitors. An apparatus can include a substrate, a TFT, a storage capacitor adjacent to the TFT, and a common electrode. The storage capacitor can be substantially transparent to increase aperture ratio of a display device. The storage capacitor can include an insulating layer between a first transparent electrode and a second transparent electrode. The TFT can include a gate electrode, a gate insulating layer, an oxide semiconductor, source and drain electrodes, and a dielectric layer. The oxide semiconductor can be formed out of the same layer as the first transparent electrode, and the common electrode can be formed out of the same layer as the oxide semiconductor or the source and drain electrodes. | 2017-10-05 |
20170287944 | ARRAY SUBSTRATE, CURVED DISPLAY PANEL AND CURVED DISPLAY DEVICE - An array substrate, a curved display panel and a curved display device are provided, to improve visual effect and image quality of the display panel being curved by external force. The array substrate includes multiple pixel units arranged in a matrix, each pixel unit comprises at least two sub-pixel units, and each sub-pixel unit is provided with a pixel electrode and a common electrode. The pixel electrodes and/or the common electrodes in an identical pixel unit have an identical structure, and the pixel electrodes or the common electrodes in different pixel units have at least two structures. The pixel electrodes or the common electrodes are symmetrically arranged relative to a central axis of the array substrate. The central axis is a straight line located in the center of the array substrate and extending in a direction parallel to the array substrate, and an extending direction of the central axis does not change when the array substrate is curved. | 2017-10-05 |
20170287945 | THIN FILM TRANSISTOR ARRAY PANNEL AND MANUFACTURING METHOD OF THE SAME - A thin film transistor array panel includes a substrate, a data line and a light blocking layer disposed on the substrate, a thin film transistor disposed on the light blocking layer and including a source electrode, a drain electrode, and an oxide semiconductor layer, and an insulating layer disposed on the substrate and including a first contact hole overlapping a portion of the data line, a second contact hole overlapping a portion of the source electrode, and a third contact hole overlapping a portion of the drain electrode, wherein the first contact hole, the second contact hole, and the third contact hole are arranged in a row in a first direction perpendicular to a direction in which the data line is extended. | 2017-10-05 |
20170287946 | SEMICONDUCTOR DEVICE AND ACTIVE MATRIX SUBSTRATE USING SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes an insulating substrate including a pixel area and a peripheral circuit area around the pixel area, a first insulating layer which is provided on the insulating substrate and includes at least nitrogen, a second insulating layer at least provided on the first insulating layer of the peripheral circuit area, a first thin-film transistor which is provided above the first insulating layer of the pixel area and includes a first oxide semiconductor layer, and a second thin-film transistor which is provided on the second insulating layer of the peripheral circuit area and includes a second oxide semiconductor layer. The second insulating layer in the pixel area is thinner than that in the peripheral circuit area. | 2017-10-05 |
20170287947 | ARRAY SUBSTRATE AND FABRICATION METHOD, DISPLAY PANEL, AND DISPLAY DEVICE - The present disclosure provides an array substrate, including a substrate, a first functional layer configured on one side of the substrate, a first insulating layer configured on the first functional layer facing away from the substrate, a second functional layer configured on the first insulating layer facing away from the substrate, a second insulating layer configured on the second functional layer facing away from the substrate, a third functional layer configured on the second insulating layer facing away from the substrate, a third insulating layer configured on the third functional layer facing away from the substrate, a fourth functional layer configured on the third insulating layer facing away from the substrate, and a plurality of through-holes configured to electrically connect different functional layers, wherein the depth of any through-holes does not exceed the thickness of two adjacent insulating layers. | 2017-10-05 |
20170287948 | DISPLAY SUBSTRATE, MANUFACTURING METHOD THEREFOR AND DISPLAY DEVICE - Provided is a display substrate. The display substrate includes a base substrate and a thin film transistor which is formed on the base substrate, wherein the thin film transistor includes a drain electrode, and at least one pad structure is arranged on an outer side of the drain electrode; a vertical distance between a top surface of the pad structure and the base substrate is less than the vertical distance between the top surface of the drain electrode and the base substrate, and is greater than the vertical distance between the top surface of the substrate, which is located on one side of the pad structure is far away from the drain electrode, and the base substrate. Further provided are a manufacturing method for the display substrate and a display device. | 2017-10-05 |
20170287949 | DISPLAY DEVICE - A display device is disclosed. In one aspect, the display device includes a substrate, a first signal line formed over the substrate and a first insulating layer formed over the substrate and the first signal line. The display device also includes a second signal line formed over the first insulating layer and including an overlapping area that overlaps the first signal line, a second insulating layer formed over the second signal line and having a via hole that exposes at least a part of the overlapping area. The display device further includes an auxiliary wiring layer covering the via hole and connected to the overlapping area through the via hole. | 2017-10-05 |
20170287950 | THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE, AND DISPLAY DEVICE - The technical disclosure relates to a thin film transistor and a manufacturing method thereof, an array substrate and a display device. The thin film transistor comprises a base substrate, a gate electrode, an active layer, source/drain electrodes, a pixel electrode and one or more insulating layers, wherein at least one of the insulating layers comprises a bottom insulating sub-layer and a top insulating sub-layer, the top insulating sub-layer having a hydrogen content higher than that of the bottom insulating sub-layer. | 2017-10-05 |
20170287951 | DISPLAY DEVICE - Provided is a display device including: a capacitor having a first electrode, a first insulating film over the first electrode, and a second electrode over the first insulating film; and a first transistor over the capacitor. The first transistor includes the second electrode, a second insulating film over the second electrode, an oxide semiconductor film over the second insulating film, and a first source electrode and a first drain electrode over the oxide semiconductor film. The first source electrode and the first drain electrode are electrically connected to the oxide semiconductor film. | 2017-10-05 |
20170287952 | ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE - An array substrate, a display panel and a display device are provided. The array substrate comprises: an active area, a package area and a drive circuit area, wherein the drive circuit area is located between the active area and the package area. A package metal layer is provided at the package area, and at least one groove structure is provided on a side of the package metal layer in a proximity to the drive circuit area. At least one drive unit is provided at the drive circuit area and comprises at least one element, wherein the element is provided in the groove structure. | 2017-10-05 |
20170287953 | FIELD-EFFECT TRANSISTOR DEVICES HAVING PROXIMITY CONTACT FEATURES - Field-effect transistor (FET) devices are described herein that include an insulator layer, a field-effect transistor implemented over the insulator layer, a substrate layer implemented under the insulator layer, and a proximity electrode that extends at least partially through the insulator layer and positioned from the FET by a distance that is less than about 5 μm. The FET device can include one or more substrate contact features as well. | 2017-10-05 |
20170287954 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - The present disclosure provides a semiconductor device including: a light receiving portion provided in a semiconductor layer of a first conductor type, the light receiving portion being of a second conductor type that is different from the first conductor type a buffer layer provided at a light incidence side of the light receiving portion, the buffer layer being of the first conductor type: and a low refractive index layer provided at a light incidence side of the buffer layer, the low refractive index layer having a lower refractive index than refractive indices of the semiconductor layer and the buffer layer. | 2017-10-05 |
20170287955 | PHOTOELECTRIC CONVERSION APPARATUS AND CAMERA - A photoelectric conversion apparatus includes an element isolating portion that is disposed on a side of a front surface of a semiconductor layer and constituted by an insulator, and a pixel isolating portion. The pixel isolating portion includes a part that overlaps an isolating region in a normal direction. The semiconductor layer is continuous across semiconductor regions in an intermediate plane. The part is located between a semiconductor region and another semiconductor region. | 2017-10-05 |
20170287956 | SOLID-STATE IMAGING DEVICE - A solid-state imaging device includes a well formed of a first semiconductor region of a first conductivity type provided in a semiconductor substrate, a pixel provided in the well, and including a photoelectric conversion element, and a transistor including a second semiconductor region of a second conductivity type, a first contact electrode electrically connected to the first semiconductor region, and a second contact electrode electrically connected to the second semiconductor region. The first contact electrode has a contact area to the semiconductor substrate larger than that of the second contact electrode, and has different widths in a first direction and a second direction perpendicular to the first direction in a planar view. The width of the first contact electrode in the first direction is smaller than a width of the second contact electrode. | 2017-10-05 |
20170287957 | SOLID STATE IMAGING DEVICE AND ELECTRONIC APPARATUS - Provided is a solid state imaging device including: a pixel portion where pixel sharing units are disposed in an array shape and where another one pixel transistor group excluding transfer transistors is shared by a plurality of photoelectric conversion portions; transfer wiring lines which are connected to the transfer gate electrodes of the transfer transistors of the pixel sharing unit and which are disposed to extend in a horizontal direction and to be in parallel in a vertical direction as seen from the top plane; and parallel wiring lines which are disposed to be adjacent to the necessary transfer wiring lines in the pixel sharing unit and which are disposed to be in parallel to the transfer wiring lines as seen from the top plane, wherein voltages which are used to suppress potential change of the transfer gate electrodes are supplied to the parallel wiring lines. | 2017-10-05 |
20170287958 | SOLID-STATE IMAGE PICKUP APPARATUS AND ELECTRONIC APPARATUS - The present disclosure relates to a solid-state image pickup apparatus and an electronic apparatus capable of preventing charges accumulated in a PD from being lost and suppressing reductions of an S/N and a dynamic range. The apparatus according to an embodiment of the present disclosure includes: a photoelectric conversion unit; a first holding unit that holds the charge transferred from the photoelectric conversion unit; a first transfer gate unit that controls the transfer of the charge; a charge drain unit that is a drain destination of the charge generated by the photoelectric conversion unit; a first drain gate unit that controls the transfer of the charge from the photoelectric conversion unit to the charge drain unit; and a second drain gate unit that connects the charge drain unit with a constant voltage source. The present disclosure can be applied to a CIS and an electronic apparatus provided with the CIS. | 2017-10-05 |
20170287959 | IMAGE SENSOR - An image sensor may include: a photoelectric conversion element including a second conductive layer formed over a first conductive layer; an insulating layer and a third conductive layer which are sequentially formed over the second conductive layer; an opening exposing the second conductive layer through the third conductive layer and the insulating layer; a channel layer formed along the surface of the opening, and including first and second channel layers which are coupled to each other while having different conductivity types; and a transfer gate formed over the channel layer to fill the opening, and partially formed over the third conductive layer. | 2017-10-05 |
20170287960 | SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS - The present disclosure relates to a solid-state imaging device that is designed to reduce reflection of incident light at the sidewall surface of the light blocking layer of each phase difference detection pixel, and to an electronic apparatus. | 2017-10-05 |
20170287961 | SOLID STATE IMAGING DEVICE AND ELECTRONIC APPARATUS - A solid state imaging device including: a pixel region that is formed on a light incidence side of a substrate and to which a plurality of pixels that include photoelectric conversion units is arranged; a peripheral circuit unit that is formed in a lower portion in the substrate depth direction of the pixel region and that includes an active element; and a light shielding member that is formed between the pixel region and the peripheral circuit unit and that shields the incidence of light, emitted from an active element, to the photoelectric conversion unit. | 2017-10-05 |
20170287962 | SOLID-STATE IMAGING DEVICE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS - The present disclosure relates to a solid-state imaging device that can achieve a higher image quality by reducing image quality degradation, a method of manufacturing the solid-state imaging device, and an electronic apparatus. The solid-state imaging device includes: a semiconductor substrate having photodiodes formed for respective pixels, the photodiodes performing photoelectric conversion; color filters that pass light in the colors corresponding to the respective pixels, the color filters being stacked on the light incident surface side of the semiconductor substrate; and a light shielding film provided between the color filters of the respective pixels, the light shielding film being formed by stacking a first light shielding film and a second light shielding film, the first light shielding film and the second light shielding film being formed with two different materials from each other. The first light shielding film is formed with a metal having a light shielding effect, and the second light shielding film is formed with a resin having photosensitivity. The present technology can be applied to back-illuminated CMOS image sensors, for example. | 2017-10-05 |
20170287963 | OPTOELECTRONIC MODULES HAVING A SILICON SUBSTRATE, AND FABRICATION METHODS FOR SUCH MODULES - Optoelectronic modules include a silicon substrate in which or on which there is an optoelectronic device. An optics assembly is disposed over the optoelectronic device, and a spacer separates the silicon substrate from the optics assembly. Methods of fabricating such modules also are described. | 2017-10-05 |
20170287964 | SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS - Provided is a semiconductor device including: a multilayer substrate including an optical element; a light-transmitting plate provided on the substrate to cover the optical element; and a lens of an inorganic material provided between the substrate and the light-transmitting plate. A structure having a same strength as a strength per unit area of the lens is provided at a portion outside an effective photosensitive region where the optical element is formed, when the substrate is viewed in plan. | 2017-10-05 |
20170287965 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - The semiconductor device includes a semiconductor substrate having a main surface and a back surface, an device isolation film, formed over the main surface of the semiconductor substrate and having a first surface making contact with the main surface and a second surface opposed to the first surface, a plate electrode disposed over the device isolation film in contact with the second surface of the device isolation film, and a pad electrode disposed adjacent to the first surface of the device isolation film and making contact with the plate electrode. | 2017-10-05 |
20170287966 | Image Sensor Contact Enhancement - A method of image sensor fabrication includes providing a plurality of photodiodes disposed in a semiconductor material and a floating diffusion disposed in the semiconductor material. The method also includes providing peripheral circuitry disposed in the semiconductor material, including a first electrical contact to the semiconductor material, and forming a transfer gate disposed to transfer image charge from the photodiode to the floating diffusion. An isolation layer is deposited on a surface of the semiconductor material, and contact holes are etched in the isolation layer. A first silicide layer disposed on the floating diffusion, a second silicide layer disposed on the transfer gate, and a third silicide layer disposed on the first electrical contact to the semiconductor material are formed in the contact holes by depositing a silicon layer in the contact holes and metalizing the silicon layer. | 2017-10-05 |
20170287967 | VIA STRUCTURES INCLUDING ETCH-DELAY STRUCTURES AND SEMICONDUCTOR DEVICES HAVING VIA PLUGS - A semiconductor device includes a lower device and an upper device disposed on the lower device. The lower device includes a lower substrate, a lower plug pad disposed on the lower substrate, and a lower interlayer dielectric layer on the lower plug pad. The upper device includes an upper substrate, an etch-delay structure in a lower portion of the upper substrate, an upper plug pad disposed on a bottom surface of the upper substrate, an upper interlayer dielectric layer on the upper plug pad, and a via plug configured to penetrate the upper substrate and contact the upper plug pad and the lower plug pad. The via plug includes a first portion in contact with the upper plug pad and the first etch-delay structure, and a second portion in contact with the lower plug pad. | 2017-10-05 |
20170287968 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, AND ELECTRONIC DEVICE - Disclosed herein is a semiconductor device including: a first semiconductor chip having an electronic circuit section and a first connecting section formed on one surface thereof; a second semiconductor chip having a second connecting section formed on one surface thereof, the second semiconductor chip being mounted on the first semiconductor chip with the first and the second connecting sections connected to each other by a bump; a dam formed to fill a gap between the first and the second semiconductor chips on a part of an outer edge of the second semiconductor chip, the part of the outer edge being on a side of a region of formation of the electronic circuit section; and an underfill resin layer filled into the gap, protrusion of the resin layer from the outer edge of the second semiconductor chip to a side of the electronic circuit section being prevented by the dam. | 2017-10-05 |
20170287969 | SEMICONDUCTOR IMAGE SENSORS HAVING CHANNEL STOP REGIONS AND METHODS OF FABRICATING THE SAME - A semiconductor device includes a light-receiving element which outputs electric charges in response to incident light, and a drive transistor which is gated by an output of the light-receiving element to generate a source-drain current in proportion to the incident light, wherein the drive transistor include a first gate electrode, a first channel region which is disposed under the first gate electrode, first source-drain regions which are disposed at respective ends of the first channel region and that have a first conductivity type, and a first channel stop region which is disposed on a side of the first channel region, and that separates the light-receiving element and the first channel region, the first channel stop region having a second conductivity type that is different from the first conductivity type. | 2017-10-05 |
20170287970 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - Provided is a semiconductor device with improved performance. In a method for manufacturing a semiconductor device, after forming a gate electrode of a transfer transistor over a p-type well, a photodiode is formed in one part of the p-type well positioned on one side with respect to the gate electrode. Then, a cap insulating film including silicon and nitrogen is formed over the photodiode before implanting impurity ions for formation of an n-type low-concentration semiconductor region of the transfer transistor, into the other part of the p-type well positioned on a side opposite to the one side with respect to the gate electrode. | 2017-10-05 |
20170287971 | IMAGE SENSOR AND ELECTRONIC DEVICE INCLUDING THE SAME - An image sensor includes a semiconductor substrate and a photoelectric conversion device on the semiconductor substrate and including a plurality of pixel electrodes, a light absorption layer, and a common electrode. The plurality of pixel electrodes may include a first pixel electrode and a second pixel electrode. The photoelectric conversion device may include a first photoelectric conversion region defined in an overlapping region with the first pixel electrode, the light absorption layer, and the common electrode, and a second photoelectric conversion region defined in an overlapping region with the second pixel electrode, the light absorption layer, and the common electrode. Sensitivity of the first photoelectric conversion region may be higher than sensitivity of the second photoelectric conversion region. An electronic device may include the image sensor. | 2017-10-05 |
20170287972 | SOLID-STATE IMAGE SENSOR, IMAGING DEVICE, AND ELECTRONIC EQUIPMENT - The present technology relates to a solid-state image sensor, an imaging device, and electronic equipment configured such that an FD is shared by a plurality of pixels to further miniaturize the pixels at low cost without lowering of sensitivity and a conversion efficiency. | 2017-10-05 |
20170287973 | ELECTRONIC DEVICE, METHOD OF MANUFACTURING THE SAME, AND CAMERA - A method of manufacturing an electronic device, comprising fixing a first wafer on a second wafer to form a space theirbetween, via a surrounding member configured to surround the space, forming an opening on a bottom side of the first wafer to expose a conductive member included in the first wafer, and then forming an electrode connected to the conductive member, wherein, in the fixing, the first wafer includes a trench intersecting the surrounding member, on an upper side of the first surface, and, in the forming, the electrode is formed under a condition that the space communicates with an external space via the trench. | 2017-10-05 |
20170287974 | METHOD OF MANUFACTURING SOLID-STATE IMAGE SENSOR - A method of manufacturing a solid-state image sensor is provided. The method comprises: depositing a gate electrode film above the semiconductor layer; etching the gate electrode film to form a first gate electrode patterned in a pixel region, leaving the gate electrode film in a peripheral region; depositing a first insulating film above the semiconductor layer after the forming the first gate electrode; removing the first insulating film formed in the peripheral region; etching the gate electrode film left in the peripheral region to form a second gate electrode patterned in the peripheral region after the removing the first insulating film; forming a second insulating film above the semiconductor layer after the forming the second gate electrode; and forming a side wall on side surface of the second gate electrode by etching the second insulating film. | 2017-10-05 |
20170287975 | Image Sensors Including Conductive Pixel Separation Structures - An image sensor includes a substrate having adjacent pixel regions and respective photodiode regions therein, and a pixel separation portion including a trench extending into the substrate between the adjacent pixel regions. The trench includes a conductive common bias line therein and an insulating device isolation layer between the common bias line and surfaces of the trench. A conductive interconnection is coupled to the common bias line and is configured to provide a negative voltage thereto. Related fabrication methods are also discussed. | 2017-10-05 |
20170287976 | IMAGE PICKUP ELEMENT, IMAGE PICKUP APPARATUS, AND METHOD OF MANUFACTURING IMAGE PICKUP ELEMENT - Image quality is improved. | 2017-10-05 |
20170287977 | POWER HARVESTING FOR INTEGRATED CIRCUITS - Integrated circuit devices which include a thermoelectric generator which recycles heat generated by operation of an integrated circuit, into electrical energy that is then used to help support the power requirements of that integrated circuit. Roughly described, the device includes an integrated circuit die having an integrated circuit thereon, the integrated circuit having power supply terminals for connection to a primary power source, and a thermoelectric generator structure disposed in sufficient thermal communication with the integrated circuit die so as to derive, from heat generated by the die, a voltage difference across first and second terminals of the thermoelectric generator structure. A powering structure is arranged to help power the integrated circuit, from the voltage difference across the first and second terminals of the thermoelectric generator. The thermoelectric generator can include IC packaging material that is made from thermoelectric semiconductor materials. | 2017-10-05 |
20170287978 | DOMAIN WALL MAGNETIC MEMORY - Devices and methods of forming a device are disclosed. The method includes providing a substrate with a cell region. Selector units and storage units are formed within the substrate. The selector unit includes first and second bipolar junction transistors (BJTs). The selector unit includes first and second bipolar junction transistors (BJTs). A BJT includes first, second and third BJT terminals. The second BJT terminals of the first and second BJTs are coupled to or serve as a common wordline terminal. The third BJT terminal of the first BJT serves as a first bitline terminal, and the third BJT terminal of the second BJT serves as a second bitline terminal. A storage unit is disposed over the selector unit. The storage unit includes a first pinning layer which is coupled to the first BJT terminal of the first BJT, a second pinning layer which is coupled to the first BJT terminal of the second BJT, a free layer which includes an elongated member with first and second major surfaces and first and second end regions separated by a free region. The first pinning layer is coupled to the second major surface of the free layer in the first end region and the second pinning layer is coupled to the second major surface of the free layer in the second end region. A reference stack is disposed on the first major surface of the free layer in the free region. The reference stack serves as a read bitline terminal. | 2017-10-05 |
20170287979 | STRAIN ASSISTED SPIN TORQUE SWITCHING SPIN TRANSFER TORQUE MEMORY - Described is an apparatus which comprises: a magnetic tunneling junction (MTJ) having a free magnetic layer; a piezoelectric layer; and a conducting strain transfer layer coupled to the free magnetic layer and the piezoelectric layer. Described is a method, which comprises: exciting a piezoelectric layer with a voltage driven capacitive stimulus; and writing to a MTJ coupled to the piezoelectric layer via a strain assist layer. Described is also an apparatus which comprises: a transistor; a conductive strain transfer layer coupled to the transistor; and a MTJ device having a free magnetic layer coupled to the conductive strain transfer layer. | 2017-10-05 |
20170287980 | THERMAL INSULATION FOR THREE-DIMENSIONAL MEMORY ARRAYS - Methods, systems, and devices for a three-dimensional memory array are described. Memory cells may transform when exposed to elevated temperatures, including elevated temperatures associated with a read or write operation of a neighboring cell, corrupting the data stored in them. To prevent this thermal disturb effect, memory cells may be separated from one another by thermally insulating regions that include one or several interfaces. The interfaces may be formed by layering different materials upon one another or adjusting the deposition parameters of a material during formation. The layers may be created with planar thin-film deposition techniques, for example. | 2017-10-05 |
20170287981 | IMAGE SENSOR INCLUDING NANOSTRUCTURE COLOR FILTER - An image sensor includes a first light sensor layer including light sensing cells configured to sense first light of an incident light and generate electrical signals based on the sensed first light, and a color filter array layer disposed on the first light sensor layer, and including color filters respectively facing the light sensing cells. The image sensor further includes a second light sensor layer disposed on the color filter array layer, and configured to sense second light of the incident light and generate an electrical signal based on the sensed second light. Each of the color filters includes a nanostructure including a first material having a first refractive index, and a second material having a second refractive index greater than the first refractive index, the first material and the second material being alternately disposed with a period. | 2017-10-05 |
20170287982 | SOLID-STATE IMAGE PICKUP DEVICE AND MANUFACTURING METHOD THEREOF, AND ELECTRONIC APPARATUS - Provided is a solid-state image pickup device that makes it possible to enhance image quality, and a manufacturing method thereof, and an electronic apparatus. A solid-state image pickup device includes a pixel section that includes a plurality of pixels, the pixels each including one or more organic photoelectric conversion sections, wherein the pixel section includes an effective pixel region and an optical black region, and the organic photoelectric conversion sections of the optical black region include a light-shielding film and a buffer film on a light-incidence side. | 2017-10-05 |
20170287983 | DISPLAY DEVICE - A display device includes a display unit in which pixels are arranged in a matrix. The pixels each include a first sub-pixel having the largest area among sub-pixels, a second sub-pixel adjacent to the first sub-pixel and having an area smaller than that of the first sub-pixel, and a third sub-pixel adjacent to the first and second sub-pixels, having an area smaller than that of the first sub-pixel, and arranged in the same column as that of second sub-pixels. First, second, and third pixels are aligned in at least one of a column direction or a row direction and each include the first, second, and third sub-pixels that can display different one of first, second, and third colors. Areas of the first, second, and third colors displayable by the first, second, and third pixels in total are equal to one another. | 2017-10-05 |
20170287984 | DISPLAY PANEL AND METHOD FOR MANUFACTURING SAME - A display panel includes an EL panel section, a CF panel section, and a sealing resin layer. In the EL panel section, the surface of a sealing layer has a projected and recessed shape in a Z-axis direction as a whole, wherein a light-emitting region corresponding to a region between banks is a recessed section, and a non-light-emitting region corresponding to a top portion of the bank is a projected section. The sealing resin layer includes a first sealing resin layer and a second sealing resin layer. Prior to performing heating or light irradiation in a step of forming the first and second sealing resin layers, the viscosity of a second non-fluid resin constituting the second sealing resin layer is lower than the viscosity of a first non-fluid resin constituting the first sealing resin layer. | 2017-10-05 |
20170287985 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - An organic light emitting display device includes a first emission part between an anode and a cathode and a second emission part on the first emission part. At least one of the first emission part and the second emission part includes at least three emission layers emitting lights of different colors, and one of the at least three emission layers include a green emission layer including a phosphorescent material. Accordingly, a lifetime and color reproduction rate of the organic light emitting display device having green lifetime is enhanced. | 2017-10-05 |
20170287986 | DISPLAY PANEL AND METHOD OF MANUFACTURING THE SAME - A display panel includes a base substrate, an active pattern on the base substrate, and including a first active pattern of a first transistor, and a second active pattern of a second transistor, a gate pattern on the base substrate, and including a first gate electrode that overlaps the first active pattern, and a second gate electrode that overlaps the second active pattern, an insulation layer covering the gate pattern, a first conductive pattern on the insulation layer, and electrically connected to the first gate electrode through a first contact hole formed through the insulation layer, and a second conductive pattern electrically connected to the second gate electrode through a second contact hole formed through the insulation layer, wherein each of the first contact hole and the second contact hole overlaps, partially overlaps, or does not overlap each of the first active pattern and the second active pattern, and wherein a first overlapped area at which the first active pattern overlaps the first contact hole is different from a second overlapped area at which the second active pattern overlaps the second contact hole. | 2017-10-05 |
20170287987 | HIGH RESOLUTION LOW POWER CONSUMPTION OLED DISPLAY WITH EXTENDED LIFETIME - Systems and techniques are provided that allow for fabrication of full-color OLED displays that include only two colors of emissive regions and four or more sub-pixels within pixels of the device. Mask arrangements for fabricating such devices are also provided. | 2017-10-05 |
20170287988 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - Provided is an organic light emitting display device including a plurality of sub pixels. Areas of emission regions of green sub pixels of the plurality of sub pixels are the same as or larger than an area of an emission region of at least one non-green sub pixel of the plurality of sub pixels. Also the organic light emitting display device includes an area of an emission region of a green sub pixel having a low luminance lifetime being the same as or larger than areas of emission regions of non-green sub pixels. Accordingly, it is possible to make the luminance lifetime of the green sub pixel and the luminance lifetimes of the non-green sub pixels uniform. Further, it is possible to minimize a color change of the organic light emitting display device. | 2017-10-05 |
20170287989 | DISPLAY DEVICE - According to an aspect, a display device includes a display unit in which a plurality of pixels are arranged in a matrix along two directions intersecting with each other. Each of the pixels includes three sub-pixels corresponding to three of four colors including a first color, a second color, a third color, and a fourth color. An area of one sub-pixel among the three sub-pixels is larger than the area of each of the other two sub-pixels. A sub-pixel of the fourth color is one of the other two sub-pixels. Pixels each including the sub-pixel of the fourth color are not adjacent to each other in at least one of the two directions in the display unit. | 2017-10-05 |
20170287990 | ORGANIC LIGHT EMITTING DISPLAY DEVICE INCLUDING A SOUND GENERATING APPARATUS - Embodiments of the present disclosure relate to an organic light emitting display device which directly vibrates an organic light emitting display panel to generate sound, and includes: an organic light emitting display panel including a light emitting layer including an organic light emitting material layer and an encapsulation layer disposed at one side of the light emitting layer; and a sound generating actuator in direct contact with the organic light emitting display panel to vibrate the organic light emitting display panel to generate sound. Especially, the organic light emitting display panel is a bottom emission type device, and thus can prevent generation of a weighted color mixing phenomenon in a wide viewing angle at the time of panel vibration and reduce the thickness or weight of the panel to thereby enhance the sound generation characteristic. | 2017-10-05 |
20170287991 | LIGHT SENSITIVE CIRCUIT, LIGHT SENSING PANEL HAVING THE LIGHT SENSITIVE CIRCUIT AND DISPLAY APPARATUS HAVING THE LIGHT SENSING PANEL - A light sensitive circuit includes a light sensing capacitor and a driving transistor. The light sensing capacitor is configured to sense light of a predetermined one or more wavelengths. The driving transistor includes a gate electrode electrically connected to the light sensing capacitor and is configured to generate a light sensing current according to a voltage of the gate electrode in the driving transistor. A light sensing accuracy and a light sensing signal to noise ratio (SNR) of the display apparatus including a plurality of such light sensing capacitors may be improved relative to ones that do not include such light sensing capacitors. | 2017-10-05 |
20170287992 | ELECTRONIC DEVICE INCLUDING DISPLAY AND CAMERA - An electronic device is provided. The electronic device includes a housing, comprising a first surface including a transparent later and a second surface, a display exposed through the transparent layer and including an active area, a first adhesive layer, a touchscreen panel, and a second adhesive layer, an opening formed at least partially through the first adhesive layer, a plurality of conductive lines disposed extending around a periphery of the opening so as not to optically block the opening, a camera device positioned including an image sensor disposed through at least a portion of the opening, and an integrated circuit (IC) electrically coupled to the plurality of conductive lines, wherein the IC is configured to provide image data to the display. | 2017-10-05 |
20170287993 | DISPLAY PANEL AND METHOD FOR MANUFACTURING SAME - A display panel including a substrate; first, second, and third lower electrodes; first and second column banks; first, second, and third organic light-emitting layers; and an upper electrode. When a first ink for forming the first organic light-emitting layer, a second ink for forming the second organic light-emitting layer, and a third ink for forming the third organic light-emitting layer are applied, ink-separating capability of the first column bank for separating the first ink and the second ink is lower than ink-separating capability of the second column bank for separating the second ink and the third ink, and ink-separating capability depends on: (i) a height of the first and second column banks, or (ii) liquid repellency of the first column bank against the first ink and the second ink and liquid repellency of the second column bank against the second ink and the third ink. | 2017-10-05 |
20170287994 | ORGANIC LIGHT-EMITTING DISPLAY DEVICE - An organic light-emitting display device includes a pixel including a first region to display an image, a second region to transmit external light, and a third region between the first region and the second region. The pixel includes a pixel electrode in the first region, a pixel-defining layer in at least the first region, an auxiliary electrode in at least the third region, and an intermediate layer on the pixel electrode. The pixel-defining layer includes a first opening exposing a portion of the pixel electrode and a second opening corresponding to at least the second region and third region. The pixel electrode is exposed via the first opening, and the intermediate layer includes an organic emission layer. An opposite electrode is on the intermediate layer and contacts the auxiliary electrode in the third region. | 2017-10-05 |
20170287995 | DISPLAY DEVICE WITH PROTECTION AND ENCAPSULATION LAYERS TO SEAL DISPLAY UNIT - A display device includes a substrate, a display unit disposed over the substrate, and an encapsulation layer sealing the display unit. The display unit includes a thin film transistor, a display element electrically connected to the thin film transistor, a protection layer, and a planarization layer. The protection layer and the planarization layer are disposed between the thin film transistor and the display element. The display unit includes a display area and a non-display area outside the display area. The non-display area includes a voltage line. The planarization layer includes a dividing region dividing the planarization layer into a center portion and an outer portion. The dividing region surrounds the display area. The voltage line is partially disposed in the dividing region. The protection layer at least covers the sides of the voltage line disposed in the dividing region. | 2017-10-05 |
20170287996 | ORGANIC LIGHT-EMITTING DISPLAY APPARATUS - An organic light-emitting display apparatus includes a plurality of pixels. At least one of the pixels includes a first conductive layer over a substrate, a first organic insulating layer including a first opening exposing a portion of the first conductive layer, a first inorganic insulating layer over the first organic insulating layer and including a second opening exposing the portion of the first conductive layer exposed through the first opening, and a second conductive layer on the first inorganic insulating layer and contacting the portion of the first conductive layer exposed through the first opening and the second opening. | 2017-10-05 |
20170287997 | FLEXIBLE DISPLAY APPARATUS - A flexible display apparatus including a substrate including a flat surface portion and at least one curved surface portion, and a display including a first display region above the flat surface portion and a second display region above the at least one curved surface portion. The second display region includes a correcting layer including a first point and a second point apart from each other. The second point is farther away from the first display region than the first point. A thickness of the correcting layer at the second point is greater than a thickness of the correcting layer at the first point. The correcting layer includes a curved portion between the first point and the second point. | 2017-10-05 |
20170287998 | ORGANIC EL DISPLAY DEVICE AND METHOD OF MANUFACTURING AN ORGANIC EL DISPLAY DEVICE - An organic EL display device includes a plurality of pixels and a transistor in each of the pixels. The transistor includes a drain electrode and a source electrode. A first gate electrode formed between the source electrode and the drain electrode, and a semiconductor film formed at a lower layer side of the first gate electrode. A first region that is one of a region between the first gate electrode and the drain electrode and a region between the first gate electrode and the source electrode of the semiconductor film has a high density of n-type ions and a second region that is the other one of the region between the first gate electrode and the drain electrode and the region between the first gate electrode and the source electrode of the semiconductor film has a low density of n-type ions. | 2017-10-05 |
20170287999 | SEMICONDUCTOR DEVICE AND DISPLAY DEVICE - A display device includes a substrate having flexibility, a transistor having a gate insulating film and further having a semiconductor layer and a gate electrode that sandwich the gate insulating film, the transistor formed in an area where the substrate is bent, and a gate wiring line so formed on the substrate as to be connected to the gate electrode, and the gate electrode has an area that is present in an area where the gate electrode overlaps with the semiconductor layer and is thinner than at least part of the gate wiring line. | 2017-10-05 |
20170288000 | PIXEL STRUCTURE HAVING HIGH APERTURE RATIO AND CIRCUIT - A pixel circuit and a pixel structure having high aperture ratio are provided. A first gate electrode, a layer including a first source electrode and a first drain electrode, and an etching stopper layer, a first semiconductor layer, and a gate isolation layer sandwiched between the first gate electrode and the layer of the first source electrode and the first drain electrode construct a first thin film transistor. A second gate electrode, a layer including a second source electrode and a second drain electrode, and an etching stopper layer, a second semiconductor layer, and the gate isolation layer sandwiched between the second gate electrode and the layer of the second source electrode and the second drain electrode construct a second thin film transistor. A transparent electrode, a pixel electrode and a flat isolation layer sandwiched between the transparent electrode and the pixel electrode construct a transparent capacitor. | 2017-10-05 |
20170288001 | PHOTOSENSOR AND DISPLAY DEVICE HAVING THE SAME - A photosensor includes a first light-shielding layer provided on an insulating surface; a first insulating layer covering the first light-shielding layer; a semiconductor layer provided on the first insulating layer, the semiconductor layer being connected to a first electrode and a second electrode, and the semiconductor layer configuring a diode; a second insulating layer covering the semiconductor layer; an opening provided in the second insulating layer so as to surround the semiconductor layer as viewed from a planar direction and the opening reaching at least the first insulating layer; and a second light-shielding layer covering at least a side wall of the opening. | 2017-10-05 |
20170288002 | DISPLAY DEVICE - A display device includes a display portion defining a display area and including a plurality of pixels, a scan driver disposed in a non-display area that is outside of the display area, and a plurality of scan connection lines. Each of the pixels is connected to a scan line from among a plurality of scan lines and a data line from among a plurality of data lines. The scan connection lines connect the scan driver to the scan lines. Each of the scan connection lines is connected to one of the scan lines through a contact hole disposed in at least one insulating layer, which is disposed between the scan lines and the scan connection lines in a cross-sectional view. | 2017-10-05 |
20170288003 | DISPLAY DEVICE - A display device includes a through portion passing through a display layer. The display includes a plurality of scan lines above the substrate and extending in a first direction, a plurality of data lines extending in a second direction, and a plurality of pixels connected to the scan lines and data lines. The data lines include a first data line and a second data line disconnected by the through portion, and a third data line spaced apart from the through portion along the first direction. The first data line is electrically connected with the third data line. | 2017-10-05 |
20170288004 | DISPLAY DEVICE - A display device includes: a substrate; an insulating layer arranged above the substrate; a through portion configured to pass through the substrate and the insulating layer; a pixel array located above the insulating layer and including pixels each including a light-emitting element including a pixel electrode, an opposite electrode facing the pixel electrode, and an emission layer arranged between the pixel electrode and the opposite electrode, the pixels at least partially surrounding the through portion; and a pattern portion arranged between the through portion and the pixel array, wherein the pattern portion includes: a recess that is concave along a thickness direction of the insulating layer; and a cladding layer arranged above the insulating layer, configured to cover the recess, and including a material different from the insulating layer. | 2017-10-05 |
20170288005 | DISPLAY DEVICE - According to one embodiment, a display device comprises a flexible substrate, a first insulating film disposed on the flexible substrate, a switching element disposed on the first insulating film, a signal wiring electrically connected with the switching element, a first organic film disposed on the signal wiring, a connection wiring disposed on the first organic film, a second organic film disposed on the connection wiring and a pad electrode disposed on the second organic film. The connection wiring is located between the first organic film and the second organic film and is in contact with the first organic film and the second organic film. | 2017-10-05 |
20170288006 | DISPLAY MODULE AND ELECTRONIC DEVICE HAVING SAID DISPLAY MODULE - A display module ( | 2017-10-05 |
20170288007 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF THAT MAY MINIMIZE AN OCCURRENCE OF A DEFECT IN THE DISPLAY DEVICE - A display device includes a substrate divided into an encapsulation area and a non-encapsulation area. The display device includes an interlayer insulating layer disposed over the substrate. The display device includes a first inner contact hole passing through the interlayer insulating layer in the encapsulation area, and connecting an inner conductive layer to an inner lower conductive layer. The display device includes an outer contact hole passing through the interlayer insulating layer in the non-encapsulation area, and connecting an outer conductive layer to an outer lower conductive layer. A slope angle formed by a lateral wall of the outer contact hole with respect to an upper surface of the substrate is less than a slope angle formed by a lateral wall of the first inner contact hole with respect to the upper surface of the substrate. | 2017-10-05 |
20170288008 | DISPLAY APPARATUS - A display apparatus includes a substrate. A display unit is disposed on the substrate and includes a display region and a non-display region. At least one light-emitting device is disposed in the display region. First and second power supply lines, configured to supply driving power to the at least one light-emitting device, and a pad unit, are disposed in the non-display region. The first power supply line includes a first fan-out wire portion electrically connected to the pad unit, and a first extension portion electrically connected to the first fan-out wire portion. The second power supply line includes a second fan-out wire portion electrically connected to the pad unit, and a second extension portion electrically connected to the second fan-out wire portion. The first extension portion has a width W | 2017-10-05 |
20170288009 | DISPLAY DEVICE HAVING A BENDING AREA - A display device includes a substrate including a bending area located between a first area and a second area. The substrate is bent in relation to a bending axis. A first wiring unit including a plurality of first wirings is arranged on the substrate to sequentially extend over the first area, the bending area, and the second area. First central axes included in each of the plurality of first wirings are spaced apart from each other by a first pitch in the bending area. A second wiring unit including a plurality of second wirings is arranged on the substrate to sequentially extend over the first area, the bending area, and the second area. Second central axes included in each of the plurality of second wirings are spaced apart from each other by a second pitch greater than the first pitch in the bending area. | 2017-10-05 |
20170288010 | Organic Light Emitting Display Device - Disclosed is an organic light emitting display device that may include first and second pads on a pad area of a substrate, wherein the first pad includes a first bonding region and a first link region, and the second pad includes a second bonding region, a contact region, and a second link region. A first bonding electrode in the first bonding region is electrically connected to one or more signal lines in the active area of the device through contact holes in the first bonding region. A second bonding electrode is electrically connected to one or more signal lines of the device through contact holes in the contact region. The contact region is closer to the active area than the first bonding region. | 2017-10-05 |
20170288011 | HIGH-DENSITY MIM CAPACITORS - Capacitors and methods of forming the same include forming a gap in a dielectric layer underneath one or more conducting lines, such that the one or more conducting lines are suspended over the gap. A capacitor stack is deposited in the gap and on the conducting lines. Respective contacts are deposited on the conducting lines and on the capacitor stack. | 2017-10-05 |
20170288012 | ANALOG CAPACITOR - An analog capacitor is disclosed. The analog capacitor may include a main analog capacitor, an interlayer insulating layer, and a plurality of stacked sub analog capacitors. The main analog capacitor may be formed over a semiconductor substrate. The interlayer insulating layer may be interposed between the semiconductor substrate and the main analog capacitor. The plurality of stacked sub analog capacitors may be inserted into the interlayer insulating layer. | 2017-10-05 |
20170288013 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a high voltage transistor formation region defined by an element isolation insulating film, a transistor formation region defined by an element isolation insulating film, and a substrate contact portion. A crystal defect region is formed at a portion of a semiconductor substrate that is positioned immediately below each of the substrate contact portion and element isolation insulating films. | 2017-10-05 |
20170288014 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device may include a semiconductor substrate in which a semiconductor element is provided, and an insulation film provided on the semiconductor substrate, in which the semiconductor substrate may include a first portion and a second portion which has a thickness thinner than a thickness of the first portion, an upper surface of the second portion may be positioned lower than an upper surface of the first portion, a recess extending in a thickness direction of the semiconductor substrate may be provided on the upper surface of the second portion located at a position where the first portion and the second portion adjoin to each other, and the insulation film may extend over from the first portion to the second portion, and fill the recess. | 2017-10-05 |
20170288015 | SEMICONDUCTOR STRUCTURE INCLUDING A TRENCH CAPPING LAYER - A semiconductor structure includes a trench isolation structure and a trench capping layer positioned over the trench isolation structure, wherein the trench isolation layer includes a first electrically insulating material and the trench capping layer includes a second electrically insulating material that is different from the first electrically insulating material. The semiconductor structure also includes a gate structure having a gate insulation layer and a gate electrode positioned over the gate insulation layer, wherein the gate insulation layer includes a high-k material and the gate structure includes a first portion that is positioned over the trench capping layer. A sidewall spacer is positioned adjacent to the gate structure, wherein a portion of the sidewall spacer is positioned on the trench capping layer and contacts the trench capping layer laterally of the gate insulation layer. | 2017-10-05 |
20170288016 | FINFET WITH ISOLATED SOURCE AND DRAIN - A FinFET has shaped epitaxial structures for the source and drain that are electrically isolated from the substrate. Shaped epitaxial structures in the active region are separated from the substrate in the source and drain regions while those in the channel region remain. The gaps created by the separation in the source and drain are filled with electrically insulating material. Prior to filling the gaps, defects created by the separation may be reduced. | 2017-10-05 |
20170288017 | NANODEVICE - A nanodevice capable of controlling the state of electric charge of a metal nanoparticle is provided. The device includes: nanogap electrodes 5 including one electrode 5A and the other electrode 5B disposed so as to have a nanosize gap in between; a nanoparticle 7 placed between the nanogap electrodes 5; and a plurality of gate electrodes 9. At least one of the plurality of gate electrodes 9 is used as a floating gate electrode to control the state of electric charge of the nanoparticle 7, which achieves a multivalued memory and rewritable logical operation. | 2017-10-05 |
20170288018 | NANOWIRE TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A method for fabricating a nanowire transistor is disclosed. First, a substrate is provided, and a stack structure is formed on the substrate, in which the stack structure includes a first semiconductor layer and a second semiconductor layer and the first semiconductor layer and the second semiconductor layer are made of different material. Next, a hard mask is formed on the stack structure and a first spacer adjacent to the hard mask, part of the stack structure is removed; a second spacer is formed adjacent to the first spacer and the stack structure; and a source/drain structure is formed adjacent to two sides of the second spacer. | 2017-10-05 |
20170288019 | SEMICONDUCTOR DEVICES WITH GERMANIUM-RICH ACTIVE LAYERS AND DOPED TRANSITION LAYERS - Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped Ge etch suppression layer (e.g., p-type SiGe) disposed there between to suppress etch of the Ge-rich device layer during removal of a sacrificial semiconductor layer richer in Si than the device layer. Rates of dissolution of Ge in wet etchants, such as aqueous hydroxide chemistries, may be dramatically decreased with the introduction of a buried p-type doped semiconductor layer into a semiconductor film stack, improving selectivity of etchant to the Ge-rich device layers. | 2017-10-05 |
20170288020 | LDMOS DEVICE - The disclosed subject matter provides an LDMOS device and fabrication method thereof. In an LDMOS device, a drift region and a body region are formed in a substrate. A first trench is formed in the drift region and in the substrate between the drift region and the body region. The first trench is separated from the drift region by a first shallow trench isolation structure. A gate dielectric layer is formed on a side surface and a bottom surface of the first trench. A gate electrode filling up the first trench is formed on the gate dielectric layer with a top surface above a top surface of the semiconductor substrate. A source region is formed in the body region on one side of the gate electrode and a drain region is formed in the drift region on another side of the gate electrode. | 2017-10-05 |
20170288021 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor layer, having a drain region, a body region, and a source region, a gate electrode, facing the body region via a gate insulating film, a first pillar layer disposed inside the semiconductor layer so as to be continuous to the body region, and a trap level region, disposed inside the semiconductor layer and containing charged particles that form a trap level, and an electric field concentration portion, where an electric field concentrates in an off state in which a channel is not formed in the body region, and the trap level region are disposed at mutually different depth positions in a depth direction of the first pillar layer. | 2017-10-05 |
20170288022 | GROUP III-N NANOWIRE TRANSISTORS - A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a source region electrically coupled with a first end of the channel region, and a drain region electrically coupled with a second end of the channel region. A second group III-N material on the first group III-N material serves as a charge inducing layer, and/or barrier layer on surfaces of nanowire. A gate insulator and/or gate conductor coaxially wraps completely around the nanowire within the channel region. Drain and source contacts may similarly coaxially wrap completely around the drain and source regions. | 2017-10-05 |
20170288023 | COMPOSITE OXIDE SEMICONDUCTOR AND METHOD FOR MANUFACTURING THE SAME - The field-effect mobility and reliability of a transistor including an oxide semiconductor film are improved. A semiconductor layer of a transistor is formed using a composite oxide semiconductor in which a first region and a second region are mixed. The first region includes a plurality of first clusters containing one or more of indium, zinc, and oxygen as a main component. The second region includes a plurality of second clusters containing one or more of indium, an element M (M represents Al, Ga, Y, or Sn), zinc, and oxygen. The first region includes a portion in which the plurality of first clusters are connected to each other. The second region includes a portion in which the plurality of second clusters are connected to each other. | 2017-10-05 |
20170288024 | GRADED BUFFER LAYERS WITH LATTICE MATCHED EPITAXIAL OXIDE INTERLAYERS - A lattice matched epitaxial oxide interlayer is disposed between each semiconductor layer of a graded buffer layer material stack. Each lattice matched epitaxial oxide interlayer inhibits propagation of threading dislocations from one semiconductor layer of the graded buffer layer material stack into an overlying semiconductor layer of the graded buffer layer material stack. This allows for decreasing the thickness of each semiconductor layer within the graded buffer layer material stack. The topmost semiconductor layer of the graded buffer layer material stack, which is a relaxed layer, contains a lower defect density than the other semiconductor layers of the graded buffer layer material stack. | 2017-10-05 |
20170288025 | SILICON CARBIDE EPITAXIAL SUBSTRATE AND METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - The silicon carbide layer has a second main surface. The second main surface has a peripheral region within 5 mm from an outer edge thereof, and a central region surrounded by the peripheral region. The silicon carbide layer has a central surface layer. An average value of a carrier concentration in the central surface layer is not less than 1×10 | 2017-10-05 |
20170288026 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor layer, having an active region, in which a functional element is formed, a first impurity region of a first conductivity type, formed at a surface layer portion of the semiconductor layer, a second impurity region of a second conductivity type, formed at a surface layer portion of the first impurity region and defining the active region, and a well region of the second conductivity type, formed along a periphery of the second impurity region at the surface layer portion of the first impurity region and having an inner side edge portion positioned at the second impurity region side, and an outer side edge portion positioned at an opposite side with respect to the second impurity region and having a second conductivity type impurity concentration lower than a second conductivity type impurity concentration of the inner side edge portion. | 2017-10-05 |
20170288027 | METHOD OF FORMING TRENCH SEMICONDUCTOR DEVICE HAVING MULTIPLE TRENCH DEPTHS - A method of forming a semiconductor includes a providing a termination trench and an active trench within a semiconductor layer. The active trench is configured to be at a shallower depth than the termination trench to provide a trench depth difference. The selected trench depth difference in combination with one or more of the dopant concentration of the semiconductor layer, the thickness of the semiconductor layer, active trench width to termination trench width, and/or dopant profile of the semiconductor layer provide a semiconductor device having improved performance characteristics. | 2017-10-05 |
20170288028 | SELF-ALIGNED CONTACT FOR TRENCH POWER MOSFET - Embodiments of the present disclosure provide a self-aligned contact for a trench power MOSFET device. The device has a layer of nitride provided over the conductive material in the gate trenches and over portions of mesas between every two adjacent contact structures. Alternatively, the device has an oxide layer over the conductive material in the gate trenches and over portions of mesas between every two adjacent contact structures. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 2017-10-05 |
20170288029 | THIN FILM TRANSISTOR, METHOD OF MANUFACTURING THIN FILM TRANSISTOR, AND DISPLAY - A thin film transistor includes a gate electrode, an insulation film disposed on the gate electrode, a semiconductor layer facing the gate electrode with the insulation film in between, and a source-drain wiring layer electrically coupled to the semiconductor layer, and including a first wiring layer and a second wiring layer. The first wiring layer is in contact with the semiconductor layer between the semiconductor layer and the insulation film, and is configured of a transparent electroconductive film. The second wiring layer is overlapped with a portion of the first wiring layer. Another semiconductor layer made of a material same as a material of the semiconductor layer is stacked on the second wiring layer. | 2017-10-05 |
20170288030 | FABRICATION OF VERTICAL FIELD EFFECT TRANSISTOR STRUCTURE WITH CONTROLLED GATE LENGTH - A method of forming a gate structure, including forming one or more vertical fins on a substrate; forming a bottom spacer on the substrate surface adjacent to the one or more vertical fins; forming a gate structure on at least a portion of the sidewalls of the one or more vertical fins; forming a gauge layer on at least a portion of the bottom spacer, wherein the gauge layer covers at least a portion of the gate structure on the sidewalls of the one or more vertical fins; and removing a portion of the gauge layer on the bottom spacer. | 2017-10-05 |