40th week of 2017 patent applcation highlights part 75 |
Patent application number | Title | Published |
20170288031 | SELF ALIGNED CONTACT SCHEME - An embodiment is a method including forming a first gate over a substrate, the first gate having first gate spacers on opposing sidewalls, forming a first hard mask layer over the first gate, forming a second hard mask layer over the first hard mask layer, the second hard mask layer having a different material composition than the first hard mask layer, forming a first dielectric layer adjacent and over the first gate, etching a first opening through the first dielectric layer to expose a portion of the substrate, at least a portion of the second hard mask layer being exposed in the first opening, filling the first opening with a conductive material, and removing the second hard mask layer and the portions of the conductive material and first dielectric layer above the first hard mask layer to form a first conductive contact in the remaining first dielectric layer. | 2017-10-05 |
20170288032 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Provided is a semiconductor device including a gate electrode, source and drain regions, and a spacer. The gate electrode is located over a substrate, and an angle of a base corner of the gate electrode is greater than 90 degrees. The source and drain regions are located in the substrate at sides of the gate electrode. The spacer is located at a sidewall of the gate electrode. | 2017-10-05 |
20170288033 | SHAPED TERMINALS FOR A BIPOLAR JUNCTION TRANSISTOR - Device structure and fabrication methods for a bipolar junction transistor. An emitter layer is formed on a base layer and etched to form an emitter of the device structure. The emitter layer has a concentration of an element that varies as a function of the thickness of the emitter layer. The etch rate of the emitter layer varies as a function of the concentration of the element such that the emitter has a variable width over the thickness of the emitter layer. | 2017-10-05 |
20170288034 | DEVICE STRUCTURE AND MANUFACTURING METHOD USING HDP DEPOSITED SOURCE-BODY IMPLANT BLOCK - This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced. | 2017-10-05 |
20170288035 | PURE BORON FOR SILICIDE CONTACT - A semiconductor device includes a gate disposed over a substrate; a source region and a drain region on opposing sides of the gate; and a pair of trench contacts over and abutting an interfacial layer portion of at least one of the source region and the drain region; wherein the interfacial layer includes boron in an amount in a range from about 5×10 | 2017-10-05 |
20170288036 | PURE BORON FOR SILICIDE CONTACT - A semiconductor device includes a gate disposed over a substrate; a source region and a drain region on opposing sides of the gate; and a pair of trench contacts over and abutting an interfacial layer portion of at least one of the source region and the drain region; wherein the interfacial layer includes boron in an amount in a range from about 5×10 | 2017-10-05 |
20170288037 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FABRICATING THE SAME - A semiconductor device structure is provided. The semiconductor device includes a semiconductor substrate, a first device, and a second device. Each of the first and second devices includes a gate extending in a first direction, source/drain regions respectively formed on opposite first and second sides of the gate, dielectric spacers formed respectively on outer sidewalls of the gate on the first side and the second side, and conductive spacers serving contacts to the source/drain regions and formed respectively on outer sidewalls of the respective gate spacers. A second direction from the source/drain region on the first side to the source/drain region on the second side crosses the first direction. | 2017-10-05 |
20170288038 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a conductive layer on a source side; a first electrode layer provided on the conductive layer; a second electrode layer provided between the conductive layer and the first electrode layer; a semiconductor layer extending through the first electrode in a first direction from the conductive layer to the first electrode layer; a first semiconductor body provided between the conductive layer and the semiconductor layer, the first semiconductor body including first impurities; and a second semiconductor body provided between the conductive layer and the first semiconductor body, the second semiconductor body including second impurities with a higher concentration than a concentration of the first impurities in the first semiconductor body. A diffusion coefficient of the second impurities in the second semiconductor body is smaller than a diffusion coefficient of the second impurities in the first semiconductor body. | 2017-10-05 |
20170288039 | FABRICATION OF VERTICAL FIELD EFFECT TRANSISTOR STRUCTURE WITH CONTROLLED GATE LENGTH - A method of forming a gate structure, including forming one or more vertical fins on a substrate; forming a bottom spacer on the substrate surface adjacent to the one or more vertical fins; forming a gate structure on at least a portion of the sidewalls of the one or more vertical fins; forming a gauge layer on at least a portion of the bottom spacer, wherein the gauge layer covers at least a portion of the gate structure on the sidewalls of the one or more vertical fins; and removing a portion of the gauge layer on the bottom spacer. | 2017-10-05 |
20170288040 | METHOD OF FORMING SIGE CHANNEL FORMATION REGION - A method comprising: forming an SiGe layer on sidewalls of one or more fins of a semiconductor device by a non-selective deposition of amorphous SiGe, the fins being formed of Si or SiGe; depositing a silicon oxide layer over the SiGe layer; and forming an SiGe channel formation region within each fin by performing Ge enrichment to diffuse Ge atoms from the SiGe layer into the one or more fins. | 2017-10-05 |
20170288041 | METHOD FOR FORMING A DOPED REGION IN A FIN USING A VARIABLE THICKNESS SPACER AND THE RESULTING DEVICE - A method includes forming a fin in a semiconductor substrate. An isolation structure is formed adjacent the fin. A first portion of the fin extends above the isolation structure. A gate electrode is formed above the first portion of the fin. A fin spacer is formed on the first portion of the fin. The fin spacer covers less than 50% of a height of the first portion of the fin. An implantation process is performed in the presence of the fin spacer to form a doped region in the first portion of the fin. | 2017-10-05 |
20170288042 | METHOD FOR MANUFACTURING A TRANSISTOR - A method comprises arranging a stack, on a semiconductor substrate, comprising a sacrificial layer and an insulating layer. The insulator layer is at least partially arranged between the semiconductor substrate and the sacrificial layer. A recess is formed within the stack. The recess extends through the stack to the semiconductor substrate so that the recess at least partially overlaps with a surface of the collector region of the semiconductor substrate. The collector region extends from a main surface of the semiconductor substrate into the substrate material. The method further comprises generating a base structure at the collector region and in the recess. The base structure contacts and covers the collector region within the recess of the sacrificial layer. The method further comprises generating an emitter structure at the base structure. The emitter structure contacts and at least partially covers the base structure within the recess of the sacrificial layer. | 2017-10-05 |
20170288043 | POWER SEMICONDUCTOR DEVICE - A method for forming a power semiconductor device is provided. The method includes providing a substrate having a first surface and a second surface; and forming a plurality of trenches in the second surface of the substrate. The method also includes forming a semiconductor pillar in each of the plurality of trenches, wherein the semiconductor pillars and the substrate form a plurality of super junctions of the power semiconductor device for increasing the breakdown voltage of the power semiconductor device and reducing the on-stage voltage of the power semiconductor device; and forming a gate structure on the first surface of the substrate. Further, the method includes forming a plurality of well regions in the first surface of the substrate around the gate structure; and forming a source region in each of the plurality of well regions around the gate structure. | 2017-10-05 |
20170288044 | VERTICAL POWER COMPONENT - A vertical power component includes a doped silicon substrate of a first conductivity type. A local well of a second conductivity type extends from an upper surface of the substrate. A passivation structure coats a peripheral region of the upper surface side of the substrate surrounding the well. This passivation structure includes, on top of and in contact with the peripheral substrate region, a first region made of a first passivation material and a second region made of a second passivation material. The second region generates, in a surface region of the substrate in contact with said second region, a local increase of the concentration of majority carriers in the substrate. | 2017-10-05 |
20170288045 | Multichannel Devices with Improved Performance and Methods of Making the Same - A transistor device is provided that comprises a base structure, and a superlattice structure overlying the base structure and comprising a multichannel ridge having sloping sidewalls. The multichannel ridge comprises a plurality of heterostructures that each form a channel of the multichannel ridge, wherein a parameter of at least one of the heterostructures is varied relative to other heterostructures of the plurality of heterostructures. The transistor device further comprises a three-sided gate contact that wraps around and substantially surrounds the top and sides of the multichannel ridge along at least a portion of its depth. | 2017-10-05 |
20170288046 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A property of a semiconductor device (high electron mobility transistor) is improved. A semiconductor device having a buffer layer, a channel layer, an electron supply layer, a mesa type cap layer, a source electrode, a drain electrode and a gate insulating film covering the cap layer, and a gate electrode formed on the gate insulating film, is configured as follows. The cap layer and the gate electrode are separated from each other by the gate insulating film, and side surfaces of the cap layer, the side surfaces being closer to the drain electrode and the source electrode, have tapered shapes. For example, a taper angle (θ1) of the side surface of the cap layer (mesa portion) is equal to or larger than 120 degrees. By this configuration, a TDDB life can be effectively improved, and variation in an ON-resistance can be effectively suppressed. | 2017-10-05 |
20170288047 | Shallow-Trench Semi-Super-Junction VDMOS Device and Manufacturing Method Therefor - A shallow-trench semi-super-junction VDMOS device and a manufacturing method thereof are disclosed. According to an example of the present invention, the shallow-trench semi-super-junction VDMOS device includes: a substrate of a first conduction type; a first epitaxial layer over the substrate; a second epitaxial layer over the first epitaxial layer; two trench regions on both sides of the second epitaxial layer and extending from an upper surface to a bottom of the second epitaxial layer; a third epitaxial layer of a second conduction type formed in each of the trench regions; a fourth epitaxial layer over the second epitaxial layer; and well regions implanted from both sides of the upper surface of the fourth epitaxial layer and connected with the third epitaxial layers in the two trench regions. The present invention gives consideration to the cost of technical process and the convenience of production. At the same time, due to the existence of the semi-super-junction structure, the forward conduction resistance of the VDMOS device is drastically reduced and the capability of current conduction per unit area is enhanced. | 2017-10-05 |
20170288048 | SILICON CARBIDE (SiC) DEVICE WITH IMPROVED GATE DIELECTRIC SHIELDING - In one general aspect, an apparatus can include a silicon carbide (SiC) device can include a gate dielectric, a first doped region having a first conductivity type, a source, a body region of the first conductivity type, and a second doped region having a second conductivity type. The second doped region can have a first portion and a second portion. The first portion can be disposed between the first doped region and the body region and the second portion can be disposed between the first doped region and the gate dielectric. The first portion of the second doped region can have a width less than a width of the first doped region. | 2017-10-05 |
20170288049 | METHOD FOR FABRICATING FINFET STRUCTURE - A method of forming a semiconductor device includes providing a substrate structure having a semiconductor substrate and a fin structure on the semiconductor substrate. The fin structure includes a semiconductor layer and a hard mask layer on top of the semiconductor layer. The method also includes forming a spacer layer on sidewalls of the fin structure. Next, using the hard mask layer and the spacer layer as a mask, the semiconductor substrate is etched to form recesses on both sides of the fin structure that extend partially to underneath the bottom of the fin structure. The method further includes forming a filler material to fill at least the recesses, thereby forming the first filler layer. The first filler layer may be oxidized to form a porous oxide layer and the remaining portion of the substrate under the fin structures may be oxidized to form an oxide layer. | 2017-10-05 |
20170288050 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR - To improve the breakdown voltage of a semiconductor device. In a terminal region of the semiconductor device, a mesa groove, a recess groove, an electric field relaxation region, and a gradient distributed low concentration p-type layer region are formed. A recess groove is fromed between a device region and the mesa groove so as to surround the device region. A region where a p-type layer is thinned by the recess groove is the electric field relaxation region. The gradient distributed low concentration p-type layer region is formed on the surface of the electric field relaxation region. The average carrier concentration of the entire gradient distributed low concentration p-type layer region is lower than the carrier concentration of the p-type layer. By forming the gradient distributed low concentration p-type layer region, the electric field relaxation region is quickly completely depleted when a reverse voltage is applied, thereby improving the breakdown voltage. | 2017-10-05 |
20170288051 | TRENCH MOSFET SHIELD POLY CONTACT - A recess is formed at a semiconductor layer of a device to define a plurality of mesas. An active trench portion of the recess residing between adjacent mesas. A termination portion of the trench residing between the end of each mesa and a perimeter of the recess. The transverse spacing between the mesas and the lateral spacing between the mesas and an outer perimeter of a recess forming the mesas are substantially the same. A shield structure within the trench extends from the region between the mesas to the region between the ends of the mesas and the outer perimeter of the recess forming the mesas. A contact resides between a shield electrode terminal and the shield portion residing in the trench. | 2017-10-05 |
20170288052 | Multiple Shielding Trench Gate FET - A semiconductor device contains a vertical MOS transistor having a trench gate in trenches extending through a vertical drift region to a drain region. The trenches have field plates under the gate; the field plates are adjacent to the drift region and have a plurality of segments. A dielectric liner in the trenches separating the field plates from the drift region has a thickness great than a gate dielectric layer between the gate and the body. The dielectric liner is thicker on a lower segment of the field plate, at a bottom of the trenches, than an upper segment, immediately under the gate. The trench gate may be electrically isolated from the field plates, or may be connected to the upper segment. The segments of the field plates may be electrically isolated from each other or may be connected to each other in the trenches. | 2017-10-05 |
20170288053 | SEMICONDUCTOR DEVICE - A control electrode GE | 2017-10-05 |
20170288054 | Lateral MOSFET - A method includes forming a first isolation region in a substrate, wherein a top surface of the first isolation region is level with a top surface of the substrate, removing an upper portion of the first isolation region to form a recess, depositing a gate dielectric layer over the first isolation region, forming a gate electrode layer over the gate dielectric layer and patterning the gate electrode layer to form a gate electrode region, wherein a first portion of the gate electrode region is vertically aligned with the first isolation region and a second portion of the gate electrode region is formed over the substrate, and where a top surface of the first portion is lower than a top surface of the second portion. | 2017-10-05 |
20170288055 | Aluminum Nitride Based Silicon-On-Insulator Substrate Structure - A substrate structure includes a polycrystalline substrate, a plurality of thin film layers disposed on the polycrystalline substrate, a bonding layer coupled to at least a portion of the plurality of thin films, and a single crystal silicon layer joined to the bonding layer. | 2017-10-05 |
20170288056 | FABRICATION OF VERTICAL FIN TRANSISTOR WITH MULTIPLE THRESHOLD VOLTAGES - A vertical fin field effect transistor including a doped region in a substrate, wherein the doped region has the same crystal orientation as the substrate, a first portion of a vertical fin on the doped region, wherein the first portion of the vertical fin has the same crystal orientation as the substrate and a first portion width, a second portion of the vertical fin on the first portion of the vertical fin, wherein the second portion of the vertical fin has the same crystal orientation as the first portion of the vertical fin, and the second portion of the vertical fin has a second portion width less than the first portion width, a gate structure on the second portion of the vertical fin, and a source/drain region on the top of the second portion of the vertical fin. | 2017-10-05 |
20170288057 | KITE SHAPED CAVITY FOR EMBEDDING MATERIAL - The present invention is directed to semiconductor processes and devices. More specifically, embodiments of the present invention provide a semiconductor device that comprises a kite-shaped cavity, and the shaped cavity is filled with silicon and germanium material. There are other embodiments as well. | 2017-10-05 |
20170288058 | ELECTROSTATIC DISCHARGE DEVICE - A semiconductor device includes a body and a transistor fabricated into the body. Isolation material at least partially encases the body. Biasing is coupled to the isolation material, wherein the biasing is for changing the electric potential of the isolation material in response to an electrostatic discharge event. | 2017-10-05 |
20170288059 | ENHANCED SUBSTRATE CONTACT FOR MOS TRANSISTOR IN AN SOI SUBSTRATE, IN PARTICULAR AN FDSOI SUBSTRATE - An integrated electronic device includes a semiconductive film above a buried insulating layer that is situated above a supporting substrate. An active zone is delimited within the semiconductive film. A MOS transistor supported within the active zone includes a gate region situated above the active zone. The gate region includes a rectilinear part situated between source and drain regions. The gate region further includes a forked part extending from the rectilinear part. A raised semiconductive region situated above the active zone is positioned at least partly between portions of the forked part. A substrate contact for the transistor is electrically coupled to the raised semiconductive region. | 2017-10-05 |
20170288060 | THIN FILM TRANSISTOR, METHOD FOR MANUFACTURING THE SAME, ARRAY SUBSTRATE AND DISPLAY DEVICE - A TFT is provided. The TFT includes an active layer, and the active layer includes a first active layer and a second active layer. The second active layer is made of the oxide semiconductor material, and the first active layer has conductivity greater than conductivity of the second active layer. | 2017-10-05 |
20170288061 | SEMICONDUCTOR ELEMENT AND PRODUCTION METHOD FOR SAME - A semiconductor element includes a high-resistivity substrate that includes a β-Ga | 2017-10-05 |
20170288062 | SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING SEMICONDUCTOR DEVICE - A semiconductor device includes an oxide semiconductor film, a first insulating film, and a second insulating film. The oxide semiconductor film is made of oxide semiconductor material. The oxide semiconductor film includes a low resistance portion having an electrical resistance lower than another portion. The low resistance portion is separated from the other portion. The first insulating film is formed in an upper layer relative to the oxide semiconductor film. The first insulating film includes a hole at a position overlapping the low resistance portion. The second insulating film is formed in an upper layer relative to the first insulating film. The second insulating film and contains hydrogen. | 2017-10-05 |
20170288063 | SEMICONDUCTOR DEVICE - A highly reliable semiconductor device the yield of which can be prevented from decreasing due to electrostatic discharge damage is provided. A semiconductor device is provided which includes a gate electrode layer, a gate insulating layer over the gate electrode layer, an oxide insulating layer over the gate insulating layer, an oxide semiconductor layer being above and in contact with the oxide insulating layer and overlapping with the gate electrode layer, and a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer. The gate insulating layer includes a silicon film containing nitrogen. The oxide insulating layer contains one or more metal elements selected from the constituent elements of the oxide semiconductor layer. The thickness of the gate insulating layer is larger than that of the oxide insulating layer. | 2017-10-05 |
20170288064 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE - A semiconductor device includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor layer over the first metal oxide layer, a second metal oxide layer over the oxide semiconductor layer, a gate insulating layer over the second metal oxide layer, a second insulating layer over the second metal oxide layer, and a gate electrode layer over the gate insulating layer. The gate insulating layer includes a region in contact with a side surface of the gate electrode layer. The second insulating layer includes a region in contact with the gate insulating layer. The oxide semiconductor layer includes first to third regions. The first region includes a region overlapping with the gate electrode layer. The second region, which is between the first and third regions, includes a region overlapping with the gate insulating layer or the second insulating layer. The second and third regions each include a region containing an element N (N is phosphorus, argon, or xenon). | 2017-10-05 |
20170288065 | Trenched MOS Gate Controlled Rectifier - A trenched MOS gate controlled rectifier has an asymmetric trench structure between the active area of active trenches and the termination area of termination trenches. The asymmetric trench structure has a gate electrode on one side of the trench to turn on and off the channel of the MOS structure effectively and a field plate structure on the other side with field dielectric sufficiently thick in order to sustain the high electric field during the reverse bias condition. | 2017-10-05 |
20170288066 | DIODE STRUCTURES WITH CONTROLLED INJECTION EFFICIENCY FOR FAST SWITCHING - This invention discloses a semiconductor device disposed in a semiconductor substrate. The semiconductor device includes a first semiconductor layer of a first conductivity type on a first major surface. The semiconductor device further includes a second semiconductor layer of a second conductivity type on a second major surface opposite the first major surface. The semiconductor device further includes an injection efficiency controlling buffer layer of a first conductivity type disposed immediately below the second semiconductor layer to control the injection efficiency of the second semiconductor layer. | 2017-10-05 |
20170288067 | OPTICAL SENSOR SHIELD - Techniques for shielding an optical sensor are described. An example of an electronic device includes an optical sensor and a combined light-focusing and electrical-shielding unit disposed over the optical sensor. The light-focusing and electrical-shielding unit has two portions. The first portion gathers light and focuses the light on the electrical sensor. The second portion encloses sides of the first portion and is coated with an electrically conductive material to shield the optical sensor from electromagnetic interference. | 2017-10-05 |
20170288068 | VOLTAGE BREAKDOWN DEVICE FOR SOLAR CELLS - Voltage breakdown devices for solar cells are described. For example, a solar cell includes a semiconductor substrate. A plurality of alternating N-type and P-type semiconductor regions is disposed in or above the substrate. A plurality of conductive contacts is coupled to the plurality of alternating N-type and P-type semiconductor regions. A voltage breakdown device is disposed above the substrate. The voltage breakdown device includes one of the plurality of conductive contacts in electrical contact with one of the N-type semiconductor regions and with one of the P-type semiconductor regions of the plurality of alternating N-type and P-type semiconductor regions disposed in or above the substrate. | 2017-10-05 |
20170288069 | METHOD OF MANUFACTURING SOLAR CELL MODULE - A method of manufacturing a solar cell module includes: placing a light reflection member across a gap between adjacent two solar cells set on a work table; and attaching the light reflection member to respective ends of the adjacent two solar cells, by thermocompression-bonding respective overlap regions of the light reflection member with the adjacent two solar cells using a compression bonding head that includes: a first thermocompression bonding portion and a second thermocompression bonding portion each having a contact surface that comes into contact with the light reflection member; and a non-thermocompression bonding portion interposed between the first thermocompression bonding portion and the second thermocompression bonding portion and not thermocompression-bonding the light reflection member. | 2017-10-05 |
20170288070 | TRI-LAYER SEMICONDUCTOR STACKS FOR PATTERNING FEATURES ON SOLAR CELLS - Tri-layer semiconductor stacks for patterning features on solar cells, and the resulting solar cells, are described herein. In an example, a solar cell includes a substrate. A semiconductor structure is disposed above the substrate. The semiconductor structure includes a P-type semiconductor layer disposed directly on a first semiconductor layer. A third semiconductor layer is disposed directly on the P-type semiconductor layer. An outermost edge of the third semiconductor layer is laterally recessed from an outermost edge of the first semiconductor layer by a width. An outermost edge of the P-type semiconductor layer is sloped from the outermost edge of the third semiconductor layer to the outermost edge of the third semiconductor layer. A conductive contact structure is electrically connected to the semiconductor structure. | 2017-10-05 |
20170288071 | THREE-DIMENSIONAL CONDUCTIVE ELECTRODE FOR SOLAR CELL - A photovoltaic device and method include forming a plurality of pillar structures in a substrate, forming a first electrode layer on the pillar structures and forming a continuous photovoltaic stack including an N-type layer, a P-type layer and an intrinsic layer on the first electrode. A second electrode layer is deposited over the photovoltaic stack such that gaps or fissures occur in the second electrode layer between the pillar structures. The second electrode layer is wet etched to open up the gaps or fissures and reduce the second electrode layer to form a three-dimensional electrode of substantially uniform thickness over the photovoltaic stack. | 2017-10-05 |
20170288072 | THERMOCOMPRESSION BONDING APPROACHES FOR FOIL-BASED METALLIZATION OF NON-METAL SURFACES OF SOLAR CELLS - Thermocompression bonding approaches for foil-based metallization of non-metal surfaces of solar cells, and the resulting solar cells, are described. For example, a solar cell includes a substrate and a plurality of alternating N-type and P-type semiconductor regions disposed in or above the substrate. A plurality of conductive contact structures is electrically connected to the plurality of alternating N-type and P-type semiconductor regions. Each conductive contact structure includes a metal foil portion disposed in direct contact with a corresponding one of the alternating N-type and P-type semiconductor regions. | 2017-10-05 |
20170288073 | PHOTOVOLTAIC DEVICE AND METHODS OF FORMING THE SAME - Methods and devices are described for a photovoltaic device. The photovoltaic device includes a glass substrate, a semiconductor absorber layer formed over the glass substrate, a metal back contact layer formed over the semiconductor absorber layer, and a p-type back contact buffer layer formed from one of MnTe, Cd | 2017-10-05 |
20170288074 | METALLIZATION OF SOLAR CELLS WITH DIFFERENTIATED P-TYPE AND N-TYPE REGION ARCHITECTURES - Methods of fabricating solar cell emitter regions with differentiated P-type and N-type regions architectures, and resulting solar cells, are described. In an example, a back contact solar cell can include a substrate having a light-receiving surface and a back surface. A first polycrystalline silicon emitter region of a first conductivity type is disposed on a first thin dielectric layer disposed on the back surface of the substrate. A second polycrystalline silicon emitter region of a second, different, conductivity type is disposed on a second thin dielectric layer disposed on the back surface of the substrate. A third thin dielectric layer is disposed over an exposed outer portion of the first polycrystalline silicon emitter region and is disposed laterally directly between the first and second polycrystalline silicon emitter regions. A first conductive contact structure is disposed on the first polycrystalline silicon emitter region. A second conductive contact structure is disposed on the second polycrystalline silicon emitter region. Metallization methods, include etching techniques for forming a first and second conductive contact structure are also described. | 2017-10-05 |
20170288075 | METHOD OF PREPARING METAL CHALCOGENIDE NANOPARTICLES AND METHOD OF PRODUCING LIGHT ABSORPTION LAYER THIN FILM BASED THEREON - Disclosed are a single-source precursor for synthesizing metal chalcogenide nanoparticles for producing a light absorption layer of solar cells comprising a Group VI element linked as a ligand to any one metal selected from the group consisting of copper (Cu), zinc (Zn) and tin (Sn), metal chalcogenide nanoparticles produced by heat-treating at least one type of the single-source precursor, a method of preparing the same, a thin film produced using the same and a method of producing the thin film. | 2017-10-05 |
20170288076 | SILICON-BASED QUANTUM DOT DEVICE - A silicon-based quantum dot device ( | 2017-10-05 |
20170288077 | SOLAR CELL MODULE INCLUDING PLURALITY OF SOLAR CELLS - A plurality of solar cells are sealed by an encapsulant between a first protective member and a second protective member. A fixing member fixes, among the plurality of solar cells, a first solar cell and a second solar cell that are adjacent to each other. The fixing member includes a release surface and a non-release surface that are oriented in opposite directions. The non-release surface has disposed thereon a first bonding region and a second bonding region that have adhesive strength, and a non-bonding region different from the first bonding region and the second bonding region. | 2017-10-05 |
20170288078 | INTERCONNECT ASSEMBLY - An interconnect assembly. The interconnect assembly includes a trace that includes a plurality of electrically conductive portions. The plurality of electrically conductive portions is configured both to collect current from a first solar cell and to interconnect electrically to a second solar cell. In addition, the plurality of electrically conductive portions is configured such that solar-cell efficiency is substantially undiminished in an event that any one of the plurality of electrically conductive portions is conductively impaired. | 2017-10-05 |
20170288079 | TWO-STAGE LIGHT CONCENTRATOR - A light concentrator includes a luminescent concentrator and a gain medium. The luminescent concentrator includes a semiconductor material and the semiconductor material absorbs first photons. The first photons have energy greater than or equal to a threshold energy, and the semiconductor material emits second photons through a spontaneous emission process where the second photons have less energy than the first photons. The gain medium is optically coupled to the luminescent concentrator to receive the second photons. The gain medium absorbs the second photons, and in response to absorbing the second photons, the gain medium emits third photons through a stimulated emission process. The third photons have less energy than the second photons. | 2017-10-05 |
20170288080 | Luminescent Electricity-Generating Window for Plant Growth - A window for a greenhouse is provided that is comprised of a sheet of luminescent material [ | 2017-10-05 |
20170288081 | PHOTOVOLTAIC MODULE - A photovoltaic module has a flexible backing substrate, a plurality of photovoltaic cells, and an electrical conduit. The photovoltaic cells are mounted on the backing substrate. Each photovoltaic cell has a metallic article, the metallic article including a plurality of electroformed elements comprising a cell interconnection element integral with a continuous grid having a plurality of first elements intersecting a plurality of second elements. The electroformed elements are interconnected and integral, with the continuous grid in contact with the light-incident surface of the photovoltaic cell. The cell interconnection element extends beyond the light-incident surface and couples the continuous grid to a neighboring photovoltaic cell. The electrical conduit has a flexible strip of electrically conductive material. The electrical conduit electrically couples the cell interconnection element of a first photovoltaic cell in the plurality of photovoltaic cells to a neighboring second photovoltaic cell in the plurality of photovoltaic cells. | 2017-10-05 |
20170288082 | SEMICONDUCTOR STRUCTURE, METHOD FOR THE PRODUCTION THEREOF AND USE THEREOF - The invention relates to a semiconductor structure made of a substrate and a semiconductor layer which are bonded integrally to each other via a thermally and/or chemically cured adhesive. Likewise, the invention relates to a method for the production of such integral bonds. Use in such semiconductor structures, in particular as solar cell or solar cell module. | 2017-10-05 |
20170288083 | METHOD AND APPARATUS FOR A THERMOPHOTOVOLTAIC CELL - The present device is a thermophotovoltaic (TPV) cell adapted to charge the battery of an electronic device efficiently and cost-effectively. This is accomplished by specifically layering N-Type and P-type semiconductors in several layers while also introducing extrinsic doping agents that add to the conductivity of the oxides used for generating energy using ambient thermal energy. As such, electrical energy can effectively be drawn from a single heat reservoir. | 2017-10-05 |
20170288084 | PHOTOVOLTAIC STRUCTURE CLEAVING SYSTEM - A cleaving system and method are described. The system can include a holding apparatus to retain a photovoltaic structure at a center section of a cleaving platform. The system can further include a contact apparatus to make contact with the photovoltaic structure and separate it into a plurality of strips. During operation, the system can activate an actuator to move the contact apparatus against the photovoltaic structure, thereby separating the photovoltaic structure into strips. | 2017-10-05 |
20170288085 | Apparatus For Reduction of Solar Cell LID - Reduction of solar wafer LID by exposure to continuous or intermittent High-Intensity full-spectrum Light Radiation, HILR, by an Enhanced Light Source, ELS, producing 3-10 Sols, optionally in the presence of forming gas or/and heating to within the range of from 100° C.-300° C. HILR is provided by ELS modules for stand-alone bulk/continuous processing, or integrated in wafer processing lines in a High-Intensity Light Zone, HILZ, downstream of a wafer firing furnace. A finger drive wafer transport provides continuous shadowless processing speeds of 200-400 inches/minute in the integrated furnace/HILZ. Wafer dwell time in the peak-firing zone is 1-2 seconds. Wafers are immediately cooled from peak firing temperature of 850° C.-1050° C. in a quench zone ahead of the HILZ-ELS modules. Dwell in the HILZ is from about 10 sec to 5 minutes, preferably 10-180 seconds. Intermittent HILR exposure is produced by electronic control, a mask, rotating slotted plate or moving belt. | 2017-10-05 |
20170288086 | LIGHT EMITTING DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a light-emitting device including the steps of forming a first resin including a phosphor on a light-emitting diode chip mounted on a package body, measuring color coordinates of light emitted by combination of the light-emitting diode chip and the phosphor, correcting the color coordinates by forming a second resin on the first resin, and curing the first resin and the second resin after correcting the color coordinates, in which the first resin is not fully cured before measuring and correcting the color coordinates. | 2017-10-05 |
20170288087 | MICRO-SIZE DEVICES FORMED BY ETCH OF SACRIFICIAL EPITAXIAL LAYERS - Embodiments regard micro-size devices formed by etch of sacrificial epitaxial layers. An embodiment of a method includes forming a plurality of epitaxial layers on a sapphire crystal, wherein the epitaxial layers include a buffer layer on the sapphire crystal, a sacrificial layer above the buffer layer, and one or more device layers above the sacrificial layer; etching to singulate the semiconductor devices, the etching being through the one or more device layers and wholly or partially through the sacrificial layer; electrochemical etching of the sacrificial layer; and lift-off of one or more semiconductor devices from the buffer layer. | 2017-10-05 |
20170288088 | UV LIGHT EMITTING DIODE PACKAGE AND LIGHT EMITTING DIODE MODULE HAVING THE SAME - A UV LED package and an LED module including the same. The UV LED package includes an upper semiconductor layer; a mesa disposed under the upper semiconductor layer, having an inclined side surface, and comprising an active layer and a lower semiconductor layer; a first insulation layer covering the mesa and having an opening exposing the upper semiconductor layer; a first contact layer contacting the upper semiconductor layer through the opening of the first insulation layer; a second contact layer formed between the mesa and the first insulation layer and contacting the lower semiconductor layer; a first electrode pad and a second electrode pad disposed under the first contact layer and electrically connected to the first contact layer and second contact layer, respectively; and a second insulation layer located between the first contact layer and the first and second electrode pads, wherein the active layer emits UV light having a wavelength of 405 nm or less. With this structure, the LED package has high efficiency and high heat dissipation characteristics. | 2017-10-05 |
20170288089 | LIGHT EMITTING DIODES WITH N-POLARITY AND ASSOCIATED METHODS OF MANUFACTURING - Light emitting diodes (“LEDs”) with N-polarity and associated methods of manufacturing are disclosed herein. In one embodiment, a method for forming a light emitting diode on a substrate having a substrate material includes forming a nitrogen-rich environment at least proximate a surface of the substrate without forming a nitrodizing product of the substrate material on the surface of the substrate. The method also includes forming an LED structure with a nitrogen polarity on the surface of the substrate with a nitrogen-rich environment. | 2017-10-05 |
20170288090 | ACTIVE LAYER STRUCTURE, SEMICONDUCTOR LIGHT EMITTING ELEMENT, AND DISPLAY APPARATUS - [Solving Means] A semiconductor light emitting element includes a first conductive layer, a second conductive layer, and an active layer provided between the first conductive layer and the second conductive layer. The first conductive layer has a current constriction structure, a current injection region being constricted in the current constriction structure. The active layer includes a plurality of quantum well layers, a first light emission wavelength being in a wavelength range of an intensity peak of an entire light emission spectrum, the first light emission wavelength corresponding to a light emission recombination level energy gap of a first quantum well layer of the plurality of quantum well layers, the first quantum well layer being provided at a position closest to the current constriction structure. | 2017-10-05 |
20170288091 | METHOD FOR PRODUCING AN OPTOELECTRONIC SEMICONDUCTOR COMPONENT AND OPTOELECTRONIC SEMICONDUCTOR COMPONENT - The invention provides an optoelectronic semiconductor component and a method for producing an optoelectronic semiconductor component ( | 2017-10-05 |
20170288092 | SEMICONDUCTOR STRUCTURE - A nitride semiconductor structure and a semiconductor light emitting device including the same are revealed. The nitride semiconductor structure mainly includes a stress control layer disposed between a light emitting layer and a p-type carrier blocking layer. The p-type carrier blocking layer is made from Al | 2017-10-05 |
20170288093 | LED LIGHT SOURCE MODULE AND DISPLAY DEVICE - An LED light source module includes a light emitting stacked body, and a first through electrode structure and a second through electrode structure passing through a portion of the light emitting stacked body. The light emitting stacked body includes a base insulating layer, light emitting layers sequentially stacked on the base insulating layer, each of the light emitting layers including a first conductivity-type semiconductor layer, a second conductivity-type semiconductor layer, and an active layer disposed between the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer, and an interlayer insulating layer disposed between the light emitting layers. The first through electrode structure is connected to the first conductivity-type semiconductor layer of each of the light emitting layers, and the second through electrode structure is connected to any one or any combination of the second conductivity-type semiconductor layer of each of the light emitting layers. | 2017-10-05 |
20170288094 | OPTOELECTRONIC SEMICONDUCTOR COMPONENT - Disclosed is an optoelectronic semiconductor component ( | 2017-10-05 |
20170288095 | LIGHT-EMITTING DEVICE - A light-emitting device includes a light-emitting element, and a covering layer. The light-emitting element includes a top surface, a bottom surface, a light-emitting stack between the top surface and the bottom surface, and an adhesion enhancing layer surrounding the light-emitting stack. The covering layer covers the light-emitting element and contacts the adhesion enhancing layer. Moreover, the adhesion enhancing layer includes an oxide and a thickness greater than 5 nm and less than 1000 nm. | 2017-10-05 |
20170288096 | LIGHT-EMITTING DEVICE - A light-emitting device includes a substrate including a substrate second upper surface provided between a substrate bottom surface and a substrate first upper surface in a height direction. A light-emitting element to emit ultraviolet light is provided on the substrate first upper surface. A protective element includes a protective element upper surface provided between the substrate first upper surface and the substrate second upper surface in the height direction. A frame is bonded to the substrate first upper surface via adhesive members to surround the light-emitting element. The frame includes a frame lower surface opposite to the substrate first upper surface and the substrate second upper surface in the height direction to provide a gap between the substrate first upper surface and the frame lower surface. A space in which the light-emitting element is provided communicates with an outside of the light-emitting device via the gap. | 2017-10-05 |
20170288097 | Display Device And Display Module - A display device and a display module. The display module includes: a blue LED chip, a yellow phosphor layer and a colour filter. A peak wavelength of a blue light emitted from the blue LED chip is in a range of 460±5 nm. The blue LED chip excites the yellow phosphor layer to emit a white light. The colour filter is disposed outside the yellow phosphor layer, and the white light emitted irradiates on colour filter. Through right shifting the peak wavelength of the blue band emitted from the blue LED chip to about 460 nm to realize the low blue energy and decrease the radiation. The transmittance of blue light of the colour filter is less than 7%, the transmission peak wavelength of blue light is in a range of 440-450 nm. The display module can decrease the energy of the blue band and ensure the display effect. | 2017-10-05 |
20170288098 | ILLUMINATION DEVICE - Embodiments of the invention include a semiconductor light emitting device for emitting a first light at a first wavelength and a wavelength conversion medium arranged to convert at least part of the first light into a second light at a second wavelength. The wavelength conversion medium is disposed between a periodic antenna array and the semiconductor light emitting device. The periodic antenna array includes a plurality of antennas. The periodic antenna array supports surface lattice resonances arising from diffractive coupling of localized surface plasmon resonances in at least one of the antennas. | 2017-10-05 |
20170288099 | LED PACKAGE STRUCTURE AND LED LIGHT-EMITTING DEVICE - The present disclosure provides a LED package structure and a LED light-emitting device. The LED package structure comprises a LED chip and a wavelength converting layer covering the LED chip. The wavelength converting layer contains red phosphor, which has lower amount in edge portion than in center portion. It is possible to avoid direct or indirect excitation for generating red light in edge portion of the LED chip by adjusting the amount of red phosphor in edge portion to be lower, so that the color temperature in edge portion may be adjusted toward to high color temperature, and thus the phenomenon of yellow halo may be alleviated. | 2017-10-05 |
20170288100 | PACKAGE METHOD AND PACKAGE - A package method includes steps of providing a light emitting module, a mold and a molding compound, wherein the light emitting module includes a substrate and at least one light emitting unit disposed on the substrate, the mold has at least one recess, and a side wall of the recess is parallel to a side surface of the light emitting unit; filling the recess with the molding compound; placing the substrate on the mold reversely, so that the light emitting unit is immersed into the recess and the molding compound directly encapsulates the light emitting unit; and heating and pressing the substrate and the mold, so as to solidify the molding compound. | 2017-10-05 |
20170288101 | LED EMISSION SOURCE FOR SEQUENTIAL DRIVERS - An LED emission source is described herein. While the LED emission source can include any suitable component, in some implementations it includes a substrate that includes an insulating heat conducting material. In some cases, the emission source further includes two or more LED crystal groups, multiple electrical contacts for a driver connection, with the electrical contacts being disposed at a front face of the substrate, and a metal heat radiator that includes a plate having a surface that includes a dielectric layer, wherein the dielectric layer is located on a back side of the metal heat radiator and is configured to provide heat exchange with the substrate, and wherein a number of the electrical contacts is one unit more than a number of the LED crystal groups. Other implementations are described. | 2017-10-05 |
20170288102 | THROUGH BACKPLANE LASER IRRADIATION FOR DIE TRANSFER - Light emitting devices can be disposed on the front side of a transparent backplane. A laser beam can be irradiated through the transparent backplane and onto a component located on the front side of the transparent backplane. In one embodiment, the component may be a solder material portion that is reflowed to bond the light emitting devices to the transparent backplane. In another embodiment, the component may be a solder material bonded to a defective bonded light emitting device. In this case, the laser irradiation can reflow the solder material to dissociate the defective bonded light emitting device from the transparent backplane. In yet another embodiment, the component may be a device component that is electrically modified by the laser irradiation. | 2017-10-05 |
20170288103 | LEAD FRAME, PACKAGE, AND LIGHT-EMITTING DEVICE, AND METHODS FOR MANUFACTURING THE SAME - A lead frame includes an electrode, a hanger lead, and an outer frame and is formed integrally with a supporting member supporting the electrode, so that a package having a depression in which a light-emitting element will be mounted is formed. The depression is open on the upper side, its side walls are mainly constituted of the supporting member, and at least a part of its bottom surface includes the electrode. The electrode is disposed in a supporting member forming region. The hanger lead extends from the outer frame to reach the supporting member forming region. A chamfered surface is formed on at least a part of an upper side corner of an end of the hanger lead. | 2017-10-05 |
20170288104 | LIGHT EMITTING DEVICE - A light emitting device includes one or more light emitting elements; a first lead on which the one or more light emitting elements are disposed; a second lead electrically connected to the one or more light emitting elements; a resin member supporting the first lead and the second lead, and including one or more projected portions; and a resin frame surrounding the light emitting elements, and covering at least a portion of each of the projected portions. | 2017-10-05 |
20170288105 | METHOD OF MANUFACTURING LIGHT EMITTING ELEMENT MOUNTING BASE MEMBER, METHOD OF MANUFACTURING LIGHT EMITTING DEVICE USING THE LIGHT EMITTING ELEMENT MOUNTING BASE MEMBER, LIGHT EMITTING ELEMENT MOUNTING BASE MEMBER, AND LIGHT EMITTING DEVICE USING THE LIGHT EMITTING ELEMENT MOUNTING BASE MEMBER - A method of manufacturing a light emitting element mounting base member includes: arranging a plurality of core members each including an electrical conductor core and a light-reflecting insulating member provided on a surface of the electrical conductor core; cutting the arranged core members to form a base member preparatory body including at least one cut surface on which at least one of the electrical conductor cores and the insulating members are exposed; and insert molding by placing the base member preparatory body in a set of mold, and injecting a light blocking resin composition into the set of mold such that at least one of the electrical conductor cores or at least one metal film formed on at least one of the electrical conductor cores are exposed on at least one outer surface of the light emitting element mounting base member. | 2017-10-05 |
20170288106 | METHOD OF MANUFACTURING LIGHT EMITTING ELEMENT MOUNTING BASE MEMBER, METHOD OF MANUFACTURING LIGHT EMITTING DEVICE USING THE LIGHT EMITTING ELEMENT MOUNTING BASE MEMBER, LIGHT EMITTING ELEMENT MOUNTING BASE MEMBER, AND LIGHT EMITTING DEVICE USING THE LIGHT EMITTING ELEMENT MOUNTING BASE MEMBER - A method of manufacturing a light emitting element mounting base member includes: arranging a plurality of core members each including an electrical conductor core and a light-reflecting insulating member provided on a surface of the electrical conductor core; integrally holding the core members with a light blocking resin; and partially removing the insulating members such that at least one surface of the electrical conductor cores is exposed from the light blocking resin. | 2017-10-05 |
20170288107 | METHOD OF MANUFACTURING LIGHT EMITTING ELEMENT MOUNTING BASE MEMBER, METHOD OF MANUFACTURING LIGHT EMITTING DEVICE USING THE LIGHT EMITTING ELEMENT MOUNTING BASE MEMBER, LIGHT EMITTING ELEMENT MOUNTING BASE MEMBER, AND LIGHT EMITTING DEVICE USING THE LIGHT EMITTING ELEMENT MOUNTING BASE MEMBER - A method of manufacturing a light emitting element mounting base member includes: providing a first insulating member in a plate shaped having at least one recess portion or at least one through-hole; disposing in the recess portion or in the through-hole a light blocking resin and a plurality of core members each equipped with a second insulating member having light reflectivity on each surface of a plurality of electrical conductor cores; and exposing at least one of the surface of the electrical conductor cores from the second insulating members by removing each part of at least one of the second insulating members. | 2017-10-05 |
20170288108 | LIGHT-EMITTING DIODE DEVICE - An optoelectronic device includes a printed circuit board, and a light source arranged on a surface of the printed circuit board, said light source comprising at least one luminous face formed by at least one light-emitting diode wherein the light-emitting diode is electrically connected to the printed circuit board, wherein the light-emitting diode is at least partly enclosed by molding by a potting compound. | 2017-10-05 |
20170288109 | LIGHT EMITTING DEVICE PACKAGE - A packaged light emitting device die | 2017-10-05 |
20170288110 | HIGH-VOLTAGE SOLID-STATE TRANSDUCERS AND ASSOCIATED SYSTEMS AND METHODS - High-voltage solid-state transducer (SST) devices and associated systems and methods are disclosed herein. An SST device in accordance with a particular embodiment of the present technology includes a carrier substrate, a first terminal, a second terminal and a plurality of SST dies connected in series between the first and second terminals. The individual SST dies can include a transducer structure having a p-n junction, a first contact and a second contact. The transducer structure forms a boundary between a first region and a second region with the carrier substrate being in the first region. The first and second terminals can be configured to receive an output voltage and each SST die can have a forward junction voltage less than the output voltage. | 2017-10-05 |
20170288111 | LIGHT EMITTING DEVICE PACKAGE AND LIGHT UNIT INCLUDING THE SAME - Disclosed are a light emitting device package. The light emitting device package includes a body having recess; a first lead frame including a first and second portions on a first region of the body; a second lead frame including a third and fourth portions on a second region of the body; a third lead frame between the first and second lead frame. The body has a length of the first direction greater than a width of the second direction, wherein the second portion of the first lead frame extends toward the second lead frame and has a small width, and wherein the fourth portion of the second lead frame extends toward the first lead frame. A first light emitting device is disposed on the first portion of the first lead frame and a second light emitting device is disposed on the third portion of the second lead frame. | 2017-10-05 |
20170288112 | Fabrication of Stable Electrode/Diffusion Barrier Layers for Thermoelectric Filled Skutterudite Devices - Disclosed are methods for the manufacture of n-type and p-type filled skutterudite thermoelectric legs of an electrical contact. A first material of CoSi | 2017-10-05 |
20170288113 | Metallic Junction Thermoelectric Generator - A metal junction thermoelectric device includes at least one thermoelectric element. The thermoelectric element has first and second opposite sides, and a first conductor made from a first metal, and a second conductor made from a second metal. The first and second conductors are electrically interconnected in series, and the first and second conductors are arranged to conduct heat in parallel between the first and second sides. The first metal has a first occupancy state, and the second metal has a second occupancy state that is lower than the first occupancy state. A temperature difference between the first and second sides of the thermoelectric element causes a charge potential due to the difference in occupancy states of the first and second metals. The charge potential generates electrical power. | 2017-10-05 |
20170288114 | THERMOELECTRIC POLYMER COMPOSITES - An embodiment of the present disclosure is directed to a thermoelectric polymer composite. The composite comprises: at least one polymer selected from semiconducting polymers and conducting polymers; and at least one particle inclusion having one or more dimensions of 1 millimeter or less and at least one dimension of 10 nanometer or more. A sufficient amount of the particle inclusion is distributed within the polymer so that the power factor of the composite is greater that the power factor of either the polymer or the particle inclusion separately. | 2017-10-05 |
20170288115 | THERMOELECTRIC GENERATING SYSTEM AND VEHICLE EXHAUST MANIFOLD HAVING THE SAME - A thermoelectric generating system may include a base substrate configured to be installed at a side of a vehicle exhaust line part; and at least one thermoelectric module configured to be installed on a top surface of the base substrate, in which a side of the exhaust line part is provided with an opening communicating with an internal space of the exhaust line part, the base substrate is installed to seal the opening of the exhaust line part, and the base substrate is made of a thermal conductive material and a surface of the base substrate is formed with an insulating layer. | 2017-10-05 |
20170288116 | Stress Relaxation Structure and Thermoelectric Conversion Module - To provide a stress relaxation structure that can achieve both high thermal conductivity and high thermal stress relaxation ability and has excellent vibration durability, and a thermoelectric conversion module having such a stress relaxation structure. The stress relaxation structure includes a rolled-up body having a first thermal conductor and a second thermal conductor that are alternately rolled up. The first thermal conductor is metal foil, and the second thermal conductor is porous metal foil. | 2017-10-05 |
20170288117 | THERMOELECTRIC MODULE AND METHOD FOR MANUFACTURING THE SAME - A thermoelectric module may include a plurality of P-type thermoelectric elements formed of an organic material, a plurality of N-type thermoelectric elements disposed to be parallel between the plurality of P-type thermoelectric elements and formed of a metal, a first electrode part configured to connect an upper end of each of the plurality of N-type thermoelectric elements and an upper end of each of the plurality of P-type thermoelectric elements, and a second electrode part configured to connect a lower end of each of the N-type thermoelectric elements and a lower end of each of the plurality of P-type thermoelectric elements, wherein the first electrode part, the second electrode part, and the plurality of N-type thermoelectric elements are formed of a metal. | 2017-10-05 |
20170288118 | THERMAL DEVICE FOR SOLID AND LIQUID PRODUCTS - The present work depicts a thermal device for solid and liquid products consisting of a container with an external surface with one or more thermoelectric plates ( | 2017-10-05 |
20170288119 | Circuit Arrangement for Charging and Discharging a Piezo Actuator - The disclosure relates to a circuit arrangement that includes a first DC-DC converter that is connected on the output side to a capacitor. A first terminal of the capacitor is a supply voltage terminal and a second terminal of the capacitor is a reference potential terminal. The circuit arrangement also includes a second DC-DC converter, which is connected on the input side with the capacitor and on the output side to a first terminal of a piezo actuator. The second terminal of the piezo actuator is connected to the first terminal of the capacitor. | 2017-10-05 |
20170288120 | Control Apparatus And Fluid Feeder Control Method - A control apparatus controls driving of an oil feeding unit. The oil feeding unit includes a piezoelectric body that deforms in response to a voltage applied thereto, and a reservoir to store lubricating oil. The capacity of the reservoir changes in accordance with deformation of the piezoelectric body so as to discharge lubricating oil from the oil feeding unit. The control apparatus includes N driving circuits | 2017-10-05 |
20170288121 | ACOUSTIC RESONATOR INCLUDING COMPOSITE POLARITY PIEZOELECTRIC LAYER HAVING OPPOSITE POLARITIES - A bulk acoustic wave (BAW) resonator device includes a bottom electrode disposed over a substrate and an acoustic reflector, a seed layer formed of a dielectric material disposed over the bottom electrode, a split piezoelectric layer disposed on the seed layer, and a top electrode disposed over the split piezoelectric layer. The split piezoelectric layer includes a first portion having a positive polarity due to the seed layer, a second portion having a negative polarity that is substantially opposite to the positive polarity of the first portion, and a metal interposer between the first portion and the second portion. The first portion of the piezoelectric layer has a first thickness and the second portion of the piezoelectric layer has a second thickness that is not equal to the first thickness, thereby lowering a coupling coefficient kt | 2017-10-05 |
20170288122 | BAW RESONATOR HAVING THIN SEED LAYER - A bulk acoustic wave (BAW) resonator comprises: a seed layer disposed over a substrate; a first electrode disposed over the seed layer; and a second electrode disposed over a piezoelectric layer. The seed layer has a thickness in the range of approximately 30 Å to approximately 150 Å. | 2017-10-05 |
20170288123 | PIEZOELECTRIC DEVICE AND METHOD FOR MANUFACTURING THE SAME - A lead-out wiring, which is connected to a comb-shaped electrode formed on a principal surface of a piezoelectric substrate and is disposed to extend to an outer edge of the piezoelectric substrate an outer surrounding wall layer, which is arranged surrounding an outer periphery of the piezoelectric substrate including the lead-out wiring and forms a hollow portion that serves as an operation space for the comb-shaped electrode, and a top board, which bridges the outer surrounding wall layer to seal the hollow portion, are included. | 2017-10-05 |
20170288124 | STACKED PIEZOELECTRIC CERAMIC ELEMENT - The present invention relates to a stacked piezoelectric ceramic element and can provide a stacked piezoelectric ceramic element produced by stacking two or more ceramic green sheets, the stacked piezoelectric ceramic element having a structure in which a ceramic porous or defective part constituting the stacked piezoelectric ceramic element is impregnated with an organic resin, thereby improving waterproof performance capable of preventing the deterioration of insulation resistance in a highly humid environment. | 2017-10-05 |
20170288125 | MEMS Heater or Emitter Structure for Fast Heating and Cooling Cycles - According to various embodiments, a MEMS device includes a substrate, an electrically movable heating element having a first node coupled to a first terminal of a first voltage source and the second node coupled to a reference voltage source, a first anchor anchoring the first node and a second anchor anchoring the second node of the electrically movable heating element to the substrate, and a cavity between the first anchor and the second anchor and between the electrically movable heating element and the substrate. | 2017-10-05 |
20170288126 | PIEZOELECTRIC ELEMENT - The piezoelectric element comprises a piezoelectric body extending in a lateral direction and a first and second electrodes that are provided on the piezoelectric body. The piezoelectric body has an active portion sandwiched between the first and second electrodes in a thickness direction that is vertical to the lateral direction, and an inactive portion connected to the active portion in the lateral direction. The first electrode has an active electrode portion disposed on the active portion. The active electrode portion includes an interface region that is adjacent to the interface of the active portion and the inactive portion in the lateral direction, and an inner region that is separated from the interface of the active portion and the inactive portion in the lateral direction. The cross sectional surface area per unit length of the interface region in the cross section of the active electrode portion is greater than the cross sectional area per unit length of the inner region. | 2017-10-05 |
20170288127 | PIEZOELECTRIC CERAMIC SPUTTERING TARGET, LEAD-FREE PIEZOELECTRIC THIN FILM AND PIEZOELECTRIC THIN FILM ELEMENT USING THE SAME - A piezoelectric ceramic sputtering target containing a perovskite type oxide represented by chemical formula (I) of ABO | 2017-10-05 |
20170288128 | PIEZOELECTRIC CERAMIC SPUTTERING TARGET, LEAD-FREE PIEZOELECTRIC THIN FILM AND PIEZOELECTRIC THIN FILM ELEMENT USING THE SAME - A piezoelectric ceramic sputtering target containing a perovskite type oxide represented by chemical formula (I) of ABO | 2017-10-05 |
20170288129 | PIEZOELECTRIC ELEMENT - A piezoelectric element includes a piezoelectric body having a main phase configured by lead zirconate titanate and a heterogenous phase configured by a different component to lead zirconate titanate, and a pair of electrodes provided on the piezoelectric body. The piezoelectric body has a surface region within 10 μm of a surface, and an inner region more than 10 μm from the surface. A surface area coverage of the heterogenous phase in a cross section of the surface region is at least 0.75% greater than a surface area coverage of the heterogenous phase in a cross section of the inner region. | 2017-10-05 |
20170288130 | SEMICONDUCTOR DEVICE INCLUDING AN ENCAPSULATION MATERIAL DEFINING A THROUGH-HOLE - A semiconductor device includes a substrate, a semiconductor die attached to the substrate, and an encapsulation material. The semiconductor die includes a sensing element. The encapsulation material encapsulates the semiconductor die and a portion of the substrate. The encapsulation material defines a through-hole to receive a conductive element. The sensing element may include a magnetic field sensor to sense a magnetic field generated by the conductive element. | 2017-10-05 |