40th week of 2017 patent applcation highlights part 81 |
Patent application number | Title | Published |
20170288631 | ACOUSTIC WAVE DEVICE - In order to pass a signal having a wide pass bandwidth with respect to a center frequency of a pass band, a surface acoustic wave device includes a first surface acoustic wave element provided with a first pass band; and a second surface acoustic wave element having a second pass band in a high frequency band compared with the first pass band of the first surface acoustic wave element, in which the first surface acoustic wave element and the second surface acoustic wave element have a common input terminal and a common output terminal, and a frequency of a high frequency side of the first pass band of the first surface acoustic wave element is partially overlapped with a frequency of a low frequency side of the second pass band of the second surface acoustic wave element. | 2017-10-05 |
20170288632 | VARIABLE FILTER CIRCUIT, RF FRONT END CIRCUIT AND COMMUNICATION DEVICE - Provided is a variable filter circuit that can control the bandwidth and center frequency of a pass band, can realize steep attenuation characteristics in bands close to the pass band, and enables the total number of variable reactance units to be reduced. A variable filter circuit includes an inductor (Ls | 2017-10-05 |
20170288633 | HIGH PASS FILTER - A high pass filter includes a first LC series resonator including a first end connected to a signal path, and a second end connected to at least one ground terminal, a second LC series resonator including a third end electrically connected to the signal path, and a fourth end connected to the at least one ground terminal, and a third capacitor between a first portion extending from a first capacitor to a first inductor and a second portion extending from a second capacitor to a second inductor. | 2017-10-05 |
20170288634 | NONVOLATILE MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME AND METHOD OF OPERATING THE SAME - A nonvolatile memory device includes a first memory structure. The first memory structure includes first through N-th memory dies that may be connected to an external memory controller via a first channel. N is a natural number equal to or greater than two. At least one of the first through N-th memory dies is configured to be used as a first representative die that performs an on-die termination (ODT) operation while a data write operation is performed for one of the first through N-th memory dies. | 2017-10-05 |
20170288635 | PIEZOELECTRIC PACKAGE-INTEGRATED CRYSTAL DEVICES - Embodiments of the invention include a piezoelectric resonator which includes an input transducer having a first piezoelectric material, a vibrating structure coupled to the input transducer, and an output transducer coupled to the vibrating structure. In one example, the vibrating structure is positioned above a cavity of an organic substrate. The output transducer includes a second piezoelectric material. In operation the input transducer causes an input electrical signal to be converted into mechanical vibrations which propagate across the vibrating structure to the output transducer. | 2017-10-05 |
20170288636 | TEMPERATURE COMPENSATED ACOUSTIC RESONATOR DEVICE HAVING THIN SEED INTERLAYER - An acoustic resonator device includes a composite first electrode disposed over a substrate; a piezoelectric layer disposed on the composite first electrode, the piezoelectric layer including a piezoelectric material doped with scandium for improving piezoelectric properties of the piezoelectric layer; and a second electrode disposed on the piezoelectric layer. The composite first electrode includes a base electrode layer disposed over the substrate; a temperature compensation layer disposed on the base electrode layer; a seed interlayer disposed on the temperature compensation layer, the seed interlayer having a thickness between about 5 Å and about 150 Å; and a conductive interposer layer disposed on at least the seed interlayer, at least a portion of the conductive interposer layer contacting the base electrode layer. The piezoelectric layer has a negative temperature coefficient and the temperature compensation layer has a positive temperature coefficient that at least partially offsets the negative temperature coefficient of the piezoelectric layer. | 2017-10-05 |
20170288637 | PIEZOELECTRIC VIBRATION COMPONENT AND METHOD FOR MANUFACTURING THE SAME - A piezoelectric vibration component that includes a substrate having a principal surface and a side face, a piezoelectric vibrator, a lid, and an adhesive layer that hermetically seals the piezoelectric vibrator in a space between the lid and the principal surface. The adhesive layer extends from the principal surface to at least a portion of the side face of the substrate. | 2017-10-05 |
20170288638 | COLLECTIVE PROCESS FOR ULTRASOUND TRANSDUCERS - The present disclosure relates to the bulk manufacture of transducer arrays, including arrays having at least one 3D printed (or otherwise additive manufactured) acoustic matching layers. In certain implementations, the manufactured transducers include a composite-piezoelectric transducer on a de-matching layer. In one implementation, by producing multiple arrays at once on a common carrier, and by using direct-deposit additive processes for the matching layers, the described processes greatly reduce the number of parts and the number of manual operations. | 2017-10-05 |
20170288639 | PIEZOELECTRIC PACKAGE-INTEGRATED DELAY LINES - Embodiments of the invention include a waveguide structure that includes a first piezoelectric transducer that is positioned in proximity to a first end of a cavity of an organic substrate. The first piezoelectric transducer receives an input electrical signal and generates an acoustic wave to be transmitted with a transmission medium. A second piezoelectric transducer is positioned in proximity to a second end of the cavity. The second piezoelectric transducer receives the acoustic wave from the transmission medium and generates an output electrical signal. | 2017-10-05 |
20170288640 | DELAY COMPENSATION APPARATUS - A delay compensation apparatus is provided, where a surface acoustic wave component is used as a main delay component for delay compensation. A size of the surface acoustic wave component is relatively small. Therefore, the delay compensation apparatus provided in embodiments of the present invention features a relatively small size and a relatively high device integration level. | 2017-10-05 |
20170288641 | BAW FILTER AND METHOD FOR MANUFACTURING THE SAME - A bulk acoustic wave (BAW) filter includes: a substrate including a first mounting region and a second mounting region which are spaced apart from each other; a first fixing member disposed adjacent to the first mounting region; a second fixing member disposed adjacent to the second mounting region; a Tx filter mounted on the first mounting region and fixed by the first fixing member; and an Rx filter mounted on the second mounting region and fixed by the second fixing member. | 2017-10-05 |
20170288642 | PIEZOELECTRIC PACKAGE-INTEGRATED CONTOUR MODE FILTER DEVICES - Embodiments of the invention include a filtering device that includes a first electrode, a piezoelectric material in contact with the first electrode, and a second electrode in contact with the piezoelectric material. The piezoelectric filtering device expands and contracts laterally in a plane of an organic substrate in response to application of an electrical signal between the first and second electrodes. | 2017-10-05 |
20170288643 | DISPLACEMENT CONVERSION MECHANISM AND TUNABLE FILTER DEVICE - A displacement conversion mechanism of an embodiment is a displacement conversion mechanism which is provided with a base, a displacement element which is in contact with the base and is displaced in a first direction, a first displacement portion which is in contact with the displacement element and can be displaced in the first direction, a second displacement portion which connects to an end of the first displacement portion at a first connection portion, and connects to the base at a second connection portion, and a third displacement portion which connects to the other end of the first displacement portion, connects to an end portion of the second displacement portion at a fourth connection portion, and can be displaced in a second direction intersecting with the first direction. | 2017-10-05 |
20170288644 | BAW DEVICES HAVING TOP ELECTRODE LEADS WITH REDUCED REFLECTANCE - The present disclosure relates to a Wafer-level-packaged Bulk Acoustic Wave (BAW) device, which includes a bottom electrode, a top electrode, a top electrode lead, a piezoelectric layer sandwiched between the bottom and the top electrodes, an enclosure, and an anti-reflective layer (ARL). Herein, an active region for a resonator is formed where the bottom electrode and the top electrode overlap. The top electrode lead is over the piezoelectric layer and extending from the top electrode. The enclosure includes a cap and an outer wall that extends from the cap toward the piezoelectric layer to form a cavity. The top electrode resides in the cavity and a first portion of the outer wall resides over the top electrode lead. The ARL, with a reflectance less than 40% R, is between the first portion of the outer wall and the top electrode lead. | 2017-10-05 |
20170288645 | ACOUSTIC WAVE DEVICE AND METHOD FOR MANUFACTURING THE SAME - An acoustic wave device includes: a substrate; an acoustic wave generating part disposed on a surface of the substrate; a ground pad disposed on the surface of the substrate; a support part spaced apart from the acoustic wave generating part on the surface of the substrate; a shielding member disposed on the support part, and spaced apart from the acoustic wave generating part; and a ground terminal disposed on the ground pad, wherein the ground pad and the shielding member are electrically connected to each other through the ground terminal. | 2017-10-05 |
20170288646 | HIGH-FREQUENCY SWITCH MODULE - A high-frequency switch module includes a switch element, a filter element, an inductor, and first and second transmission conductors. The switch element includes a common terminal and first and second selected terminals selectively connected to the common terminal. The first transmission conductor connects the first selected terminal and a SAW filter of the filter element. The second transmission conductor connects the second selected terminal and a SAW filter of the filter element. The inductor is connected between the first and second transmission conductors. A separation distance between at least a portion of the first transmission conductor and a portion of the second transmission conductor is shorter than a separation distance between a land conductor of the first selected terminal and a land conductor of the second selected terminal, and the transmission conductors are capacitively coupled. | 2017-10-05 |
20170288647 | EMBEDDED BUFFER CIRCUIT COMPENSATION SCHEME FOR INTEGRATED CIRCUITS - Some embodiments include apparatus and methods using a package substrate and a die coupled to the package substrate. The package substrate includes conductive contacts, conductive paths coupled to the conductive contacts, and a resistor embedded in the package substrate. The die includes buffer circuits and a calibration module coupled to the buffer circuits and the resistor. The buffer circuits include output nodes coupled to the conductive contacts through the conductive paths. The calibration module is configured to perform a calibration operation to adjust resistances of the buffer circuits based on a value of a voltage at a terminal of the resistor during the calibration operation. | 2017-10-05 |
20170288648 | Pulse-Width Modulation Voltage Identification Interface - Systems, methods, and devices for voltage identification using a pulse-width modulation signal are provided. Such an integrated circuit device may include an input/output (I/O) interface and voltage identification (VID) circuitry. The VID circuitry may be coupled to the input/output interface. The voltage identification circuitry may generate a voltage identification signal that is output on the input/output interface. The voltage identification signal may include a pulsed signal having a particular duty cycle that corresponds to a specified voltage level to enable a voltage regulator that receives the voltage identification signal to provide an input voltage to the integrated circuit device at the specified voltage level. | 2017-10-05 |
20170288649 | POWER MANAGERS FOR AN INTEGRATED CIRCUIT - Systems and methods manage power in an integrated circuit using power islands. The integrated circuit includes a plurality of power islands where power consumption is independently controlled within each of the power islands. A power manager determines a target power level for one of the power islands. The power manager then determines an action to change a consumption power level of the one of the power islands to the target power level. The power manager performs the action to change the consumption power level of the one of the power islands to the target power level. | 2017-10-05 |
20170288650 | TANK CIRCUIT AND FREQUENCY HOPPING FOR ISOLATORS - Embodiments of the present disclosure may provide a circuit comprising a tank circuit. The tank circuit may include an inductor having a pair of terminals, a first pair of transistors, and a first pair of capacitors. Each transistor may be coupled between a respective terminal of the inductor and a reference voltage along a source-to-drain path of the transistor. Each capacitor may be provided in a signal path between an inductor terminal coupled to a respective first transistor in the first pair and a gate of a second transistor in the first pair. | 2017-10-05 |
20170288651 | HIGH STABLE OSCILLATOR FOR VARIOUS OPERATING MODE - A frequency stable oscillator with compensation circuit, the device includes a ring oscillator circuit having S number of stages, a current generator circuit configured to generate a first current, a replica circuit having an inverter with output connected to input, configured to generate a first voltage upon dumping a second current onto the replica circuit, a first operational transconductance amplifier (OTA) with an input as the first voltage, configured to generate a third current and a current mirror circuit configured to generate a fourth current by adding the first current and the third current in a particular ratio M:N, wherein the inverter of the replica circuit is equivalent to a single stage of the ring oscillator circuit and wherein the fourth current is the total current for the ring oscillator circuit and is as close as possible to S times the second current. | 2017-10-05 |
20170288652 | Interference-Immunized Multiplexer - A multiplexer comprises: an output circuit comprising a multiplexer output; and a first buffer coupled to the output circuit and comprising: a first selection input configured to receive a first selection signal; a first logical input configured to receive a first logical input signal; and a first ground; wherein the multiplexer is configured to: couple the first logical input to the multiplexer output when the first selection signal is a first value; and couple the first logical input to the first ground when the first selection signal is a second value. A method comprises: receiving a selection signal and a first logical input signal; coupling a first logical input to a multiplexer output when the selection signal is a first value; and coupling the first logical input to a ground when the selection signal is a second value. | 2017-10-05 |
20170288653 | SEMICONDUCTOR DEVICE - There is a problem in related-art semiconductor devices that the chip size of a semiconductor device having an active Miller clamp function cannot be reduced. According to one embodiment, a semiconductor device is configured to, when a power device is turned on or off, monitor a gate voltage Vg of the power device, set a predetermined range within a transition range, the transition range being a range within which the gate voltage Vg changes, change, when the gate voltage Vg is within the predetermined range, the gate voltage Vg of the power device by using a predetermined number of constant-current circuits, and change, when the gate voltage Vg is outside the predetermined range, the gate voltage Vg by using a larger number of constant-current circuits than the number of constant-current circuits that are used when the gate voltage Vg is within the predetermined range. | 2017-10-05 |
20170288654 | Half Bridge Circuit, Method of Operating a Half Bridge Circuit and a Half Bridge Circuit Package - A half bridge circuit includes an input connection configured to supply an electric input, an output connection configured to supply an electric output to a load to be connected to the output connection, a switch and a diode arranged between the input connection and the output connection and a voltage limiting inductance arranged in series between the switch and the diode. The voltage limiting inductance is configured to limit, upon switching the switch, a maximum voltage across the switch to below a breakdown voltage of the switch. A corresponding method of operating the half bridge circuit and package are also described. | 2017-10-05 |
20170288655 | Arbitrary Delay Buffer - A signal may be arbitrarily delayed in discrete steps by an arbitrary delay buffer having an analog delay and a digital delay. An analog delay may have a number of selectable delay stages (e.g. ring oscillator with VCDL stages). A digital delay may have rising and falling edge detectors, resettable ring oscillators that oscillate in response to rising or falling edges and counters to count oscillations and generate rising and falling edge delay signals when oscillation counts reach rising and falling edge delay counts. A resettable ring oscillator may have a resettable stage (e.g. VCDL) that may be enabled and disabled. Selection of one or both digital and analog delays and respective delay times may be based on one or more characteristics. For example, an analog delay may delay an input signal or a delayed input signal received from the digital delay based on input signal frequency or total delay. | 2017-10-05 |
20170288656 | DEVICE FOR CORRECTING MULTI-PHASE CLOCK SIGNAL - A device for correcting a multi-phase clock signal includes a first duty ratio adjusting circuit (DRAC) to adjust a duty ratio of a first clock signal; a variable delay line (VDL) delaying a second clock signal; a second DRAC adjusting a duty ratio of the VDL output; first and second differential clock generating circuits (DFCGs) generating differential signals from first and second DRAC outputs, respectively; an edge combining circuit combining edges of outputs from the DFCGs; a duty ratio detecting circuit (DRDC) detecting a duty ratio of a first DRAC output or a first DFCG output in a first mode and of an edge combining circuit output in a second mode; a first control circuit controlling the first and second DRACs using a DRDC output in the first mode; and a second control circuit controlling the VDL using the DRDC output in the second mode. | 2017-10-05 |
20170288657 | GATE DRIVE CIRCUIT - A gate drive circuit has a capacitor and a gate drive voltage source connected in series with a gate terminal of a voltage-driven switching device. The gate drive source voltage feeds, as a gate drive voltage, a voltage higher than the sum of the voltage applied to a gate-source parasitic capacitance of the switching device when the switching device is in a steady ON state and the voltage applied to, of any circuit component interposed between the gate drive voltage source and the gate terminal of the switching device, a circuit component other than the capacitor (such as an upper transistor forming the output stage of the driver). No other circuit component (such as a resistor connected in parallel with the capacitor) is essential but the capacitor as the sole circuit component to be directly connected to the gate terminal of the switching device. | 2017-10-05 |
20170288658 | RESISTOR ARRAY, OUTPUT BUFFER, AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE - A resistor array made of a semiconductor includes a plurality of resistor groups and a common line that electrically connects the M-th resistors of the plurality of resistor groups. Each resistor group includes first to M-th resistors connected in series, M being an integer of 2 or greater, and at least one short-circuit line, each short-circuiting at least one, but not all, of the M resistors. | 2017-10-05 |
20170288659 | APPARATUS WITH MAIN TRANSISTOR-BASED SWITCH AND ON-STATE LINEARIZATION NETWORK - An apparatus including a main transistor-based switch having a first end node and a second end node and an ON-state linearization network that is coupled between the first end node and the second end node of the main transistor-based switch is disclosed. The ON-state linearization network is configured to receive a monitored signal that corresponds to a signal across the first end node and the second end node and cancel at least a portion of non-linear distortion generated by the main transistor-based switch when the main transistor-based switch is in an ON-state based on the monitored signal. A control signal applied to a control input of the ON-state linearization network causes the ON-state linearization network to activate when the main transistor-based switch is in the ON-state and to deactivate the ON-state linearization network when the main transistor-based switch is an OFF-state. | 2017-10-05 |
20170288660 | Ultra-Low Quiescent Current Multi-Function Switching Circuit and Method for Connecting a Voltage Source to an Output Load with Deep Sleep Capability - Described are apparatus and methods for a load switch with reset and deep sleep capability. The slew rate control methods of the PMOS load switches contained in the load switch configuration is also described. A preferred slew rate control circuit includes a power PMOS transistor that is capable of handling load currents of several amperes along with an integrated controller. The integrated reset and deep sleep functions allow the user to control the basic timing control of the voltages that are required by the system and to save battery power in an extended deep sleep mode such as storage and shipping. | 2017-10-05 |
20170288661 | Gate Driver That Drives With A Sequence Of Gate Resistances - A gate driver integrated circuit for driving a gate of an IGBT or MOSFET receives an input signal. In response to a rising edge of the input signal, the integrated circuit causes the gate to be driven in a first sequence of time periods. In each period, the gate is driven high (pulled up) via a corresponding one of a plurality of different effective gate resistances. In response to a falling edge of the input signal, the integrated circuit causes the gate to be driven in a second sequence of time periods. In each period, the gate is driven low (pulled down) via a corresponding one of the different effective gate resistances. In one example, the duration of each time period is set by a corresponding external passive circuit component. The different effective gate resistances are set by external gate resistors disposed between the integrated circuit and the gate. | 2017-10-05 |
20170288662 | System and Method for a High-Side Power Switch - A system and method for a high-side power switch includes a gate driver configured to be coupled to a power switch, a voltage measurement circuit configured to be coupled directly to the power switch, a switch monitoring circuit configured to be coupled to the power switch, the switch monitoring circuit configured to measure an output current of the power switch, a current limitation circuit coupled to the gate driver and the switch monitoring circuit, the current limitation circuit configured to regulate gate-source voltage of the gate driver when the output current exceeds a threshold value, and a controller coupled to the current limitation circuit and the voltage measurement circuit, the controller configured to determine a mode of operation according to a startup voltage measured by the voltage measurement circuit during a startup sequence, the controller further configured to provide the threshold value to the current limitation circuit according to the mode of operation and a switch voltage measured by the voltage measurement circuit | 2017-10-05 |
20170288663 | METHODS AND APPARATUS FOR LEVEL-SHIFTING HIGH SPEED SERIAL DATA WITH LOW POWER CONSUMPTION - A driver circuit for driving a transmission line, such as a cable or a metal trace on a printed circuit board is described. The driver may be configured to drive lines with voltages exceeding the maximum voltage than a transistor can withstand for a given fabrication node. The driver may be configured to receive a supply voltage larger than that indicated by manufacturers. The driver may use a fast path and a slow path. Signals provided by the slow path and the fast path may be combine to adapt the input signals to levels that do cause stress to a transistor. A plurality of drivers of the type described herein may be used to provide digital-to-analog conversion. | 2017-10-05 |
20170288664 | MULTI-ORIENTATION INTEGRATED CELL, IN PARTICULAR INPUT/OUTPUT CELL OF AN INTEGRATED CIRCUIT - An integrated circuit includes at least one integrated cell disposed at a location of the integrated circuit. The at least one integrated cell may have two integrated devices coupled to at least one site of the integrated cell and a multiplexer, and the two integrated devices respectively oriented in two different directions of orientation. A first integrated device of the two integrated devices that is oriented in one of the two directions of orientation is usable. The integrated circuit may include a controller configured to detect the direction of orientation which, having regard to the disposition of the integrated cell at the location, may allow the first integrated device to be usable, and to control the multiplexer to couple the first integrated device electrically to the at least one site. | 2017-10-05 |
20170288665 | METHOD AND APPARATUS FOR EDGE EQUALIZATION FOR HIGH SPEED DRIVERS - A line driver for signal equalization is described. The line driver may comprise an equalization driver and a gating circuit. The gating circuit may be configured to gate the equalization driver between a first transition and a second transition, such as between a rising edge and a falling edge. The gating circuit may comprise one or more delay elements, such as one or more inverters, configured to generate the second transition in response to receiving the first transition, where the second transition is delayed with respect to the first transition. Such line driver may be used to signals having high data rates to transmission lines, such as cables or metal connection on printed circuit boards. | 2017-10-05 |
20170288666 | VOLTAGE-CONTROLLED MAGNETIC-BASED DEVICES HAVING TOPOLOGICAL INSULATOR/MAGNETIC INSULATOR HETEROSTRUCTURE - A voltage-controlled magnetic based device is described that includes a magnetic insulator; a topological insulator adjacent the magnetic insulator; and magnetic dopants within the topological insulator. The magnetic dopants are located within an edge region of the topological insulator to inhibit charge current flow in the topological insulator during a switching operation using an applied electric field generating by applying a switching voltage across two electrodes at opposite sides of the topological insulator. Power dissipation due to carrier-based currents can be avoided or at least minimized by the magnetic dopants at the edges of the topological insulator. | 2017-10-05 |
20170288667 | LIGHTING DEVICE - The invention relates to a lighting device comprising an illuminant embodied as an OLED, and comprising a capacitive switching means, which are arranged on a substrate, wherein the illuminant has a first electrically conductive electrode and a second electrically conductive electrode, wherein a layer comprising organic, electroluminescent material is arranged between the first electrode and the second electrode, wherein the switching means has an electrode, wherein one electrode from the first electrode or the second electrode of the illuminant together with the electrode of the switching means is arranged in one plane, wherein a nonconductive spacing amounting to between 100 μm and 700 μm, more particularly between 400 μm and 600 μm, is present between said one electrode of the illuminant and the electrode of the switching means in the plane. | 2017-10-05 |
20170288668 | VOLTAGE TOLERANT TERMINATION PRESENCE DETECTION - Apparatuses and methods associated with voltage tolerant termination presence detection for universal serial bus type-C connectors are disclosed herein. In embodiments, an apparatus to enable voltage tolerant termination presence detection may include sensor circuitry to determine whether a device coupled to the sensor circuitry is to operate in host mode or device mode based on a signal on a configuration channel between the device and the sensor circuitry. In embodiments, the apparatus may further include termination circuitry to bias the configuration channel in accordance with the host mode or the device mode based on the determination of whether the device is to operate in the host mode or the device mode. Other embodiments may be described and/or claimed. | 2017-10-05 |
20170288669 | CALIBRATION CIRCUIT AND CALIBRATION APPARATUS INCLUDING THE SAME - A calibration circuit sharing a resistor for impedance matching includes a command decoder configured to receive a command signal and decode the command signal into a calibration enable signal; a selector configured to select one of the calibration enable signal and a start signal according to a select signal, and provide a driving signal; and a calibration driver configured to perform an impedance matching operation in response to the driving signal, and generate a completion signal when performance is completed, wherein the start signal corresponds to a completion signal provided from another calibration circuit which shares the resistor for the impedance matching. | 2017-10-05 |
20170288670 | Semiconductor Device, Electronic Component, and Electronic Device - Skew of a multi-context PLD in context switch is reduced to achieve low power consumption. The frequency of a clock signal is switched in context switch operation in accordance with circuit operation to secure time required for context switch. By returning the frequency of the clock signal to the original frequency after executing the context switch, the PLD can maintain high-speed processing and perform the context switch accurately and safely. The time required for the context switch mainly depends on a hardware structure (circuit layout including a parasitic component). Thus, the reliability in the context switch can be improved when time that is equal to or longer than the longest time required for circuit change is secured. | 2017-10-05 |
20170288671 | PIPELINED INTERCONNECT CIRCUITRY WITH DOUBLE DATA RATE INTERCONNECTIONS - An integrated circuit may have pipelined interconnects that are configurable to operate in registered single data rate mode, registered double data rate mode, or in combinational mode. The pipelined interconnect may include routing multiplexers for selecting incoming signals, circuitry for serialization and de-serialization, and memory elements that are configurable to store one or two signals per clock period. Operating the pipeline interconnects in double data rate mode may provide a trade-off between reducing the number of physical wires that are required to implement a design at a constant bandwidth or increasing the bandwidth while keeping the number of physical wires constant. | 2017-10-05 |
20170288672 | LEVEL SHIFTER AND METHOD OF CALIBRATION - A level shifter includes a signal generator that generates differential signals on a first output and a second output. A first capacitor is coupled between the first output and a first node and a second capacitor is coupled between the second output and a second node. A third capacitor is coupled between the first node and a first voltage potential, wherein the capacitance of the third capacitor is variable. A fourth capacitor is coupled between the second node and the first voltage potential, wherein the capacitance of the fourth capacitor is variable. | 2017-10-05 |
20170288673 | POWER EFFICIENT VOLTAGE LEVEL TRANSLATOR CIRCUIT - Disclosed systems and methods relate to a power efficient voltage level translator. In a normal mode wherein a first supply voltage of the first voltage domain and a second supply voltage of the second voltage domain are different, the voltage level translator translates an input signal in a first voltage domain to an output signal in a second voltage domain In a bypass mode wherein the first supply voltage and the second supply voltage are substantially the same, a bypass circuit is configured to bypass the voltage level translator and provide the input signal as the output signal in the first voltage domain, thus avoiding delay introduced by the voltage level translator in the bypass mode. Further, a power-down circuit is configured to power-down the voltage level translator in the bypass mode but not in the normal mode. | 2017-10-05 |
20170288674 | HUM GENERATION USING REPRESENTATIVE CIRCUITRY - Disclosed embodiments select a proper hum frequency reference by utilizing one or more functional logic circuits within a cluster. he slowest logic circuit is determined, and an instance of that logic circuit is used in timing circuitry for the cluster. Multiple logic circuits with similar characteristics are incorporated into the timing circuit. Each cluster is interconnected to a second level timing circuit. Each cluster inputs timing information into the second level timing circuit. The second level timing circuit then determines when the next cycle, or tic, of the self-generated clock starts, and the process repeats, providing a self-generated clock signal. | 2017-10-05 |
20170288675 | CORRELATED ELECTRON SWITCH DEVICE - Disclosed are a circuit and method for implementing a switching function. In an embodiment, the circuit includes a first logic circuit, a second logic circuit, and a Correlated electron switch (CES) element. The CES element is configurable to have a non-volatile state to enable or disable an electrical connection between the first logic circuit and the second logic circuit. | 2017-10-05 |
20170288676 | COMMUNICATION APPARATUS, SEMICONDUCTOR DEVICE, AND FREQUENCY CHARACTERISTIC CHANGING METHOD - The communication apparatus includes a logical device, a wiring line, and a changing unit; the logical device is a programmable device; the wiring line supplies a voltage to the logical device; and the changing unit changes a frequency characteristic of the wiring line based on an operating characteristic obtained by monitoring of the operating characteristic of the logical device for operating by receiving supply of the voltage. According to this, occurrence of voltage drop can be suppressed even if a circuit configured in a programmable logical device is changed. | 2017-10-05 |
20170288677 | CLOCK SIGNAL STOP DETECTION CIRCUIT - A semiconductor device detects an edge of input data input into a data retention circuit to which a clock signal is supplied, resets a first count value obtained by counting an edge detection frequency with a clock signal, resets a second count value obtained by counting the edge detection frequency with an inverted clock signal, and thereby detects an abnormality of the clock signal in accordance with a situation that either of the first count value and the second count value has reached a value indicative of an overflow state. | 2017-10-05 |
20170288678 | OVEN CONTROLLED CRYSTAL OSCILLATOR DEVICE COVER - A device cover for temperature control of a component device includes at least one heating element enclosed using the device cover, and multiple sections. Each section is located at a distinct location on the device cover and includes a reflection angle for the distinct location. The reflection angle is configured to reflect heat to the component device enclosed using the device cover, the heat originating from the at least one heating element. | 2017-10-05 |
20170288679 | Adaptive Temperature Compensation - A method of compensating for the temperature related frequency drift of an oscillator. The method comprises using an external reference frequency signal to derive oscillator compensation data over a range of operating temperatures, storing the oscillator compensation data in a first table, and, for a given operating temperature, using the first table to obtain corresponding oscillator compensation data and applying that data to provide compensation for the temperature related frequency drift. The method further comprises defining, for the range of operating temperatures, a series of temperature slots each sub-divided into a series of temperature bins. The step of using an external reference frequency signal to derive oscillator compensation data over the range of operating temperatures comprises
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20170288680 | CRYSTAL OSCILLATOR CIRCUIT - A crystal oscillator circuit is provided. The crystal oscillator circuit includes an oscillator start-up circuit having a first output terminal and a second output terminal, where the second output terminal outputs a first oscillation signal; and a waveform conversion circuit configured to convert the first oscillation signal to a rectangular wave signal. The crystal oscillator circuit also includes a first current source configured to output a first current to drive the oscillator start-up circuit; and a second current source configured to output a second current, and being connected in parallel with the first current source to jointly drive the oscillator start-up circuit. Further the crystal oscillator circuit includes a pulse generation circuit configured to generate a control pulse signal to control the second current source to output the second current after power on and to stop outputting the second current after a preset time. | 2017-10-05 |
20170288681 | DEVICE AND METHOD FOR MULTIPLE REFERENCE SYSTEM TIMER - A device and method is presented to allow the high frequency clock generators and functional blocks of a wireless communication device to enter a very low power sleep state while the low frequency reference clock generator within the wireless communications device remains in an active state. The timing block provides methods of increasing and maintaining accuracy of the system timer which may have been reduced by temperature variation or manufacturing defects. The timing block also allows for selection of the highest accuracy clock from among multiple high frequency clock references. A device for timing control is presented comprising at least one high frequency reference clock, a low frequency reference clock and a timing controller for generating a system timer, wherein the timing controller selects one of the at least one high frequency reference clock and processes the low frequency reference clock with the selected high frequency reference clock. | 2017-10-05 |
20170288682 | CLOCK SIGNAL AND SUPPLY VOLTAGE VARIATION TRACKING - Embodiments disclosed herein provide an apparatus comprising a clock generation circuit configured to generate a first signal for a first time period and a second signal for a second time period, a charge pump circuit coupled to the clock generation circuit and configured to generate a first voltage and a second voltage based, at least in part, on the first time period and the second time period, and a comparison circuit coupled to the charge pump circuit, the comparison circuit configured to compare a difference between the first voltage and the second voltage with a threshold value and generate an active tracking enablement signal in response to determining that the difference between the first and second voltages exceeds the threshold value. | 2017-10-05 |
20170288683 | COARSE DELAY LOCK ESTIMATION FOR DIGITAL DLL CIRCUITS - Digital delay locked loop circuits, devices systems, and associated methods are provided and described. Such devices, systems, and methods utilize an open loop measurement for establishing a coarse delay lock. | 2017-10-05 |
20170288684 | PROCESSING APPARATUS AND PROCESSING SYSTEM - A processing apparatus includes an FPGA unit connected to an oscillator configured to output a first clock, wherein the FPGA unit includes: a PLL circuit configured to output a second clock with a frequency of a predetermined ratio with respect to a frequency of the first clock and configured to output a lock signal (detection signal); an input and output monitoring unit configured to detect a ratio between the frequencies of the first clock and the second clock, compare the detected ratio with the predetermined ratio, and output an abnormal signal when the detected ratio does not coincide with the predetermined ratio; and an initialization unit configured to output a reset signal when the input and output monitoring unit outputs the abnormal signal and configured to output the reset signal when the PLL circuit outputs the lock signal. | 2017-10-05 |
20170288685 | OSCILLATOR CIRCUIT - An oscillator circuit includes an oscillating unit, a counter unit, and a set value generator. The oscillating unit is configured to output an oscillation signal having a frequency corresponding to an input frequency setting value. The counter unit is configured to count a number of pulses of the oscillation signal during a time period corresponding to a period of a reference signal input from outside. The set value generator is configured to generate the frequency setting value every predetermined time period based on the count of the pulses counted by the counter unit. | 2017-10-05 |
20170288686 | METHOD FOR CONTROLLING DIGITAL FRACTIONAL FREQUENCY-DIVISION PHASE-LOCKED LOOP AND PHASE-LOCKED LOOP - A method for controlling a digital fractional frequency-division phase-locked loop and a phase-locked loop are disclosed. The phase-locked loop includes a control apparatus, a TDC, a DLF, a DCO, a DIV, and an SDM. The control apparatus performs delay processing on an active edge of a reference clock according to a frequency control word and a frequency division control word to obtain a delayed reference clock; and sends the delayed reference clock to the TDC so that the TDC performs phase discrimination processing on the delayed reference clock and a feedback clock. A control apparatus added to a phase-locked loop may perform delay processing on a reference clock according to a current frequency control word and a current frequency division control word, so that a feedback clock and a delayed reference clock have active edges that approximately correspond in time. | 2017-10-05 |
20170288687 | QUANTUM INTERFERENCE DEVICE, ATOMIC OSCILLATOR, ELECTRONIC APPARATUS, AND VEHICLE - A quantum interference device includes an atom cell, a light source emits light to the alkali metal atoms, a photodetector that detects the light transmitted through the atom cell, a thermal conductor, which is disposed so as to straddle the light source side and the photodetector side of the atom cell, and the thermal conductor having higher thermal conductively than the atom cell, and a support, which is disposed so as to be separated from the thermal conductor, and supports the atom cell, the light source, the photodetector, and the thermal conductor in a lump, the support having lower thermal conductivity than the thermal conductor. | 2017-10-05 |
20170288688 | QUANTUM INTERFERENCE DEVICE, ATOMIC OSCILLATOR, ELECTRONIC APPARATUS, AND MOVING OBJECT - A quantum interference device includes an atomic cell, a light source, a light detector, a package, and a reflective portion. The atomic cell has alkali metal atoms disposed within, and the light source emits light to excite the alkali metal atoms in the atomic cell. The light detector detects light transmitted through the atomic cell. The package defines an internal space and houses at least the light source. The reflective portion is provided between an inner surface of the package and the light source, and has reflectance to an electromagnetic wave having a wavelength of 4 μm, where the reflectance is greater than or equal to 50%. | 2017-10-05 |
20170288689 | MICROCOMPUTER FOR MICROPHONE - The objective of the present invention is to make it possible to execute each of a plurality of application programs without taking into account the addresses of the programs. A microcomputer ( | 2017-10-05 |
20170288690 | ADAPTIVE CONFIGURATION TO ACHIEVE LOW NOISE AND LOW DISTORTION IN AN ANALOG SYSTEM - Noise and distortion reduction in a signal processed through analog circuitry includes providing noise reduction circuitry to reduce signal noise generated by at least one analog circuit element. The noise reduction circuitry is adaptively configured to adjust a rate to apply noise reduction to the signal without introducing unwanted distortion. Distortion reduction circuitry is adaptively configured to adjust a rate to apply distortion reduction to the signal without introducing unwanted noise. The signal is processed through the analog circuitry using the adaptively configured noise reduction circuitry and adaptively configured distortion reduction circuitry to reduce both noise and distortion in the signal. | 2017-10-05 |
20170288691 | SEMICONDUCTOR APPARATUS, SOLID-STATE IMAGE SENSING APPARATUS, AND CAMERA SYSTEM - A semiconductor apparatus, a solid-state image sensing apparatus, and a camera system capable of reducing interference between signals transmitted through adjacent via holes, preventing an increase in the number of the via holes, reducing the area of a chip having sensors thereon and the number of mounting steps thereof. First and second chips are bonded together to form a laminated structure, a wiring between the first chip and the second chip being connected through via holes, the first chip transmitting signals obtained by time-discretizing analog signals generated by respective sensors to the second chip through the corresponding via holes, the second chip sampling the signals transmitted from the first chip through the via holes at a timing different from a timing at which the signals are sampled by the first chip and quantizing the sampled signals to obtain digital signals. | 2017-10-05 |
20170288692 | APPARATUS FOR OVERLOAD RECOVERY OF AN INTEGRATOR IN A SIGMA-DELTA MODULATOR - Described is an apparatus which comprises: a first integrator to receive an input signal and to generate a first output; a second integrator to receive the first output or a version of the first output and to generate a second output; and an analog-to-digital converter (ADC) to quantize the second output into a digital representation, the ADC including a detection circuit to detect an overload condition in the second output. | 2017-10-05 |
20170288693 | CONTINUOUS TIME DELTA-SIGMA MODULATOR WITH A TIME INTERLEAVED QUANTIZATION FUNCTION - A wide band continuous time delta-sigma modulator implements a time interleaved quantization processing operation. The modulator may provide for an inherent finite impulse response filtering in the feedback loop. Additionally, further finite impulse response filtering in each time interleaved feedback path may be provided. | 2017-10-05 |
20170288694 | COMPUTER-READABLE RECORDING MEDIUM, ENCODING DEVICE, ENCODING METHOD, DECODING DEVICE, AND DECODING METHOD - An encoding device | 2017-10-05 |
20170288695 | Methods for Compressing and Decompressing IQ Data, and Associated Devices - A method for compressing IQ data for high speed transport link and an associated device. The method comprises: determining, based on dynamical statistical distribution of the IQ data, one or more parameters of a companding function for a nonlinear companding operation (S | 2017-10-05 |
20170288696 | PROXYING READ REQUESTS WHEN PERFORMANCE OR AVAILABILITY FAILURE IS ANTICIPATED - A method includes receiving, by a read threshold number of storage units of a dispersed storage network (DSN), the read threshold number of read requests regarding the read threshold number of encoded data slices of a set of encoded data slices. The method further includes determining, by each storage unit of the read threshold number of storage units, whether the storage unit is capable of processing a respective read request. When a particular storage unit is not capable of processing the respective read request, the method further includes sending, by the particular storage unit, a proxy read request to another storage unit that is not in the read threshold number of storage units. The method further includes determining, by the other storage unit, whether the other storage unit is capable of processing the proxy read request and, when it is, processing the proxy read request. | 2017-10-05 |
20170288697 | LDPC SHUFFLE DECODER WITH INITIALIZATION CIRCUIT COMPRISING ORDERED SET MEMORY - A low-density parity check (LDPC) decoding apparatus for performing shuffle decoding includes: an input wrapper, for receiving input data and padding the input data; an LDPC decoder, coupled to the input wrapper, for receiving the padded input data, performing a plurality of iterations of LDPC decoding upon the padded input data to generate channel values corresponding to the padded input data, and outputting a hard decision channel value in a final iteration; and an initialization circuit, coupled to the LDPC decoder, for receiving the input data in a first iteration of the plurality of iterations, storing the input data into an ordered set data, and immediately sending the ordered set data to the LDPC decoder. | 2017-10-05 |
20170288698 | POWER SAVING FOR BIT FLIPPING DECODING ALGORITHM IN LDPC DECODER - A method for determining when to end a bit flipping algorithm during hard decision soft decoding in a low density parity check (LDPC) decoder includes: selecting a certain number of iterations as a first threshold; when the first threshold is reached, determining a highest variable node codeword for each iteration performed so far; comparing the highest variable node codewords with a second threshold; and when the value of the highest variable node codewords is less than or equal to the second threshold, ending the bit flipping algorithm. | 2017-10-05 |
20170288699 | BIT FLIPPING ALGORITHM FOR PROVIDING SOFT INFORMATION DURING HARD DECISION HARD DECODING - A method for using a first decoder operating in a hard decision hard decoding mode to generate soft information for a second decoder operating in a hard decision soft decoding mode includes: generating a look-up table (LUT) linking a number of failed check nodes to a log-likelihood ratio (LLR) value; in a first iteration of the first decoder, inputting the number of failed check nodes to the LUT table to generate an LLR value; and outputting the LLR value to the second decoder. | 2017-10-05 |
20170288700 | BCH DECORDER IN WHICH FOLDED MULTIPLIER IS EQUIPPED - Provided is a BCH decoder in which a folded multiplier is equipped. The BCH decoder may include a key equation solver including a plurality of multipliers. The multiplier includes a plurality of calculation blocks configured to perform a calculation operation. Each of the calculation blocks repeatedly performs a calculation operation of a calculation stage for a plurality of calculation stages, outputs one output value on the basis of at least one input value in each calculation stage, and is connected to at least one another calculation block to transfer an output value of a current calculation stage as an input value of the at least one another calculation block in a next calculation stage. | 2017-10-05 |
20170288701 | Restoration of Erasure-Coded Data Via Data Shuttle in Distributed Storage System - Embodiments use data shuttle devices to restore erasure-coded data in a distributed storage environment. In some embodiments, a first data shuttle is communicatively coupled to a first node of the storage environment. On the data shuttle, first restoration data is generated from a first erasure-coded data portion stored on the first node. The first data shuttle or a second data shuttle is communicatively coupled to a second node of the storage environment. On the data shuttle at the second node, second restoration data is generated from a second erasure-coded data portion stored on the second node. Subsequent to transporting the first or second data shuttle from at least one of the other nodes to a third node, a third erasure-coded data portion is restored at the third node. The third erasure-coded data portion is generated via an erasure-coding process from one or more of the first or second restoration data. | 2017-10-05 |
20170288702 | DYNAMICALLY CONTROLLING ERASURE CODE DISTRIBUTION IN AN OBJECT STORE - Example apparatus and methods monitor conditions in an object storage system. The conditions monitored may include a load balance measure in the system, a capacity balance measure in the system, a fault tolerance measure in the system, or a usage pattern measure in the system. A distribution plan or redistribution plan for storing or moving erasure codes in the object storage system may be determined based on the conditions. The distribution plan or the redistribution plan for the erasure codes may be updated dynamically in response to changing conditions in the object storage system. The distribution or redistribution may depend on a weighted combination of the load balance measure, the capacity balance measure, the fault tolerance measure, or the usage pattern measure so that responding to one sub-optimal condition (e.g., load imbalance) does not create a different sub-optimal condition (e.g., unacceptable fault tolerance). | 2017-10-05 |
20170288703 | POLAR CODE ENCODING METHOD AND ENCODING APPARATUS - The present invention discloses a polar code encoding method and encoding apparatus. The method includes: mapping M reserved bits of a broadcast signaling respectively to M low-reliability information bits in K information bits of a polar code, and mapping remaining bits of the broadcast signaling to remaining information bits of the K information bits, to obtain bits after mapping, where M2017-10-05 | |
20170288704 | ACCELERATED ERASURE CODING FOR STORAGE SYSTEMS - A method for generating coded fragments comprises receiving data to be encoded, splitting the data into a plurality of data fragments, identifying a first group of data fragments from among the plurality of data fragments using a coding matrix, summing the data fragments within the first group of data fragments to generate a first group sum, and using the first group sum to calculate at least a portion of two or more coded fragments. | 2017-10-05 |
20170288705 | SHARED MEMORY WITH ENHANCED ERROR CORRECTION - A memory system that detects and corrects bit errors performs a first decoding procedure regarding a serial unit of the encoded data to produce a decoded serial unit. The memory system further determines the first decoding procedure regarding the serial unit was not successful and performs the first decoding procedure regarding a plurality of additional serial units of the encoded data to produce a plurality of additional decoded serial units. The serial unit and the plurality of additional serial units constitute a predefined grouping of the encoded data. The memory system also performs a second decoding procedure regarding a plurality of derivative units to produce a plurality of decoded derivative units. Each successive bit in each of the plurality of derivative units is correlated to a corresponding sequential position in the decoded serial unit and each of the decoded additional serial units. | 2017-10-05 |
20170288706 | METHOD AND APPARATUS FOR SHORTENING AND PUNCTURING NON-BINARY CODE - The present disclosure relates to a pre-5 | 2017-10-05 |
20170288707 | LC FILTER LAYER STACKING BY LAYER TRANSFER TO MAKE 3D MULTIPLEXER STRUCTURES - A three dimensional (3D) multiplexer structure may include a first two dimensional (2D) inductor capacitor (LC) filter layer. The first 2D LC filter layer may include a first 2D spiral inductor and a first capacitor(s). The 3D multiplexer structure may also include a second 2D LC filter layer. The second 2D LC filter layer may include a second 2D spiral inductor and a second capacitor(s) stacked directly on and communicably coupled to the first 2D LC filter. | 2017-10-05 |
20170288708 | DISTORTION COMPENSATION DEVICE AND DISTORTION COMPENSATION METHOD - A distortion compensation device includes: an odd-order distortion compensation unit that compensates an odd-order distortion occurring at first frequencies used for transmitting an amplified signal, the first frequencies including a plurality of frequencies; and an even-order distortion compensation unit that compensates an even-order distortion occurring at second frequencies different from the first frequencies due to the amplification of the signal, the second frequencies including one or more frequencies. | 2017-10-05 |
20170288709 | AMPLIFICATION APPARATUS - An amplification apparatus includes a separator configured to separate an input signal into a first signal and a second signal, a first and second amplifiers amplify the first and second signal, a storage, and a processor coupled to the storage and configured to adjust a phase of the second signal on the basis of a first phase value corresponding to a power value of the input signal or a second phase value set within a period in which the first phase value is updated, calculate a power value of an output signal that is synthesis of an output of the first amplifier and an output of the second amplifier, and update the first phase value to the second phase value after the change of the power value of the calculated output signal when the first phase value is the power value of the input signal. | 2017-10-05 |
20170288710 | TOMLINSON-HARASHIMA PRECODING IN AN OTFS COMMUNICATION SYSTEM - A method for signal transmission using precoded symbol information involves estimating a two-dimensional model of a communication channel in a delay-Doppler domain. A perturbation vector is determined in a delay-time domain wherein the delay-time domain is related to the delay-Doppler domain by an FFT operation. User symbols are modified based upon the perturbation vector so as to produce perturbed user symbols. A set of Tomlinson-Harashima precoders corresponding to a set of fixed times in the delay-time domain may then be determined using a delay-time model of the communication channel. Precoded user symbols are generated by applying the Tomlinson-Harashima precoders to the perturbed user symbols. A modulated signal is then generated based upon the precoded user symbols and provided for transmission over the communication channel. | 2017-10-05 |
20170288711 | METHODS AND APPARATUS FOR COMMUNICATING WITH A RECEIVING UNIT - In some embodiments, techniques are provided for extending the functionality of a receiving unit which is configured to express a state during an event. In some embodiments, a receiving unit configured to receive a first set of transmissions during an event from one or more transmitting units and express a state in response may also be configured to receive a second set of transmissions from other components at a time other than during the event and express a state in response to receiving the second set of transmissions. | 2017-10-05 |
20170288712 | Removing Impulsive Noise In A Radio - In one example, an apparatus includes: a delay unit to delay a demodulated signal obtained from an input radio frequency (RF) frequency modulation (FM) signal; a filter to filter the demodulated signal and output a filtered demodulated signal; an impulse detection circuit to receive the filtered demodulated signal and detect presence of an impulse in the demodulated signal; and an impulse removal circuit to remove the detected impulse from the demodulated signal. | 2017-10-05 |
20170288713 | SIGNAL PROCESSING APPARATUS, SIGNAL PROCESSING METHOD, AND STORAGE MEDIUM - A signal processing apparatus includes a unit configured to generate noise cut data by deducting a predetermined noise value from values of respective signals constituting input data and a stochastic resonance processing unit configured to subject the noise cut data to a predetermined stochastic resonance processing. The predetermined stochastic resonance processing is processing to output, in a method of synthesizing a result of parallelly performing steps of adding new noise to the noise cut data to subject the resultant data to a binary processing, a value obtained in a case where the parallel number is infinite. | 2017-10-05 |
20170288714 | AGGREGATE SIGNAL AMPLIFICATION DEVICE AND METHOD - A surface acoustic wave (SAW) filter that receives an aggregate circuit and outputs two or more sub-signals on outputs each of a different frequency band. The sub-signals are amplified by low noise amplifiers and, in one implementation, the amplified sub-signals can be summed. The outputs are connected via a switched passive network so that portions of the sub-signals on the outputs that are not in the selected frequency band are at least partially terminated. | 2017-10-05 |
20170288715 | Processing A Noisy Analogue Signal - A device is provided for correlating at least one noisy analogue signal which is one of a plurality of signals obtained by a plurality of receivers. The device comprises a 1-bit quantisation element to which is supplied, in use, the noisy signal; a comparator configured to compare the quantised signal with a reference signal which is a consensus signal obtained by averaging data from the plurality of receivers; and an up/down counter that is configured to be incremented by a subset of the comparison signal. | 2017-10-05 |
20170288716 | REDUCING OUT-OF-CHANNEL NOISE IN A WIRELESS DISTRIBUTION SYSTEM (WDS) - Embodiments of the disclosure relate to reducing out-of-channel noise in a wireless distribution system (WDS). A digital filter in a remote unit is configured to suppress out-of-channel noise in a downlink digital communications signal based on at least one filter configuration parameter received from a control circuit. The control circuit is configured to determine the filter configuration parameter based on physical characteristics of the downlink digital communications signal. By suppressing the out-of-channel noise of the downlink digital communications signal, it is possible to provide a downlink RF communications signal communicated from the remote unit that complies with a spectrum emission mask (SEM). Further, by suppressing the out-of-channel noise at the remote unit, it is not necessary for a central unit to perform digital filtering before distributing the downlink digital communications signal to the remote unit, thus helping reduce complexity, cost, physical size, and power consumption of the central unit. | 2017-10-05 |
20170288717 | RECEPTION INTERFACE CIRCUITS SUPPORTING MULTIPLE COMMUNICATION STANDARDS AND MEMORY SYSTEMS INCLUDING THE SAME - A reception interface circuit includes a termination circuit, a buffer and an interface controller. The termination circuit is configured to change a termination mode in response to a termination control signal. The buffer is configured to change a reception characteristic in response to a buffer control signal. The interface controller is configured to generate the termination control signal and the buffer control signal such that the reception characteristic of the buffer is changed in association with the change in the termination mode. The reception interface circuit may support various communication standards by changing the reception characteristic of the buffer in association with the termination mode. Using the reception interface circuit, communication efficiency of transceiver systems such as a memory system and/or compatibility between a transmitter device and a receiver device may be improved. | 2017-10-05 |
20170288718 | WIRELESS COMMUNICATION HELMET SYSTEM AND METHOD - A wireless communication helmet system preferably includes a helmet assembly, a power-cord, and a control assembly. The helmet assembly preferably includes a helmet, a speaker, a microphone, and a power-supply. Preferably, the control assembly includes a wireless-communications-device, a digital-screen, and a volume-control, where the control assembly is in wireless communication with the helmet assembly, and the power-cord is removably coupleable to the helmet assembly. The wireless communication helmet system allows a user to communicate to at least one remote individual without a need to hold a communications device in a hand of the user. | 2017-10-05 |
20170288719 | Advanced Device Locking Criteria - Systems and methods for providing additional control over user equipment (UE) using standardized features of a subscriber identity module (SIM) is provided. The UE can impose SIMLocking criteria based on subscriber related attributes (such as rate plan, prepay, postpay, etc.). The SIM module can comprise multiple unique entries and one value for each entry. One or more entries on the SIM can be subdivided to provide additional values with each value made up of a subset of bits from a particular entry. Thus, a single entry can provide a plurality of values to make up a SIM configuration. The SIM configuration can be compared to a UE SIMLock configuration with the same, or similar, entries to determine if the SIM is compatible for use with the UE. The SIM configuration can be updated dynamically to reflect changes in the account associated with the UE or the SIM. | 2017-10-05 |
20170288720 | ELECTRONIC PRODUCT METAL SHELL WITH AN ANTENNA GROOVE AND METHOD OF MANUFACTURING THE SAME - The present disclosure provides an electronic product metal shell with an antenna groove and a method of manufacturing the same. The electronic product metal shell includes a metal layer, a hard anodic oxidation layer, a step recess, an antenna groove and a non-conductive material filled in the antenna groove. The metal layer may have a first surface and a second surface. The hard anodic oxidation layer may be coated on the first surface and the second surface of the metal layer. The step recess may be formed through the hard anodic oxidation layer on the first surface of the metal layer and partially into the metal layer. The antenna groove may be formed within the step recess extending through the metal layer to expose an inner side of the hard anodic oxidation layer on the second surface of the metal layer. | 2017-10-05 |
20170288721 | METAL SHELL OF COMMUNICATION EQUIPMENT - The present disclosure provides a metal shell of communication equipment. The metal shell of communication equipment includes a metal substrate, a slit penetrating an inner and an outer surface of the metal substrate, a plastic-supporting layer formed on the inner surface of the metal substrate and a decorative layer formed on the outer surface of the metal substrate, wherein a width of the slit on the outer surface of the metal substrate is 15-500 μm, a width of the slit on the inner surface of the metal substrate is 20-600 μm, and a ratio of the width of the slit on the inner surface of the metal substrate to the width of the slit on the outer surface of the metal substrate is between 1.05:1 and 1.5:1. | 2017-10-05 |
20170288722 | SYSTEM AND METHOD FOR MOBILE DATA EXPANSION AND VIRTUAL PATHWAY DESIGNATION - A data expansion system that provides for wireless communication includes a set of roadway communication devices configured to enable vehicle-to-vehicle (V2V) communication. The system includes a first roadway communication device configured to receive data from a first electronic device in a first vehicle and a second roadway communication device communicatively coupled to the first roadway device. The second roadway communication device is configured to communicate the data to a second electronic device in a second vehicle. Each roadway communication device includes a wireless transceiver to transmit and receive data; a communication interface to establish communication links with other roadway communication devices; and processing circuitry to relay the data between the other roadway communication devices or electronic devices in respective vehicles. Each roadway communication device also includes a housing that contains the processing circuitry, communication interface and the wireless transceiver. The housing is configured to be mounted within a roadway surface. | 2017-10-05 |
20170288723 | CO-CHANNEL WIRELESS DETECTION - An electronic device includes an antenna configured to receive a wireless signal. The electronic device also includes a first correlator configured to correlate the wireless signal to a communication of a first wireless protocol type and a second correlator configured to correlate the wireless signal to a communication of a second wireless protocol type. | 2017-10-05 |
20170288724 | TUNABLE RADIO FREQUENCY SYSTEMS USING PIEZOELECTRIC PACKAGE-INTEGRATED SWITCHING DEVICES - Embodiments of the invention include a tunable radio frequency (RF) communication module that includes a transmitting component having at least one tunable component and a receiving component having at least one tunable component. The tunable RF communication module includes at least one piezoelectric switching device coupled to at least one of the transmitting and receiving components. The at least one piezoelectric switching device is formed within an organic substrate having organic material and is designed to tune at least one tunable component of the tunable RF communication module. | 2017-10-05 |
20170288725 | Dynamic Reconfiguration of Uplink Transmission in a TDD Wireless Communication System - Embodiments of the invention use signaling mechanisms that enable dynamic reconfiguration of the UL/DL resource partitioning by user equipment (UE) in a TDD wireless communication system, such as the 3GPP TDD Long Term Evolution (TD-LTE) system. The dynamic reconfiguration of the UL/DL resource partitioning disclosed herein may also be applied to any other TDD wireless system employing dynamic reconfiguration of the TDD UL/DL configuration. | 2017-10-05 |
20170288726 | METHODS AND SYSTEMS FOR SPREAD SPECTRUM COMMUNICATIONS - Wireless communications have become ubiquitous for society with the availability of low cost front end transmitter and receiver circuits. Network operators strive to provide wireless signals with good Signal to Noise and Interference Ratio (SNIR) whilst increasing useable network capacity and bandwidth using maximum over-the-air data rate and controlling or minimizing over-the-air congestion. Historically this has been achieved via evolutions of network and consumer hardware, firmware, software and hence it would be beneficial to provide network operators with a means of increasing network capacity without requiring either additional hardware complexity and/or additional computational complexity in the receiving devices. The inventor has established a new domain within the network, the spreading code domain, to increase the data rate, by using spreading codes to map the data in conjunction with the constellation symbols and reduce the amount of transmitted data required. | 2017-10-05 |
20170288727 | BROADBAND REPEATER WITH SECURITY FOR ULTRAWIDEBAND TECHNOLOGIES - An ultrawideband radio transceiver/repeater provides a low cost infrastructure solution that merges wireless and wired network devices while providing connection to the plant, flexible repeater capabilities, network security, traffic monitoring and provisioning, and traffic flow control for wired and wireless connectivity of devices or networks. The ultrawideband radio transceiver/repeater can be implemented in discrete, integrated, distributed or embedded forms. | 2017-10-05 |
20170288728 | INTERFACE CIRCUITS AND COMMUNICATION SYSTEM FOR COUPLING A HOST DEVICE TO AN ACCESSORY DEVICE AND METHOD FOR COMMUNICATION BETWEEN SUCH DEVICES - A host interface circuit operates in a power mode when connected to an accessory device compatible with a power supply via a first line of a data cable. During power mode, the host interface circuit couples a power regulator to the first line. The host interface circuit operates in a legacy mode when connected to an accessory device not compatible with such a power supply and couples the legacy terminal to the first line during legacy mode. An accessory interface circuit configured to operate in a power mode when connected to a host device capable of a power supply via a first line couples a power input of an active device to the first line and a data input of the active device to a second line during power mode. | 2017-10-05 |
20170288729 | COMMUNICATION SYSTEM AND TRANSMISSION APPARATUS - A transmission circuit includes a photocoupler, a conductive/non-conductive state of which is controlled in accordance with data to be transmitted to a communication device. A reception circuit includes a photocoupler, a conductive/non-conductive state of which is controlled in accordance with the conductive/non-conductive state of the transmission path. A transmission circuit includes a photocoupler, a conductive/non-conductive state of which is controlled in accordance with data to be transmitted to a communication device. A reception circuit includes a photocoupler, a conductive/non-conductive state of which is controlled in accordance with the conductive/non-conductive state of the transmission path. The photocoupler is included in the transmission path. The photocoupler and the photocoupler are in opposite conductive/non-conductive states. | 2017-10-05 |
20170288730 | PARALLEL TESTING OF A CONTROLLER AREA NETWORK BUS CABLE - A computer program product according to one embodiment includes a computer readable storage medium having program instructions embodied therewith, wherein the computer readable storage medium is not a transitory signal per se, the program instructions executable by a processing system to cause the processing system to perform a method that includes sending a data testing signal through a data lead of a cable via a first interface, sending a power signal through a power lead of the cable via the first interface, receiving and analyzing the data testing signal from the data lead of the cable via a second interface, and receiving and analyzing the power signal passing through the power lead of the cable via the second interface. | 2017-10-05 |