40th week of 2021 patent applcation highlights part 58 |
Patent application number | Title | Published |
20210312941 | AUDIO STEM IDENTIFICATION SYSTEMS AND METHODS - Methods, systems and computer program products are provided for determining acoustic feature vectors of query and target items in a first vector space, and mapping the acoustic feature vectors to a second vector space having a lower dimension. The distribution of vectors in the second vector space can then be used to identify items from the same songs, and/or items that are complementary. A mapping function is trained using a machine learning algorithm, such that complementary audio items are closer in the second vector space than the first, according to a given distance metric. | 2021-10-07 |
20210312942 | SYSTEM, METHOD, AND COMPUTER PROGRAM FOR COGNITIVE TRAINING - There is provided a system, method, and computer program for cognitive assessment scoring and planning in the field of neurological and/or behavioral testing. A system for automatic scoring for cognitive assessment can include quantifying cognitive states given automatic measures applied to language data. A system for automatic construction of assessment plans can include quantifying cognitive states using mathematical models, given measures extracted automatically from speech and language data. | 2021-10-07 |
20210312943 | METHOD AND APPARATUS FOR TARGET SOUND DETECTION - A device to perform target sound detection includes one or more processors. The one or more processors include a buffer configured to store audio data and a target sound detector. The target sound detector includes a first stage and a second stage. The first stage includes a binary target sound classifier configured to process the audio data. The first stage is configured to activate the second stage in response to detection of a target sound. The second stage is configured to receive the audio data from the buffer in response to the detection of the target sound. | 2021-10-07 |
20210312944 | END-OF-TALK PREDICTION DEVICE, END-OF-TALK PREDICTION METHOD, AND NON-TRANSITORY COMPUTER READABLE RECORDING MEDIUM - The end-of-talk prediction device ( | 2021-10-07 |
20210312945 | ASSEMBLY THAT ENABLES REDUCTION IN DISK TO DISK SPACING - A data storage system includes a data storage foil mounted within the data storage system, the data storage foil has at least one data storage surface. The data storage system also includes a head configured to interact with the at least one data storage surface to carry out at least one of data read or data write operations. | 2021-10-07 |
20210312946 | HEAD GIMBAL ASSEMBLY - The disclosure describes a head gimbal assembly including a suspension and a damping layer on a surface of the suspension. The suspension may include a slider mount configured to establish mechanical communication with a slider and the layer may be displaced from the slider mount. The layer may be configured to provide passive damping or active damping. | 2021-10-07 |
20210312947 | TAPE CARTRIDGE - A tape cartridge according to an embodiment of the present technology includes: a reel; a cartridge case; a reel lock member; and a reel lock release member. The reel includes a reel hub including a cylindrical bottom portion. The reel lock member includes a projecting portion projecting toward the cylindrical bottom portion in a uniaxial direction and is urged in the uniaxial direction to engage with the reel hub. The reel lock release member includes a main body and a plurality of leg portions, the main body being disposed between the reel lock member and the cylindrical bottom portion, the plurality of leg portions extending from the main body in the uniaxial direction and being inserted into a plurality of through holes, the reel lock release member releasing engagement of the reel lock member and the reel hub. The main body includes a central portion and a plurality of extension portions, the central portion being in contact with the projecting portion, the plurality of extension portions extending radially along a direction perpendicular to the uniaxial direction from the central portion to end portions connected to the plurality of leg portions, thicknesses of the plurality of extension portions along the uniaxial direction gradually decreasing from the central portion toward the end portions. | 2021-10-07 |
20210312948 | System and Method for Compiling User-Generated Videos - A system and method are operable within a computer network environment for compiling videos into a compilation, where each video is programmatically inserted into the compilation, and the resulting video compilation plays alongside an audio track preferably sourced using a unique identifier for the audio track. The system includes a solution stack comprising a remote service system and at least one client, which may be operable to generate at least one video to be associated with an audio track section, with such section determined by select start/end times, programmatically identified, or programmatically associated based on selected metadata. The system then operates to compile at least one user-generated video into an audiovisual set which may be presented as a social post, and further into a video compilation which may include additional filler content, to play alongside a section or the entirety of an audio track. | 2021-10-07 |
20210312949 | SYSTEMS AND METHODS FOR INTRAOPERATIVE VIDEO REVIEW - Systems, methods, and computer readable media related to providing intraoperative video review are disclosed. They involve receiving a plurality of video frames from a surgical video of an ongoing surgical procedure. Stored data based on prior surgical procedures may be accessed and at least one expected future event in the ongoing surgical procedure may be predicted based on the plurality of video frames and the stored data. At least one option to review at least one surgical video clip associated with the expected future event in the surgical procedure may be generated. A data structure containing the at least one surgical video clip may be accessed and the at least one surgical video clip associated with the expected future event may be outputted for intra-surgical presentation. | 2021-10-07 |
20210312950 | HYPERMEDIA ENABLED PROCEDURES FOR INDUSTRIAL WORKFLOWS ON A VOICE DRIVEN PLATFORM - Various embodiments described herein relate to hypermedia enabled procedures for industrial workflows on a voice driven platform. In this regard, a system compares media data related to a step of a video procedure for an industrial task with a category dictionary to determine a category for the step of the video procedure. The system also links, based on the category for the step of the video procedure, the step of the video procedure with at least a portion of a second video procedure to generate a hypervideo that comprises an industrial sub-task for the industrial task. Furthermore, the system displays the hypervideo via a head-mounted visual display of a wearable device. | 2021-10-07 |
20210312951 | HYPERMEDIA ENABLED PROCEDURES FOR INDUSTRIAL WORKFLOWS ON A VOICE DRIVEN PLATFORM - Various embodiments described herein relate to hypermedia enabled procedures for industrial workflows on a voice driven platform. In this regard, a system compares media data related to a step of a video procedure for an industrial task with a category dictionary to determine a category for the step of the video procedure. The system also links, based on the category for the step of the video procedure, the step of the video procedure with at least a portion of a second video procedure to generate a hypervideo that comprises an industrial sub-task for the industrial task. Furthermore, the system displays the hypervideo via a head-mounted visual display of a wearable device. | 2021-10-07 |
20210312952 | INTERCONNECT ARCHITECTURE FOR THREE-DIMENSIONAL PROCESSING SYSTEMS - A processing system includes a plurality of processor cores formed in a first layer of an integrated circuit device and a plurality of partitions of memory formed in one or more second layers of the integrated circuit device. The one or more second layers are deployed in a stacked configuration with the first layer. Each of the partitions is associated with a subset of the processor cores that have overlapping footprints with the partitions. The processing system also includes first memory paths between the processor cores and their corresponding subsets of partitions. The processing system further includes second memory paths between the processor cores and the partitions. | 2021-10-07 |
20210312953 | DIMM SOCKET WITH SEATING FLOOR TO MEET BOTH LONGER LENGTH EDGE CONTACTS AND SHORTER LENGTH EDGE CONTACTS - An apparatus is described. The apparatus includes a DIMM socket having a seating floor that is to meet both longer length contacts and shorter length contacts of a DIMM when the DIMM is fully seated in the socket. | 2021-10-07 |
20210312954 | APPARATUSES AND METHODS FOR DIFFERENT IO WIDTHS FOR STACKED DIE - Apparatuses and methods for providing data from stacked memory are described. The stacked memory may include multiple die. In some examples, a master die may receive data from one or more slave die. The master die may provide data from the master die and the data from the one or more slave die to a plurality of output terminals. Different ones of the output terminals may provide data from a different die of the stacked memory. In some examples, the data may be retrieved from the multiple die concurrently. | 2021-10-07 |
20210312955 | BIAS CURRENT GENERATOR CIRCUITRY - A supply voltage sensitivity of an output current of a bias current generator circuit is reduced. The bias current generator includes a plurality of transistors and a plurality of resistors coupled to the plurality of transistors. The supply voltage sensitivity of the output current of the bias current generator circuit is reduced by applying a second bias current generated by the bias current generator circuit to a first bias current generated by the bias current generator circuit. | 2021-10-07 |
20210312956 | MEMORY APPARATUS HAVING STRUCTURE COUPLING PAD AND CIRCUIT - A memory apparatus includes an internal circuit configured to output a plurality of output signals, a signal conversion circuit configured to convert a control signal to generate a selection signal, and a selection circuit configured to output one of the plurality of output signals based on the selection signal. The memory apparatus also includes a buffer configured to buffer output of the selection circuit and output the buffered output to a pad. | 2021-10-07 |
20210312957 | SEMICONDUCTOR STORING APPARATUS AND PRE-CHARGE METHOD - A semiconductor storing apparatus capable of suppressing a peak current in a pre-charge operation and shortening a sense time is provided. A pre-charge method of a bit line of an NAND type flash memory includes: turning on a transistor (BLPRE) and supplying a pre-charge voltage to a sense node (SNS) at time (t | 2021-10-07 |
20210312958 | MEMORY WITH PER PIN INPUT/OUTPUT TERMINATION AND DRIVER IMPEDANCE CALIBRATION - Memory devices and systems with per pin input/output termination and driver impedance calibration capabilities, and associated methods, are disclosed herein. In one embodiment, a device apparatus includes circuitry dedicated to an individual DQ pin of the device apparatus. The circuitry can be configured to (i) generate, at least in part, a voltage at the DQ pin based, at least in part, on an impedance internal to a host device electrically connected to the device apparatus and (ii) compare the voltage to a target voltage. Based, at least in part, on the comparison, the circuitry can be configured to adjust a resistance of an output driver and/or a termination circuit of the device apparatus that correspond to the DQ pin to adjust the impedance of the output driver and/or termination circuit to match an impedance associated with a corresponding input/output pin of the host device. | 2021-10-07 |
20210312959 | IN-MEMORY COMPUTING CIRCUIT FOR FULLY CONNECTED BINARY NEURAL NETWORK - An in-memory computing circuit for a fully connected binary neural network includes an input latch circuit, a counting addressing module, an address selector, a decoding and word line drive circuit, a memory array, a pre-charge circuit, a writing bit line drive circuit, a replica bit line column cell, a timing control circuit, a sensitive amplifier and a NAND gate array, an output latch circuit and an analog delay chain. A parallel XNOR operation is performed in the circuit on the SRAM bit line, and the accumulation operation, activation operation and other operations are performed by the delay chain in the time domain. Partial calculation is completed while reading the data, and the delay chain with a small area occupation can be integrated with SRAM, thus reducing the energy consumption of the memory access process. Multi-column parallel computing also improves system throughput. | 2021-10-07 |
20210312960 | MEMORY DEVICES WITH IMPROVED REFRESHING OPERATION - A memory device for memory cell programming and erasing with refreshing operation is disclosed. The memory device includes multiple location-related memory cells and a refresh module. The location-related memory cells are coupled to a bit line on which a selecting voltage is applied. The refresh module rewrites a stored data of a first cell of the location-related memory cells to the first cell of the location-related memory cells in response to an operation count being smaller than a number N. N is related to the number of the location-related memory cells. | 2021-10-07 |
20210312961 | APPARATUSES AND METHODS FOR COMMAND/ADDRESS TRACKING - Tracking circuitry may be used to determine if commands and/or command sequences include illegal commands and/or illegal command sequences. If the commands and/or command sequences include illegal commands and/or illegal command sequences, the tracking circuitry may activate signals that prevent execution of the commands and/or notice of the detected illegal commands and/or command sequences. | 2021-10-07 |
20210312962 | DATA TRANSMISSION BETWEEN CLOCK DOMAINS FOR CIRCUITS SUCH AS MICROCONTROLLERS - A data producer stores input data in a buffer in response to a slow clock signal and provides read data from the buffer in response to a read pointer signal. A data movement circuit reads the input data from the buffer using the read pointer signal and provides an update read pointer signal in response to reading the input data. The data movement circuit operates in response to a fast clock signal, and includes a metastable-free synchronizer circuit having inputs for receiving the update read pointer signal, the slow clock signal, and the read pointer signal, and an output for providing a synchronized read pointer signal equal to the read pointer signal except between a change in the read pointer signal while the slow clock signal is active until an inactivation of the slow clock signal. The buffer provides the read data in response to the synchronized read pointer signal. | 2021-10-07 |
20210312963 | MEMORY DEVICE AND OPERATING METHOD THEREOF - An electronic device is provided. A buffer circuit, performing an optimized operation according to the present disclosure, includes a pause detector, a toggle detector, and an output signal controller. The pause detector receives an input signal and generates a pause signal which indicates whether the input signal is in a pause state. The toggle detector receives the input signal and the pause signal and generates a toggle signal which indicates whether the input signal is in a toggle state. The output signal controller generates an output signal which controls input buffer circuits according to the toggle signal. | 2021-10-07 |
20210312964 | Cross-Point MRAM Including Self-Compliance Selector - The present invention is directed to a magnetic memory cell including a magnetic tunnel junction (MTJ) memory element and a two-terminal bidirectional selector coupled in series between two conductive lines. The MTJ memory element includes a magnetic free layer; a magnetic reference layer; and an insulating tunnel junction layer interposed therebetween. The two-terminal bidirectional selector includes a bottom electrode; a top electrode; a load-resistance layer interposed between the bottom and top electrodes and comprising a first tantalum oxide; a first volatile switching layer interposed between the bottom and top electrodes and comprising a metal dopant and a second tantalum oxide that has a higher oxygen content than the first tantalum oxide; and a second volatile switching layer in contact with the first volatile switching layer and comprising a third tantalum oxide that has a higher oxygen content than the first tantalum oxide. | 2021-10-07 |
20210312965 | MAGNETIC TUNNEL JUNCTION DEVICE AND METHOD OF FORMING SAME - A semiconductor device and a method of forming the same are provided. The method includes forming a bottom electrode layer over a substrate. A magnetic tunnel junction (MTJ) layers are formed over the bottom electrode layer. A top electrode layer is formed over the MTJ layers. The top electrode layer is patterned. After patterning the top electrode layer, one or more process cycles are performed on the MTJ layers and the bottom electrode layer. A patterned top electrode layer, patterned MTJ layers and a patterned bottom electrode layer form MTJ structures. Each of the one or more process cycles includes performing an etching process on the MTJ layers and the bottom electrode layer for a first duration and performing a magnetic treatment on the MTJ layers and the bottom electrode layer for a second duration. | 2021-10-07 |
20210312966 | SEMICONDUCTOR CIRCUIT AND ELECTRONIC DEVICE - A semiconductor circuit according to the present disclosure includes: a first circuit that generates an inverted voltage of a voltage at a first node, and applies the inverted voltage to a second node; a second circuit that generates an inverted voltage of a voltage at the second node, and applies the inverted voltage to the first node; a first memory element that has a first terminal, a second terminal, and a third terminal, and stores information by setting a resistance state between the second terminal and the third terminal to a first resistance state or a second resistance state in accordance with a direction of a first current flowing between the first terminal and the second terminal; a first transistor that couples the first node to the third terminal of the first memory element by being turned on; and a second transistor that is coupled to a first coupling node being one of the first node and the second node, and causes the first current to flow to the second terminal of the first memory element on the basis of a voltage at the first coupling node. | 2021-10-07 |
20210312967 | FERROELECTRIC MEMORY PLATE POWER REDUCTION - Methods, systems, and devices for ferroelectric memory plate power reduction are described. A plate line may be coupled with a voltage source, a capacitor, and one or more sections of a bank of ferroelectric memory cells. During a write operation, the capacitor may be discharged onto the plate line and the resulting voltage may be adjusted (e.g., increased) by the voltage source before writing one or more memory cells. During a write-back operation, a capacitor associated with one or more memory cells may be discharged onto the plate line and stored at the capacitor. The charge may be re-applied to the plate line and adjusted (e.g., increased) by the voltage source during the write-back. | 2021-10-07 |
20210312968 | LOW VOLTAGE FERROELECTRIC MEMORY CELL SENSING - Methods, systems, and devices for low voltage ferroelectric memory cell sensing are described. As part of an access operation for a memory cell, gates of two cascodes may be biased to compensate for associated threshold voltages. An extracted signal corresponding to a charge stored in the memory cell may be transferred through a first cascode to charge a first capacitor. Similarly, a reference signal developed at a dummy digit line may be transferred through a second cascode to charge a second capacitor. By comparing the reference signal developed at the dummy digit line to the extracted signal from the memory cell, the effect of variations in memory cell performance on the sense window may be reduced. Additionally, based on biasing the gates of the cascodes, the difference between the signals compared at the sense component may be low compared to other sensing schemes. | 2021-10-07 |
20210312969 | VOLTAGE SUPPLY CIRCUIT, MEMORY CELL ARRANGEMENT, TRANSISTOR ARRANGEMENT, AND METHODS THEREOF - An electronic circuit may be operated based on two or more supply voltages ramped in accordance with a digital control scheme, the digital control scheme may include ramping a voltage value of a first output voltage generated via a first digitally controlled voltage converter from a first target voltage value to a third target voltage value such that the voltage value of the first output voltage matches a second target voltage value during a first ramp interval and the third target voltage value during a second ramp interval; and ramping a voltage value of a second output voltage generated via a second digitally controlled voltage converter from the first target voltage value to the second target voltage value such that the voltage value of the second output voltage matches the second target voltage value during the first ramp interval, and the second target voltage value during the second ramp interval. | 2021-10-07 |
20210312970 | SEMICONDUCTOR DEVICE, OPERATION METHOD THEREOF, AND ELECTRONIC DEVICE - A semiconductor device having a novel structure is provided. The semiconductor device includes a first transistor one of a source and a drain of which is electrically connected to a first wiring for reading data; a second transistor one of a source and a drain of which is electrically connected to a gate of the first transistor and the other of the source and the drain of which is electrically connected to a second wiring for writing the data; and a third transistor one of a source and a drain of which is electrically connected to the gate of the first transistor and the other of the source and the drain of which is electrically connected to a capacitor for retaining electric charge corresponding to the data, and the third transistor includes a metal oxide in a channel formation region. | 2021-10-07 |
20210312971 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING SYSTEM, AND SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, an information processing apparatus includes a connector into which a first-type semiconductor storage device operating with n types of power supply voltages or a second-type semiconductor storage device operating with m types of power supply voltages less than the n types of power supply voltages is capable of being placed. The apparatus checks whether or not a notch is formed at a predetermined position of a semiconductor storage device placed into the connector, and supplies the m types of power supply voltages to the semiconductor storage device when the notch is formed at the predetermined position. | 2021-10-07 |
20210312972 | APPARATUS, SYSTEM AND METHOD TO DETECT AND IMPROVE AN INPUT CLOCK PERFORMANCE OF A MEMORY DEVICE - A method, apparatus and system. The method includes: performing one or more training iterations to tune a target clock signal frequency to be applied at a memory device, each of the one or more training iterations including: causing a modified clock signal frequency to be applied at the memory device; and decoding a quality feedback message from the memory device including an indication of a performance of the clock signal frequency at the memory device; and in response to a determination that the performance of the clock signal frequency falls within a target performance range of the memory device and that the clock signal frequency is below the target clock signal frequency, performing a subsequent training iteration of the one or more training iterations, and otherwise causing application at the memory device, during a memory operation, of a highest clock signal frequency corresponding to a training iteration for which performance of the clock signal was within the target performance range. | 2021-10-07 |
20210312973 | NON-VOLATILE MEMORY DEVICE AND CONTROL METHOD - A non-volatile memory device and a control method are provided e disclosed. The non-volatile memory device includes a memory array, a bit line, a plurality of word lines, a first control circuit, and second control circuit. The bit line is connected to a first memory string of the memory array. The plurality of word lines are connected to memory cells of the first memory string and each word line is connected to a respective memory cell. The first control circuit is configured to apply a bit line pre-pulse signal to the bit line during a pre-charge period. The second control circuit is configured to apply a word line signal to a selected word line and apply a plurality of word line pre-pulse signals to word lines disposed between a select gate line and the selected word line. Voltage levels of the plurality of word line pre-pulse signals are incremental. | 2021-10-07 |
20210312974 | SEMICONDUCTOR DEVICES - A semiconductor device includes a read write control circuit configured to generate first and second write command pulses from an external control signal for performing a write operation; a flag generation circuit configured to generate a write flag, a write shifting flag, an internal write flag and an internal write shifting flag based on the second write command pulse, a bank mode signal and a bank group mode signal; and a bank group selection signal generation circuit configured to store a bank address based on an write input control pulse generated from the second write command pulse in a bank mode, and output the stored bank address as a bank group selection signal based on a write output control pulse generated from the write flag. | 2021-10-07 |
20210312975 | MEMORY DEVICE - A memory device is disclosed, in which node contacts extend into a substrate, where they are come into electrical connection with active areas. This allows greater contact areas between the node contacts and the active areas and electrical connection of the node contacts with high ion concentration portions of the active areas. As a result, even when voids are formed in the node contacts, the node contacts can still possess desired connection performance. For node contacts allowed to contain voids, this enables them to be fabricated faster with lower difficulty, thus increasing manufacturing throughput of the memory device. | 2021-10-07 |
20210312976 | READ REFRESH OPERATION - Methods, systems, and devices for read refresh operations are described. A memory device may include a plurality of sub-blocks of memory cells. Each sub-block may undergo a quantity of access operations (e.g., read operations, write operations). Based on the quantity of access operations performed on any one sub-block over a period of time, a read refresh operation may be performed on the memory cells of the sub-block. A read refresh operation may refresh and/or restore the data stored to the memory cells of the sub-block, and be initiated based on the memory device receiving an operation code (e.g., from a host device). | 2021-10-07 |
20210312977 | MEMORY PROCESSING UNIT ARCHITECTURE - A memory processing unit architecture can include a plurality of memory regions and a plurality of processing regions interleaved between the plurality of memory regions. The plurality of processing regions can be configured to perform computation functions of a model such as an artificial neural network. Data can be transferred between the computation functions in respective memory processing regions. In addition, the memory regions can be utilized to transfer data between a computation function in one processing region and a computation function in another processing region adjacent to the given memory region. | 2021-10-07 |
20210312978 | ACCESS LINE GRAIN MODULATION IN A MEMORY DEVICE - Methods, systems, and devices for access line grain modulation in a memory device are described. A memory cell stack in a cross-point memory array may be formed. In some examples, the memory cell stack may comprise a storage element. A barrier material may be formed above the memory cell stack. The barrier material may initially have an undulating top surface. In some cases, the top surface of the barrier material may be planarized. After the top surface of the barrier material is planarized, a metal layer for an access line may be formed on the top surface of the barrier material. Planarizing the top surface of the barrier material may impact the grain size of the metal layer. In some cases, planarizing the top surface of the barrier material may decrease the resistivity of access lines formed from the metal layer and thus increase current delivery throughout the memory device. | 2021-10-07 |
20210312979 | Read Circuitry for Resistive Change Memories - Read circuitry for a memory cell of a resistive change memory is suggested, wherein a signal of a bit-line that is connected to the memory cell is compared with a reference signal, and wherein the reference signal is determined based on a first dummy circuit that determines a leakage current of memory cells addressed by the bit-line. Also, a corresponding method is provided. | 2021-10-07 |
20210312980 | MEMORY DRIVING DEVICE - A memory driving device, comprising a switch, a voltage setting circuit, and a bias control circuit. The switch is coupled to a memory at a node. The voltage setting circuit is coupled to the switch and configured to provide a set signal during a first period to turn on the switch, so as to generate current flowing through the switch to the memory unit. The bias control circuit is respectively coupled to the switch and the node, and, during a second period, continuously provides a bias signal to control the switch so as to adaptively adjust a value of the setting current of the switch. The configuration setting terminal is coupled to the voltage setting circuit and the bias control circuit to control the first and the second period. | 2021-10-07 |
20210312981 | Mux Decoder with Polarity Transition Capability - A decoder in an integrated circuit memory device having: a positive section having a first input line; a negative section having a second input line; and an output line connected from both the positive section and the negative section to a voltage driver connected to a memory cell. The positive section and the negative sections are controlled by a polarity control signal. When the polarity control signal indicates positive polarity, the positive section drives the output line according to signals received in the first input line; and when the polarity control signal indicates negative polarity, the negative section drives the output line according to signals received in the second input line. | 2021-10-07 |
20210312982 | NONVOLATILE MEMORY DEVICE INCLUDING TEMPERATURE COMPENSATION CIRCUIT - A nonvolatile memory device includes a differential current driver that receives a first differential signal and a second differential signal, which are based on a temperature, and generates a first compensation current and a second compensation current corresponding to a difference value between the first and second differential signals. A current mirror circuit copies a first current, which is a sum of a reference current and the first compensation current, to generate a second current having a same value as a value of the first current and regulates the reference current depending on a difference value of the second current and the second compensation current. A trimming circuit generates a program current or a read current based on the regulated reference current. | 2021-10-07 |
20210312983 | DISTINCT CHIP IDENTIFIER SEQUENCE UTILIZING UNCLONABLE CHARACTERISTICS OF RESISTIVE MEMORY ON A CHIP - Stochastic or near-stochastic physical characteristics of resistive switching devices are utilized for generating data distinct to those resistive switching devices. The distinct data can be utilized for applications related to electronic identification. As one example, data generated from physical characteristics of resistive switching devices on a semiconductor chip can be utilized to form a distinct identifier sequence for that semiconductor chip, utilized for verification applications for communications with the semiconductor chip or utilized for generating cryptographic keys or the like for cryptographic applications. | 2021-10-07 |
20210312984 | DISTINCT CHIP IDENTIFIER SEQUENCE UTILIZING UNCLONABLE CHARACTERISTICS OF RESISTIVE MEMORY ON A CHIP - Stochastic or near-stochastic physical characteristics of resistive switching devices are utilized for generating data distinct to those resistive switching devices. The distinct data can be utilized for applications related to electronic identification. As one example, data generated from physical characteristics of resistive switching devices on a semiconductor chip can be utilized to form a distinct identifier sequence for that semiconductor chip, utilized for verification applications for communications with the semiconductor chip or utilized for generating cryptographic keys or the like for cryptographic applications. | 2021-10-07 |
20210312985 | DISTINCT CHIP IDENTIFIER SEQUENCE UTILIZING UNCLONABLE CHARACTERISTICS OF RESISTIVE MEMORY ON A CHIP - Stochastic or near-stochastic physical characteristics of resistive switching devices are utilized for generating data distinct to those resistive switching devices. The distinct data can be utilized for applications related to electronic identification. As one example, data generated from physical characteristics of resistive switching devices on a semiconductor chip can be utilized to form a distinct identifier sequence for that semiconductor chip, utilized for verification applications for communications with the semiconductor chip or utilized for generating cryptographic keys or the like for cryptographic applications. | 2021-10-07 |
20210312986 | DISTINCT CHIP IDENTIFIER SEQUENCE UTILIZING UNCLONABLE CHARACTERISTICS OF RESISTIVE MEMORY ON A CHIP - Stochastic or near-stochastic physical characteristics of resistive switching devices are utilized for generating data distinct to those resistive switching devices. The distinct data can be utilized for applications related to electronic identification. As one example, data generated from physical characteristics of resistive switching devices on a semiconductor chip can be utilized to form a distinct identifier sequence for that semiconductor chip, utilized for verification applications for communications with the semiconductor chip or utilized for generating cryptographic keys or the like for cryptographic applications. | 2021-10-07 |
20210312987 | STRESSING ALGORITHM FOR SOLVING CELL-TO-CELL VARIATIONS IN PHASE CHANGE MEMORY - A process is provided to trim PCRAM cells to have consistent programming curves. Initial programming curves of PCRAM cells are measured. A target programming curve is set up for the PCRAM cells. Each PCRAM cell is then modulated individually to meet the target programming curve. | 2021-10-07 |
20210312988 | VARIABLE RESISTANCE MEMORY WITH LATTICE ARRAY USING ENCLOSING TRANSISTORS - A variable resistance memory array, programming a variable resistance memory element and methods of forming the array. A variable resistance memory array is formed with a plurality of word line transistors surrounding each phase change memory element. To program a selected variable resistance memory element, all of the bitlines are grounded or biased at the same voltage. A top electrode select line that is in contact with the selected variable resistance memory element is selected. The word line having the word line transistors surrounding the selected variable resistance memory element are turned on to supply programming current to the element. Current flows from the selected top electrode select line through the variable resistance memory element into the common source/drain region of the surrounding word line transistors, across the transistors to the nearest bitline contacts. The word lines are patterned in various lattice configurations | 2021-10-07 |
20210312989 | NONVOLATILE MEMORY DEVICE AND OPERATION METHOD THEREOF - A nonvolatile memory device and an operating method are provided. The nonvolatile memory device includes a memory cell array including a plurality of planes, each plane including a plurality of memory blocks, an address decoder connected to the memory cell array, a voltage generator configured to apply an operating voltage to the address decoder, a page buffer circuit including page buffers corresponding to each of the planes, a data input/output circuit connected to the page buffer circuit configured to input and output data and a control unit configured to control the operation of the address decoder, the voltage generator, the page buffer circuit, and the data input/output circuit, wherein the control unit is configured to operate in a multi-operation or a single operation by checking whether a memory block of an access address is a bad block. | 2021-10-07 |
20210312990 | METHOD, ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF FOR PERFORMING PROGRAMMING MANAGEMENT - A memory device includes a non-volatile (NV) memory including a plurality of NV memory elements. A method for performing programming management of the NV memory includes: setting a programming sequence of the NV memory elements; determining a selection interval between each of the NV memory elements according to the programming sequence and a serial number of each of the NV memory elements; for a target NV memory element of the plurality of NV memory elements in the programming sequence, determining a serial number of an immediately previous NV memory element in the programming sequence according to the selection interval and a serial number of the target NV memory element; determining whether the immediately previous NV memory element is in a busy state; and only when the immediately previous NV memory element is not in the busy state, programming the target NV memory element. | 2021-10-07 |
20210312991 | SEMICONDUCTOR DEVICE - A semiconductor device is provided which includes: a first group including a plurality of first memory blocks; a second group including a plurality of second memory blocks; a first common source line connected to the first group; a second common source line connected to the second group; a source line voltage supplying circuit supplying a source line voltage; a first switch controlling a connection between the first common source line and the source line voltage supplying circuit; and a second switch controlling a connection between the second common source line and the source line voltage supplying circuit. When one first memory block among the plurality of first memory blocks of the first group is selected, the first switch may be turned on, and the second switch may be turned off. | 2021-10-07 |
20210312992 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes a bit line, a memory cell transistor electrically connected to the bit line, and a sense amplifier that reads data from the memory cell transistor via the bit line. During an operation of determining first data and second data, while continuously applying a first voltage to a gate of the memory cell transistor, the sense amplifier first determines the first data based upon a second voltage, and then determines the second data based upon a third voltage lower than the second voltage. | 2021-10-07 |
20210312993 | MEMORY DEVICE AND METHOD OF OPERATING THE SAME - Provided herein is a memory device and a method of operating the same. The memory device may include a memory block, a voltage generation circuit configured to operate in a first mode in which an operating voltage is generated using an internal voltage or a second mode in which the operating voltage is generated using an external voltage, and to provide the operating voltage to the memory block, and a control logic configured to measure and store a first rising time during which the operating voltage rises to a target level in the first mode, and to control the voltage generation circuit so that a second rising time during which the operating voltage rises to the target level in the second mode is equal to or longer than the first rising time. | 2021-10-07 |
20210312994 | APPARATUS FOR DETERMINING AN EXPECTED DATA AGE OF MEMORY CELLS - Apparatus including an array of memory cells, and a controller configured to cause the apparatus to determine a first value indicative of a number of memory cells of a plurality of memory cells that are activated in response to a control gate voltage having a particular voltage level, compare the first value to a plurality of second values, and determine an expected data age of the plurality of memory cells or a plurality of read voltages in response to the comparison of the first value to the plurality of second values. | 2021-10-07 |
20210312995 | RESISTIVE RANDOM ACCESS MEMORY ERASE TECHNIQUES AND APPARATUS - A method for erasing a memory cell includes applying a first erase to memory cells to erase the memory cells, wherein first memory cells are in a weakly erased state in response to the first erase, and wherein second memory cells are in a normally erased state in response to the first erase, thereafter applying a first weak program to the memory cells, wherein the second memory cells enter a programmed state and the third memory cells remain in the erased state in response to the first weak program, and thereafter applying a read to the memory cells to identify the second memory cells, and applying a second erase to the second memory cells to thereby erase the second memory cells. | 2021-10-07 |
20210312996 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF SHORTENING ERASE TIME - In a memory cell array, a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix. A control circuit controls the potentials of said plurality of word lines and said plurality of bit lines. In an erase operation, the control circuit erases an n number of memory cells (n is a natural number equal to or larger than 2) of said plurality of memory cells at the same time using a first erase voltage, carries out a verify operation using a first verify level, finds the number of cells k (k≤n) exceeding the first verify level, determines a second erase voltage according to the number k, and carries out an erase operation again using the second erase voltage. | 2021-10-07 |
20210312997 | SEMICONDUCTOR MEMORY STRUCTURE - A semiconductor memory device includes a first word line formed over a first active region. In some embodiments, a first metal line is disposed over and perpendicular to the first word line, where the first metal line is electrically connected to the first word line using a first conductive via, and where the first conductive via is disposed over the first active region. In some examples, the semiconductor memory device further includes a second metal line and a third metal line both parallel to the first metal line and disposed on opposing sides of the first metal line, where the second metal line is electrically connected to a source/drain region of the first active region using a second conductive via, and where the third metal line is electrically connected to the source/drain region of the first active region using a third conductive via. | 2021-10-07 |
20210312998 | ONE-TIME PROGRAMMABLE MEMORY AND AN OPERATION METHOD THEREOF - A one-time programmable (OTP) memory cell is disclosed, which comprises an electric fuse structure, an anti-fuse transistor and a word select transistor. One end of the electric fuse structure is electrically connected to a gate of the anti-fuse transistor to form a first port of the OTP memory cell, the other end of the electric fuse structure is electrically connected to a source of the anti-fuse transistor and is connected to a drain of the word select transistor, and a gate and a source of the word select transistor form a second port and a third port of the OTP memory cell respectively. The operation method of the OTP memory cell has the capability of one-time correction, expanding the practicability of the OTP memory cell. | 2021-10-07 |
20210312999 | TEST DEVICE FOR MEMORY, METHOD FOR DETECTING HARDWARE FAILURE IN MEMORY DEVICE, AND TEST APPARATUS OF MEMORY ARRAY - A testing device for memory includes a memory array and a test apparatus. The test apparatus includes a controller and a pattern generator. The pattern generator generates a background data, a first pattern data, and a second pattern data. The controller sets up the background data to a to-be-tested memory sub-array of the memory sub-arrays, performs a first memory test operation with the to-be-tested memory sub-array according to the first pattern data for detecting whether the hardware failure of the to-be-tested memory sub-array is occurred during the first memory test operation. The controller performs a second memory test operation with the to-be-tested memory sub-array according to the second pattern data for detecting whether the hardware failure of the to-be-tested memory sub-array is occurred during the second memory test operation in response to the hardware failure of the to-be-tested memory sub-array is not occurred during the first memory test operation. | 2021-10-07 |
20210313000 | APPARATUS AND METHOD FOR TESTING A DEFECT OF A MEMORY MODULE AND A MEMORY SYSTEM - The present application discloses an apparatus for testing defects of a memory module comprises a central buffer for generating a test write command and a test read command to indicate testing to a target address in a memory module; and a data buffer coupled to the central buffer to receive the test write command and the test read command; the data buffer is configured to, in response to the test write command, use target data as repair data corresponding to the target address, and write the target data into the memory module; and, in response to the test read command, to read target data from the target address and compare the target data with the repair data, and to send to the central buffer a comparison result of the target data and the repair data; the central buffer is further configured to record the target address as a tested address when generating the test write command, and determine whether to add the tested address to defective address information based on the comparison result associated with the tested address, defective address information is to indicate one or more defective memory addresses in the memory module. | 2021-10-07 |
20210313001 | MEMORY DEVICE AND TEST METHOD THEREOF - A memory device includes: a plurality of sense amplifier circuits sensing a data bit in response to a parallel test signal from a plurality of banks; a plurality of comparators comparing the data bit from each of the plurality of sense amplifier circuits with a test bit; and a logic circuit receiving output signals of the plurality of comparators and outputting a test result, wherein each of the plurality of comparators receives the test bit, an evolved parallel bit test (PBT) signal, at least one test ignore signal, and a test pass signal, and compares the data bit and the test bit in response to the evolved parallel bit test (PBT) signal, the at least one logic state test setting signal, and the test pass signal, and passes a corresponding bank regardless of a test operation in response to the test pass signal. | 2021-10-07 |
20210313002 | METHOD FOR READING AND WRITING AND MEMORY DEVICE - The embodiments provide a method for reading and writing and a memory device. The method includes: applying a read command to the memory device, the read command pointing to address information; reading data to be read out from a memory cell corresponding to the address information pointed to by the read command; storing the address information pointed to by the read command into a memory bit of a preset memory space if an error occurs in the data to be read out, wherein the preset memory space is provided with a plurality of the memory bits, each of the plurality of memory bits being associated with a spare memory cell; and backing up the address information stored in the preset memory space into a non-volatile memory cell according to a preset rule. | 2021-10-07 |
20210313003 | METHOD FOR READING AND WRITING AND MEMORY DEVICE - The embodiments provide a method for reading and writing and a memory device. The method includes: applying a read command to the memory device, the read command pointing to address information; reading data to be read out from a memory cell corresponding to the address information pointed to by the read command; and setting a mark of the address information pointed to by the read command as invalid if an error occurs in the data to be read out, and backing up the address information pointed to by the read command and the mark into a non-volatile memory cell according to a preset rule. | 2021-10-07 |
20210313004 | MEMORY - A memory includes a plurality of memory dies that includes a plurality of memory regions stacked on each other, the plurality of memory regions including a memory cell region that stores data and a redundant cell region that stores data as an alternative when a part of the memory cell region fails; a multiplexer that outputs data supplied to a local memory region or data supplied to another memory region to the redundant cell region of the local memory region on a basis of an input selection signal from outside; and a selector that outputs data output from the redundant cell region of the local memory region or data output from the redundant cell region of the other memory region to a data terminal of the local memory region on a basis of an output selection signal from outside. | 2021-10-07 |
20210313005 | APPARATUS AND METHOD FOR REPAIRING A DEFECT OF A MEMORY MODULE, AND A MEMORY SYSTEM - The present application discloses an apparatus for repairing a defect of a memory module, comprises: a central buffer having an address recording module for recording defective address information indicating one or more defective memory addresses in the memory module; the central buffer is configured to receive an access command for accessing a target address in the memory module from a memory interface, and to determine whether to generate a repair access command for repairing the target address according to a comparison result; and a data buffer having a data recording module for recording repair data; wherein the data buffer is coupled between the memory interface and the memory module to buffer data interacted therebetween, and is coupled to the central buffer to receive the access command or the repair access command; the data buffer is configured to write target data associated with the access command into the data recording module as repair data corresponding to a target address according to the repair access command, or read repair data from the data recording module as target data corresponding to a target address. | 2021-10-07 |
20210313006 | Cancer Classification with Genomic Region Modeling - Methods and systems for detecting cancer and/or determining a cancer tissue of origin are disclosed. Fragments are grouped into genomic regions, wherein a region model is trained for each genomic region. Fragments are input into the region models, and the outputs are used to generate a feature vector for cancer classification. In one embodiment, the region models are shallow neural networks configured to generate a score indicating a likelihood that a fragment is derived from a cancer biological sample. The feature vector is determined based on counts of fragments having scores above threshold scores for the various genomic regions. In another embodiment, the regions models are configured to generate a region embedding for an input methylation embedding of a fragment. The region embeddings are pooled by region and then pooled again to generate the feature vector. | 2021-10-07 |
20210313007 | A METHOD FOR IDENTIFYING INTERMEDIATES - A method for identifying target protein folding intermediates, suitable to be tested as targets for drug discovery procedures. The method is carried out by means of electronic computing. The method provides a step of modelling a sequence in time of events defining a folding pathway of a protein, which includes modelling and/or calculating structural and/or energy and/or physical-chemical properties of one or more protein folding intermediate states along the folding pathway. Then, the method includes identifying at least one candidate protein folding intermediate, along the modelled folding pathway, based on identification properties, and selecting one or more target protein folding intermediates, among the at least one candidate protein folding intermediate, based on selection properties. The selection properties are related to the druggability of the protein folding intermediate. A related method for in silico drug discovery based on folding intermediate targeting is also provided. | 2021-10-07 |
20210313008 | MACHINE LEARNING FOR DETERMINING PROTEIN STRUCTURES - Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for performing protein structure prediction and protein domain segmentation. In one aspect, a method comprises generating a plurality of predicted structures of a protein, wherein generating a predicted structure of the protein comprises: updating initial values of a plurality of structure parameters of the protein, comprising, at each of a plurality of update iterations: determining a gradient of a quality score for the current values of the structure parameters with respect to the current values of the structure parameters; and updating the current values of the structure parameters using the gradient. | 2021-10-07 |
20210313009 | HARDWARE ACCELERATED K-MER GRAPH GENERATION - Methods, systems, and apparatus for hardware-accelerated generation of a K-mer graph using a programmable logic device. In one aspect, a method includes actions of obtaining a first set of nucleic acid sequences, generating a K-mer graph using the obtained first set of nucleic acid sequences and using a plurality of non-pipelined hardware logic units of a programmable logic device, and periodically updating, with a control machine, graph description data for the K-mer graph after performance of the one or more operations by each hardware logic unit. | 2021-10-07 |
20210313010 | METHODS AND SYSTEMS FOR A DIGITAL PCR EXPERIMENT DESIGNER - A computer-implemented method for designing a digital PCR (dPCR) experiment is provided. The method includes receiving, from a user, a selection of optimization type. The optimization type may be maximizing the dynamic range, minimizing the number of substrates including reaction sites needed for the experiment, determining a dilution factor, or determining the lower limit of detection, for example. The method further includes receiving, from the user, a precision measure for an experiment, and a minimum concentration of a target in a reaction site for the experiment. The method also includes determining a set of dPCR experiment design factors for the experiment based on the optimization type. The set of dPCR experiment design factors is then displayed to the user. | 2021-10-07 |
20210313011 | GENOMIC SEQUENCING SELECTION SYSTEM - The systems and methods discussed herein can calculate sequencing statistics such as coverage depth for sequencing data. The present solution can determine variant frequencies and identify clinically relevant variants. The present solution can read BAM and VCF input files and Phred scaled quality scores. The present solution can select relatively high quality reads based on the quality scores and can calculate reference and alternative allele counts for SNPs, insertions and deletions (INDELs), and structural variants. | 2021-10-07 |
20210313012 | DIFFERENCE-BASED GENOMIC IDENTITY SCORES - Methods for analyzing omics data and using the omics data to determine genetic distances and/or difference scores among a plurality of biological samples to so further determine the homogeneity of a group having a plurality of biological samples and/or exclude an individual biological sample from a group of biological samples as an outlier are presented. In preferred methods, a plurality of local differential string sets among the plurality of sequence strings is generated using a plurality of local alignments. The local different string is an indicative of genetic difference between one sequence string and one of the rests of the sequence strings among the plurality of sequence strings. From the plurality of local differential string sets, a plurality of difference scores among the plurality of sequence strings can be determined. | 2021-10-07 |
20210313013 | FINDING RELATIVES IN A DATABASE - Determining relative relationships of people who share a common ancestor within at least a threshold number of generations includes: receiving recombinable deoxyribonucleic acid (DNA) sequence information of a first user and recombinable DNA sequence information of a plurality of users; processing, using one or more computer processors, the recombinable DNA sequence information of the plurality of users in parallel; determining, based at least in part on a result of processing the recombinable DNA information of the plurality of users in parallel, a predicted degree of relationship between the first user and a user among the plurality of users, the predicted degree of relative relationship corresponding to a number of generations within which the first user and the second user share a common ancestor. | 2021-10-07 |
20210313014 | Bioinformatics Systems, Apparatuses, and Methods Executed on an Integrated Circuit Processing Platform - A system, method and apparatus for executing a sequence analysis pipeline on genetic sequence data includes an integrated circuit formed of a set of hardwired digital logic circuits that are interconnected by physical electrical interconnects. One of the physical electrical interconnects forms an input to the integrated circuit connected with an electronic data source for receiving reads of genomic data. The hardwired digital logic circuits are arranged as a set of processing engines, each processing engine being formed of a subset of the hardwired digital logic circuits to perform one or more steps in the sequence analysis pipeline on the reads of genomic data. Each subset of the hardwired digital logic circuits is formed in a wired configuration to perform the one or more steps in the sequence analysis pipeline. | 2021-10-07 |
20210313015 | SPECIFICALLY-SHAPED CRYSTAL OF COMPOUND AND METHOD FOR PRODUCING SAME - The present invention provides a method for obtaining a specifically-shaped crystal (specifically, spherocrystal) of a compound with good reproducibility. This method for producing a specifically-shaped crystal (specifically spherocrystal) of a compound comprises: (1) a step for preparing a supersaturated solution of a compound having a degree of supersaturation equal to or higher than a critical degree of supersaturation; and (2) a step for precipitating a specifically-shaped crystal (specifically spherocrystal) of a compound from the supersaturated solution. | 2021-10-07 |
20210313016 | MACHINE-LEARNING METHOD AND APPARATUS TO ISOLATE CHEMICAL SIGNATURES - A processing workflow centered on machine-learning algorithms that identifies a number of chemical features that can best distinguish the presence or absence of a chemical source. These chemical features are a chemical fingerprint that is unique to each source. The analysis workflow is rapid (e.g., fingerprints can be generated in minutes). The analysis workflow has wide-ranging applications such as detecting markers of pollution sources in rivers and fish tissues, forest pathogen outbreaks, and hard-to-diagnose diseases. | 2021-10-07 |
20210313017 | PERSONALIZED OFFLINE RETRIEVAL OF DATA - An approach is disclosed for a method, a system, and a computer program product for storing information tailored to a user and a condition to be accessed offline on a local device. The information is retrieved from a set of online sources. The retrieved information is tailored according to a criteria and the condition to form a curated data. The curated data is on the local device. An index is provided to access a selected portion of the curated data. The index is used to answer queries from the user. Responsive to identifying a question without an answer identified in the retrieved content, searching for the answer when the device is online. Responsive to finding the answer online, updating the curated data stored on the local device. | 2021-10-07 |
20210313018 | PATIENT ASSESSMENT SUPPORT DEVICE, PATIENT ASSESSMENT SUPPORT METHOD, AND RECORDING MEDIUM - A patient assessment support device includes an output unit which outputs estimated support information estimated based on question information relating to nursing care for a patient when a record of known support information relating to the patient is determined as being absent. | 2021-10-07 |
20210313019 | System and Method for Synthetic Interaction with User and Devices - Systems and methods for conducting automated synthetic interactions with a user, such as a patient at home following a medical procedure. A digital coach having a processor and memory initiates a session with a user's interactive device, and presents pre-recorded scripts as video and/or audio through the interactive device. The user's responses are received by the digital coach through the interactive device. Peripheral devices, such as medical devices, may be used by the user or controlled by the digital coach to obtain data measurements regarding the physiological condition of the user. The processor of the digital coach analyzes the data from the user responses and devices, and semantically interprets the responses and data to determine the next action and script to present the user in the session. The digital coach provides a conversational, dynamic, adaptive session with a user based on semantically expanded interpretations of data by the processor. | 2021-10-07 |
20210313020 | METHOD AND APPARATUS FOR REHABILITATION TRAINING OF COGNITIVE FUNCTION - Disclosed are a method and an apparatus for rehabilitation training of a cognitive function. A method for rehabilitation training of a cognitive function may comprise the steps of: performing a cognitive function test by a cognitive rehabilitation service server; receiving a cognitive function test result of the cognitive function test by the cognitive rehabilitation service server; determining a rehabilitation method matching the cognitive function test result, by the cognitive rehabilitation service server; and providing a user device with a rehabilitation content according to the rehabilitation method so as to perform rehabilitation training, by the cognitive rehabilitation service server. | 2021-10-07 |
20210313021 | HEALTH INFORMATION EXCHANGE SYSTEM - The method includes receiving a request for relevant subject health information associated with a subject for a clinical trial; matching a subject identifier associated with the subject to a patient identifier; transmitting a health data query comprising the patient identifier to at least one of an electronic health record (EHR) system or a data transfer application programming interface to obtain EHR data associated with the subject; receiving the EHR data associated with the patient identifier; parsing the EHR data into relevant EHR data and nonrelevant EHR data; applying an EDC mapping function to the relevant EHR data; and/or producing EDC clinical data in a final standardized data set usable in an EDC system in response to the applying the EDC mapping function to the relevant EHR data. | 2021-10-07 |
20210313022 | ENGINE FOR AUGMENTED MEDICAL CODING - A method for real-time, augmented coding classification of text inputs is provided. The method includes receiving a string input from a client device, the string input being part of a technical chart for a user of the client device, wherein the user is associated with a healthcare provider and the string input comprises a healthcare report of a patient. The method also includes standardizing the string input according to a set of technical rules, storing the string input in a database, and providing at least a portion of the string input to a processing circuit. The method also includes receiving, from the processing circuit, a code associated with the string input, causing a display in the client device to display the code for the user and providing, to the remote client, a result associated with the technical input data. A system to perform the above method is also provided. | 2021-10-07 |
20210313023 | HELP NOW SYSTEM - The subject technology is in the technical field of immediate crisis management for patients who are under physical, mental, or emotional distress, and who are in remote or difficult-to-access-locations. In particular, the subject technology serves such patients who recognize during “moments of clarity” that they need and want immediate help. Yet, they may be reluctant to seek help under normal circumstances because of a need to conceal the problem from others. The subject technology is a system and methods using cellular, Internet, geo-location, and other technology that make assistance available upon a simple action (clicking an icon), and deliverable through mobile or desktop devices. The system accommodates patients who remain anonymous, with information continuity across anonymous session, and those who choose to identify themselves in order to seek more extensive assistance. | 2021-10-07 |
20210313024 | ADMINISTRATION MANAGING APPARATUS, ADMINISTRATION MANAGING METHOD, AND PROGRAM - A target hemoglobin level of a patient; a current hemoglobin level of the patient; a specific decrease amount per unit period indicating an amount of decrease of a hemoglobin level of the patient when an erythropoiesis stimulating agent is not administered during the unit period; and a specific increase amount per unit period being an amount of increase of the hemoglobin level of the patient when an erythropoiesis stimulating agent at a maximum allowable unit amount per unit period is administered during the unit period and indicating a relative amount of increase in which the hemoglobin level when the erythropoiesis stimulating agent is not administered during the unit period is used as a reference are acquired. Furthermore, an amount of erythropoiesis stimulating agent to be administered to the patient per unit period is calculated on the basis of these pieces of information. | 2021-10-07 |
20210313025 | Deduplication of Medical Concepts from Patient Information - Mechanisms are provided to implement a patient summary generation engine with deduplication of instances of medical concepts. The patient summary generation engine parses a patient electronic medical record (EMR) to extract a plurality of instances of a medical concept, at least two of which utilize different representations of the medical concept. The patient summary generation engine performs a similarity analysis between each of the instances of a medical concept to thereby calculate, for a plurality of combinations of instances of the medical concept, a similarity metric value. The patient summary generation engine clusters the instances of the medical concept based on the calculated similarity metric values for each combination of instances in the plurality of combinations of instances of the medical concept to thereby generate one or more clusters, and select a representative instance of the medical concept from each cluster in the one or more clusters. The patient summary generation engine generates a summary output of the patient EMR comprising the selected representative instances of the medical concept from each cluster. | 2021-10-07 |
20210313026 | SYSTEMS AND METHODS FOR ACCELERATED EPIDEMIC RECOVERY - A method comprising receiving, from a user device, a user identifier, the user identifier being associated with a user of the user device, confirming that the user's identity has been confirmed, retrieving, from a remote health record maintained by a third-party health service provider, health information regarding a virus-related test provided on the user, providing a virus-related test status based on the virus-related test results to the user device, receiving an invalidity indication from the third-party health-related entity, the invalidity indication indicating that a particular test is no longer considered valid, reviewing a record of the user to confirm if the user received the particular test, determining that the virus-related test is no longer valid based on the invalidity indication, providing a notice to the user device that the virus-related test status is no longer considered to be valid, and providing an update to the virus-related test status. | 2021-10-07 |
20210313027 | SYSTEM AND METHOD FOR VISUALIZING THE ELECTRONIC HEALTH RECORD USING A PATTERNED TIMELINE - A system and method for creating a patterned timeline that is representative of a patient's medical history is provided. The system generally comprises a processor, a power supply, a display operably connected to the processor, a non-transitory computer-readable medium coupled to the processor and having instructions stored thereon, and a database operably connected to the processor. The processor may query the non-transitory computer-readable medium and/or database for patient health records and parse the patient health records for event data, which may be used to create medical events. The processor may then may then create patterned timelines within the user interface using the medical events so that a healthcare professional may visually navigate a patient's medical history. | 2021-10-07 |
20210313028 | PHYSIOLOGICAL MONITORING SYSTEM - A method of monitoring a patient for phrenic nerve collateral damage during a cardiac ablation procedure. The method includes measuring at least one from the group consisting of compound motor action potential (CMAP) and accelerometer signals in response to stimulating of the phrenic nerve. Real-time data is displayed on a display, the real-time data including the at least one from the group consisting of the measured CMAP and accelerometer signals. Long-term trend data is simultaneously displayed on the display, the long-term trend data being associated with the measured at least one from the group consisting of CMAP and accelerometer signals. | 2021-10-07 |
20210313029 | SYSTEM AND METHOD FOR PROMOTING A CHANGE IN CONSUMER SMOKING HABITS - A method of assisting smoking cessation is provided, including: measuring a level of a toxicant in a user; displaying the measured level of the toxicant to the user; providing the user with a heated tobacco product or an electronic smoking device; measuring a new level of the toxicant in the user after a period of use of the heated tobacco product or the electronic smoking device; and displaying the new level of the toxicant to the user. A toxicant testing station is also provided, including: a toxicant testing device to detect a level of a toxicant in a user; a processing device connected to the testing device; and a display device connected to the processing device, the processing device to provide to the display device a graphical representation of the level of toxicant detected by the testing device in comparison to an average level of toxicant within a population. | 2021-10-07 |
20210313030 | METHOD, APPARATUS, AND SYSTEM TO MANAGE PATIENT TREATMENT - A care plan risk rating (CPR | 2021-10-07 |
20210313031 | SYSTEM, METHODS, AND APPARATUS FOR REMOTE VERIFICATION OF PHARMACY PRESCRIPTION PREPARATION - A system, method, and apparatus for pharmacy remote verification is disclosed. In an example, a pharmacy remote verification apparatus is configured to receive, from a local pharmacy system, a set of prescription fill information for remote verification for a plurality of prescriptions. The pharmacy remote verification apparatus creates an ordered list of the prescriptions based on an urgency such that a most urgent prescription is ordered first for review. The pharmacy remote verification apparatus receives, from a remote verifier device, a request message to review a prescription. In response, the pharmacy remote verification apparatus causes the first ordered prescription to be displayed on the remote verifier device. The remote verifier device may provide a verified message, which is relayed by the pharmacy remote verification apparatus to the local pharmacy system to enable the corresponding prescribed medication to be released to a patient. | 2021-10-07 |
20210313032 | SYSTEMS AND METHODS FOR DYNAMIC INTERACTIVE DRUG SAVINGS REPORTS SERVICES - Described herein are methods and systems for controlling the operation of one or more prescription cost savings systems, including methods and systems for the interactive and dynamic generation of Drug Savings Reports. | 2021-10-07 |
20210313033 | Monitoring System and Method for Biopharmaceutical Products - A monitoring system comprises a manufacture system with capability to manufacture a plurality of biopharmaceutical products, at least one image capture device arranged to capture a scene comprising the manufacture system, and a processing element connected to said at least one image capture device and arranged to process images captured by said at least one image capture device to track operator interactions and/or a result of operator interactions within the scene. The processing element is further is arranged to compare a predefined workflow process scheme relating to the selected biopharmaceutical product to at least a part of the tracked operator interactions with the manufacture system and/or to at least a part of the result of the tracked operator interactions with the manufacture system, and determine whether at least one pre-set criterion set by the workflow process scheme is fulfilled based on the comparison. | 2021-10-07 |
20210313034 | MEDICAL DRUG VERIFICATION DEVICE, MEDICAL DRUG VERIFICATION METHOD, AND MEDICAL DRUG VERIFICATION SYSTEM - A medical drug verification device includes: an exterior information acquiring unit configured to acquire exterior information on a medical drug; a matching unit configured to perform matching between matching target information based on the exterior information and a reference information group of medical drugs stored in a storage device; a display control configured to cause a display device to display, based on the degree of the matching, candidates of reference information for a medical drug which is contained in the reference information group and corresponds to the exterior information; an accepting configured to accept selection of the reference information contained in the candidates; and a reflecting unit configured to reflect the exterior information and/or the matching target information corresponding to the selected reference information in the stored reference information group, wherein the reflecting unit performs the reflection when the degree of the matching for the selected reference information does not satisfy a predetermined criterion. | 2021-10-07 |
20210313035 | CONTROL METHOD FOR ELECTRONIC DEVICE, AND COMPUTER-READABLE RECORDING MEDIUM FOR STORING PROGRAM FOR PERFORMING SAME - A control method for an electronic apparatus, and a computer-readable recording medium for storing a program for performing same are provided. The control method for an electronic apparatus can transmit a payment request for medicine to an external device, receive medication information for the medicine from the external device in response to the payment request, store the medication information for the medicine, and provide a medication alarm for the medicine to a user on the basis of the stored medication information. | 2021-10-07 |
20210313036 | METHOD AND SYSTEM FOR THE SAFETY, ANALYSIS AND SUPERVISION OF INSULIN PUMP ACTION AND OTHER MODES OF INSULIN DELIVERY IN DIABETES - An insulin delivery supervisor (IDS) with a safety analysis and supervision function that can reside between the insulin request and the insulin delivery and can intercept any excessive insulin requests before the insulin was delivered. The IDS can be implemented in any system based on insulin pump or pen and will work with either SMBG or CGM modes of blood glucose monitoring. | 2021-10-07 |
20210313037 | EARLY EXERCISE DETECTION FOR DIABETES MANAGEMENT - A system, techniques, and computer-readable media includes examples that provide an indication of an early exercise detection are described. An example of an early exercise detection application executed by a processor may cause the processor to perform functions and be operable to obtain image data including metadata from a camera of a mobile device during, for example, an unlock procedure of a mobile device. The processor may determine whether the obtained image data includes location or timestamp information in metadata or has image data that may be recognized as exercise-related objects. Based on the determinations, the processor may output an indication of early exercise detection to an artificial pancreas application, which is operable to adjust an amount of insulin to be delivered to a user. | 2021-10-07 |
20210313038 | METHODS AND APPARATUS FOR VIRTUAL COMPETITION - A system configured to be coupled with a participant of an activity. The system comprises: a participant activity monitoring unit configured for monitoring a performance of the activity by the participant; an activity information module configured for storing performance information corresponding to the activity; and a participant performance correlator configured for delivering comparative performance data based on the monitored performance of the activity by the participant and the stored performance information. | 2021-10-07 |
20210313039 | Systems and Methods for Diet Quality Photo Navigation Utilizing Dietary Fingerprints for Diet Assessment - Embodiments of the present disclosure are related to systems, methods, and computer-readable medium for image-based diet assessment. Image vignettes can form digital fingerprints that are derived from composite images of dietary patterns over a period of time, where the images can correspond to a grid of diet types and diet quality levels. Embodiments of the present disclosure include an image vignette generation and rendering process that is controlled based on a hierarchical algorithm and properties of the devices upon which the image vignettes are rendered. | 2021-10-07 |
20210313040 | EXPERT-DRIVEN, TECHNOLOGY-FACILITATED INTERVENTION SYSTEM FOR IMPROVING INTERPERSONAL RELATIONSHIPS - A method for promoting interpersonal interactions includes a step of receiving data streams from a plurality of mobile smart devices from a plurality of users, the data streams recording information about users' daily lives. Intervention signals are sent to a user in response to data acquired from two or more individuals and interpreted with respect to user internal states, moods, emotions, predetermined behaviors, and interactions with other users. | 2021-10-07 |