40th week of 2021 patent applcation highlights part 61 |
Patent application number | Title | Published |
20210313241 | SHAPE MEMORY POLYMER FOR USE IN SEMICONDUCTOR DEVICE FABRICATION - A method for forming a semiconductor structure includes curing a shape memory polymer in a first shape. The shape memory polymer is coupled to a conductive layer. The method further includes folding the shape memory polymer from the first shape into a second shape. The method also includes bonding a semiconductor wafer to the conductive layer while the shape memory polymer is in the second shape. The semiconductor wafer has first and second dies. The semiconductor wafer is then singulated to separate the first die from the second die. The method further includes expanding the shape memory polymer to its first shape and singulating the shape memory polymer to separate the first and second dies. | 2021-10-07 |
20210313242 | SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR APPARATUS LEAK INSPECTION METHOD - A semiconductor device, a leak detection device, an outer wall, and a separation wall are provided on a substrate. A first hollow structure in contact with the semiconductor device and a second hollow structure in contact with the leak detection device are separated by the separation wall and formed in a hermetically sealed state. At least a part of a portion of the leak detection device in contact with the second hollow structure is made of a corrodible metal or an alloy containing a corrodible metal. At least a part of the outer wall is in contact with the second hollow structure. | 2021-10-07 |
20210313243 | POWER MODULE - The present disclosure relates to a power module comprising a substrate, first and second pluralities of vertical power devices, and first and second terminal assemblies. The substrate has a top surface with a first trace and a second trace. The first plurality of vertical power devices and a second plurality of vertical power devices are electrically coupled to form part of a power circuit. The first plurality of vertical power devices are electrically and mechanically directly coupled between the first trace and a bottom of a first elongated bar of the first terminal assembly. The second plurality of vertical power devices are electrically and mechanically directly coupled between the second trace and a bottom of a second elongated bar of the second terminal assembly. | 2021-10-07 |
20210313244 | FINGERPRINT IDENTIFICATION CHIP PACKAGE AND METHOD FOR MAKING SAME - A fingerprint identification chip package of reduced thickness in not requiring a supporting substrate includes a packaging material layer, a fingerprint identification chip in the packaging material layer, conductive pillars in the packaging material layer for structural support, the pillars being spaced apart from the fingerprint identification chip, and a redistribution layer on a side of the packaging material layer. The redistribution layer includes connecting wires, each wire is electrically coupled between the fingerprint identification chip and one conductive pillar. A plurality of pins is on a side of the packaging material layer opposite to the redistribution layer, each pin is electrically coupled to one conductive pillar. | 2021-10-07 |
20210313245 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip having a passivation film, a stress relieving layer provided on the passivation film, and a groove formed in a periphery of a surface of the semiconductor chip, the groove being provided inside of an edge of the semiconductor chip, wherein the stress relieving layer is partly disposed in the groove. | 2021-10-07 |
20210313246 | SEMICONDUCTOR DIE INCLUDING EDGE RING STRUCTURES AND METHODS FOR MAKING THE SAME - Semiconductor devices laterally surrounded by at least one dielectric material portion are formed over a substrate. At least one edge seal ring structure is formed around the semiconductor devices and the at least one dielectric material portion. One or more of the at least one edge seal ring structure has a horizontal cross-sectional profile that includes laterally-extending regions that extend laterally with a uniform width between an inner sidewall and an outer sidewall, and notch regions connecting neighboring pairs of the laterally-extending regions and having a greater width than the uniform width. Cavities in the laterally-extending regions are connected to cavities in the notch regions to allow outgassing from the material of the at least one edge seal ring structure. | 2021-10-07 |
20210313247 | METHODS AND SYSTEMS FOR EVAPORATION OF LIQUID FROM DROPLET CONFINED ON HOLLOW PILLAR - A heat exchanger for thermal management of an electronic device includes a liquid delivery layer thermally coupled to the electronic device and configured to receive a liquid from a source. The heat exchanger also includes an evaporation layer comprising hollow pillars configured to receive a continuous flow of the liquid from the liquid delivery layer and evaporate the continuous flow of the liquid from droplets maintained on the hollow pillars. Each hollow pillar has an evaporation surface and a pore configured to channel the continuous flow of the liquid through the hollow pillar to the evaporation surface. The evaporation surface being configured to maintain a droplet on the respective hollow pillar within a contact line. The evaporation surface has a wetting efficiency of at least about 95% and the contact line has a length of less than about 0.0314 mm. | 2021-10-07 |
20210313248 | CIRCUIT BOARD WITH PHASE CHANGE MATERIAL - Various circuit board embodiments are disclosed. In one aspect, an apparatus is provided that includes a circuit board and a first phase change material pocket positioned on or in the circuit board and contacting a surface of the circuit board. | 2021-10-07 |
20210313249 | SEMICONDUCTOR MODULE AND VEHICLE - Provided is a semiconductor module including semiconductor devices and a cooling apparatus, wherein the semiconductor device has semiconductor chips and a circuit board with the semiconductor chips implemented thereon; the cooling apparatus has a top plate, a side wall, a bottom plate, a coolant flow portion, an inlet, an outlet and a plurality of fins; the top plate and the bottom plate have three through holes that are through holes for inserting fastening members that fasten the semiconductor module to an external apparatus, penetrating the top plate and the bottom plate in one direction respectively; and a geometric center of gravity of a aperture of at least one of the inlet and the outlet may also be positioned inside a virtual triangle with the three through holes being vertexes in planar view. | 2021-10-07 |
20210313250 | UNIBODY LATERAL VIA - A diode semiconductor structure is described. In one example, a diode device includes a substrate, a layer of first semiconductor material of a first doping type, a layer of intrinsic semiconductor material, and a layer of second semiconductor material of a second doping type. The diode device also includes a metal contact formed on the layer of first semiconductor material and a metal via formed from a backside of the substrate, through the substrate, and through the layer of first semiconductor material, where the metal via contacts a bottom surface of the metal contact on the layer of first semiconductor material. In this configuration, a direct electrical connection can be achieved between the backside of the substrate and the metal contact on the layer of first semiconductor material without the need for an additional metal connection, such as a metal air bridge, to the metal contact. | 2021-10-07 |
20210313251 | NOVEL THROUGH SILICON CONTACT STRUCTURE AND METHOD OF FORMING THE SAME - In a method for forming an integrated structure, a top dielectric layer is formed over a top surface of a substrate. The top dielectric layer includes a plurality of vias that are formed through the top dielectric layer and extend into the substrate. A bottom dielectric layer is formed on a bottom surface of the substrate. An isolation opening and a plurality of contact openings are further formed in the bottom dielectric layer and the substrate, where the isolation opening passes through the bottom dielectric layer and extends from the bottom surface to the top surface of the substrate. The isolation opening is filled with an insulating layer to form an isolation trench. The plurality of contact openings are filled with a conductive layer to form a plurality of through silicon contacts (TSCs). A conductive plate is further formed over the bottom dielectric layer. | 2021-10-07 |
20210313252 | HALF BURIED nFET/pFET EPITAXY SOURCE/DRAIN STRAP - A method is presented for reducing parasitic capacitance. The method includes forming a p-type epitaxial region and an n-type epitaxial region over a substrate, depositing an epitaxial growth over the p-type epitaxial region and the n-type epitaxial region, depositing a first dielectric between the p-type epitaxial region and the n-type epitaxial region such that an airgap is defined therebetween, and selectively removing the epitaxial growth to expose top surfaces of the p-type and n-type epitaxial regions. The method further includes depositing a second dielectric in direct contact with the exposed top surfaces of the p-type and n-type epitaxial regions, selectively etching the first and second dielectrics to form a strapped contact, and applying a metallization layer over the strapped contact. | 2021-10-07 |
20210313253 | SEMICONDUCTOR DEVICE, POWER CONVERSION DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes: a substrate; a semiconductor element arranged on the substrate; a plate-like member electrically connected to the semiconductor element; a first electrode formed on the semiconductor element and joined to the plate-like member with solder; a second electrode formed on the semiconductor element and spaced from the first electrode, and including a metal capable of forming an alloy with the solder; and a metal film formed on the semiconductor element and spaced from the second electrode in a region on the first electrode side as seen from the second electrode, in a two-dimensional view of the semiconductor element as seen from the plate-like member, and including a metal capable of forming an alloy with the solder. | 2021-10-07 |
20210313254 | PACKAGE STRUCTURE WITH PHOTONIC DIE AND METHOD - Provided is a package structure including a photonic die, an electronic die, a conductive layer, a circuit substrate, and an underfill. The electronic die is bonded on a front side of the photonic die. The conductive layer is disposed on a back side of the photonic die. The conductive layer includes a plurality of conductive pads and a dam structure between the conductive pads and a first sidewall of the photonic die. The circuit substrate is bonded on the back side of the photonic die through a plurality of connectors and the conductive pads. The underfill laterally encapsulates the connectors, the conductive pads, and the dam structure. The underfill at the first sidewall of the photonic die has a first height, the underfill at a second sidewall of the photonic die has a second height, and the first height is lower than the second height. | 2021-10-07 |
20210313255 | LEADLESS SEMICONDUCTOR PACKAGE WITH WETTABLE FLANKS AND METHOD FOR MANUFACTURING THE SAME - The present disclosure is directed to leadless semiconductor packages with improved wettable flanks that encourage the formation of solder fillets when the leadless semiconductor package is mounted to a substrate. The solder fillets are consistently formed and are easily detectable by inspection systems, such as automated optical inspection (AOI) systems. | 2021-10-07 |
20210313256 | POWER MODULE - The present disclosure describes a power module having a substrate, first and second pluralities of vertical power devices, and first and second terminal assemblies. The substrate has a top surface with a first trace and a second trace. The first plurality of vertical power devices and the second plurality of vertical power devices are electrically coupled to form part of a power circuit. The first plurality of vertical power devices is electrically and mechanically directly coupled between the first trace and a bottom of a first elongated bar of the first terminal assembly. The second plurality of vertical power devices are electrically and mechanically directly coupled between the second trace and a bottom of a second elongated bar of the second terminal assembly. | 2021-10-07 |
20210313257 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a first electrode terminal; a second electrode terminal; a semiconductor element having an electrode on one surface connected to one surface of the first electrode terminal; a wire that connects an electrode on the other surface of the semiconductor element and the second electrode terminal; and a resin portion formed of an insulator covering the semiconductor element, a part of the second electrode terminal, and the one surface of the first electrode terminal, wherein a chamfered portion is formed on at least one of end portions where the first electrode terminal and the second electrode terminal face each other. | 2021-10-07 |
20210313258 | HALL SENSOR PACKAGES - In some examples, a package comprises first and second terminals and a conductive pathway coupling the first and second terminals. The conductive pathway is configured to generate a magnetic field. The package comprises a conductive member aligned with and coupled to the conductive pathway. The conductive pathway and the conductive member have a common shape. The package also comprises an insulative layer coupled to the conductive member and a die coupled to the insulative layer and having a circuit configured to measure the magnetic field. The circuit faces the conductive pathway. | 2021-10-07 |
20210313259 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME - The present disclosure provides a semiconductor device package. The semiconductor device package includes a semiconductor substrate having a first surface and a first optical coupler disposed on the first surface of the semiconductor substrate. The first optical coupler includes a first surface facing away from the first surface of the semiconductor substrate and a first lateral surface connected to the first surface of the first optical coupler. The first surface of the first optical coupler and the first lateral surface of the optical coupler define an angle greater than 90 degrees. A method of manufacturing a semiconductor device package is also disclosed. | 2021-10-07 |
20210313260 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A semiconductor structure and a method for forming the semiconductor structure are provided. The semiconductor structure includes a substrate structure including a device region, a first interconnection structure, and a plurality of third interconnection layers. The device region includes a plurality of first regions and one or more second regions that are arranged along a first direction. The first interconnection structure includes a plurality of first interconnection layers and a plurality of second interconnection layers that are extended along a second direction. A first interconnection layer has a length greater than a second interconnection layer in the second direction, and the first direction is perpendicular to the second direction. A third interconnection layer is disposed over the second region, and the third interconnection layer is electrically interconnected with the second interconnection layer. The third interconnection layer has a length greater than the second interconnection layer in the second direction. | 2021-10-07 |
20210313261 | 3D IC DECOUPLING CAPACITOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor structure is disclosed. The semiconductor structure includes: a polymer base layer, a backside redistribution layer (RDL) over the polymer base layer; a molding layer over the backside RDL; a polymer layer over the molding layer, a front side RDL over the polymer layer; and a metal-insulator-metal (MIM) capacitor vertically passing through the molding layer, the MIM capacitor including a first electrode, an insulation layer and a second electrode, wherein the insulation layer surrounds the first electrode, and the second electrode surrounds the insulation layer, and the molding layer surrounds the second electrode. An associated method for manufacturing a semiconductor structure is also disclosed. | 2021-10-07 |
20210313262 | Hybrid Method for Forming Semiconductor Interconnect Structure - The present disclosure provides a method for forming semiconductor structures. The method includes providing a device having a substrate, a first dielectric layer over the substrate, and a first conductive feature over the first dielectric layer, the first conductive feature comprising a first metal, the first metal being a noble metal. The method also includes depositing a second dielectric layer over the first dielectric layer and covering at least sidewalls of the first conductive feature; etching the second dielectric layer to form a trench; and forming a second conductive feature in the trench. The second conductive feature comprises a second metal different from the first metal. | 2021-10-07 |
20210313263 | SEMICONDUCTOR DEVICES - A semiconductor device includes a base, source, drain and gate electrodes, signal tracks and a power mesh. The source, drain and gate electrodes are arranged on a surface of the base, wherein the gate electrodes are extended along a first direction. The signal tracks arranged above the first surface of the base and above the source and drain electrodes and the gate electrodes, wherein the signal tracks are extended along the first directions. A power mesh arranged below the first surface of the base, the power mesh comprising first power rails extended in the second direction and second power rails extended in a first direction, wherein the second direction is substantially perpendicular to the first direction. | 2021-10-07 |
20210313264 | BACK END OF LINE METALLIZATION - Interconnect structures and methods for forming the interconnect structures generally include a subtractive etching process to form a fully aligned top via and metal line interconnect structure. The interconnect structure includes a top via and a metal line formed of an alternative metal other than copper or tungsten. A conductive etch stop layer is intermediate the top via and the metal line. The top via is fully aligned to the metal line. | 2021-10-07 |
20210313265 | TOP VIA WITH NEXT LEVEL LINE SELECTIVE GROWTH - Embodiments of the present invention are directed to fabrication methods and resulting interconnect structures having a conductive thin metal layer on a top via that promotes the selective growth of the next level interconnect lines (the line above). In a non-limiting embodiment of the invention, a first conductive line is formed in a dielectric layer. A via is formed on the first conductive line and a seed layer is formed on the via and the dielectric layer. A surface of the seed layer is exposed and a second conductive line is deposited onto the exposed surface of the seed layer. In a non-limiting embodiment of the invention, the second conductive line is selectively grown from the seed layer. | 2021-10-07 |
20210313266 | PACKAGE COMPRISING A SUBSTRATE WITH INTERCONNECT ROUTING OVER SOLDER RESIST LAYER - A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes (i) at least one inner dielectric layer, (ii) a plurality of interconnects located in the at least one inner dielectric layer, where the plurality of interconnects includes a pad located on a bottom metal layer of the substrate, (iii) an outer dielectric layer located over the at least one dielectric layer, (iv) at least one routing interconnect coupled to the plurality of interconnects, where the at least one routing interconnect is located over the outer dielectric layer, where the at least one routing interconnect is located below the bottom metal layer of the substrate, and (v) a cover dielectric layer located over the outer dielectric layer and the at least one routing interconnect. The package includes a solder interconnect coupled to the pad located on the bottom metal layer of the substrate. | 2021-10-07 |
20210313267 | Reduction of OHMIC Losses in Monolithic Chip Inductors and Transformers of Radio Frequency Integrated Circuits - An inductor or transformer with the inductor can include one or more windings split into strands along a radial path of the winding and provide for a more uniform current distribution across a width of the winding. The winding(s) can comprise twisting components as twistings or strand crossings located at various locations along the winding. The twisting components span the winding along a winding width with a connector or crossing strand and change a position of one strand to another at points that different strands of the winding are cut or spliced. | 2021-10-07 |
20210313268 | ADVANCED NODE INTERCONNECT ROUTING METHODOLOGY - In one embodiment, an integrated circuit includes a first pattern metal layer, a second pattern metal layer formed over the first pattern metal layer, wherein the second pattern metal layer comprises a second plurality of metal tracks extending in a first direction and less than 9, a third pattern metal layer disposed between the first pattern metal layer and the second pattern metal layer, the third pattern metal layer including, a first metal track segment, a second metal track segment shifted in a second direction from the first metal track segment, and a third metal track segment shifted in the second direction from the second metal track segment, wherein the second plurality of metal tracks, and at least a portion of each of the first metal track segment, the second metal track segment, and the third metal track segment are within a double cell height in the second direction. | 2021-10-07 |
20210313269 | INTEGRATED CIRCUIT PACKAGE WITH INTEGRATED VOLTAGE REGULATOR - Various semiconductor chip devices and methods of making the same are disclosed. In one aspect, an apparatus is provided that includes a first redistribution layer (RDL) structure having a first plurality of conductor traces, a first molding layer on the first RDL structure, plural conductive pillars in the first molding layer, each of the conductive pillars including a first end and a second end, a second RDL structure on the first molding layer, the second RDL structure having a second plurality of conductor traces, and wherein some of the conductive pillars are electrically connected between some of the first plurality of conductor traces and some of the second plurality of conductor traces to provide a first inductor coil. | 2021-10-07 |
20210313270 | Semiconductor Structure and Method of Making the Same - A semiconductor structure includes: a buried power rail disposed between a first fin structure and a second fin structure on a substrate extending in a first direction in a horizontal plane, the first fin structure located in a first cell, the second fin structure located in a second cell abutting the first cell at a boundary line extending in the first direction, the buried power rail providing a first voltage; and a metal one (M1) metal track disposed in a M1 layer extending in a second direction in the horizontal plane. At an intersection of the buried power rail and the M1 metal track, the semiconductor structure further includes an electrically conductive path to provide the first voltage to the M1 metal track, the electrically conductive path having a first metal zero (M0) metal track extending in the first direction over the boundary line. | 2021-10-07 |
20210313271 | SEMICONDUCTOR PACKAGE STRUCTURE - A semiconductor package structure includes a substrate, a first redistribution layer, a second redistribution layer, a bridge structure, a first semiconductor component, and a second semiconductor component. The first redistribution layer is over the substrate. The second redistribution layer is over the first redistribution layer. The bridge structure is between the first redistribution layer and the second redistribution layer, wherein the bridge structure includes an active device. The first semiconductor component and the second semiconductor component are located over the second redistribution layer, wherein the first semiconductor component is electrically coupled to the second semiconductor component through the second redistribution layer and the bridge structure. | 2021-10-07 |
20210313272 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device may include first and second sub chips stacked sequentially and a through contact electrically connecting the first and second sub chips to each other. Each of the first and second sub chips may include a substrate and a plurality of interconnection lines, which are interposed between the substrates. The interconnection lines of the second sub chip may include first and second interconnection lines having first and second openings, respectively, which are horizontally offset from each other. The through contact may be extended from the substrate of the second sub chip toward the first sub chip and may include an auxiliary contact, which is extended toward the first sub chip through the first and second openings and has a bottom surface higher than a top surface of the uppermost one of the interconnection lines of the first sub chip. | 2021-10-07 |
20210313273 | METHOD FOR FABRICATING A SEMICONDUCTOR PACKAGE, SEMICONDUCTOR PACKAGE AND EMBEDDED PCB MODULE - A method for fabricating a semiconductor package includes: providing a semiconductor wafer having opposing first and second sides, the semiconductor wafer being arranged on a first carrier such that the second side of the wafer faces the carrier; masking sawing lines on the first side of the semiconductor wafer with a mask; depositing a first metal layer on the masked first side of the semiconductor wafer by cold spraying or by high velocity oxygen fuel spraying or by cold plasma assisted deposition, such that the first metal layer does not cover the sawing lines, the deposited first metal layer having a thickness of 50 μm or more; singulating the semiconductor wafer into a plurality of semiconductor dies by sawing the semiconductor wafer along the sawing lines; and encapsulating the plurality of semiconductor dies with an encapsulant such that the first metal layer is exposed on a first side of the encapsulant. | 2021-10-07 |
20210313274 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package is provided. The semiconductor package can include a first redistributed layer on which a plurality of semiconductor chips and a plurality of passive devices are mounted on one surface, a second redistributed layer electrically connected to the first redistributed layer through a via, an external connection terminal formed on the lower surface of the second redistributed layer, a first mold provided to cover the plurality of semiconductor chips and the plurality of passive devices on the first redistributed layer, and a second mold provided between the first redistributed layer and the second redistributed layer. Each of the first redistributed layer and the second redistributed layer includes a wiring pattern and an insulating layer and is composed of a plurality of layers, and at least one of the plurality of semiconductor chips is disposed between the first redistributed layer and the second redistributed layer. | 2021-10-07 |
20210313275 | PACKAGED SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING A PACKAGED SEMICONDUCTOR DEVICE - A method for fabricating packaged semiconductor devices is disclosed. In one example the method comprises providing a plurality of semiconductor dies, the semiconductor dies being arranged in an array on a carrier such that a first side of the semiconductor dies faces the carrier and such that an empty space is arranged laterally besides each semiconductor die. A substrate comprising a plurality of conductive elements is arranged over the plurality of semiconductor dies such that a conductive element is arranged in the respective empty space besides each one of the semiconductor dies. The plurality of semiconductor dies are molded over to form a molded body, and singulating packaged semiconductor devices from the molded body by cutting through the molded body. | 2021-10-07 |
20210313276 | SEMICONDUCTOR PACKAGE AND ANTENNA MODULE COMPRISING THE SAME - A method including forming a frame having an opening, forming a first metal layer, forming a first encapsulant, forming an insulation layer on the first metal layer, forming a first through-hole and a second through-hole penetrating the insulation layer and the first encapsulant, forming a second metal layer and a third metal layer, forming a second encapsulant, forming a first metal via and a second metal via penetrating the second encapsulant and a metal pattern layer on the second encapsulant, and forming a connection structure. The first metal layer and the second metal layer respectively are formed to extend to a surface of each of the first encapsulant and the frame, facing the metal pattern layer, and the first metal layer and the second metal layer are connected to the metal pattern layer through the first metal via and the second metal via having heights different from each other. | 2021-10-07 |
20210313277 | MULTI-LAYER LINE STRUCTURE AND METHOD FOR MANUFACTURING THEREOF - A multi-layer line structure including a substrate, a lower layer Cu line located on the substrate, an upper layer Cu line located on an insulating layer including an inorganic film located on the lower layer Cu line and an organic resin film located on the inorganic film, and a via connection part located in a via connection hole running in an up-down direction through the insulating layer in an area where the lower layer Cu line and the upper layer Cu line overlap each other is provided. The via connection part includes a barrier conductive layer located on a part of the lower layer Cu line exposed to a bottom part of the via connection hole and on an inner wall of the via connection hole. | 2021-10-07 |
20210313278 | DETERMINATION METHOD AND APPARATUS, PROGRAM, INFORMATION RECORDING MEDIUM, EXPOSURE APPARATUS, LAYOUT INFORMATION PROVIDING METHOD, LAYOUT METHOD, MARK DETECTION METHOD, EXPOSURE METHOD, AND DEVICE MANUFACTURING METHOD - A determination apparatus has a calculation section, where first and second direction pitches intersecting within a predetermined plane of a plurality of detection areas are D | 2021-10-07 |
20210313279 | CIRCUIT SYSTEMS - Various circuit board systems and methods of use and manufacture thereof are disclosed. A circuit board system can have a first circuit board including a substrate and a first component susceptible to electromagnetic interference carried by the substrate. The system can also include a second circuit board including a second substrate, and a shield engaged to the substrate of the first component, the shield at least partially covering the first component and being configured to protect the first component from electromagnetic interference, wherein the shield couples the substrate of the first circuit board to the substrate of the second circuit board. | 2021-10-07 |
20210313280 | INTEGRATED CIRCUIT PROVIDED WITH DECOYS AGAINST REVERSE ENGINEERING AND CORRESPONDING FABRICATION PROCESS - An integrated circuit includes a first domain supplied with power at a first supply voltage. A first transistor comprising in the first domain includes a first gate region and a first gate dielectric region. A second domain is supply with power at a second supply voltage and includes a second transistor having a second gate region and a second gate dielectric region, the second gate region being biased at a voltage that is higher than the first supply voltage. The first and second gate dielectric regions have the same composition, wherein that composition configures the first transistor in a permanently turned off condition in response to a gate bias voltage lower than or equal to the first supply voltage. The second transistor is a floating gate memory cell transistor, with the second gate dielectric region located between the floating and control gates. | 2021-10-07 |
20210313281 | SEMICONDUCTOR DIE INCLUDING EDGE RING STRUCTURES AND METHODS FOR MAKING THE SAME - A semiconductor die includes semiconductor devices located over a substrate, at least one dielectric material portion that laterally surrounds the semiconductor devices, and interconnect-level dielectric material layers. At least one edge seal ring structure can be provided, each including a composite edge seal via structure and a set of metal barrier structures. The composite edge seal via structure includes a metallic material layer and a dielectric fill material portion. Alternatively or additionally, at least one slit ring structure can laterally surround the semiconductor devices and the metal interconnect structures. Each slit ring structure continuously extends through each of the interconnect-level dielectric material layers and into the at least one dielectric material portion, and includes at least one dielectric material. | 2021-10-07 |
20210313282 | RF AMPLIFIER DEVICES AND METHODS OF MANUFACTURING - A transistor amplifier includes a group III-nitride based amplifier die including a gate terminal, a drain terminal, and a source terminal on a first surface of the amplifier die and an interconnect structure electrically bonded to the gate terminal, drain terminal and source terminal of the amplifier die on the first surface of the amplifier die and electrically bonded to an input path and output path of the transistor amplifier. | 2021-10-07 |
20210313283 | MULTI LEVEL RADIO FREQUENCY (RF) INTEGRATED CIRCUIT COMPONENTS INCLUDING PASSIVE DEVICES - A multi-level radio frequency (RF) integrated circuit component includes an upper level including at least one inductor, and a lower level including at least one conductive element that provides electrical connection to the at least one inductor. The lower level separates the at least one inductor from a lower surface that is configured to be attached to a conductive pad. Related integrated circuit device packages are also discussed. | 2021-10-07 |
20210313284 | STACKED RF CIRCUIT TOPOLOGY - An integrated circuit device package includes a substrate, a first die comprising active electronic components attached to the substrate, and package leads configured to conduct electrical signals between the first die and an external device. At least one integrated interconnect structure is provided on the first die opposite the substrate. The at least one integrated interconnect structure extends from the first die to an adjacent die attached to the substrate and/or to at least one of the package leads, and provides electrical connection therebetween. Related devices and power amplifier circuits are also discussed. | 2021-10-07 |
20210313285 | STACKED RF CIRCUIT TOPOLOGY USING TRANSISTOR DIE WITH THROUGH SILICON CARBIDE VIAS ON GATE AND/OR DRAIN - A radio frequency (RF) power amplifier device package includes a substrate and a first die attached to the substrate at a bottom surface of the first die. The first die includes top gate or drain contacts on a top surface of the first die opposite the bottom surface. At least one of the top gate or drain contacts is electrically connected to a respective bottom gate or drain contact on the bottom surface of the first die by a respective conductive via structure. An integrated interconnect structure, which is on the first die opposite the substrate, includes a first contact pad on the top gate contact or the top drain contact of the first die, and at least one second contact pad connected to a package lead, a contact of a second die, impedance matching circuitry, and/or harmonic termination circuitry. | 2021-10-07 |
20210313286 | GROUP III NITRIDE-BASED RADIO FREQUENCY AMPLIFIERS HAVING BACK SIDE SOURCE, GATE AND/OR DRAIN TERMINALS - RF amplifiers are provided that include an interconnection structure and a Group III nitride-based RF amplifier die that is mounted on top of the interconnection structure. The Group III nitride-based RF amplifier die includes a semiconductor layer structure. A plurality of unit cell transistors are provided in an upper portion of the semiconductor layer structure, and a gate terminal, a drain terminal and a source terminal are provided on a lower surface of the semiconductor layer structure that is adjacent the interconnection structure. | 2021-10-07 |
20210313287 | Solderless Interconnection Structure and Method of Forming Same - An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion. | 2021-10-07 |
20210313288 | SEMICONDUCTOR MEMORY DEVICE HAVING WAFER-TO-WAFER BONDING STRUCTURE - A semiconductor memory device includes first column line pads, having a longer width and a shorter width, defined on one surface of a cell wafer, and coupled to a memory cell array of the cell wafer; second column line pads, having a longer width and a shorter width, defined on one surface of a peripheral wafer that is bonded to the one surface of the cell wafer, coupled to a page buffer circuit of the peripheral wafer, and bonded respectively to the first column line pads; first row line pads defined on the one surface of the cell wafer, and coupled to the memory cell array; and second row line pads defined on the one surface of the peripheral wafer, coupled to a row decoder of the peripheral wafer, and bonded respectively to the first row line pads. The longer widths of the first and second column line pads and the longer widths of the first and second row line pads extend in the same direction. | 2021-10-07 |
20210313289 | PACKAGE FOR POWER ELECTRONICS - A package for power electronics includes a power substrate, a number of power semiconductor die, and a Kelvin connection contact. Each one of the power semiconductor die are on the power substrate and include a first power switching pad, a second power switching pad, a control pad, a semiconductor structure, and a Kelvin connection pad. The semiconductor structure is between the first power switching pad, the second power switching pad, and the control pad, and is configured such that a resistance of a power switching path between the first power switching pad and the second power switching pad is based on a control signal provided at the control pad. The Kelvin connection pad is coupled to the power switching path. The Kelvin connection contact is coupled to the Kelvin connection pad of each one of the power semiconductor die via a Kelvin conductive trace on the power substrate. | 2021-10-07 |
20210313290 | METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE - The present disclosure relates to a method for manufacturing a semiconductor package including vacuum-laminating a non-conductive film on a substrate on which a plurality of through silicon vias are provided and bump electrodes are formed, and then performing UV irradiation, wherein an increase in melt viscosity before and after UV irradiation can be adjusted to 30% or less, whereby a bonding can be performed without voids during thermo-compression bonding, and resin-insertion phenomenon between solders can be prevented, fillets can be minimized and reliability can be improved. | 2021-10-07 |
20210313291 | COPPER WIRE BOND ON GOLD BUMP ON SEMICONDUCTOR DIE BOND PAD - A semiconductor package includes a conductive pad, a semiconductor die with an aluminum bond pad over a dielectric layer of the semiconductor die, a gold bump on the aluminum bond pad, a first intermetallic layer of gold and aluminum between the aluminum bond pad and the gold bump, a copper ball bond on the gold bump, a second intermetallic layer of copper and gold between the copper ball bond and the gold bump, a copper wire extending from the copper ball bond to the conductive pad, a stitch bond between the copper wire and the conductive pad. | 2021-10-07 |
20210313292 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package including a plurality of semiconductor devices, an insulating layer, and a redistribution layer is provided. The insulating layer is disposed over the semiconductor device. The redistribution layer is disposed over the insulating layer and electrically connected to the semiconductor device. The redistribution layer includes a conductive line portion. The semiconductor package has a stitching zone, and the insulating layer has a ridge structure on a surface away from the semiconductor device and positioned within the stitching zone. | 2021-10-07 |
20210313293 | RF AMPLIFIER DEVICES AND METHODS OF MANUFACTURING - A transistor amplifier includes a semiconductor layer structure comprising first and second major surfaces and a plurality of unit cell transistors on the first major surface that are electrically connected in parallel, each unit cell transistor comprising a gate finger coupled to a gate manifold, a drain finger coupled to a drain manifold, and a source finger. The semiconductor layer structure is free of a via to the source fingers on the second major surface. | 2021-10-07 |
20210313294 | SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME - A semiconductor package includes a carrier having a recess, a semiconductor die arranged on the carrier such that a first side of the semiconductor die faces the carrier, and a contact clip arranged over a second side of the semiconductor die, opposite the first side. The contact clip includes a lowered part. The lowered part is arranged in the recess. | 2021-10-07 |
20210313295 | SEMICONDUCTOR DEVICE - A semiconductor device according to the present invention includes a substrate, a resin case, and a wiring member having an exposed portion adjacent to a first fixing portion fixed in a wall surface of the resin case and exposed to outside, and a second fixing portion fixed in the wall surface of the resin case at a position different from the first fixing portion with respect to a portion extending from the first fixing portion into the resin case, in which the wiring member is bonded to a surface of the semiconductor element by solder in the resin case, and has a plate shape having a length, a thickness, and a width, in which the wiring member has the thickness being uniform and is flat in the resin case, and the width of the second fixing portion is narrower than the width of the exposed portion. | 2021-10-07 |
20210313296 | HALF-BRIDGE MODULE FOR AN INVERTER OF AN ELECTRIC DRIVE OF AN ELECTRIC VEHICLE OR A HYBRID VEHICLE AND AN INVERTER FOR AN ELECTRIC DRIVE OF AN ELECTRIC VEHICLE OR A HYBRID VEHICLE - The invention relates to a half-bridge module for an inverter in an electric drive for an electric vehicle or a hybrid vehicle, comprising a substrate, semiconductor switches arranged on the substrate, power connections, and signal connections, wherein the signal connections are electrically connected to the semiconductor switches such that the semiconductor switches can be switched via the signal connections, and wherein the power connections are electrically connected to the semiconductor switches such that the semiconductor switches allow or interrupt electricity transmission between the power connections. The half-bridge module according to the invention is distinguished in that the semiconductor switches are in electrical contact in part via bond wires and in part via lead frames. The invention also relates to a corresponding inverter. | 2021-10-07 |
20210313297 | METHOD FOR MANUFACTURING ELECTRONIC DEVICE - A method for manufacturing an electronic component includes preparing a mounting substrate provided with a first region to mount an electronic component thereon and a second region having conductivity, covering the second region with resin, applying a metal paste on the first region, mounting the electronic component on the first region with the metal paste, and removing the resin covering the second region. The mounting includes heating the mounting substrate to cure the metal paste with the electronic components being placed on the metal paste applied on the first region. The resin peeled from the second region by the heating is removed in the removing. | 2021-10-07 |
20210313298 | DISPLAY ASSEMBLIES - A backplane for controlling a display is disclosed. The backplane includes a plurality of tiles formed into an array. Each of the plurality of tiles includes a plurality of complementary metal-oxide-semiconductor backplane dies. Edges of the backplane dies that form a perimeter of the array include electrical connections that direct electrical signals to at least one of the CMOS backplane dies. A display assembly is also disclosed wherein the display assembly includes a backplane having an array of tiles. Each tile includes a plurality of electrically coupled CMOS backplane dies, where edges of the tiles that form an outer perimeter of the array include electrical connections directing electrical signals to one or more of the plurality of CMOS backplane dies. The display assembly further includes at least one light emitting diode array electrically coupled with at least one tile. | 2021-10-07 |
20210313299 | SEMICONDUCTOR PACKAGE STRUCTURE - A semiconductor package structure includes a substrate, a redistribution layer, a first semiconductor component, a conductive pillar, and a second semiconductor component. The redistribution layer is over the substrate. The first semiconductor component is over the redistribution layer. The conductive pillar is adjacent to the first semiconductor component, wherein the first semiconductor component and the conductive pillar are surrounded by a molding material. The second semiconductor component is over the molding material, wherein the second semiconductor component is electrically coupled to the redistribution layer through the conductive pillar. | 2021-10-07 |
20210313300 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An electronic device and a method of making an electronic device. As non-limiting examples, various aspects of this disclosure provide various methods of manufacturing electronic devices, and electronic devices manufactured thereby, that comprise utilizing an adhesive layer to attach an upper electronic package to a lower die and/or utilizing metal pillars for electrically connecting the upper electronic package to a lower substrate, wherein the metal pillars have a smaller height above the lower substrate than the lower die. | 2021-10-07 |
20210313301 | DISPLAY PANEL AND ELECTRONIC DEVICE - The present disclosure provides a display panel including a plurality of light-emitting elements arranged at intervals, and an elastomer covering the plurality of light-emitting elements. Each light-emitting element is provided with a light-emitting region, and a connecting region arranged around the light-emitting region. The light-emitting element includes a light-emitting island arranged in the light-emitting region, and the light-emitting island at least includes an inorganic light-emitting diode. The light-emitting element further includes an elastic connector arranged in the connecting region, and light-emitting islands in two adjacent light-emitting elements are connected via the elastic connector. The present disclosure further provides an electronic device. | 2021-10-07 |
20210313302 | SURFACE LIGHT SOURCE AND METHOD OF MANUFACTURING SURFACE LIGHT SOURCE - A method of manufacturing a surface light source includes providing an intermediate structure body that includes a composite board including a supporting member and a wiring layer disposed on the supporting member and includes a plurality of light-emitting elements disposed apart from each other on the wiring layer of the composite board, disposing a plurality of covering members apart from each other to cover upper surfaces and lateral surfaces of the light-emitting elements and portions of the composite board around the light-emitting elements, disposing a light-shielding member such that a gap between the covering members is filled, removing the covering members to form a plurality of hole portions, and disposing a light-transmissive member in the hole portions. | 2021-10-07 |
20210313303 | DISPLAYING APPARATUS HAVING LIGHT EMITTING DEVICE, METHOD OF MANUFACTURING THE SAME AND METHOD OF TRANSFERRING LIGHT EMITTING DEVICE - A displaying apparatus includes a pixel unit. The pixel unit includes at least one pixel having a light emitting device and a light conversion layer for converting a first wavelength of light of the light emitting device into a second wavelength of light different from the first wavelength; and an insulation layer covers side surfaces of the light emitting device and the light conversion layer. | 2021-10-07 |
20210313304 | PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME - A package structure and method of forming the same are provided. The package structure includes a first die, a second die, a wall structure and an encapsulant. The second die is electrically bonded to the first die. The wall structure is laterally aside the second die and on the first die. The wall structure is in contact with the first die and a hole is defined within the wall structure for accommodating an optical element insertion. The encapsulant laterally encapsulates the second die and the wall structure. | 2021-10-07 |
20210313305 | METHOD FOR INTEGRATING A LIGHT EMITTING DEVICE - Light emitting devices and methods of integrating micro LED devices into light emitting device are described. In an embodiment a light emitting device includes a reflective bank structure within a bank layer, and a conductive line atop the bank layer and elevated above the reflective bank structure. A micro LED device is within the reflective bank structure and a passivation layer is over the bank layer and laterally around the micro LED device within the reflective bank structure. A portion of the micro LED device and a conductive line atop the bank layer protrude above a top surface of the passivation layer. | 2021-10-07 |
20210313306 | METHOD AND SYSTEM FOR SELECTIVELY ILLLUMINATED INTEGRATED PHOTODETECTORS WITH CONFIGURED LAUNCHING AND ADAPTIVE JUNCTION PROFILE FOR BANDWIDTH IMPROVEMENT - Methods and systems for selectively illuminated integrated photodetectors with configured launching and adaptive junction profile for bandwidth improvement may include a photonic chip comprising an input waveguide and a photodiode. The photodiode comprises an absorbing region with a p-doped region on a first side of the absorbing region and an n-doped region on a second side of the absorbing region. An optical signal is received in the absorbing region via the input waveguide, which is offset to one side of a center axis of the absorbing region; an electrical signal is generated based on the received optical signal. The first side of the absorbing region may be p-doped. P-doped and n-doped regions may alternate on the first and second sides of the absorbing region along the length of the photodiode. The absorbing region may comprise germanium, silicon, silicon/germanium, or similar material that absorbs light of a desired wavelength. | 2021-10-07 |
20210313307 | DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a display device includes forming a circuit layer on a base layer, forming a first preliminary electrode and a second preliminary electrode on the circuit layer, forming a photoresist layer on the first preliminary electrode and the second preliminary electrode, patterning the photoresist layer to form a photoresist pattern, treating a region of each of the first preliminary electrode and the second preliminary electrode to form a first electrode and a second electrode having regions of lower and higher electrical resistance, and disposing a light-emitting element on the first electrode and the second electrode at regions having lower electrical resistance. | 2021-10-07 |
20210313308 | MICRO LED DISPLAY PANEL AND METHOD FOR MAKING SAME - A micro LED display panel includes a blue LED layer, a green LED layer, and a red LED layer. The blue LED layer, the green LED layer, and the red LED layer are in a stacked formation. The blue, the green, and the red LED layers each include a plurality of micro LEDs spaced apart from each other. The composition of the layers is such that light emitted from all but the bottom layer is able to pass through transparent material in other layers before exiting the panel and being viewed. | 2021-10-07 |
20210313309 | METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE STRUCTURE - Methods of manufacturing a semiconductor package structure are provided. A method includes: bonding dies and dummy dies to a wafer; forming a dielectric material layer on the wafer to cover the dies and the dummy dies; performing a first planarization process to remove a first portion of the dielectric material layer over top surfaces of the dies and the dummy dies; and performing a second planarization process to remove portions of the dies, portions of the dummy dies and a second portion of the dielectric material layer, and a dielectric layer is formed laterally aside the dies and the dummy dies; wherein after the second planarization process is performed, a total thickness variation of the dies is less than a total thickness variation of the dummy dies. | 2021-10-07 |
20210313310 | INTEGRATED CIRCUIT INCLUDING STANDARD CELLS - An integrated circuit including a plurality of standard cells is provided. The integrated circuit includes a first standard cell group including at least two first standard cells, a second standard cell group adjacent to the first standard cell group in a first direction, the second standard cell group including at least one second standard cell, and a first insulating gate bordered by one side of at least one of the first standard cells and one side of the at least one second standard cell, wherein each of the first and second standard cells includes a p-type transistor (pFET) and an n-type transistor (nFET) which are integrated, wherein each of the first and second standard cells has first wiring lines of different designs, and wherein each of the first and second standard cells has the same or different placement of an active region according to the corresponding design. | 2021-10-07 |
20210313311 | Semiconductor Device - A semiconductor device includes “n” pairs of pn-junction structures, wherein the i-th pair includes two pn-junction structures of the i-th type, wherein the two pn-junction structures of the i-th type are anti-serially connected, wherein the pn-junction structure of the i-th type has an i-th junction grading coefficient m | 2021-10-07 |
20210313312 | Transient Voltage Suppression Device And Manufacturing Method Therefor - A transient voltage suppression device includes a substrate; a first conductivity type well region disposed in the substrate and comprising a first well and a second well; a third well disposed on the substrate, a bottom part of the third well extending to the substrate; a fourth well disposed in the first well; a first doped region disposed in the second well; a second doped region disposed in the third well; a third doped region disposed in the fourth well; a fourth doped region disposed in the fourth well; a fifth doped region extending from inside of the fourth well to the outside of the fourth well, a portion located outside the fourth well being located in the first well; a sixth doped region disposed in the first well; a seventh doped region disposed below the fifth doped region and in the first well. | 2021-10-07 |
20210313313 | SEMICONDUCTOR DEVICE AND ELECTROSTATIC DISCHARGE PROTECTION METHOD - The present disclosure relates to a semiconductor device, including a first source/drain region, a second source/drain region, a base region, a first electrostatic discharge region and a second electrostatic discharge region. The first source/drain region and the second source/drain region are configured to receive a first power voltage and a second power voltage, and are formed on the base region. The first electrostatic discharge region includes a first doped region and a first well. The first doped region is configured to receive the second power voltage, and formed in the first well. The second electrostatic discharge region includes a second doped region and a second well. The second doped region is configured to receive the first power voltage, and formed in the second well. The first source/drain region and the second source/drain region are disposed between the first electrostatic discharge region and the second electrostatic discharge region. | 2021-10-07 |
20210313314 | ESD PROTECTION CIRCUIT, SEMICONDUCTOR SYSTEM INCLUDING SAME, AND METHOD FOR OPERATING SAME - A method of protecting a device (protected device) in a semiconductor system from an electrostatic discharge (ESD), the protected device being coupled between a first node and a first reference voltage, the method including: coupling an ESD device between the first node and the first reference voltage; coupling a shunting device between an input of the protected device and the first reference voltage; coupling a feedback control circuit between the first node and an input of the shunting device; and using the shunting device to actively couple the input of the protected device to the first reference voltage. | 2021-10-07 |
20210313315 | Electronic Discharge Device and Split Multi Rail Network with Symmetrical Layout Design Technique - A symmetrical layout technique for an electrostatic discharge ESD device and a corresponding power supply network is presented. The ESD device protects an electronic circuit against an overvoltage or overcurrent and contains a first contact area to establish an electrical contact with a first supply rail, a second contact area to establish an electrical contact with a second supply rail, and a third contact area to establish an electrical contact with a third supply rail. The first and third supply rails provide a first supply voltage, and the second supply rail provides a second supply voltage. Within the ESD device, an axis of symmetry passes through the second contact area, and the first contact area and the third contact area are arranged on opposite sides with regard to the axis of symmetry. The symmetrical layout technique allows flipping the orientation of the ESD device with regard to the supply rails. | 2021-10-07 |
20210313316 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure includes a semiconductor substrate including a first region and a second region; a first device disposed in the first region and a second device disposed in the second region, wherein a voltage level of the first device is greater than a voltage level of the second device; a first isolation disposed in the first region, wherein the first isolation includes a first depth; and a second isolation disposed in the second region, wherein the second isolation includes a second depth, and the first depth is greater than the second depth. | 2021-10-07 |
20210313317 | SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor structure includes the first semiconductor stack and the second semiconductor stack formed over the first region and the second region of a substrate, respectively. The first and second semiconductor stacks extend in the first direction and are spaced apart from each other in the second direction. Each of the first semiconductor stack and the second semiconductor stack includes channel layers and a gate structure. The channel layers are formed above the substrate and are spaced apart from each other in the third direction. The gate structure includes the gate dielectric layers formed around the respective channel layers, and the gate electrode layer formed on the gate dielectric layers to surround the channel layers. The number of channel layers in the first semiconductor stack is different from the number of channel layers in the second semiconductor stack. | 2021-10-07 |
20210313318 | Power Supplies and Semiconductor Apparatuses with Functions of Current-Sampling and High-Voltage Startup - A semiconductor apparatus includes first, second and third transistors integrated in a monocrystal chip. Both the first and second transistors are vertical devices, each having a source node, a gate node and a drain node. The source node of the first transistor electrically connects to a primary source pin, the source node of the second transistor to a sample pin, and the gate nodes of the first and the second transistors to a control-gate pin. The third transistor is a vertical JFET with a source node, a control node and a drain node. The source node of the third transistor electrically connects to a charge pin, and the control node of the third transistor to a charge-control pin. All of the drain nodes of the first, second and third transistors are electrically connected to a high-voltage pin. | 2021-10-07 |
20210313319 | INTEGRATED CIRCUIT HAVING FINS CROSSING CELL BOUNDARY - A method of making an integrated circuit includes steps of selecting a first cell and a second cell for an integrated circuit layout from a cell library in an electronic design automation (EDA) system, the first and second cells each having a cell active area, a cell gate electrode, at least one fin of a first set of fins, and a cell border region, each cell also having the active area at an exposed side, and placing the first exposed side against the second exposed side at a cell border. The method also includes operations of aligning at least one fin of the first set of fins with at least one fin of the second set of fins across a cell border. | 2021-10-07 |
20210313320 | Fin-Based Strap Cell Structure for Improving Memory Performance - A device includes a memory cell having a gate-all-around (GAA) transistor and the well strap cell having a dummy fin-like field effect transistor (FinFET). The GAA transistor includes a first fin extending along a first direction, and the dummy FinFET includes a second fin extending along the first direction. The GAA transistor includes first source/drain features over the first fin and suspended channel layers between the first source/drain features. The first source/drain features include a first type dopant. The suspended channel layers have a first channel width along a second direction different than the first direction. The dummy FinFET includes second source/drain features over the second fin and a fin channel layer between the second source/drain features. The second source/drain features include a second type dopant. The fin channel layer has a second channel width along the second direction. The second channel width is greater than the first channel width. | 2021-10-07 |
20210313321 | MULTI-LEVEL ISOLATION STRUCTURE - One illustrative device disclosed herein includes at least one fin structure and an isolation structure comprising a stepped upper surface comprising a first region and a second region. The first region has a first upper surface and the second region has a second upper surface, wherein the first upper surface is positioned at a first level and the second upper surface is positioned at a second level and wherein the first level is below the second level. In this illustrative example, the device also includes a gate structure comprising a first portion and a second portion, wherein the first portion of the gate structure is positioned above the first upper surface of the isolation structure and above the at least one fin structure and wherein the second portion of the gate structure is positioned above the second upper surface of the isolation structure. | 2021-10-07 |
20210313322 | INTEGRATED CIRCUIT DEVICE - An integrated circuit (IC) device includes a fin-type active region extending lengthwise in a first direction, a plurality of nanosheets overlapping each other in a second direction on a fin top surface of the fin-type active region, and a source/drain region on the fin-type active region and facing the plurality of nanosheets in the first direction. The plurality of nanosheets include a first nanosheet, which is closest to the fin top surface of the fin-type active region and has a shortest length in the first direction, from among the plurality of nanosheets. The source/drain region includes a source/drain main region and a first source/drain protruding region protruding from the source/drain main region. The first source/drain protruding region protrudes from the source/drain main region toward the first nanosheet and overlaps portions of the plurality of nanosheets in the second direction. | 2021-10-07 |
20210313323 | INTEGRATED CIRCUIT STRUCTURE - An IC structure comprises first, second, and third circuits. The first circuit comprises a first semiconductor fin, a first gate electrode extending across the first semiconductor fin, and a first gate dielectric layer spacing the first gate electrode apart from the first semiconductor fin. The second circuit comprises a second semiconductor fin, a second gate electrode extending across the second semiconductor fin, and a second gate dielectric layer spacing the second gate electrode apart from the second semiconductor fin. The third circuit comprises a third semiconductor fin, a third gate electrode extending across the third semiconductor fin, and a third gate dielectric layer spacing the third gate electrode apart from the third semiconductor fin. The first gate dielectric layer has a greater thickness than the second gate dielectric layer. The third semiconductor fin has a smaller width than the second semiconductor fin. | 2021-10-07 |
20210313324 | Method for Forming Source/Drain Contacts - Semiconductor devices and methods of forming the same are provided. In one embodiments, a semiconductor device includes an n-type transistor region and a p-type transistor region. The n-type transistor region includes a first gate stack, a first gate spacer over sidewalls of the first gate stack, an n-type epitaxial feature in a source/drain (S/D) region of the n-type transistor region, and a first metal silicide layer over the n-type epitaxial feature. The p-type transistor region includes a second gate stack, a second gate spacer over sidewalls of the second gate stack, a p-type epitaxial feature in an S/D region of the p-type transistor region, a dopant-containing implant layer over the p-type epitaxial feature, and a second metal silicide layer over the dopant-containing implant layer. The dopant-containing implant layer includes a metallic dopant. | 2021-10-07 |
20210313325 | METAL GATE MODULATION TO IMPROVE KINK EFFECT - The present disclosure relates to an integrated chip. The integrated chip includes a source region and a drain region disposed within an upper surface of a substrate. One or more dielectric materials are disposed within a trench defined by sidewalls of the substrate that surround the source region and the drain region. The one or more dielectric materials include one or more interior surfaces defining a recess within the one or more dielectric materials. A gate structure is disposed over the substrate between the source region and the drain region. The gate structure includes a first gate material over the upper surface of the substrate and a second gate material. The second gate material completely fills the recess as viewed along a cross-sectional view. | 2021-10-07 |
20210313326 | TRANSISTORS IN A LAYERED ARRANGEMENT - Certain aspects of the present disclosure generally relate to transistors in a layered arrangement. An example semiconductor device generally includes a substrate, an n-type metal-oxide-semiconductor (NMOS) transistor, and a p-type metal-oxide-semiconductor (PMOS) transistor. The NMOS transistor is disposed above the substrate and is a gate-all-around (GAA) field-effect transistor (FET). The PMOS transistor is disposed above the substrate, is a fin field-effect transistor (finFET), and is in a layered arrangement with the NMOS transistor. | 2021-10-07 |
20210313327 | UNIFIED ARCHITECTURAL DESIGN FOR ENHANCED 3D CIRCUIT OPTIONS - A method of forming a semiconductor device is presented. A layer stack of alternating epitaxial materials including one or more layers is formed. The layer stack of alternating epitaxial materials into a first region of nano sheets and a second region of nano sheets is divided. A first field effect transistor on a working surface of a substrate using the nano sheets in the first region of nano sheets is formed. A stack of field effect transistors on the working surface of the substrate using the nano sheets in the second region of nano sheets is formed. | 2021-10-07 |
20210313328 | SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME - A semiconductor device includes first-type-channel field effect transistors (FETs) including a first first-type-channel FET including a first gate structure and a second first-type-channel FET including a second gate structure. The first first-type-channel FET has a smaller threshold voltage than the second first-type-channel FET. The first gate structure includes a first work function adjustment material (WFM) layer and the second gate structure includes a second WFM layer. At least one of thickness and material of the first and second WFM layers is different from each other. | 2021-10-07 |
20210313329 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is provided. The device includes a substrate including a cell region and a peripheral region; a plurality of lower electrodes disposed on the substrate in the cell region; a dielectric layer disposed on the plurality of lower electrodes; a metal containing layer disposed on the dielectric layer; a silicon germanium layer disposed on and electrically connected to the metal containing layer; a conductive pad disposed on and electrically connected to the silicon germanium layer; and an upper electrode contact plug disposed on and electrically connected to the conductive pad; The conductive pad extends from the upper electrode contact plug towards the peripheral region in a first direction, and the silicon germanium layer includes an edge portion that extends past the conductive pad in the first direction. | 2021-10-07 |
20210313330 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FORMING THE SAME - A semiconductor memory device includes a memory cell region; a memory mat end region; a memory mat including the memory cell region and the memory mat region; a plurality of first silicon regions arranged in the memory cell region; a second silicon region arranged in the memory mat end region; a first conductive layer provided in the memory cell region and the memory mat end region; and wherein upper surface position of the second silicon region in the memory mat end region is higher than the upper surface position of the first silicon region in the memory cell region; and wherein the upper surface position of the first conductive layer in the memory mat end region is higher than the upper surface position of the first conductive layer in the memory cell region. | 2021-10-07 |
20210313331 | SEMICONDUCTOR DEVICE WITH EMBEDDED STORAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME - The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a fin positioned on the substrate, a gate structure positioned on the fin, a pair of source/drain regions positioned on two sides of the fin, a dielectric layer positioned above the drain region and adjacent to the gate structure, and a storage conductive layer positioned on the dielectric layer. The drain region, the dielectric layer and the storage conductive layer form a storage structure. | 2021-10-07 |
20210313332 | MEMORY STRUCTURE AND ITS FORMATION METHOD - A memory structure and formation method are provided. The memory structure can comprise two second grooves along the row direction in each active area. The two second grooves divides each active area into a drain and two sources located on both sides of the drain. The surface of the insulating layer is lower than bottom surface of the second groove. A third groove is formed on the insulating layer between the first anti-etching dielectric layer and the second anti-etching dielectric layer to expose at least part of the surface of the sidewalls on both sides of the active area at the bottom of the second grooves and part of the surface of the sidewalls of the source and drain on both sides of the second grooves. The third groove is in connection with the second groove. A gate structure is formed in the second groove and the third groove. | 2021-10-07 |
20210313333 | MEMORY CHIP STRUCTURE HAVING GAA TRANSISTORS WITH DIFFERENT THRESHOLD VOLTAGES AND WORK FUNCTIONS FOR IMPROVING PERFORMANCES IN MULTIPLE APPLICATIONS - An exemplary semiconductor memory chip includes a first static random access memory (SRAM) cell and a second SRAM cell. The first SRAM cell has a first GAA transistor, and the second SRAM cell has a second GAA transistor. The first and the second SRAM cells have a same cell size, and the first and the second GAA transistors are of a same transistor type. Moreover, the first GAA transistor has a first threshold voltage and the second GAA transistor has a second threshold voltage. The second threshold voltage is different than the first threshold voltage. Furthermore, the first GAA transistor has a first gate stack and the second GAA transistor has a second gate stack. The first gate stack has a first work function value, and the second gate stack has a second work function value. The second work function value is different than the first work function value. | 2021-10-07 |
20210313334 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes: a first bit line; a capacitor; and a first memory cell transistor and a second memory cell transistor that are coupled in series between the first bit line and the capacitor. | 2021-10-07 |
20210313335 | MEMORY DEVICE - According to one embodiment, a memory device includes a plurality of first conductors stacked along a first direction; a second, third, and fourth conductor stacked in a same layer above the first conductors; a plurality of fifth conductors stacked along the first direction; a sixth conductor stacked above the fifth conductors; a first semiconductor extending along the first direction between the second conductor and the sixth conductor; a second semiconductor extending along the first direction between the third conductor and the sixth conductor; and a third semiconductor extending along the first direction between the fourth conductor and the sixth conductor. | 2021-10-07 |
20210313336 | VARIABLE LOW RESISTANCE LINE NONVOLATILE MEMORY DEVICE AND METHOD FOR OPERATING SAME - A variable low-resistance line memory device and an operating method thereof are provided. The memory device includes: a base including a spontaneous polarizable material; a gate arranged adjacent to the base; at least two polarization regions formed in the base by applying an electric field to the base through the gate, the at least two polarization regions having polarization in different directions from each other; a variable low-resistance line corresponding to a boundary between the at least two polarization regions selectively having polarization in different directions from each other; a source located to contact the variable low-resistance line; and a drain located to contact the variable low-resistance line, wherein the variable low-resistance line is formed in a region of the base, the region having a lower electrical resistance than other regions of the base adjacent to the variable low-resistance line. | 2021-10-07 |
20210313337 | MEMORY CELL AND METHOD OF FORMING THE MEMORY CELL - A memory cell includes: a first transistor, having a first diffusion region coupled to a bit line and a first gate electrode coupled to a first word line; a second transistor, having a second diffusion region coupled to the bit line and a second gate electrode coupled to a second word line; and a third transistor, having a third diffusion region coupled to a fourth diffusion region of the first transistor, a fifth diffusion region coupled to a sixth diffusion region of the second transistor, and a third gate electrode coupled to a third word line; wherein the first transistor is arranged to have a first threshold voltage, the second transistor is arranged to have a second threshold voltage, and the second threshold voltage is different from the first threshold voltage. | 2021-10-07 |
20210313338 | INTEGRAL MULTIFUNCTION CHIP - An integral multifunction chip is provided. The integral multifunction chip includes an electronic fuse and an interface fuse. The interface fuse and the electronic fuse are disposed in parallel and integrated in a single chip. In a case where only a single chip is provided, the integral multifunction chip of the present disclosure can be selectively operated in a working mode of the electronic fuse or the interface fuse, so that convenience of use of the integral multifunction chip can be improved. | 2021-10-07 |
20210313339 | SEMICONDUCTOR DEVICES INCLUDING FERROELECTRIC MATERIALS - A method of forming a ferroelectric memory cell. The method comprises forming an electrode material exhibiting a desired dominant crystallographic orientation. A hafnium-based material is formed over the electrode material and the hafnium-based material is crystallized to induce formation of a ferroelectric material having a desired crystallographic orientation. Additional methods are also described, as are semiconductor device structures including the ferroelectric material. | 2021-10-07 |
20210313340 | MEMORY DEVICE - A memory device includes a first conductor and a charge storage film extending along a first direction; a first semiconductor of a first conductive type; a second and third semiconductor each of a second conductive type; and a stack comprising a second conductor, a first insulator, and a third conductor sequentially stacked along the first direction and each extending along a second direction. The first conductor, the charge storage film, the first semiconductor, and the stack are arranged in this order along a third direction. The second semiconductor is in contact with the first semiconductor and the second conductor, between the second conductor or the first insulator and the charge storage film. | 2021-10-07 |