41st week of 2015 patent applcation highlights part 54 |
Patent application number | Title | Published |
20150287729 | SEMICONDUCTOR DEVICE LAYOUT AND METHOD FOR FORMING THE SAME - A semiconductor includes a gate line having a first portion in a transistor region and a second portion in a decoupling capacitor region. | 2015-10-08 |
20150287730 | ANTIFUSE OTP MEMORY CELL WITH PERFORMANCE IMPROVEMENT, AND MANUFACTURING METHOD AND OPERATING METHOD OF MEMORY - An OTP memory cell including an antifuse unit and a select transistor is provided. The antifuse unit includes an antifuse layer and an antifuse gate disposed on a substrate in sequence, a modified extension doped region disposed in the substrate below the antifuse layer, and a first doped region and a second doped region disposed in the substrate at two opposite sides of the antifuse gate. The select transistor includes a select gate, a gate dielectric layer, a second doped region, and a third doped region. The select gate is disposed on the substrate. The gate dielectric layer is disposed between the select gate and the substrate. The second and the third doped region are respectively disposed in the substrate at two opposite sides of the select gate. The doped region, the antifuse layer and the antifuse gate form a varactor. | 2015-10-08 |
20150287731 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device is provided. The semiconductor device includes a semiconductor substrate, and a memory cell disposed on the semiconductor substrate. The memory cell includes a selection transistor and a memory transistor. The selection transistor includes a selection gate, a first source, and a first drain. The memory transistor includes a floating gate, a control gate, a second source, a second drain, and a first insulating layer disposed between the floating gate and the control gate. The semiconductor device further includes a selection gate sidewall spacer disposed near an edge of a bit line of the selection gate of the selection transistor. The selection gate sidewall spacer is separated from the selection gate by a second insulating layer. The selection gate sidewall spacer and the control gate are formed of a first material. | 2015-10-08 |
20150287732 | NONVOLATILE MEMORY CELL STRUCTURE WITH ASSISTANT GATE - A nonvolatile memory (NVM) cell includes a semiconductor substrate having therein an N well and a P well; a first OD region and a second OD region disposed within the N well; a PMOS select transistor disposed on the first OD region; a PMOS floating gate transistor serially connected to the select transistor and being disposed on the on the first OD region, wherein the PMOS floating gate transistor comprises a floating gate overlying the first OD region; and an assistant gate protruding from one distal end of the floating gate to one edge of the second OD region such that the assistant gate is capacitively coupled to the second OD region and the N well. The select transistor, the floating gate transistor and the assistant gate disposed on the same N well. | 2015-10-08 |
20150287733 | IN-SITU SUPPORT STRUCTURE FOR LINE COLLAPSE ROBUSTNESS IN MEMORY ARRAYS - Methods for preventing line collapse during the fabrication of NAND flash memory and other microelectronic devices that utilize closely spaced device structures with high aspect ratios are described. In some embodiments, one or more mechanical support structures may be used to provide lateral support between closely spaced device structures to prevent collapsing of the closely spaced device structures during an etching process (e.g., during a word line etch). In one example, during fabrication of a NAND flash memory, one or more mechanical support structures may be in place prior to performing a high aspect ratio word line etch or may be formed during the word line etch. In some cases, the one or more mechanical support structures may comprise portions of an inter-poly dielectric (IPD) layer that were in place prior to performing the word line etch. | 2015-10-08 |
20150287734 | MEMORY INCLUDING BLOCKING DIELECTRIC IN ETCH STOP TIER - Vertical memories and methods of making the same are discussed generally herein. In one embodiment, a vertical memory can include a vertical pillar extending to a source, an etch stop tier over the source, and a stack of alternating dielectric tiers and conductive tiers over the etch stop tier. The etch stop tier can comprise a blocking dielectric adjacent to the pillar. In another embodiment, the etch stop tier can comprise a blocking dielectric adjacent to the pillar, and a plurality of dielectric films horizontally extending from the blocking dielectric into the etch stop tier. | 2015-10-08 |
20150287735 | NONVOLATILE MEMORY DEVICE INCLUDING A SOURCE LINE HAVING A THREE-DIMENSIONAL SHAPE - A nonvolatile memory device includes a source line having a shape of a three-dimensional (3D) cap. The nonvolatile memory device includes a first vertical channel and a second vertical channel, a source contact disposed over the first vertical channel, a drain contact disposed over the second vertical channel, a source-line barrier disposed between the source contact and the drain contact, and a source-line plate coupling the source contact and the source-line barrier. | 2015-10-08 |
20150287736 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device with a nonvolatile memory is provided which has improved characteristics. The semiconductor device includes a control gate electrode, a memory gate electrode disposed adjacent to the control gate electrode, a first insulating film, and a second insulating film including therein a charge storing portion. Among these components, the memory gate electrode is formed of a silicon film including a first silicon region positioned over the second insulating film,. and a second silicon region positioned above the first silicon region. The second silicon region contains p-type impurities, and the concentration of p-type impurities of the first silicon region is lower than that of the p-type impurities of the second silicon region. | 2015-10-08 |
20150287737 | SILICON DOT FORMATION BY SELF-ASSEMBLY METHOD AND SELECTIVE SILICON GROWTH FOR FLASH MEMORY - Some embodiments of the present disclosure relate to a method that achieves a substantially uniform pattern of discrete storage elements within a memory cell. A copolymer solution having first and second polymer species is spin-coated onto a surface of a substrate and subjected to self-assembly into a phase-separated material having a regular pattern of micro-domains of the second polymer species within a polymer matrix having the first polymer species. The second polymer species is then removed resulting with a pattern of holes within the polymer matrix. An etch is then performed through the holes utilizing the polymer matrix as a hard-mask to form a substantially identical pattern of holes in a dielectric layer disposed over a seed layer disposed over the substrate surface. Epitaxial deposition onto the seed layer then utilized to grow a substantially uniform pattern of discrete storage elements within the dielectric layer. | 2015-10-08 |
20150287738 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes a substrate, a memory device, and a select transistor. The memory device is located on the substrate. The select transistor is located on the substrate and electrically connected to the memory device. The select transistor includes a select gate, a first dielectric layer, and a second dielectric layer. The select gate is located on the substrate. The first dielectric layer is adjacent to the second dielectric layer, and located between the select gate and the substrate. The first dielectric layer is closer to the memory device than the second dielectric layer. The thickness of the first dielectric layer is greater than the thickness of the second dielectric layer. | 2015-10-08 |
20150287739 | SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD OF THE SAME - A semiconductor apparatus according to an embodiment may include a first pipe gate divided by an isolation layer, a first pipe channel layer buried in the first pipe gate, a second pipe gate covering the first pipe channel layer, the first pipe gate and the isolation layer and a second pipe channel layer buried in the second pipe gate. | 2015-10-08 |
20150287740 | STRAIN ENGINEERING IN BACK END OF THE LINE - A semiconductor device including at least one semiconductor device on a first surface of a dielectric layer, and at least one stressor structure having an intrinsic stress on a second surface of the dielectric layer. The at least one semiconductor device and the at least one stressor structure are present on opposing sides of the dielectric layer. The at least one stressor structure induces a stress on the at least one semiconductor device opposite the intrinsic stress. | 2015-10-08 |
20150287741 | ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY APPARATUS - An array substrate, a display panel and a display apparatus are provided. The array substrate includes a display region and a non-display region. The non-display region is provided with multiple gate driving circuits and multiple signal lines disposed outside the gate driving circuits. Each gate driving circuit includes at least one Thin Film Transistor and at least one capacitor. The capacitor includes a first plate and a second plate, and the capacitor is located above or below the signal lines. Since the capacitor is not arranged in a gate driving circuit region, a size of the gate driving circuit may be reduced. Accordingly, a width of a border of the display apparatus is further reduced, thereby achieving a narrow border design. | 2015-10-08 |
20150287742 | THIN FILM TRANSISTOR SUBSTRATE AND METHOD FOR PRODUCING SAME - Each of the auxiliary capacitors ( | 2015-10-08 |
20150287743 | MULTI-HEIGHT FIN FIELD EFFECT TRANSISTORS - Semiconductor fins are formed on a top surface of a substrate. A dielectric material is deposited on the top surfaces of the semiconductor fins and the substrate by an anisotropic deposition. A dielectric material layer on the top surface of the substrate is patterned so that the remaining portion of the dielectric material layer laterally surrounds each bottom portion of at least one semiconductor fin, while not contacting at least one second semiconductor fin. Dielectric material portions on the top surfaces of the semiconductor fins may be optionally removed. Each first semiconductor fin has a lesser channel height than the at least one second semiconductor fin. The first and second semiconductor fins can be employed to provide fin field effect transistors having different channel heights. | 2015-10-08 |
20150287744 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - Provided is a display device, including: an insulation substrate; a thin film transistor positioned on the insulation substrate; a pixel electrode connected with the thin film transistor; a first alignment layer positioned on the pixel electrode; a second alignment layer spaced apart from the first alignment layer by a microcavity; a common electrode positioned on the second alignment layer; a roof layer on the common electrode; a liquid crystal injection hole in the common electrode and the roof layer to extend to a part of the microcavity; a liquid crystal layer filling the microcavity; and an overcoat on the roof layer to cover the liquid crystal injection hole to seal the microcavity. Each of the first alignment layer and the second alignment layer includes a plurality of heterogeneous layers. | 2015-10-08 |
20150287745 | Semiconductor Device - A semiconductor device including a circuit that has a reduced area is provided. Alternatively, a semiconductor device including a circuit that can have a smaller power supply voltage variation is provided. | 2015-10-08 |
20150287746 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - In a step F | 2015-10-08 |
20150287747 | DISPLAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND FLEXIBLE DISPLAY DEVICE HAVING DISPLAY SUBSTRATE - The present invention provides a display substrate and a manufacturing method thereof, and a flexible display device having the display substrate, which belong to the field of display technology, and can solve the problem of poor reliability of display substrates due to the damage to thin film transistors when the existing display substrates are bent. In the display substrate provided by the present invention, by introducing stress absorption units made of resin material into the display substrate, the stress generated by the display substrate bent is released by the resin material, and thin film transistors on the display substrate are thus less likely to be damaged, so that the reliability of the whole display substrate is improved. | 2015-10-08 |
20150287748 | DISPLAY DEVICE - A display device includes a first substrate, a second substrate disposed opposite to the first substrate, and a gate drive circuit having at least one first capacitor and a gate drive element. The first capacitor is located on the first substrate, and the gate drive element is disposed on the second substrate. The display device can reduce the wiring width of the gate drive circuit, narrow the frame edge and improve the transmissivity of sealant on the gate drive circuit. | 2015-10-08 |
20150287749 | Semiconductor Device, and Module and Electronic Appliance Including the Same - First to fourth switches are provided so that conduction states are able to be controlled independently of each other. The first switch, the third switch, and the second switch are electrically connected in series between a first wiring and a third wiring. The fourth switch has a function of controlling a conduction state between the light-emitting element and a fourth wiring. In a first transistor, a gate is electrically connected to a node to which the third switch and the second switch are electrically connected, one of a source and a drain is electrically connected to a second wiring, and the other is electrically connected to the light-emitting element. A capacitor includes first and second electrodes, the first electrode is electrically connected to a node to which the first switch and the third switch are electrically connected, and the second electrode is electrically connected to the light-emitting element. | 2015-10-08 |
20150287750 | FLEXIBLE DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - Discussed is a flexible display device to reduce a width of a bezel. The flexible display device includes a substrate being formed of a flexible material, a plurality of gate lines and a plurality of data lines crossing each other, a plurality of pads formed in a pad area of a non-display area, a plurality of links formed in a link area of the non-display area a plurality of insulation films formed over the entire surface of the substrate, and a first bending hole formed in a bending area of the non-display area, the first bending hole passing through at least one of the insulation films disposed under the link, wherein the bending area is bent such that the pads are disposed on the lower surface of the substrate. | 2015-10-08 |
20150287751 | DISPLAY DEVICE - A method for manufacturing a display device includes providing a first substrate, forming at least one first capacitor on the first substrate, providing a second substrate having a gate drive element formed thereon, and bonding the first substrate in alignment with the second substrate. | 2015-10-08 |
20150287752 | SENSOR SUBSTRATE, METHOD OF MANUFACTURING THE SAME, AND DISPLAY APPARATUS HAVING THE SAME - A sensor substrate includes a base substrate, and a sensing transistor and a switching transistor, which are on the base substrate. The sensing transistor includes a first gate electrode, an optical response pattern on the first gate electrode, a first source electrode and a first drain electrode on the optical response pattern and spaced apart from each other, a first oxide semiconductor pattern between the first source electrode and the optical response pattern, and a second oxide semiconductor pattern between the first drain electrode and the optical response pattern. The switching transistor includes a second gate electrode, a third oxide semiconductor pattern on the second gate electrode, and a second source electrode and a second drain electrode on the third oxide semiconductor pattern to be spaced apart from each other. | 2015-10-08 |
20150287753 | FRICTION MATERIAL - The problem addressed by the present invention is to provide a friction material, which does not contain a copper component or a metal fiber, has stable friction characteristics, has superior wear resistance, and has a low aggressiveness with respect to a partner material. The friction material does not contain a metal fiber or a copper component, and contains 10-35 vol % of potassium titanate, which has a plurality of convex shapes; 3-10 vol of an abrasive material having a Mohs hardness of at least 7, and 10-30 vol % of an elastomer-modified phenyl resin. | 2015-10-08 |
20150287754 | SEMICONDUCTOR DEVICE AND SOLID-STATE IMAGING DEVICE WITH TANTALUM OXIDE LAYER FORMED BY DIFFUSING A MATERIAL OF AN ELECTRODE OF NECESSITY OR A COUNTER ELECTRODE - There is provided a semiconductor device including a semiconductor layer that includes an active region, semiconductor elements that are formed using the active region, connection regions that are obtained by metalizing parts of the semiconductor layer in an island shape isolated from the active region, an insulation film that is formed to cover one main surface side of the semiconductor layer, electrodes that are disposed to face the semiconductor elements and the connection regions via the insulation film, and contacts that penetrate through the insulation film to be selectively formed in portions according to necessity among portions that connect the semiconductor elements or the connection regions to the electrodes. | 2015-10-08 |
20150287755 | MEMBER FOR SOLID-STATE IMAGE PICKUP DEVICE AND METHOD FOR MANUFACTURING SOLID-STATE IMAGE PICKUP DEVICE - A member for a solid-state image pickup device having a bonding plane with no gaps and a method for manufacturing the same are provided. The manufacturing method includes the steps of providing a first substrate provided with a photoelectric converter on its primary face and a first wiring structure, providing a second substrate provided with a part of a peripheral circuit on its primary face and a second wiring structure, and performing bonding so that the first substrate, the first wiring structure, the second wiring structure, and the second substrate are disposed in this order. In addition, at least one of an upper face of the first wiring structure and an upper face of the second wiring structure has a concave portion, and a conductive material forms a bottom face of the concave portion. | 2015-10-08 |
20150287756 | CURABLE RESIN COMPOSITION, PRODUCTION METHOD OF IMAGE SENSOR CHIP USING THE SAME, AND IMAGE SENSOR CHIP - There is provided a curable resin composition which is capable of being coated on a solid-state imaging device substrate and contains a dye having a maximum absorption wavelength in a wavelength range from 600 to 850 nm, a production method of image sensor chip comprising a step of coating the curable resin composition on a solid-state imaging device substrate to form a dye-containing layer, and a step of adhering a glass substrate having an infrared ray reflecting film onto the dye-containing layer, and an image sensor chip comprising a solid-state imaging device substrate and a dye-containing layer composed of the curable resin composition. | 2015-10-08 |
20150287757 | Interconnect Structure for Connecting Dies and Methods of Forming the Same - A structure includes a first chip having a first substrate, and first dielectric layers underlying the first substrate, with a first metal pad in the first dielectric layers. A second chip includes a second substrate, second dielectric layers over the second substrate and bonded to the first dielectric layers, and a second metal pad in the second dielectric layers. A conductive plug includes a first portion extending from a top surface of the first substrate to a top surface of the first metal pad, and a second portion extending from the top surface of the first metal pad to a top surface of the second metal pad. An edge of the second portion is in physical contact with a sidewall of the first metal pad. A dielectric layer spaces the first portion of the conductive plug from the first plurality of dielectric layers. | 2015-10-08 |
20150287758 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device is provided. The method comprises a first step of forming a first hole opened to a side of a first surface of a semiconductor substrate, the semiconductor substrate including the first surface and a second surface opposite to the first surface, a step of filling the first hole with an insulating member, a step of forming, on the first surface, an insulating film that covers the insulating member, a step of forming a second hole in the insulating film and the insulating member, a step of filing the second hole with a conductive member, a step of thinning the semiconductor substrate from the side of the second surface of the semiconductor substrate so as to expose the insulating member. | 2015-10-08 |
20150287759 | SOLID-STATE IMAGING DEVICE, METHOD OF MANUFACTURING THE SAME, AND IMAGING APPARATUS - A solid-state imaging device includes a photoelectric conversion section which is disposed on a semiconductor substrate and which photoelectrically converts incident light into signal charges, a pixel transistor section which is disposed on the semiconductor substrate and which converts signal charges read out from the photoelectric conversion section into a voltage, and an element isolation region which is disposed on the semiconductor substrate and which isolates the photoelectric conversion section from an active region in which the pixel transistor section is disposed. The pixel transistor section includes a plurality of transistors. Among the plurality of transistors, in at least one transistor in which the gate width direction of its gate electrode is oriented toward the photoelectric conversion section, at least a photoelectric conversion section side portion of the gate electrode is disposed within and on the active region with a gate insulating film therebetween. | 2015-10-08 |
20150287760 | APPARATUS FOR RADIATION DETECTION IN A RADIOGRAPHY IMAGING SYSTEM - This disclosure is directed at a photoconductive element for a digital X-ray imaging system which consists of a detector element comprising at least one semiconducting layer for absorbing photons, a first electrode coupled to a surface of said semiconducting layer, a second electrode coupled to a surface of said semiconducting layer, wherein said first electrode and said second electrode are separated horizontally, and at least one of said electrodes is electrically isolated from said semiconducting layer by an insulating layer; a readout circuit element coupled to said detector element; and a dielectric layer between said detector element and said readout circuit element. | 2015-10-08 |
20150287761 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a substrate including a front side, a back side opposite to the front side, and a high absorption structure disposed over the back side of the substrate and configured to absorb an electromagnetic radiation in a predetermined wavelength; and a dielectric layer including a high dielectric constant (high k) dielectric material, wherein the dielectric layer is disposed on the high absorption structure. | 2015-10-08 |
20150287762 | LIGHT-EMITTING DIODE AND APPLICATION THEREFOR - A light-emitting diode is provided to include: a transparent substrate having a first surface, a second surface, and a side surface; a first conductive semiconductor layer positioned on the first surface of the transparent substrate; a second conductive semiconductor layer positioned on the first conductive semiconductor layer; an active layer positioned between the first conductive semiconductor layer and the second conductive semiconductor layer; a first pad electrically connected to the first conductive semiconductor layer; and a second pad electrically connected to the second conductive semiconductor layer, wherein the transparent substrate is configured to discharge light generated by the active layer through the second surface of the transparent substrate, and the light-emitting diode has a beam angle of at least 140 degrees or more. Accordingly, a light-emitting diode suitable for a backlight unit or a surface lighting apparatus can be provided. | 2015-10-08 |
20150287763 | PIXEL ARRAY - A pixel array includes a substrate and color filter patterns. The substrate has pixel areas. Each of the pixel areas has a first sub-pixel region, a second sub-pixel region, a third sub-pixel region and a fourth sub-pixel region. The first, the second, the third and the fourth sub-pixel regions are arranged sequentially in the clockwise direction. The color filter patterns are disposed on the pixel areas of the substrate and located in the first, the second, the third and the fourth sub-pixel regions. The color filter patterns located in the first, the second, the third and the fourth sub-pixel regions of each of the pixel areas respectively have different colors. The color filter patterns respectively disposed in four adjacent pixel areas and located in the first, the second, the third and the fourth sub-pixel regions adjacent to each other and arranged in the clockwise direction have the same color. | 2015-10-08 |
20150287764 | SELF-REFERENCED MRAM ELEMENT AND DEVICE HAVING IMPROVED MAGNETIC FIELD - Self-reference-based MRAM element including: first and second magnetic tunnel junctions, each having a magnetoresistance that can be varied; and a field line for passing a field current to vary the magnetoresistance of the first and second magnetic tunnel junctions. The field line includes a first branch and a second branch each branch including cladding. The first branch is arranged for passing a first portion of the field current to selectively vary the magnetoresistance of the first magnetic tunnel junction, and the second branch is electrically connected in parallel with the first branch and arranged for passing a second portion of the field current to selectively vary the magnetoresistance of the second magnetic tunnel junction. The self-referenced MRAM element and an MRAM device including corresponding MRAM elements can use a reduced field current. | 2015-10-08 |
20150287765 | PHOTOELECTRIC CONVERSION DEVICE, SOLID-STATE IMAGE PICKUP UNIT, AND ELECTRONIC APPARATUS - A photoelectric conversion device includes an organic photoelectric conversion film; a first electrode and a second electrode provided with the organic photoelectric conversion film in between; and a charge block layer provided between the second electrode and the organic photoelectric conversion film, in which the charge block layer includes a work function adjustment layer including a metal element on the second electrode side of the organic photoelectric conversion film, the metal element being adopted to adjust a work function, and a first diffusion suppression layer provided between the work function adjustment layer and the second electrode and suppressing diffusion of the metal element to the second electrode side. | 2015-10-08 |
20150287766 | UNIT PIXEL OF AN IMAGE SENSOR AND IMAGE SENSOR INCLUDING THE SAME - A unit pixel of an image sensor is provided. The unit pixel includes a visible light detection layer and an infrared light detection layer disposed on the visible light detection layer. The visible light detection layer includes visible light pixels and color filters configured to detect visible light to output first charges. The infrared light detection layer includes at least one infrared light pixel configured to detect infrared light to output second charges. | 2015-10-08 |
20150287767 | Organic Light-Emitting Diode Display With Varying Anode Pitch - An electronic device may include a display having an array of organic light-emitting diode display pixels including red, green, and blue pixels. Anodes in the pixels of each color may have a variable pitch along a first dimension on a display substrate and a constant pitch along a second dimension on the display substrate that is orthogonal to the first dimension. Anodes in a row of red pixels may have a variable pitch along the row. anodes in a row of green pixels may have a variable pitch along the row, and anodes in a row of blue pixels may have a variable pitch along the row. The anodes of each different color of pixel may have constant pitches along columns of the array. | 2015-10-08 |
20150287768 | LIGHT-EMITTING ELEMENT DISPLAY DEVICE - A light-emitting element display device includes a substrate including a display area having plural pixels arranged in matrix form, a lower electrode provided in each of the plural pixels on the substrate and made of a conductor, an organic layer provided on the lower electrode and including a light-emitting layer, an upper electrode provided on the organic layer and made of a conductor, a polymer dispersed liquid crystal layer disposed at an opposite side to a substrate side of the upper electrode and covering the display area, and an electrode layer provided at the opposite side to the substrate side of the upper electrode and made of a conductor. The electrode layer is disposed to extend over the plural pixels. | 2015-10-08 |
20150287769 | ORGANIC ELECTROLUMINESCENCE DEVICE AND MANUFACTURING METHOD THEREOF - The present invention provides an organic electroluminescence device and a manufacturing method thereof. The organic electroluminescence device includes: an organic backing layer ( | 2015-10-08 |
20150287770 | ORGANIC EL DISPLAY DEVICE - An organic EL display device includes a lower electrode that is provided at each pixel, a bank that surrounds an outer circumference of the lower electrode and overlaps an outer circumferential edge of the lower electrode, an organic layer that is formed on the lower electrode and the bank, and an upper electrode that is formed on the organic layer. The bank contains a hygroscopic material. According to this display device, it is possible to confine an influence of moisture which has permeated thereinto to a more restricted area. | 2015-10-08 |
20150287771 | ORGANIC LIGHT-EMITTING DIODE DISPLAY AND MANUFACTURING METHOD THEREOF - An organic light-emitting diode (OLED) display and a manufacturing method thereof are disclosed. One inventive aspect includes a first substrate, a second substrate, and a first insulation layer, a metal layer and a second insulation layer formed on the first insulation layer. The metal layer is formed on the first insulating layer and has a first through hole and is formed of the same material as a data line applying a data signal to the display area. The second insulation layer is formed on the metal layer and has a second through hole. The inventive aspect further includes a sealing member formed by filling the first and second through hole so as to seal the first substrate to the second substrate. | 2015-10-08 |
20150287772 | SILICON PROCESS COMPATIBLE TRENCH MAGNETIC DEVICE - A mechanism is provided for integrating an inductor into a semiconductor. A circular or other closed loop trench is formed in a substrate with sidewalls connected by a bottom surface in the substrate. A first insulator layer is deposited on the sidewalls of the trench so as to coat the sidewalls and the bottom surface. A conductor layer is deposited on the sidewalls and the bottom surface of the trench so as to coat the first insulator layer in the trench such that the conductor layer is on top of the first insulator layer in the trench. A first magnetic layer is deposited on the sidewalls and bottom surface of the trench so as to coat the first insulator layer in the trench without filling the trench. The first magnetic layer deposited on the sidewalls forms an inner closed magnetic loop and an outer closed magnetic loop within the trench. | 2015-10-08 |
20150287773 | SILICON PROCESS COMPATIBLE TRENCH MAGNETIC DEVICE - A mechanism is provided for integrating an inductor into a semiconductor. A circular or other closed loop trench is formed in a substrate with sidewalls connected by a bottom surface in the substrate. A first insulator layer is deposited on the sidewalls of the trench so as to coat the sidewalls and the bottom surface. A conductor layer is deposited on the sidewalls and the bottom surface of the trench so as to coat the first insulator layer in the trench such that the conductor layer is on top of the first insulator layer in the trench. A first magnetic layer is deposited on the sidewalls and bottom surface of the trench so as to coat the first insulator layer in the trench without filling the trench. The first magnetic layer deposited on the sidewalls forms an inner closed magnetic loop and an outer closed magnetic loop within the trench. | 2015-10-08 |
20150287774 | HIGH VOLTAGE CAPACITOR AND METHOD - In accordance with an embodiment, an electrical element includes a first portion of a first dielectric material between a first portion of a first electrical conductor and a first portion of a second electrical conductor and a second portion of the first dielectric material between a second portion of the first electrical conductor and a first portion of a third electrical conductor. In accordance with another embodiment, a method includes forming a first electrically conductive structure over a first portion of the first layer of dielectric material and forming a second electrically conductive structure over a second portion of the first layer of dielectric material. A second layer of dielectric material is formed over the first electrically conductive structure and a third electrically conductive structure over the second layer of dielectric material, wherein the third electrically conductive structure is over portions of the first and second electrically conductive structures. | 2015-10-08 |
20150287775 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device ( | 2015-10-08 |
20150287776 | LOW PARASITIC CAPACITANCE FINFET DEVICE - Embodiments in accordance with the present invention include a method of fabricating a finFET device comprising forming a dielectric layer over the top surface of a semiconductor substrate. A first semiconductor layer is deposited over the dielectric layer. A second semiconductor layer is then deposited over the first semiconductor layer, such that the first semiconductor layer can be preferentially etched with respect to the second semiconductor layer. At least a fin is formed in the second semiconductor layer. A portion of the first semiconductor layer is removed from beneath a portion of the fin such that the bottom surface of the fin is exposed. A gate oxide layer is deposited over the fin such that the gate oxide layer surrounds a portion of the fin, and a gate structure is deposited over at least a portion of the gate oxide layer such that the gate structure surrounds the fin. | 2015-10-08 |
20150287777 | WIDE BANDGAP INSULATED GATE SEMICONDUCTOR DEVICE - A wide bandgap insulated gate semiconductor device includes a semiconductor substrate made of semiconductor having a bandgap wider than silicon; n | 2015-10-08 |
20150287778 | POWER SUPERJUNCTION MOSFET DEVICE WITH RESURF REGIONS - A semiconductor device which solves the following problem of a super junction structure: due to a relatively high concentration in the body cell region (active region), in peripheral areas (peripheral regions or junction end regions), it is difficult to achieve a breakdown voltage equivalent to or higher than in the cell region through a conventional junction edge terminal structure or resurf structure. The semiconductor device includes a power MOSFET having a super junction structure formed in the cell region by a trench fill technique. Also, super junction structures having orientations parallel to the sides of the cell region are provided in a drift region around the cell region. | 2015-10-08 |
20150287779 | METHOD OF FORMING A SEMICONDUCTOR DEVICE WITH TALL FINS AND USING HARD MASK ETCH STOPS - A hard mask etch stop is formed on the top surface of tall fins to preserve the fin height and protect the top surface of the fin from damage during etching steps of the transistor fabrication process. In an embodiment, the hard mask etch stop is formed using a dual hard mask system, wherein a hard mask etch stop layer is formed over the surface of a substrate, and a second hard mask layer is used to pattern a fin with a hard mask etch stop layer on the top surface of the fin. The second hard mask layer is removed, while the hard mask etch stop layer remains to protect the top surface of the fin during subsequent fabrication steps. | 2015-10-08 |
20150287780 | STRESS ENHANCED HIGH VOLTAGE DEVICE - A method of forming a device is disclosed. A substrate having a device region is provided. The device region comprises a source region, a gate region and a drain region defined thereon. A gate is formed in the gate region, a source is formed in the source region and drain is formed in the drain region. A trench is formed in an isolation region in the device region. The isolation region underlaps a portion of the gate. An etch stop (ES) stressor layer is formed over the substrate. The ES stressor layer lines the trench. | 2015-10-08 |
20150287781 | Fluid Sensor and Method for Examining a Fluid - Embodiments relate to a fluid sensor and a method for examining a fluid. A fluid sensor includes a substrate which comprises a recess for receiving a fluid to be examined, wherein the fluid sensor is implemented to detect electrical changes in the recess caused by the fluid to be examined. | 2015-10-08 |
20150287782 | INTEGRATED CIRCUITS AND METHODS OF FABRICATION THEREOF - Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method includes providing a semiconductor substrate, defining a length on the semiconductor substrate corresponding to opposing vertices of a nanowire, removing a portion of the semiconductor substrate to provide a first fin structure and a second fin structure, etching a first cavity proximate to the first side, depositing a protective layer in the first cavity, removing a portion of the protective layer to expose a portion of the semiconductor substrate, and etching a second cavity at the exposed semiconductor substrate where the first and second cavities communicate. The first and second fin structures are adjacent where the length of the first fin structure corresponds to the opposing vertices and has a first side and a second side. | 2015-10-08 |
20150287783 | Trap Rich Layer Formation Techniques for Semiconductor Devices - A trap rich layer for an integrated circuit chip is formed by chemical etching and/or laser texturing of a surface of a semiconductor layer. In some embodiments, a trap rich layer is formed by a technique selected from the group of techniques consisting of laser texturing, chemical etch, irradiation, nanocavity formation, porous Si-etch, semi-insulating polysilicon, thermal stress relief and mechanical texturing. Additionally, combinations of two or more of these techniques may be used to form a trap rich layer. | 2015-10-08 |
20150287784 | Reducing Resistance in Source and Drain Regions of FinFETs - A semiconductor structure includes a semiconductor fin on a top surface of a substrate, wherein the semiconductor fin includes a middle section having a first width; and a first and a second end section connected to opposite ends of the middle section, wherein the first and the second end sections each comprises at least a top portion having a second width greater than the first width. The semiconductor structure further includes a gate dielectric layer on a top surface and sidewalls of the middle section of the semiconductor fin; and a gate electrode on the gate dielectric layer. | 2015-10-08 |
20150287785 | N-POLAR III-NITRIDE TRANSISTORS - An N-polar III-N transistor includes a III-N buffer layer, a first III-N barrier layer, and a III-N channel layer, the III-N channel layer having a gate region and a plurality of access regions on opposite sides of the gate region. The compositional difference between the first III-N barrier layer and the III-N channel layer causes a conductive channel to be induced in the access regions of the III-N channel layer. The transistor also includes a source, a gate, a drain, and a second III-N barrier layer between the gate and the III-N channel layer. The second III-N barrier layer has an N-face proximal to the gate and a group-III face opposite the N-face, and has a larger bandgap than the III-N channel layer. The lattice constant of the first III-N barrier layer is within 0.5% of the lattice constant of the buffer layer. | 2015-10-08 |
20150287786 | POWER DEVICE AND METHOD FOR FABRICATING THE SAME - A power device having fast switching characteristic, while keeping EMI noise to a minimum and a method of fabricating the same are provided. The power device includes a first field stop layer having a first conductivity type, a first drift region formed on the first field stop layer and having a first conductivity type in an impurity concentration that is lower than the first field stop layer, a buried region formed on the first drift region and having the first conductivity type in an impurity concentration that is higher than the first drift region, a second drift region formed on the buried region, a power device cell formed at an upper portion of the second drift region, and a collector region formed below the first field stop layer. | 2015-10-08 |
20150287787 | Graphene Device And Method Of Fabricating A Graphene Device - In accordance with an example embodiment of the present invention, a device comprising one or more porous graphene layers, the or each graphene porous layer comprising a multiplicity of pores. The device may form at least part of a flexible and/or stretchable, and or transparent electronic device. | 2015-10-08 |
20150287788 | Method for Making a Sensor Device Using a Graphene Layer - A graphene layer is generated on a substrate. A plastic material is deposited on the graphene layer to at least partially cover the graphene layer. The substrate is separated into at least two substrate pieces. | 2015-10-08 |
20150287789 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A silicon carbide semiconductor device includes trenches formed in a lattice shape on the surface of a silicon carbide substrate on which a semiconductor layer is formed, and gate electrodes formed inside of the trenches via a gate insulating film. The depth of the trenches is smaller in a portion where the trenches are crossingly formed than in a portion where the trenches are formed in parallel to each other. Consequently, the silicon carbide semiconductor device is obtained that increases a withstand voltage between the gate electrodes and corresponding drain electrodes on the semiconductor device rear surface to prevent dielectric breakdown and, at the same time, has a large area of the gate electrodes, high channel density per unit area, and low ON resistance. | 2015-10-08 |
20150287790 | SELECTIVE GALLIUM NITRIDE REGROWTH ON (100) SILICON - A semiconductor structure including a (100) silicon substrate having a plurality openings located within the silicon substrate, wherein each opening exposes a surface of the silicon substrate having a (111) crystal plane. This structure further includes an epitaxial semiconductor material located on an uppermost surface of the (100) silicon substrate, and a gallium nitride material located adjacent to the surface of the silicon substrate having the (111) crystal plane and adjacent a portion of the epitaxial semiconductor material. The structure also includes at least one semiconductor device located upon and within the gallium nitride material and at least one other semiconductor device located upon and within the epitaxial semiconductor material. | 2015-10-08 |
20150287791 | NITRIDE SEMICONDUCTOR DEVICE AND NITRIDE SEMICONDUCTOR SUBSTRATE - An object of the present invention is to provide a nitride semiconductor device and a nitride semiconductor substrate in each of which a nitride semiconductor layer formed on a silicon substrate is improved in crystallinity to realize a decrease in on-resistance of a field-effect transistor. The nitride semiconductor device includes a silicon substrate, and a first nitride semiconductor layer formed over the silicon substrate and including a nitride semiconductor, wherein a Si <111> axial direction of the silicon substrate is different from a <0001> axial direction of the first nitride semiconductor layer. | 2015-10-08 |
20150287792 | III-Nitride Based Semiconductor Structure - The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications. | 2015-10-08 |
20150287793 | SEMICONDUCTOR DEVICE, MODULE, AND ELECTRONIC DEVICE - A transistor with favorable electrical characteristics is provided. A transistor with stable electrical characteristics is provided. A transistor having a low off-state current is provided. A semiconductor device including the transistor is provided. A semiconductor device includes a first conductor, a second conductor, a third conductor, an oxide semiconductor, and an insulator. The oxide semiconductor includes a first region, a second region, and a third region. The oxide semiconductor overlaps with the first conductor with the insulator therebetween in the first region. The oxide semiconductor is in contact with the second conductor in the second region. The oxide semiconductor is in contact with the third conductor in the third region. The oxide semiconductor includes a fourth region having a single crystal structure. The fourth region includes the first region. | 2015-10-08 |
20150287794 | P-TYPE ZnO BASED COMPOUND SEMICONDUCTOR LAYER, A ZnO BASED COMPOUND SEMICONDUCTOR ELEMENT, AND AN N-TYPE ZnO BASED COMPOUND SEMICONDUCTOR LAMINATE STRUCTURE - A p-type ZnO based compound semiconductor single crystal layer, wherein the layer includes a p-type ZnO based compound semiconductor single crystal layer co-doped with (i) a Group 11 element which is Cu and/or Ag and (ii) at least one Group 13 element selected from the group consisting of B, Ga, Al, and In, and a concentration of the Group 11 element [11] and a concentration of the Group 13 element [13] fulfill the relation: 0.9≦[11]/[13]<100. | 2015-10-08 |
20150287795 | PROCESSES FOR PREPARING INTEGRATED CIRCUITS WITH IMPROVED SOURCE/DRAIN CONTACT STRUCTURES AND INTEGRATED CIRCUITS PREPARED ACCORDING TO SUCH PROCESSES - Processes for preparing an integrated circuit for contact landing, processes for fabricating an integrated circuit, and integrated circuits prepared according to these processes are provided herein. An exemplary process for preparing an integrated circuit for contact landing includes providing a semiconductor structure that includes a transistor with source and drain regions, wherein at least one of the source and drain regions has a shaped contact structure overlaid with a contact etch stop layer and a pre-metal dielectric material. The pre-metal dielectric material is removed with one or more anisotropic etches, including at least one anisotropic etch selective to the pre-metal dielectric material. And, the contact etch stop layer overlaying the shaped contact structure is removed with a third anisotropic etch selective to the contact etch stop layer material to expose the shaped contact structure. | 2015-10-08 |
20150287796 | REDUCED PARASITIC CAPACITANCE WITH SLOTTED CONTACT - A FET device fabricated by providing a first conductor on a substrate, the first conductor having a first top surface with a first height above the substrate. A second conductor is provided adjacent the first conductor, the second conductor having a second top surface with a second height above the substrate. A portion of the second conductor is removed to provide a slot, wherein the slot is defined by opposing interior sidewalls and a bottom portion, such that the bottom portion of the slot is below the first height of the first conductor. An insulating material is deposited in the slot, the insulating material having a third top surface with a third height above the substrate, the third height being below the second height of the second conductor to provide space within the slot for a third conductor. The space within the slot is then filled with the third conductor. | 2015-10-08 |
20150287797 | HIGH-VOLTAGE METAL-OXIDE SEMICONDUCTOR TRANSISTOR AND METHOD OF FABRICATING THE SAME - The present invention provides a high-voltage metal-oxide-semiconductor (HVMOS) transistor comprising a substrate, a gate dielectric layer, a gate electrode and a source and drain region. The gate dielectric layer is disposed on the substrate and includes a protruded portion and a recessed portion, wherein the protruded portion is disposed adjacent to two sides of the recessed portion and has a thickness greater than a thickness of the recessed portion. The gate electrode is disposed on the gate dielectric layer. Thus, the protruded portion of the gate dielectric layer can maintain a higher breakdown voltage, thereby keeping the current from leaking through the gate. | 2015-10-08 |
20150287798 | Device Having Sloped Gate Profile and Method of Manufacture - A semiconductor device having an open profile gate electrode, and a method of manufacture, are provided. A funnel-shaped opening is formed in a dielectric layer and a gate electrode is formed in the funnel-shaped opening, thereby providing a gate electrode having an open profile. In some embodiments, first and second gate spacers are formed alongside a dummy gate electrode. The dummy gate electrode is removed and upper portions of the first and second gate spacers are removed. The first and second gate spacers may be formed of different materials having different etch rates. | 2015-10-08 |
20150287799 | SEMICONDUCTOR DEVICE, DISPLAY PANEL, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - The present invention suppresses electrochemical corrosion in a TFT between an oxide conductor and a source/drain wiring line containing aluminum. In this semiconductor device, a gate layer containing a gate line and a gate electrode is formed on a substrate, and a semiconductor layer made of an oxide semiconductor is formed so as to overlap the gate electrode of the gate layer, with a gate insulating film therebetween. A source electrode and a drain electrode are formed by spacing apart a source wiring layer on the semiconductor layer. The source wiring layer is configured by laminating first conductive layers made of Al and a second conductive layer constituted by a metal film made of a metal other than an amphoteric metal. The drain electrode and a pixel electrode are electrically connected to each other via a contact hole in protective layers formed on the source wiring layer. | 2015-10-08 |
20150287800 | METHOD FOR DEPINNING THE FERMI LEVEL OF A SEMICONDUCTOR AT AN ELECTRICAL JUNCTION AND DEVICES INCORPORATING SUCH JUNCTIONS - An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor. | 2015-10-08 |
20150287801 | SILICIDE FORMATION DUE TO IMPROVED SIGE FACETING - An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the field oxide so that the epitaxy hard mask overlaps the semiconductor material in PMOS source/drain region. SiGe semiconductor material is epitaxially formed in the source/drain regions, so that that a top edge of the SiGe semiconductor material at the field oxide does not extend more than one third of a depth of the SiGe in the source/drain region abutting the field oxide. Dielectric spacers on lateral surfaces of the gate structure on the field oxide extend onto the SiGe; at least one third of the SiGe is exposed. Metal silicide covers at least one third of a top surface of the SiGe. A contact has at least half of a bottom of the contact directly contacts the metal silicide on the SiGe. | 2015-10-08 |
20150287802 | TUNNEL MOSFET WITH FERROELECTRIC GATE STACK - A Tunnel Field-Effect Transistor (TFET) includes a source region in a semiconductor substrate, and a drain region in the semiconductor substrate. The source region and the drain region are of opposite conductivity types. The TFET further includes a gate stack over the semiconductor substrate, with the source region and the drain region extending to opposite sides of the gate stack. The gate stack includes a gate dielectric over the semiconductor substrate, and a ferroelectric layer over the gate dielectric. | 2015-10-08 |
20150287803 | Bi-Layer Metal Deposition in Silicide Formation - A method includes performing a first sputtering to form a first metal film on a surface of a semiconductor region. The first sputtering is performed using a first ion energy. The method further includes performing a second sputtering to form a second metal film over and contacting the first metal film, wherein the first and the second metal films includes a same metal. The second sputtering is performed using a second ion energy lower than the first ion energy. An annealing is performed to react the first and the second metal films with the semiconductor region to form a metal silicide. | 2015-10-08 |
20150287804 | SPACER SHAPER FORMATION WITH CONFORMAL DIELECTRIC FILM FOR VOID FREE PMD GAP FILL - An integrated circuit may be formed by removing source/drain spacers from offset spacers on sidewalls of MOS transistor gates, forming a contact etch stop layer (CESL) spacer layer on lateral surfaces of the MOS transistor gates, etching back the CESL spacer layer to form sloped CESL spacers on the lateral surfaces of the MOS transistor gates with heights of ¼ to ¾ of the MOS transistor gates, forming a CESL over the sloped CESL spacers, the MOS transistor gates and the intervening substrate, and forming a PMD layer over the CESL. | 2015-10-08 |
20150287805 | High Power Insulated Gate Bipolar Transistors - An insulated gate bipolar transistor (IGBT) includes a substrate having a first conductivity type, a drift layer having a second conductivity type opposite the first conductivity type, and a well region in the drift layer and having the first conductivity type. An epitaxial channel adjustment layer is on the drift layer and has the second conductivity type. An emitter region extends from a surface of the epitaxial channel adjustment layer through the epitaxial channel adjustment layer and into the well region. The emitter region has the second conductivity type and at least partially defines a channel region in the well region adjacent to the emitter region. A gate oxide layer is on the channel region, and a gate is on the gate oxide layer. Related methods are also disclosed. | 2015-10-08 |
20150287806 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of making a semiconductor device includes epitaxially growing a channel layer over a substrate. The method further includes depositing an active layer over the channel layer. Additionally, the method includes forming a gate structure over the active layer, the gate structure configured to deplete a 2DEG under the gate structure, the gate structure including a dopant. Furthermore, the method includes forming a barrier layer between the gate structure and the active layer, the barrier layer configured to block diffusion of the dopant from the gate structure into the active layer. | 2015-10-08 |
20150287807 | Method for Manufacturing a Transistor Device - A method for manufacturing a transistor device comprising a channel layer is disclosed. In one example, the method includes providing a substrate, epitaxially growing a strained layer on the substrate (defect free), epitaxially growing the channel layer on the epitaxially grown strained layer, and providing a gate structure on the channel layer. In this example, the method also includes selectively etching into the channel layer and at least partially in the epitaxially grown strained layer, thereby using the gate structure as a mask, and thereby creating a protrusion extending from the substrate. The protrusion may comprise a portion of the channel layer and at least an upper portion of the epitaxially grown strained layer, and may allow for elastic relaxation in the portions. | 2015-10-08 |
20150287808 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor structure is disclosed. The method comprises: providing an SOI substrate ( | 2015-10-08 |
20150287809 | MULTI-HEIGHT FIN FIELD EFFECT TRANSISTORS - Semiconductor fins are formed on a top surface of a substrate. A dielectric material is deposited on the top surfaces of the semiconductor fins and the substrate by an anisotropic deposition. A dielectric material layer on the top surface of the substrate is patterned so that the remaining portion of the dielectric material layer laterally surrounds each bottom portion of at least one semiconductor fin, while not contacting at least one second semiconductor fin. Dielectric material portions on the top surfaces of the semiconductor fins may be optionally removed. Each first semiconductor fin has a lesser channel height than the at least one second semiconductor fin. The first and second semiconductor fins can be employed to provide fin field effect transistors having different channel heights. | 2015-10-08 |
20150287810 | SiGe FINFET WITH IMPROVED JUNCTION DOPING CONTROL - A semiconductor device and a method for fabricating the device. The method includes: providing a FinFET having a source/drain region, at least one SiGe fin, a silicon substrate, a local oxide layer is formed on the silicon substrate, a gate structure is formed on the at least one SiGe fin and the local oxide layer, the gate structure is encapsulated by a gate hard mask and sidewall spacer layers; recessing the at least one SiGe fin in the source/drain region to the sidewall spacer layers and the silicon substrate layer; recessing the local oxide layer in the source/drain region to the sidewall spacer layer and the silicon substrate; growing a n-doped silicon layer on the silicon substrate; growing a p-doped silicon layer or p-doped SiGe layer on the n-doped silicon layer; and forming a silicide layer on the p-doped silicon layer or p-doped SiGe layer. | 2015-10-08 |
20150287811 | Methods to integrate SONOS into CMOS Flow - A method of forming a transistor is described. In one embodiment the method includes: forming a channel of a transistor in a surface of a substrate; forming a dielectric stack including a first oxide layer overlying the surface of the substrate, a middle layer comprising nitride overlying the first oxide layer and a second oxide layer overlying the middle layer; forming over the dielectric stack a mask exposing source and drain (S/D) regions of the transistor; etching the dielectric stack through the mask to thin the dielectric stack by removing the second oxide layer and at least a first portion of the middle layer in S/D regions of the transistor; and implanting dopants into S/D regions of the transistor through the thinned dielectric stack to form a lightly-doped drain (LDD) adjacent to the channel of the transistor. Other embodiments are also described. | 2015-10-08 |
20150287812 | Use Disposable Gate Cap to Form Transistors, and Split Gate Charge Trapping Memory Cells - A semiconductor device and method of making such device is presented herein. The method includes disposing a gate layer over a dielectric layer on a substrate and further disposing a cap layer over the gate layer. A first transistor gate is defined having an initial thickness substantially equal to a combined thickness of the cap layer and the gate layer. A first doped region is formed in the substrate adjacent to the first transistor gate. The cap layer is subsequently removed and a second transistor gate is defined having a thickness substantially equal to the thickness of the gate layer. Afterwards, a second doped region is formed in the substrate adjacent to the second transistor gate. The first doped region extends deeper in the substrate than the second doped region, and a final thickness of the first transistor gate is substantially equal to the thickness of the second transistor gate. | 2015-10-08 |
20150287813 | Method For Manufacturing Semiconductor Device - An embodiment of the disclosed invention is a method for manufacturing a semiconductor device, which includes the steps of: forming a first insulating film; performing oxygen doping treatment on the first insulating film to supply oxygen to the first insulating film; forming a source electrode, a drain electrode, and an oxide semiconductor film electrically connected to the source electrode and the drain electrode, over the first insulating film; performing heat treatment on the oxide semiconductor film to remove a hydrogen atom in the oxide semiconductor film; forming a second insulating film over the oxide semiconductor film; and forming a gate electrode in a region overlapping with the oxide semiconductor film, over the second insulating film. The manufacturing method allows the formation of a semiconductor device including an oxide semiconductor, which has stable electrical characteristics and high reliability. | 2015-10-08 |
20150287814 | Method For Manufacturing Semiconductor Device - In a transistor including an oxide semiconductor film, a metal oxide film for preventing electrification which is in contact with the oxide semiconductor film and covers a source electrode and a drain electrode is formed. Then, oxygen is introduced (added) to the oxide semiconductor film through the metal oxide film and heat treatment is performed. Through these steps of oxygen introduction and heat treatment, impurities such as hydrogen, moisture, a hydroxyl group, or hydride are intentionally removed from the oxide semiconductor film, so that the oxide semiconductor film is highly purified. Further, by providing the metal oxide film, generation of a parasitic channel on a back channel side of the oxide semiconductor film can be prevented in the transistor. | 2015-10-08 |
20150287815 | VERTICALLY BASE-CONNECTED BIPOLAR TRANSISTOR - Methods, devices, and systems for using and forming vertically base-connected bipolar transistors have been shown. The vertically base-connected bipolar transistors in the embodiments of the present disclosure are formed with a CMOS fabrication technique that decreases the transistor size while maintaining the high performance characteristics of a bipolar transistor. | 2015-10-08 |
20150287816 | SINGLE-CHARGE TUNNELLING DEVICE - A single-charge tunnelling device is described. The device comprises source and drain regions, a semiconductor region between the source and drain regions and a conductive island in the form of a diatomic impurity molecule consisting of first and second impurity atoms disposed in the semiconductor region. The semiconductor region may comprise silicon and the impurity atoms may be, for example, arsenic atoms. The first and second atoms have an inter-atomic distance, r, no more than 10 nm. | 2015-10-08 |
20150287817 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A first portion of a silicon carbide substrate having an impurity of a first conductivity type is disposed deeper than a first depth position. A second portion is disposed to extend from the first depth position to a second depth position shallower than the first depth position. A third portion is disposed to extend from the second depth position to a main surface. The second portion has a second impurity concentration higher than a first impurity concentration of the first portion. The third portion has a third impurity concentration not less than the first impurity concentration and less than the second impurity concentration. A body region having an impurity of a second conductivity type has an impurity concentration peak at a depth position shallower than the first depth position and deeper than the second depth position. | 2015-10-08 |
20150287818 | SEMICONDUCTOR STRUCTURE - A semiconductor structure comprising a substrate, a drift layer, at least a doping region, an epitaxial channel, a gate oxide layer, a gate metal and an isolation layer is provided. The drift layer is disposed on the substrate. The doping region comprises a p-well region, an n+ region and a p+ region, wherein the n+ region and a portion of p+ region are disposed in the p-well region which is adjacent to the n+ region. The epitaxial channel is disposed over the drift layer and covers at least a portion of the n+ region. The epitaxial channel is composed of at least two epitaxial layers whose conduction types or doping concentrations are not identical. The gate oxide layer is disposed on the epitaxial channel. The gate metal is disposed on the gate oxide layer. The isolation layer is disposed on the gate metal and the gate oxide layer. | 2015-10-08 |
20150287819 | SEMICONDUCTOR DEVICE AND FORMATION THEREOF - A semiconductor device and methods of formation are provided. The semiconductor device includes a first metal alloy over a first active region of a fin and a second metal alloy over a second active region of the fin. A conductive layer is over a channel region of the fin. A semiconductive layer is over the conductive layer. The conductive layer over the channel region suppresses current leakage and the semiconductive layer over the conductive layer reduces electro flux from a source to a drain, as compared to a channel region that does not have such a conductive layer or a semiconductive layer over a conductive layer. The semiconductor device having the first metal alloy as at least one of the source or drain requires a lower activation temperature than a semiconductor device that does not have a metal alloy as a source or a drain. | 2015-10-08 |
20150287820 | CLOSED CELL LATERAL MOSFET USING SILICIDE SOURCE AND BODY REGIONS - A closed cell lateral MOSFET device includes minimally sized source/body contacts formed in one or more source cells with silicided source and body diffusion regions formed therein. In this manner, the cell pitch of the cellular transistor array is kept small while the ruggedness of the transistor is ensured. In other embodiments, a closed cell lateral MOSFET device is formed using silicided source and body diffusion regions and self-aligned contacts or borderless contacts as the source/body contacts. The polysilicon gate mesh can be formed using minimum polysilicon-to-polysilicon spacing to minimize the cell pitch of the cellular transistor array. | 2015-10-08 |
20150287821 | SEMICONDUCTOR DEVICE WITH AN SGT AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a P | 2015-10-08 |
20150287822 | SEMICONDUCTOR DEVICE PRODUCTION METHOD AND SEMICONDUCTOR DEVICE - A semiconductor device production method includes a first step of forming a planar silicon layer on a silicon substrate and forming first and second pillar-shaped silicon layers on the planar silicon layer; a second step of forming a gate insulating film around the first and second pillar-shaped silicon layers, forming a metal film and a polysilicon film around the gate insulating film, controlling a thickness of the polysilicon film to be smaller than a half of a distance between the first and second pillar-shaped silicon layers, depositing a resist, exposing the polysilicon film on side walls of upper portions of the first and second pillar-shaped semiconductor layers, etching-away the exposed polysilicon film, stripping the third resist, and etching-away the metal film; and a third step of forming a resist for forming a gate line and performing anisotropic etching to form a gate line and first and second gate electrodes. | 2015-10-08 |
20150287823 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; forming a lightly doped drain in the substrate; and performing a first implantation process for implanting fluorine ions at a tiled angle into the substrate and part of the gate structure. | 2015-10-08 |
20150287824 | INTEGRATED CIRCUITS WITH STRESSED SEMICONDUCTOR SUBSTRATES AND PROCESSES FOR PREPARING INTEGRATED CIRCUITS INCLUDING THE STRESSED SEMICONDUCTOR SUBSTRATES - Integrated circuits with stressed semiconductor substrates, processes for preparing stressed semiconductor substrates, and processes for preparing integrated circuits including stressed semiconductor substrates are provided herein. An exemplary process for preparing a stressed semiconductor substrate includes providing a semiconductor substrate of a semiconductor material having a first crystalline lattice constant; introducing a dopant on and into a surface layer of the semiconductor substrate via ion implantation at an amount above a solubility limit of the dopant in the semiconductor material to form a dopant-containing surface layer of the semiconductor substrate; applying energy to the dopant-containing surface layer of the semiconductor substrate with an ultra-short pulse laser to form a molten semiconductor:dopant layer on a surface of the semiconductor substrate; and removing the energy such that the molten semiconductor:dopant layer forms a solid semiconductor:dopant layer with a second crystalline lattice having a second lattice constant that differs from the first lattice constant. | 2015-10-08 |
20150287825 | Transistors - Some embodiments include a construction having a second semiconductor material over a first semiconductor material. A region of the second semiconductor material proximate the first semiconductor material has strain due to different lattice characteristics of the first and second semiconductor materials. A transistor gate extends downwardly into the second semiconductor material. Gate dielectric material is along sidewalls and a bottom of the transistor gate. Source/drain regions are along the sidewalls of the transistor gate, and the gate dielectric material is between the source/drain regions and the transistor gate. A channel region extends between the source/drain regions and is under the bottom of the transistor gate. At least some of the channel region is within the strained region. | 2015-10-08 |
20150287826 | METHOD OF FORMING WELL-CONTROLLED EXTENSION PROFILE IN MOSFET BY SILICON GEMANIUM BASED SACRIFICIAL LAYER - The present disclosure provides a method to improve and control the source/drain extension profile, which is compatible with device scaling. First, a sacrificial layer portion interposed between a channel layer portion and an uppermost surface of a semiconductor substrate having trenches is laterally recessed to provide a lateral recess on each side of the sacrificial layer portion. After filling the lateral recesses and trenches with a doped semiconductor material, a source/drain extension region is formed by a subsequent anneal during which dopants in the doped semiconductor material diffuse into portions of the channel layer portion over the lateral recesses and portions of the semiconductor substrate adjacent the lateral recesses. | 2015-10-08 |
20150287827 | ROBUST GATE SPACER FOR SEMICONDUCTOR DEVICES - After formation of a gate structure and a lower dielectric spacer laterally surrounding the gate structure, a disposable material layer is deposited and planarized such that the top surface of the disposable material layer is formed below the topmost surface of the lower dielectric spacer. An upper dielectric spacer is formed around the gate structure and over the top surface of the disposable material layer. The disposable material layer is removed selective to the upper and lower dielectric spacers and device components underlying the gate structure. Semiconductor surfaces of the gate structure can be laterally sealed by the stack of the lower and upper dielectric spacers. Formation of any undesirable semiconductor deposition on the gate structure can be avoided by the combination of the lower and upper dielectric spacers during a subsequent selective epitaxy process. | 2015-10-08 |
20150287828 | SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME - A semiconductor device and a method of manufacturing the same are provided, wherein an example method may include: forming a first semiconductor layer and a second semiconductor layer sequentially on a substrate; patterning the second semiconductor layer and the first semiconductor layer to form a fin; forming an isolation layer on the substrate, wherein the isolation layer exposes a portion of the first semiconductor layer; forming a sacrificial gate stack crossing over the fin on the isolation layer; selectively etching the second semiconductor layer with the sacrificial gate stack as a mask, to expose the first semiconductor layer; selectively etching the first semiconductor layer, to form a void beneath the second semiconductor layer; filling the void with a dielectric material; forming a third semiconductor layer on the substrate, to form source/drain regions; and forming a gate stack to replace the sacrificial gate stack. | 2015-10-08 |