41st week of 2020 patent applcation highlights part 63 |
Patent application number | Title | Published |
20200321302 | NANOWIRES PLATED ON NANOPARTICLES - In some examples, a system comprises a set of nanoparticles and a set of nanowires extending from the set of nanoparticles. | 2020-10-08 |
20200321303 | NANOWIRE INTERFACES - In some examples, a system comprises a first component having a first surface, a first set of nanoparticles coupled to the first surface, and a first set of nanowires extending from the first set of nanoparticles. The system also comprises a second component having a second surface, a second set of nanoparticles coupled to the second surface, and a second set of nanowires extending from the second set of nanoparticles. The system further includes an adhesive positioned between the first and second surfaces. The first and second sets of nanowires are positioned within the adhesive. | 2020-10-08 |
20200321304 | DIELECTRIC AND METALLIC NANOWIRE BOND LAYERS - In some examples, an electronic device comprises a first component having a surface, a second component having a surface, and a bond layer positioned between the surfaces of the first and second components to couple the first and second components to each other. The bond layer includes a set of metallic nanowires and a dielectric portion. The dielectric portion comprises a polymer matrix and dielectric nanoparticles. | 2020-10-08 |
20200321305 | CONNECTION STRUCTURE AND METHOD FOR PRODUCING SAME - One aspect of the invention is a method of manufacturing a connection structure, including disposing an adhesive layer between a first electronic member including a first substrate and a first electrode formed on the first substrate and a second electronic member including a second substrate and a second electrode formed on the second substrate, and pressure-bonding the first electronic member and the second electronic member via the adhesive layer such that the first electrode and the second electrode are electrically connected to each other, wherein the first electronic member further including an insulating layer formed on a side of the first electrode opposite to the first substrate, and the adhesive layer including: a first conductive particle being a dendritic conductive particle; and a second conductive particle being a conductive particle other than the first conductive particle and having a non-conductive core and a conductive layer provided on the core. | 2020-10-08 |
20200321306 | SEMICONDUCTOR DEVICE, POWER CONVERSION APPARATUS AND SEMICONDUCTOR DISPOSITION METHOD - The semiconductor device includes a semiconductor element substrate having an insulation property, and a wire for positioning the semiconductor element with respect to the semiconductor element substrate. The semiconductor element substrate includes a disposition region for disposing the semiconductor element. The wire is provided at least at a part of the periphery of the disposition region. | 2020-10-08 |
20200321307 | DIE PROCESSING - Representative implementations provide techniques and systems for processing integrated circuit (IC) dies. Dies being prepared for intimate surface bonding (to other dies, to substrates, to another surface, etc.) may be processed with a minimum of handling, to prevent contamination of the surfaces or the edges of the dies. The techniques include processing dies while the dies are on a dicing sheet or other device processing film or surface. Systems include integrated cleaning components arranged to perform multiple cleaning processes simultaneously. | 2020-10-08 |
20200321308 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device is provided with a semiconductor element having a plurality of electrodes, a plurality of terminals electrically connected to the plurality of electrodes, and a sealing resin covering the semiconductor element. The sealing resin covers the plurality of terminals such that a bottom surface of the semiconductor element in a thickness direction is exposed. A first terminal, which is one of the plurality of terminals, is disposed in a position that overlaps a first electrode, which is one of the plurality of electrodes, when viewed in the thickness direction. The semiconductor device is provided with a conductive connection member that contacts both the first terminal and the first electrode. | 2020-10-08 |
20200321309 | CHIP ASSEMBLING ON ADHESION LAYER OR DIELECTRIC LAYER, EXTENDING BEYOND CHIP, ON SUBSTRATE - Electronic module, which comprises a first substrate, a first dielectric layer on the first substrate, at least one electronic chip, which is mounted with a first main surface directly or indirectly on partial region of the first dielectric layer, a second substrate over a second main surface of the at least one electronic chip, and an electrical contacting for the electric contact of the at least one electronic chip through the first dielectric layer, wherein the first adhesion layer on the first substrate extends over an area, which exceeds the first main surface. | 2020-10-08 |
20200321310 | DEVICE AND METHOD FOR REEL-TO-REEL LASER REFLOW - The present invention relates to a reel-to-reel layer reflow method, which emits a uniformized laser beam, which can easily adjust the emission area, and which is for the purpose of improving productivity. An embodiment of the present invention provides a reel-to-reel layer reflow method comprising the steps of: a) transferring a substrate, which has been wound in a roll type, to one side while unwinding the same; b) forming a solder portion on the substrate; c) seating an emission target element on the solder portion and seating a non-emission target element on the substrate; d) surface-emitting a laser beam to the solder portion, on which the emission target element is seated, such that the emission target element is attached to the substrate; e) inspecting the substrate structure manufactured through said step d); and f) winding the substrate structure in a roll type. | 2020-10-08 |
20200321311 | METHOD OF MOUNTING DIE - A method of mounting a die includes: preparing a die having a bump formation surface on which a plurality of bump electrodes are formed; disposing a vacuum suction tool having a suction surface above the die such that the suction surface faces toward the bump formation surface; sandwiching a porous sheet between the suction surface and the bump formation surface and suctioning the die by the vacuum suction tool; and mounting the die that has been suctioned by the vacuum suction tool in a bonding region of a substrate with an adhesive material interposed therebetween, the porous sheet having a thickness equal to or greater than the protrusion height of the bump electrodes on the bump formation surface. Stabilization and ease of maintenance of vacuum suction can thereby be improved. | 2020-10-08 |
20200321312 | METAL FRAME, DUMMY WAFER, SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A metal frame that is used in a dummy wafer in which chip-like semiconductor elements and a rewiring layer are integrated. A plurality of openings in which the chip-like semiconductor elements are disposed are formed in the metal plate, and a lattice structure is formed with the frames that are the portions between adjacent openings of the plurality of openings. Of the frames forming the lattice structure, the frames located in dicing areas of the dummy wafer are arranged in a discontinuous manner. | 2020-10-08 |
20200321313 | SEMICONDUCTOR PACKAGE AND METHOD MANUFACTURING THE SAME - A semiconductor package including an insulating encapsulation, an integrated circuit component, and conductive elements is provided. The integrated circuit component is encapsulated in the insulating encapsulation, wherein the integrated circuit component has at least one through silicon via protruding from the integrated circuit component. The conductive elements are located on the insulating encapsulation, wherein one of the conductive elements is connected to the at least one through silicon via, and the integrated circuit component is electrically connected to the one of the conductive elements through the at least one through silicon via. | 2020-10-08 |
20200321314 | SEMICONDUCTOR PACKAGES AND MANUFACTURING METHODS THEREOF - A semiconductor package includes a first chip, a plurality of through vias and an encapsulant. The first chip has a first via and a protection layer thereon. The first via is disposed in the protection layer. The through vias are disposed aside the first chip. The encapsulant encapsulates the first chip and the plurality of through vias. A surface of the encapsulant is substantially coplanar with surfaces of the protection layer and the plurality of through vias. | 2020-10-08 |
20200321315 | DIE STACKS AND METHODS FORMING SAME - A method includes thinning a semiconductor substrate of a device die to reveal through-substrate vias that extend into the semiconductor substrate, and forming a first redistribution structure, which includes forming a first plurality of dielectric layers over the semiconductor substrate, and forming a first plurality of redistribution lines in the first plurality of dielectric layers. The first plurality of redistribution lines are electrically connected to the through-substrate vias. The method further includes placing a first memory die over the first redistribution structure, and forming a first plurality of metal posts over the first redistribution structure. The first plurality of metal posts are electrically connected to the first plurality of redistribution lines. The first memory die is encapsulated in a first encapsulant. A second plurality of redistribution lines are formed over, and electrically connected to, the first plurality of metal posts and the first memory die. | 2020-10-08 |
20200321316 | STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH DIE SUBSTRATE EXTENSIONS - Stacked semiconductor die assemblies with die substrate extensions are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first die mounted to the package substrate, and a second die mounted to the first die. The first die includes a first die substrate, and the second die includes a second die substrate attached to the first die substrate. At least one of the first and second dies includes a semiconductor substrate and a die substrate extension adjacent the semiconductor substrate. The die substrate extension comprises a mold material that at least partially defines a planform. | 2020-10-08 |
20200321317 | DUAL SIDED FAN-OUT PACKAGE HAVING LOW WARPAGE ACROSS ALL TEMPERATURES - Semiconductor devices including a dual-sided redistribution structure and having low-warpage across all temperatures and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die electrically coupled to a first side of a redistribution structure and a second semiconductor die electrically coupled to a second side of the redistribution structure opposite the first side. The semiconductor device also includes a first molded material on the first side, a second molded material on the second side, and conductive columns electrically coupled to the first side and extending through the first molded material. The first and second molded materials can have the same volume and/or coefficients of thermal expansion to inhibit warpage of the semiconductor device. | 2020-10-08 |
20200321318 | MEMORY DEVICES WITH CONTROLLERS UNDER MEMORY PACKAGES AND ASSOCIATED SYSTEMS AND METHODS - Semiconductor devices with controllers under stacks of semiconductor packages and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a package substrate, a controller attached to the package substrate, and at least two semiconductor packages disposed over the controller. Each semiconductor package includes a plurality of semiconductor dies. The semiconductor device further includes an encapsulant material encapsulating the controller and the at least two semiconductor packages. | 2020-10-08 |
20200321319 | POWER CONVERTER - A power converter includes: at least one pair of first and second semiconductor devices including multiple first and second semiconductor chips, having first and second switching elements providing upper and lower arms, and multiple first and second main terminals having at least one of multiple first and second high potential terminals and multiple first and second low potential terminals; and a bridging member providing an upper and lower coupling portion, together with the first low and second high potential terminals. The first and second semiconductor chips are arranged in line symmetry with respect to first and second axes and in line symmetry with the second axis as a symmetry axis to differentiate the arrangement of the second low potential terminal with respect to the second high potential terminal from the arrangement of the first low potential terminal with respect to the first high potential terminal. | 2020-10-08 |
20200321320 | SEMICONDUCTOR DEVICE - According to an embodiment, a semiconductor device includes a first metal plate, a second metal plate, and two or more semiconductor units. The two or more semiconductor units are disposed on the first metal plate. The each of the two or more semiconductor units includes a first metal member, a second metal member, and a semiconductor element. The first metal member has a first connection surface connected to the first major surface. The second metal member has a second connection surface connected to the second major surface. The semiconductor element includes an active region having surfaces respectively opposing the first connection surface and the second connection surface. A surface area of the first connection surface is greater than a surface area of the surface of the active region opposing the first connection surface. A surface area of the second connection surface is greater than a surface area of the surface of the active region opposing the second connection surface. | 2020-10-08 |
20200321321 | DISPLAYING APPARATUS HAVING LIGHT EMITTING DEVICE, METHOD OF MANUFACTURING THE SAME AND METHOD OF TRANSFERRING LIGHT EMITTING DEVICE - A displaying apparatus including: a panel substrate; a plurality of light emitting devices arranged on the panel substrate; and at least one connection tip disposed on one surface of each of the light emitting devices. Each of the light emitting devices includes a light emitting structure including a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active layer interposed between the first and second conductivity type semiconductor layers; and first and second electrode pads disposed on the light emitting structure. | 2020-10-08 |
20200321322 | DISPLAY APPARATUS - A display apparatus includes a blue light emitting element configured to emit blue light; a red light emitting element configured to emit red light; and a green light emitting element configured to emit green light. The blue light emitting element may include a first light emitting diode configured to emit light having a maximum intensity at a wavelength shorter than a blue wavelength; and a blue filter configured to transmit light having the blue wavelength. | 2020-10-08 |
20200321323 | SEMICONDUCTOR COMPOSITE DEVICE AND PACKAGE BOARD USED THEREIN - A semiconductor composite device is provided that includes a voltage regulator, a package board, and a load, and converts an input DC voltage into a different DC voltage to supply the converted DC voltage to the load. The VR includes a semiconductor active element. The package board includes a C layer in which a capacitor is formed, and an L layer in which an inductor is formed. A plurality of through holes penetrate the C layer and the L layer in a direction perpendicular to the mounting face in the package board. The capacitor is connected to the load through the through hole. The inductor is connected to the load through the through hole and to the VR through the through hole. | 2020-10-08 |
20200321324 | BONDED ASSEMBLY CONTAINING SIDE BONDING STRUCTURES AND METHODS OF MANUFACTURING THE SAME - A bonded assembly includes a first stack containing a first semiconductor die bonded to a second semiconductor die along a stacking direction, first external bonding pads formed within the first semiconductor die, and bonding connection wires. Each of the bonding connection wires extends over a sidewall of the first semiconductor die and protrudes into the first semiconductor die through the sidewall of the first semiconductor die to contact a respective one of the first external bonding pads. | 2020-10-08 |
20200321325 | 3D STACKED INTEGRATED CIRCUITS HAVING FUNCTIONAL BLOCKS CONFIGURED TO PROVIDE REDUNDANCY SITES - A three-dimensional stacked integrated circuit (3D SIC) that can have at least a first 3D XPoint (3DXP) die and, in some examples, can have at least a second 3DXP die too. In such examples, the first 3DXP die and the second 3DXP die can be stacked. The 3D SIC can be partitioned into a plurality of columns that are perpendicular to each of the stacked dies. In such examples, when a first column of the plurality of columns is determined as failing, data stored in the first column can be replicated to a second column of the plurality of columns. Also, for example, when a part of a first column of the plurality of columns is determined as failing, data stored in the part of the first column can be replicated to a corresponding part of a second column of the plurality of columns. | 2020-10-08 |
20200321326 | Stress Reduction Apparatus and Method - A method comprises depositing a protection layer over a first substrate, wherein the first substrate is part of a first semiconductor die, forming an under bump metallization structure over the protection layer, forming a connector over the under bump metallization structure, forming a first dummy plane along a first edge of a top surface of the first semiconductor die and forming a second dummy plane along a second edge of the top surface of the first semiconductor die, wherein the first dummy plane and the second dummy plane form an L-shaped region. | 2020-10-08 |
20200321327 | Transient Voltage Suppression Device with Thermal Cutoff - A transient voltage suppression (TVS) device including a TVS diode having a first electrode and a second electrode, an insulating plate disposed on the first electrode, a first terminal lead connected to the insulating plate, a second terminal lead connected to the second electrode, and an thermal cutoff element connecting the first terminal lead to the first electrode, the thermal cutoff element configured to melt and break an electrical connection between the first terminal lead and the first electrode when a temperature of the TVS diode exceeds a predetermined safety temperature. | 2020-10-08 |
20200321328 | ELECTROSTATIC DISCHARGE PROTECTION DEVICES - An electrostatic discharge protection device includes a first well region, a second well region, a first doped region, and a first heavily doped region. The first well region and the second well region are disposed in a semiconductor substrate. The first doped region is disposed in the first well region and the second well region. The first heavily doped region is disposed in the first doped region in the first well region. The first well region and the first doped region have a first conductivity type, and the second well region and the first heavily doped region have a second conductivity type that is the opposite of the first conductivity type. | 2020-10-08 |
20200321329 | DEVICE OF PROTECTION AGAINST ELECTROSTATIC DISCHARGES - A device of protection against electrostatic discharges is formed in a semiconductor substrate of a first conductivity type that is coated with a semiconductor layer of a second conductivity type. A buried region of the second conductivity type is positioned at an interface between the semiconductor substrate and the semiconductor layer. First and second wells of the first conductivity type are formed in the semiconductor layer and a region of the second conductivity type is formed in the second well. A stop channel region of the second conductivity type is provided in the semiconductor layer to laterally separating the first well from the second well, where no contact is present between this stop channel region and either of the first and second wells. | 2020-10-08 |
20200321330 | DEVICE OF PROTECTION AGAINST ELECTROSTATIC DISCHARGES - A semiconductor substrate of a first conductivity type is coated with a semiconductor layer of a second conductivity type. A buried region of the second conductivity type is formed an interface between the semiconductor substrate and the semiconductor layer. First and second wells of the first conductivity type are provided in the semiconductor layer. A second region of the second conductivity type is formed in the first well. A third region of the second conductivity type is formed in the second well. The first well, the semiconducting layer, the second well and the third region form a first lateral thyristor. The second well, the semiconductor layer, the first well and the second region form a second lateral thyristor. The buried region and semiconductor substrate form a zener diode which sets the trigger voltage for the lateral thyristors. | 2020-10-08 |
20200321331 | TRANSIENT TRIGGERED ACTIVE FET WITH SURGE IMMUNITY - A microelectronic device has a protected line and a reference line, and an active field effect transistor (FET) coupled between the protected line and the reference line. The microelectronic device includes an electrostatic discharge (ESD) trigger circuit coupled to the gate of the active FET, to turn on the active FET when an ESD event occurs on the protected line. The microelectronic device further includes a transient detection circuit having a high bandwidth detector, an ESD detector, and an output driver. The ESD detector is configured to provide a CLEAR signal to the output driver when an ESD event occurs on the protected line. The output driver is configured to turn off the active FET when a voltage surge, which can damage the active FET, occurs on the protected line, but enable operation of the active FET by the ESD trigger circuit during an ESD event. | 2020-10-08 |
20200321332 | ADDITIONAL SPACER FOR SELF-ALIGNED CONTACT FOR ONLY HIGH VOLTAGE FINFETS - A method includes forming a first region including a pair of first FinFETs and a second region including a pair of second FinFETs on a substrate. Each FinFET includes a metal gate having a first spacer adjacent thereto, and each first FinFET has a gate dielectric that is thicker than a gate dielectric of each second FinFET, such that the first FinFETs can be higher voltage input/output devices. The method forms a first contact between the metal gates of the pair of first FinFETs with a second spacer thereabout, the second spacer contacting a portion of each first spacer. The second spacer thus has a portion extending parallel to the metal gates, and a portion extending perpendicular to the metal gates. A second contact is formed between the metal gates of the pair of second FinFETs, and the second contact devoid of the second spacer. | 2020-10-08 |
20200321333 | FIN END PLUG STRUCTURES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION - Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first isolation structure over a first end of a fin. A gate structure is over the fin and is spaced apart from the first isolation structure along the direction. A second isolation structure is over a second end of the fin, the second end opposite the first end. The second isolation structure is spaced apart from the gate structure. The first isolation structure and the second isolation structure both comprise a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material. The recessed second dielectric material laterally surrounds at least a portion of a third dielectric material different from the first and second dielectric materials. | 2020-10-08 |
20200321334 | SEMICONDUCTOR DEVICE - A semiconductor device includes a fin-type pattern extending in a first direction, a device isolation film surrounding the fin-type pattern, while exposing an upper portion of the fin-type pattern, a gate electrode extending on the device isolation film and the fin-type pattern in a second direction intersecting the first direction, a gate isolation film isolating the gate electrode in the second direction, and including a first material and on the device isolation film, an interlayer insulating film filling a side surface of the fin-type pattern and including a second material different from the first material. | 2020-10-08 |
20200321335 | MULTI-BAND, DUAL-POLARIZATION REFLECTOR ANTENNA - An antenna includes a reflector and a waveguide assembly. The waveguide assembly includes a feed assembly and a support member that extends from behind the reflector to orient the feed assembly for direct illumination of the reflector. The waveguide assembly includes a first waveguide coupled to a first portion of a common waveguide, a second waveguide coupled to a second portion of the common waveguide, and a septum layer that includes a septum polarizer coupled between the common waveguide and the first and second waveguides. | 2020-10-08 |
20200321336 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A method for forming a semiconductor device is provided. The method includes removing a first portion of a substrate to form a recess in the substrate. The method includes forming an epitaxy layer in the recess. The epitaxy layer and the substrate are made of different semiconductor materials. The method includes forming a stacked structure of a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked over the substrate and the epitaxy layer. The method includes removing a second portion of the stacked structure and a third portion of the epitaxy layer to form trenches passing through the stacked structure and extending into the epitaxy layer, The stacked structure is divided into a first fin element and a second fin element by the trenches, and the first fin element and the second fin element are over the substrate and the epitaxy layer respectively. | 2020-10-08 |
20200321337 | METAL GATE MODULATION TO IMPROVE KINK EFFECT - The present disclosure relates to a method of forming an integrated chip. The method includes forming an isolation structure within a substrate. The isolation structure surrounds a device region of the substrate. A sacrificial gate material is formed over the isolation structure and the device region of the substrate. A part of the sacrificial gate material is removed and a second metal is deposited where the part of the sacrificial gate material was removed. A remainder of the sacrificial gate material is subsequently removed and a first metal is deposited where the remainder of the sacrificial gate material was removed. The first metal is different than the second metal. | 2020-10-08 |
20200321338 | SEMICONDUCTOR DEVICE - A semiconductor device includes: channel patterns disposed on a substrate; a pair of source/drain patterns disposed at first and second sides of each of the channel patterns; and a gate electrode disposed around the channel patterns, wherein the gate electrode includes a first recessed top surface between adjacent channel patterns, wherein the channel patterns are spaced apart from the substrate, and wherein the gate electrode is disposed between the substrate and the channel patterns. | 2020-10-08 |
20200321339 | Method and Structure for FinFET Device - The present disclosure describes a fin-like field-effect transistor (FinFET). The device includes one or more fin structures over a substrate, each with source/drain (S/D) features and a high-k/metal gate (HK/MG). A first HK/MG in a first gate region wraps over an upper portion of a first fin structure, the first fin structure including an epitaxial silicon (Si) layer as its upper portion and an epitaxial growth silicon germanium (SiGe), with a silicon germanium oxide (SiGeO) feature at its outer layer, as its middle portion, and the substrate as its bottom portion. A second HK/MG in a second gate region, wraps over an upper portion of a second fin structure, the second fin structure including an epitaxial SiGe layer as its upper portion, an epitaxial Si layer as it upper middle portion, an epitaxial SiGe layer as its lower middle portion, and the substrate as its bottom portion. | 2020-10-08 |
20200321340 | DEVICES, METHODS OF FORMING A DEVICE, AND MEMORY DEVICES - A method of forming an apparatus comprises forming a first metal nitride material over an upper surface of a conductive material within an opening extending through at least one dielectric material through a non-conformal deposition process. A second metal nitride material is formed over an upper surface of the first metal nitride material and side surfaces of the at least one dielectric material partially defining boundaries of the opening through a conformal deposition process. A conductive structure is formed over surfaces of the second metal nitride material within the opening. Apparatuses and electronic systems are also described. | 2020-10-08 |
20200321341 | Integrated Assemblies which Include Two Different Types of Silicon Nitride, and Methods of Forming Integrated Assemblies - Some embodiments include an integrated assembly which has bitline structures that extend along a first direction. The bitline structures include conductive bitlines, and include insulative shells which extend over the conductive bitlines and along sidewalls of the conductive bitlines. The insulative shells include a first silicon nitride composition. The bitline structures are spaced from one another by intervening regions. Semiconductor structures and insulative spacers are within the intervening regions. The semiconductor structures and insulative spacers alternate with one another along the first direction. The insulative spacers include a second silicon nitride composition which is characterized as having a faster etch rate than the first silicon nitride composition by a mixture which contains sulfuric acid and hydrogen peroxide. Some embodiments include methods of forming integrated assemblies. | 2020-10-08 |
20200321342 | DYNAMIC RANDOM ACCESS MEMORY - A dynamic random access memory (DRAM) including a substrate, transistors, bit line sets, conductive structures, and word line sets is provided. The transistors are arranged on the substrate in an array. Each transistor includes a first conductive layer, a second conductive layer, and a third conductive layer. The bit line sets are disposed in parallel along a Y direction and pass through the transistors. Each bit line set includes a first bit line and a second bit line electrically connected to the first conductive layer of each transistor respectively. The conductive structures are located in the transistors. The conductive structures are electrically connected to the second conductive layer of the transistors and the substrate. The word line sets are disposed in parallel along an X direction. Each word line set includes a first word line and a second word line located on sidewalls of each transistor respectively. | 2020-10-08 |
20200321343 | SEMICONDUCTOR DEVICE - A semiconductor device is provided. The semiconductor can apply different voltages to sources and bases (bulks, N-type well) of pull-up transistors and improves write margin of memory cells. An SRAM of the invention includes P-well regions PW_ | 2020-10-08 |
20200321344 | DOPED POLAR LAYERS AND SEMICONDUCTOR DEVICE INCORPORATING SAME - The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor which in turn comprises a polar layer comprising a base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen. The dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The capacitor stack additionally comprises first and second crystalline conductive oxide electrodes on opposing sides of the polar layer. The capacitor stack further comprises first and second barrier metal layers on respective ones of the first and second crystalline conductive oxide electrodes on opposing sides of the polar layer | 2020-10-08 |
20200321345 | CELL BOUNDARY STRUCTURE FOR EMBEDDED MEMORY - Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A multilayer film is formed covering the semiconductor substrate. A memory structure is formed on the memory region from the multilayer film. An etch is performed into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure. A spacer layer is formed covering the memory structure, the isolation structure, and the logic region, and further lining the dummy sidewall. An etch is performed into the spacer layer to form a spacer on dummy sidewall from the spacer layer. A logic device structure is formed on the logic region. | 2020-10-08 |
20200321346 | SEMICONDUCTOR DEVICE - First and second memory cells are arranged on a semiconductor substrate. The memory cell includes, between a first or second source region and a first or second drain, a configuration in which a first or second selection gate and a first or second floating gate are arranged in series. The first memory cell and the second memory cell are adjacent to each other in a first direction. A first signal line extending in the first direction and connected to the first and second selection gates is further provided. The first and second source regions are configured to share a first region. The first selection gate extends in a direction different from the first direction. | 2020-10-08 |
20200321347 | Integrated Assemblies and Methods of Forming Integrated Assemblies - Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies. | 2020-10-08 |
20200321348 | FLASH MEMORY STRUCTURE WITH ENHANCED FLOATING GATE - The present disclosure relates to a flash memory structure. The flash memory structure includes a first doped region and a second doped region disposed within a substrate. A select gate is disposed over the substrate between the first doped region and the second doped region. A floating gate is disposed over the substrate between the select gate and the first doped region, and a control gate is over the floating gate. The floating gate extends along multiple surfaces of the substrate. | 2020-10-08 |
20200321349 | VERTICAL CAPACITOR STRUCTURE AND NON-VOLATILE MEMORY DEVICE INCLUDING THE SAME - A non-volatile memory device includes a substrate, a memory cell string including a vertical channel structure and memory cells, a voltage generator including a first transistor and configured to provide various voltages to the memory cells, and a vertical capacitor structure. The vertical capacitor structure includes first and second active patterns apart from each other in a first horizontal direction, a first gate pattern located above a channel region between the first and second active patterns, a first gate insulating film between the first gate pattern and the substrate in a vertical direction, and capacitor electrodes each extending in the vertical direction. The first transistor includes a second gate pattern and a second gate insulating film between the second gate pattern and the substrate in the vertical direction. The first gate insulating film has a thickness greater than a thickness of the second gate insulating film in the vertical direction. | 2020-10-08 |
20200321350 | SEMICONDUCTOR MEMORY - A semiconductor memory includes first to fourth stacked bodies. The first stacked body includes a first conductor, and an alternating stack of first insulators and second conductors above the first conductor in a region. The second stacked body includes a third conductor, and an alternating stack of second insulators and fourth conductors above the third conductor in another region. The third stacked body includes a fifth conductor adjacent to the first conductor via a third insulator in a separation region. The fourth stacked body includes a seventh conductor adjacent to the third conductor via a fifth insulator in the separation region. The fifth conductor is electrically insulated from the seventh conductor. | 2020-10-08 |
20200321351 | Integrated Assemblies Having Charge-Trapping Material Arranged in Vertically-Spaced Segments, and Methods of Forming Integrated Assemblies - Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. The wordline levels have conductive terminal ends within control gate regions. The control gate regions are vertically spaced from one another by first insulative regions which include first insulative material. Charge-storage material is laterally outward of the conductive terminal ends, and is configured as segments. The segments of the charge-storage material are arranged one atop another and are vertically spaced from one another by second insulative regions which include second insulative material. The second insulative material has a different dielectric constant than the first insulative material. Charge-tunneling material extends vertically along the stack, and is adjacent to the segments of the charge-trapping material. Channel material extends vertically along the stack, and is adjacent to the charge-tunneling material. Some embodiments include methods of forming integrated assemblies. | 2020-10-08 |
20200321352 | Integrated Structures Including Material Containing Silicon, Nitrogen, and at Least One of Carbon, Oxygen, Boron and Phosphorus - Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. A layer over the conductive levels includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus. In some embodiments the vertically-stacked conductive levels are wordline levels within a NAND memory array. Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. Vertically-stacked NAND memory cells are along the conductive levels within a memory array region. A staircase region is proximate the memory array region. The staircase region has electrical contacts in one-to-one correspondence with the conductive levels. A layer is over the memory array region and over the staircase region. The layer includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus. | 2020-10-08 |
20200321353 | FERROELECTRIC MEMORY DEVICES EMPLOYING CONDUCTIVITY MODULATION OF A THIN SEMICONDUCTOR MATERIAL OR A TWO-DIMENSIONAL CHARGE CARRIER GAS AND METHODS OF OPERATING THE SAME - A ferroelectric memory device contains a two-dimensional semiconductor material layer having a band gap of at least 1.1 eV and at least one of a thickness of 1 to 5 monolayers of atoms of the semiconductor material or includes a two-dimensional charge carrier gas layer, a source contact contacting a first portion of the two-dimensional semiconductor material layer, a drain contact contacting a second portion of the two-dimensional semiconductor material layer, a ferroelectric memory element located between the source and drain contacts and adjacent to a first surface of the two-dimensional semiconductor material layer, and a conductive gate electrode located adjacent to the ferroelectric memory element. | 2020-10-08 |
20200321354 | SEMICONDUCTOR DEVICES INCLUDING FERROELECTRIC LAYER AND METHODS OF FABRICATING THE SAME - A semiconductor device includes a stack structure having a plurality of interlayer insulation layers and a plurality of gate electrode layers which are alternately stacked on a substrate, a ferroelectric insulation layer and a channel layer sequentially stacked on a sidewall of a trench that penetrates the stack structure, and a capping oxide pattern disposed between the ferroelectric insulation layer and each of the plurality of interlayer insulation layers. The capping oxide pattern and the ferroelectric insulation layer include the same metal oxide material. | 2020-10-08 |
20200321355 | INTEGRATED CIRCUITS AND SEMICONDUCTOR DEVICE INCLUDING STANDARD CELL - A semiconductor device including first and second active regions extending in a first direction; a field region between the first and second active regions; a gate structure including an upper gate electrode overlapping the first active region and extending in a second direction crossing the first direction, and a lower gate electrode overlapping the second active region, extending in the second direction, and on a same line as the upper gate electrode; a gate isolation layer between the upper and lower gate electrodes; source/drain regions on respective sides of the upper gate electrode; a contact jumper crossing the upper gate electrode in the second active region and electrically connecting the source/drain regions; and a first upper contact extending in the second direction in the field region and overlapping the lower gate electrode and the gate isolation layer, wherein the upper gate electrode is a dummy gate electrode. | 2020-10-08 |
20200321356 | ARRAY SUBSTRATE AND DISPLAY DEVICE - The present disclosure provides an array substrate and a display device. The array substrate includes a plurality of thin film transistors, each of the plurality of thin film transistors including a gate layer, a source/drain layer and a gate insulating layer. The source/drain layer is provided above the gate layer, and the gate insulating layer is provided between the gate layer and the source/drain layer. A via hole platform in the gate insulating layer and above the gate layer of one of the plurality of thin film transistors is arranged to at least partially overlap a via hole platform in the source/drain layer of another of the plurality of thin film transistors. | 2020-10-08 |
20200321357 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE - An object is to improve the drive capability of a semiconductor device. The semiconductor device includes a first transistor and a second transistor. A first terminal of the first transistor is electrically connected to a first wiring. A second terminal of the first transistor is electrically connected to a second wiring. A gate of the second transistor is electrically connected to a third wiring. A first terminal of the second transistor is electrically connected to the third wiring. A second terminal of the second transistor is electrically connected to a gate of the first transistor. A channel region is formed using an oxide semiconductor layer in each of the first transistor and the second transistor. The off-state current of each of the first transistor and the second transistor per channel width of 1 μm is 1 aA or less. | 2020-10-08 |
20200321358 | WIRING SUBSTRATE AND DISPLAY DEVICE - A wiring substrate includes a signal supply unit, a plurality of wirings disposed in a wiring region in which an intermediate region is interposed between the wiring region and the signal supply units, and having different distances from the signal supply unit, and a plurality of coupling wirings disposed in the intermediate region, and coupled to the signal supply unit and the plurality of wirings, in which the plurality of coupling wirings includes a first coupling wiring coupled to a wiring having a short distance from the signal supply unit, and a second coupling wiring coupled to a wiring having a long distance from the signal supply unit among the plurality of wirings, and the first coupling wiring is folded back to the signal supply unit side in the middle of running from the signal supply unit to the wiring region. | 2020-10-08 |
20200321359 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes an insulating substrate, a first semiconductor layer located above the insulating substrate, a second semiconductor layer located above the insulating substrate, an insulating layer which covers the first semiconductor layer and the second semiconductor layer, and includes a first contact hole reaching the first semiconductor layer and a second contact hole reaching the second semiconductor layer, a barrier layer which covers one of the first semiconductor layer inside the first contact hole and the second semiconductor layer inside the second contact hole, and a first conductive layer which is in contact with the barrier layer. | 2020-10-08 |
20200321360 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE - The semiconductor device includes a first layer including a first transistor, a second layer including a first insulating film over the first layer, a third layer including a second insulating film over the second layer, and a fourth layer including a second transistor over the third layer. A first conductive film electrically connects the first transistor and the second transistor to each other through an opening provided in the first insulating film. A second conductive film electrically connects the first transistor, the second transistor, and the first conductive film to one another through an opening provided in the second insulating film. A channel formation region of the first transistor includes a single crystal semiconductor. A channel formation region of the second transistor includes an oxide semiconductor. The width of a bottom surface of the second conductive film is 5 nm or less. | 2020-10-08 |
20200321361 | ELECTRONIC DEVICE - An electronic device includes a flexible substrate and a peripheral trace. The flexible substrate includes an active region and a peripheral region situated outside of the active region. The flexible substrate includes a first bending part, a second bending part and a first cutting structure in the peripheral region. The first bending part is disposed on a first side region of the peripheral region and extending along a first direction. The second bending part is disposed on a second side region of the peripheral region and extending along a second direction not parallel to the first direction, and the second side region is adjacent to the first side region. The first cutting structure is adjacent to the first bending part and the second bending part. The peripheral trace is disposed on the flexible substrate and disposed between the active region and the first cutting structure. | 2020-10-08 |
20200321362 | SEMICONDUCTOR DEVICE - A semiconductor device including a capacitor whose charge capacity is increased while improving the aperture ratio is provided. Further, a semiconductor device which consumes less power is provided. A transistor which includes a light-transmitting semiconductor film, a capacitor in which a dielectric film is provided between a pair of electrodes, an insulating film which is provided over the light-transmitting semiconductor film, and a first light-transmitting conductive film which is provided over the insulating film are included. The capacitor includes the first light-transmitting conductive film which serves as one electrode, the insulating film which functions as a dielectric, and a second light-transmitting conductive film which faces the first light-transmitting conductive film with the insulating film positioned therebetween and functions as the other electrode. The second light-transmitting conductive film is formed over the same surface as the light-transmitting semiconductor film of the transistor and is a metal oxide film containing a dopant. | 2020-10-08 |
20200321363 | PROCESS AND SYSTEM FOR MEASURING MORPHOLOGICAL CHARACTERISTICS OF FIBER LASER ANNEALED POLYCRYSTALLINE SILICON FILMS FOR FLAT PANEL DISPLAY - A method of measuring morphological characteristics of a laser annealed film having a crystalline structure, which is defined by at least one row of side-to-side positioned grains each having a length (Lg), which is uniform for the grains, and width (Wg), wherein a length of the row (Lr) corresponds to a cumulative width Wg of the grains and creates a diffraction of various orders of diffraction, the method includes generating a monochromatic light; training the monochromatic light onto a surface of the laser annealed film at an angle varying in a range between 0° (incident) and grazing angles; and measuring variations of properties of the monochromatic light diffracted from the surface, thereby measuring the morphological characteristics of the laser annealed film along the length (Lr) of the one row. | 2020-10-08 |
20200321364 | IMAGING UNIT - An imaging unit including: first semiconductor substrate including a photoelectric converter; a heat conductive wiring line provided in contact with the first semiconductor substrate; and a cooling device that controls a temperature of the photoelectric converter via the heat conductive wiring line. | 2020-10-08 |
20200321365 | IMAGING DEVICE AND CAMERA SYSTEM, AND DRIVING METHOD OF IMAGING DEVICE - An imaging device includes: a photoelectric converter including first and second electrodes, and a photoelectric conversion layer located between the first electrode and the second electrode; a voltage supply circuit applying a bias voltage between the first electrode and the second electrode: an amplifier transistor including a gate electrically connected to the second electrode, the amplifier transistor configured to output a signal corresponding to a potential of the second electrode; and a detection circuit configured to detect a level of the signal from the amplifier transistor. The voltage supply circuit applies the bias voltage in a first voltage range when the level detected by the detection circuit is greater than or equal to a first threshold value, and applies the bias voltage in a second voltage range that is greater than the first voltage range when the level detected by the detection circuit is less than a second threshold value. | 2020-10-08 |
20200321366 | IMAGING DEVICE, IMAGING SYSTEM, AND MOVING BODY - An imaging device includes a first transmission line connected to a plurality of bit memories, a plurality of second bit memories disposed outside the memory area, and connected to the first transmission line, and each are configured to hold a digital signal of one bit that is one of different bits among a plurality of bits, a second transmission line connected to a part of the plurality of second bit memories, and a third transmission line connected to another part of the plurality of second bit memories. | 2020-10-08 |
20200321367 | SOLID-STATE IMAGING DEVICE AND ELECTRONIC EQUIPMENT - The present technology relates to a solid-state imaging device and electronic equipment to suppress degradation of Dark characteristics. A photoelectric converting unit configured to perform photoelectric conversion, and a PN junction region including a P-type region and an N-type region on a side of a light incident surface of the photoelectric converting unit are included. Further, on a vertical cross-section, the PN junction region is formed at three sides including a side of the light incident surface among four sides enclosing the photoelectric converting unit. Further, a trench which penetrates through a semiconductor substrate in a depth direction and which is formed between the photoelectric converting units each formed at adjacent pixels is included, and the PN junction region is also provided on a side wall of the trench. The present technology can be applied, for example, to a backside irradiation type CMOS image sensor. | 2020-10-08 |
20200321368 | DETECTOR DEVICE WITH MAJORITY CURRENT AND ISOLATION MEANS - The present disclosure relates to a detector device assisted by majority current, comprising a semiconductor layer of a first conductivity type, at least two control regions of the first conductivity type, at least one detection region of a second conductivity type opposite to the first conductivity type and a source for generating a majority carrier current associated with an electrical field, characterized in that it further comprises isolation means formed in the semiconductor layer and located between said two control regions, for deflecting the first majority carrier current generated by the first source between said two control regions and, hence, increasing the length of the first majority current path, reducing the amplitude of said first majority carrier current and, therefore, reducing the power consumption of the detector device. | 2020-10-08 |
20200321369 | PHOTODETECTOR - A sensor includes a first substrate including at least a first pixel. The first pixel includes an avalanche photodiode to convert incident light into electric charge and includes an anode and a cathode. The cathode is in a well region of the first substrate. The first pixel includes an isolation region that isolates the well region from at least a second pixel that is adjacent to the first pixel. The first pixel includes a hole accumulation region between the isolation region and the well region. The hole accumulation region is electrically connected to the anode. | 2020-10-08 |
20200321370 | IMAGE SENSORS AND METHODS OF FORMING THE SAME - An image sensor includes a substrate including a light-receiving region and a light-shielding region, a device isolation pattern in the substrate of the light-receiving region to define active pixels, and a device isolation region in the substrate of the light-shielding region to define reference pixels. An isolation technique of the device isolation pattern is different from that of the device isolation region. | 2020-10-08 |
20200321371 | IMAGE SENSORS AND METHODS OF FORMING THE SAME - An image sensor includes a substrate including a light-receiving region and a light-shielding region, a device isolation pattern in the substrate of the light-receiving region to define active pixels, and a device isolation region in the substrate of the light-shielding region to define reference pixels. An isolation technique of the device isolation pattern is different from that of the device isolation region. | 2020-10-08 |
20200321372 | PHOTOELECTRIC CONVERSION APPARATUS AND IMAGING SYSTEM USING THE SAME - In a photoelectric conversion apparatus including charge storing portions in its imaging region, isolation regions for the charge storing portions include first isolation portion each having a PN junction, and second isolation portions each having an insulator. A second isolation portion is arranged between a charge storing portion and at least a part of a plurality of transistors. | 2020-10-08 |
20200321373 | IMAGE SENSOR DEVICE - The present disclosure relates to a semiconductor device. The semiconductor device includes a gate structure arranged on a first surface of a substrate. A doped isolation region is arranged within the substrate along opposing sides of the gate structure. The substrate includes a first region between sides of the doped isolation region and a second region having a different doping characteristic than the first region. The second region contacts a bottom of the first region and a bottom of the doped isolation region. | 2020-10-08 |
20200321374 | IMAGE SENSOR ARCHITECTURE - A image sensor includes a first integrated circuit layer including pixel sensors that are grouped based on position into pixel sensor groups, a second integrated circuit layer in electrical communication with the first integrated circuit layer, the second integrated circuit layer including image processing circuitry groups that are configured to each receive pixel information from a corresponding pixel sensor group, the image processing circuitry groups further configured to perform image processing operations on the pixel information to provide processed pixel information during operation of the image sensor, a third integrated circuit layer in electrical communication with the second integrated circuit layer, and the third integrated circuit layer including neural network circuitry groups that are configured to each receive the processed pixel information from a corresponding image processing circuitry group and perform analysis for object detection on the processed pixel information during operation of the image sensor. | 2020-10-08 |
20200321375 | CONTROLLABLE GAP HEIGHT FOR AN IMAGE SENSOR PACKAGE - According to an aspect, an image sensor package includes a transparent member, a substrate, and an interposer disposed between and coupled to the transparent member and the substrate, where the interposer defines a first cavity area and a second cavity area. The image sensor package includes an image sensor die disposed within the first cavity area of the interposer, where the image sensor die has a sensor array configured to receive light through the transparent member and the second cavity area. The image sensor package includes a bonding material that couples the image sensor die to the interposer within the first cavity area. | 2020-10-08 |
20200321376 | IMAGE SENSOR AND IMAGING DEVICE - The incidence of incident light transmitted through a photoelectric conversion unit onto a charge holding unit, a pixel in the adjacency, and the like can be blocked in a pixel, and deterioration in image quality can be prevented. An image sensor includes a pixel, a wiring layer, and an incident light attenuation unit. The pixel includes a photoelectric conversion unit that is formed in a semiconductor substrate and performs photoelectric conversion based on incident light, and a pixel circuit that generates an image signal according to a charge generated by the photoelectric conversion. The wiring layer is arranged on a surface of the semiconductor substrate different from a surface onto which the incident light is incident, and transports either the image signal or a signal applied to the pixel circuit. The incident light attenuation unit attenuates the incident light transmitted through the photoelectric conversion unit. | 2020-10-08 |
20200321377 | SYSTEM AND METHOD FOR OPTICAL SENSING - A processing system for an optical sensing device may comprise receiver circuitry and a determination module. The processing system may also include drive circuitry configured to drive a light source to emit light. The receiver circuitry is coupled to a photodetector, and the receiver circuitry is configured to acquire a resulting signal from the photodetector, and generate a measurement of light received by the photodetector based on the resulting signal. The receiver circuitry includes high-pass filter circuitry configured to high-pass filter the resulting signal to generate a high-pass filtered signal based. The determination module is configured to generate a light measurement based on the high-pass filtered signal. | 2020-10-08 |
20200321378 | LENS-FREE COMPOUND EYE CAMERAS BASED ON ANGLE-SENSITIVE META-SURFACES - A lens-free ultrathin imaging sensor using a compound-eye vision modality can be formed by forming a metasurface on each pixel of an array of pixels in a solid state imaging sensor. The metasurface can be configured to form a diffraction grating that directs light incident on the metasurface at a predefined angle to excite surface plasmon polaritons into the solid state imaging sensor and light incident at any other angle is reflected or diffracted away from the metasurface. Each pixel of the imaging sensor can be configured using the metasurface to only receive light incident from a different portion of a field of view. A computational imaging system can be used to construct the image from the individual pixels. | 2020-10-08 |
20200321379 | POLARIZERS FOR IMAGE SENSOR DEVICES - The present disclosure is directed to a method of forming a polarization grating structure (e.g., polarizer) as part of a grid structure of a back side illuminated image sensor device. For example, the method includes forming a layer stack over a semiconductor layer with radiation-sensing regions. Further, the method includes forming grating elements of one or more polarization grating structures within a grid structure, where forming the grating elements includes (i) etching the layer stack to form the grid structure and (ii) etching the layer stack to form grating elements oriented to a polarization angle. | 2020-10-08 |
20200321380 | IMAGE SENSOR, MANUFACTURING METHOD, AND ELECTRONIC DEVICE - The present technology relates to an image sensor, a manufacturing method and an electronic device capable of preventing a ghost. In the image sensor, a plate-like transparent member larger than a sensor chip in size is affixed to a side of a pixel array unit of the sensor chip having the pixel array unit in which pixels that perform photoelectric conversion are arrayed. The present technology can be applied to a case of capturing an image by receiving light, regardless of whether the light is visible light or not. | 2020-10-08 |
20200321381 | MANUFACTURE OF SEMICONDUCTOR MODULE WITH DUAL MOLDING - A method for manufacturing a semiconductor module for an image-sensing device is disclosed. The method may comprise forming a first molding component on a first surface of a printed circuit board (PCB); mounting at least a photosensitive member to a second surface of the PCB; and forming a second molding component on the second surface of the PCB. The PCB may comprise at least an electric component on the first surface of the PCB. The first molding component may encapsulate the at least one electric component with the PCB. The second molding component may secure the photosensitive member on the PCB. | 2020-10-08 |
20200321382 | IMAGE SENSOR HAVING SHIELDING INTERCONNECTS - An image sensor includes one or more first unit pixels. Each of the one or more first unit pixels may include a first photoelectric conversion region including first photoelectric conversion elements arranged in the form of a matrix, and a first floating diffusion region at a center of the first photoelectric conversion elements; a first transistor region including a first active region in which a first reset gate, a first select gate and a first drive gate are disposed; a first signal interconnect electrically connecting the first floating diffusion region to the first drive gate; and a first shielding interconnect separated from the first signal interconnect and extending parallel to the first signal interconnect. | 2020-10-08 |
20200321383 | IMAGE SENSOR AND SYSTEM INCLUDING THE IMAGE SENSOR - An image sensor includes: a pixel array outputting a pixel signal; and a column wiring unit including at least one first column routing wiring extending from the pixel array and including a first connection wiring portion and a protrusion and at least one second column routing wiring including a second connection wiring portion, wherein a sum of lengths of the at least one first connection wiring portion and the protrusion is substantially identical to a length of the at least one second connection wiring portion; and a readout circuit receiving the pixel signal from the column wiring unit. | 2020-10-08 |
20200321384 | PHOTODETECTION APPARATUS AND PHOTODETECTION SENSOR USED THEREFOR - A photodetection apparatus includes a display unit ( | 2020-10-08 |
20200321385 | IMAGING DEVICE - An imaging device including a semiconductor substrate having a first surface, the semiconductor substrate including: a first layer containing an impurity of a first conductivity type; a second layer containing an impurity of a second conductivity type different from the first conductivity type, the second layer being closer to the first surface than the first layer is; and a pixel. The pixel includes a photoelectric converter configured to convert light into charge; and a first diffusion region containing an impurity of the first conductivity type, the first diffusion region facing the first layer via the second layer, configured to store at least a part of the charge. The first layer having a second surface adjacent to the second layer, the second surface including a convex portion toward the first surface, and the convex portion facing the first diffusion region. | 2020-10-08 |
20200321386 | LIGHT RECEIVING ELEMENT AND ELECTRONIC APPARATUS - A first light receiving element according to an embodiment of the present disclosure includes a plurality of pixels, a photoelectric converter that is provided as a layer common to the plurality of pixels, and contains a compound semiconductor material, and a first electrode layer that is provided between the plurality of pixels on light incident surface side of the photoelectric converter, and has a light-shielding property. | 2020-10-08 |
20200321387 | IMAGE SENSOR AND DISPLAY DEVICE HAVING THE SAME - An image sensor includes a sensor pixel. The sensor pixel includes a first transistor coupled between a first power source and a first node, where the first transistor is turned on in response to a first control signal, a light-sensing element coupled between the first node and a second power source, where the light-sensing element generates photocharges in response to incident light, a storage capacitor coupled in parallel to the light-sensing element between the first node and the second power source, and an amplifier including a plurality of transistors coupled in series between the first power source and an output line, where the amplifier outputs a sensing signal corresponding to a voltage of the first node in response to a first driving signal. | 2020-10-08 |
20200321388 | METHOD OF MANUFACTURING AN IMAGER AND IMAGER DEVICE - Techniques are discloses regarding methods of manufacturing an imager as well as an imager device. | 2020-10-08 |
20200321389 | IMAGE PICKUP ELEMENT, IMAGE PICKUP APPARATUS, AND METHOD OF MANUFACTURING IMAGE PICKUP ELEMENT - Image quality is improved. | 2020-10-08 |
20200321390 | System and Method for Making Micro LED Display - By using chip-by-chip, mainly separation technology, micro LED can be made very accurately and efficiently. First, after epitaxial process, the LED epi-wafer is processed into micro LEDs. Second, bonding substrates with driving circuits are provided for the LED epi-wafer. Then, each LED chip is fastened to the substrate chip-by-chip simultaneously or sequentially, and each LED chip may be transferred by using separation technology simultaneously or sequentially. The LED epi-wafer per se can be also provided as LED display substrate. | 2020-10-08 |
20200321391 | WHITE LIGHT EMITTING DIODE (LED) AND METHOD OF REPAIRING LIGHT EMITTING DEVICE USING SAME - A white LED and a method of repairing a light emitting device including, the method including colored light emitting diodes (LEDs) configured to emit different colors of light and arranged in pixels on a backplane of the device, the method including: determining whether each pixel is a functional pixel or a defective pixel; and repairing the defective pixels by transferring white LEDs to the backplane in each defective pixel. | 2020-10-08 |
20200321392 | MICRO LIGHT-EMITTING COMPONENT, MICRO LIGHT-EMITTING COMPONENT MATRIX, AND METHOD FOR MANUFACTURING THE MICRO LIGHT-EMITTING COMPONENT MATRIX - Disclosed is a micro light-emitting component, a micro light-emitting diode, and a transfer layer. The transfer layer has a recess for receiving the micro light-emitting diode to permit the micro light-emitting diode to be retained by the transfer layer, and is transformable from a first state, in which the transfer layer is deformed by the micro light-emitting diode to form the recess, to a second state, in which the micro light-emitting diode received in the recess is retained by the transfer layer. Also disclosed are micro light-emitting component matrix and a method for manufacturing the micro light-emitting component matrix. | 2020-10-08 |
20200321393 | CROSS-POINT MAGNETIC RANDOM ACCESS MEMORY WITH PIEZOELECTRIC SELECTOR - A three dimensional (3D) array of magnetic random access memory (MRAM) bit-cells is described, wherein the array includes a mesh of: a first interconnect extending along a first axis; a second interconnect extending along a second axis; and a third interconnect extending along a third axis, wherein the first, second and third axes are orthogonal to one another, and wherein a bit-cell of the MRAM bit-cells includes: a magnetic junction device including a first electrode coupled to the first interconnect; a piezoelectric (PZe) layer adjacent to a second electrode, wherein the second electrode is coupled to the second interconnect; and a first layer adjacent to the PZe layer and the magnetic junction, wherein the first layer is coupled the third interconnect. | 2020-10-08 |
20200321394 | MAGNETIC RANDOM ACCESS MEMORY (MRAM) STRUCTURE WITH SMALL BOTTOM ELECTRODE - A semiconductor structure and fabrication method of forming a semiconductor structure. The structure is a MRAM element having a first conductive electrode embedded in a first interconnect dielectric material layer upon which a multi-layered magnetic tunnel junction (MTJ) memory element is formed in a magnetoresistive random access memory (MRAM) device area. The first conductive electrode includes a first end having a top surface of a first surface area and a second end having a bottom surface of a second surface area, the first surface area being smaller than the second surface area. The second end of the bottom electrode includes a barrier liner material including a metal fill material, and the first end of the bottom electrode is a pillar structure formed as a result of an etchback process in which the metal barrier liner is recessed relative to the metal fill material. | 2020-10-08 |
20200321395 | INDEPENDENTLY SCALING SELECTOR AND MEMORY IN MEMORY CELL - Embedded non-volatile memory structures having an independently sized selector element and memory element are described. In an example, a memory device includes a metal layer. A selector element is above the metal layer. A memory element is above the metal line. A spacer surrounds one of the selector element and the memory element having a smallest width, and wherein the one of the selector element and the memory element not surrounded by the spacer has a width substantially identical to the spacer and is in alignment with the spacer. | 2020-10-08 |
20200321396 | INTEGRATED CIRCUITS WITH RESISTIVE NON-VOLATILE MEMORY CELLS AND METHODS FOR PRODUCING THE SAME - Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a memory cell, wherein the memory cell includes a transistor having a source and a drain, a first resistive unit in electrical communication with the source, and a second resistive unit in electrical communication with the drain. The first resistive unit includes a first bottom electrode, a first top electrode, and a first resistive element positioned between the first bottom electrode and the first top electrode. The second resistive unit includes a second bottom electrode, a second top electrode, and a second resistive element positioned between the second bottom electrode and the second top electrode. | 2020-10-08 |
20200321397 | METHOD OF PRODUCING A RECURRENT NEURAL NETWORK COMPUTER - A method of producing a recurrent neural network computer includes consecutive steps of providing a substrate with a first electrode; structuring the first electrode by etching using a first mask made of block copolymers, such that said electrode has free regions which are randomly spatially distributed; forming a resistive-RAM-type memory layer on the first structured electrode; forming a second electrode on the memory layer; and structuring the second electrode by etching, using a second mask made of block copolymers such that said electrode has free regions which are randomly spatially distributed. | 2020-10-08 |
20200321398 | SEMICONDUCTOR MEMORY DEVICE - An electronic device includes a semiconductor memory. The semiconductor memory comprises a first variable resistance element coupled between a first wiring and a second wiring, the first variable resistance element including a first variable resistance layer having a first width at a first distance from the first wiring; and a second variable resistance element coupled between the second wiring and a third wiring, the second variable resistance element including a second variable resistance layer having a second width at the first distance from the second wiring. The first width is greater than the second width. | 2020-10-08 |
20200321399 | MEMORY ARRAY, METHOD FOR MANUFACTURING MEMORY ARRAY, MEMORY ARRAY SHEET, METHOD FOR MANUFACTURING MEMORY ARRAY SHEET, AND WIRELESS COMMUNICATION APPARATUS - A memory array includes: a plurality of first wires; at least one second wire crossing the first wires; and a plurality of memory elements provided in correspondence with respective intersections of the first wires and the at least one second wire and each having a first electrode and a second electrode arranged spaced apart from each other, a third electrode connected to one of the at least one second wire, and an insulating layer that electrically insulates the first electrode and the second electrode and the third electrode from each other, the first wires, the at least one second wire, and the first wires, the at least one second wire, and the memory elements being formed on a substrate. | 2020-10-08 |
20200321400 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A display device and method of manufacturing same includes: a display panel having a pixel area and a peripheral area adjacent to the pixel area, a light control layer disposed on the display panel and at least partially overlapping the pixel area, a light blocking portion at least partially overlapping the peripheral area, and a protective layer disposed between the light control layer and the light blocking portion. | 2020-10-08 |
20200321401 | DISPLAY DEVICE - A display device includes a lower substrate, a sub-pixel structure, an optical filter layer, a color filter layer, an upper substrate, and an alignment structure. The lower substrate has a display area and a peripheral area surrounding the display area. The sub-pixel structure is disposed in the display area on the lower substrate. The optical filter layer is disposed on the sub-pixel structure. The color filter layer is disposed on the optical filter layer. The upper substrate is disposed on the color filter layer. The alignment structure is disposed in the peripheral area on a bottom surface of the upper substrate, and contains a material equal to a material forming the optical filter layer and the color filter layer. | 2020-10-08 |