41st week of 2020 patent applcation highlights part 64 |
Patent application number | Title | Published |
20200321402 | ELECTRONIC PANEL AND ELECTRONIC APPARATUS INCLUDING THE SAME - An electronic panel may include a plurality of sensing electrodes and a plurality of sensing lines. The sensing lines may include a plurality of first group sensing lines and a plurality of second group sensing lines, which are spaced apart from each other in a specific direction and are alternately arranged with respect to each other. Each of the first group sensing lines and the second group sensing lines may include a first pattern layer and a second pattern layer, which are spaced apart from each other with an insulating layer interposed therebetween and are coupled to each other through the insulating layer. Each of the first group sensing lines may include a first pattern layer in a specific region, and each of the second group sensing lines may include a second pattern layer in the specific region. | 2020-10-08 |
20200321403 | PRESSURE SENSITIVE DISPLAY DEVICE - Provided is a pressure sensitive display device including a sensing substrate, a reaction substrate provided on the sensing substrate, and spacers provided between the sensing substrate and the reaction substrate to space the sensing substrate apart from the reaction substrate. Here, the sensing substrate includes a flexible substrate and a touch electrode provided on one surface of the flexible substrate, which faces the reaction substrate. The reaction substrate includes a transparent substrate, a transparent electrode provided on one surface of the transparent substrate, which faces the sensing substrate, and a light emitting layer disposed on the transparent electrode. | 2020-10-08 |
20200321404 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - An organic light emitting display device includes: a substrate including pixel areas and a pixel separating area; a plurality of pixels; a plurality of spacers in the pixel separating area and spaced apart from each other; and a touch electrode unit disposed over the plurality of pixels and spacers. The touch electrode unit includes first touch electrodes arranged in a first direction and second touch electrodes arranged in a second direction. The touch electrode unit includes a plurality of touch pattern unit blocks repeatedly arranged. Each touch pattern unit block includes portions of each of neighboring first touch electrodes and portions of each of neighboring second touch electrodes. The spacers of each touch pattern unit block corresponds to a plurality of spacer pattern unit blocks repeatedly arranged. Each spacer pattern unit includes at least one spacer and is smaller than the touch pattern unit block. | 2020-10-08 |
20200321405 | DISPLAY APPARATUS INCLUDING SENSOR - A display apparatus including a sensor includes: a pixel group including a predetermined number of pixels, each of which includes a pixel circuit and a light-emitting device electrically connected to the pixel circuit; and a sensing pixel including a sensing circuit and a sensing electrode connected to the sensing circuit, where the sensing electrode forms a variable capacitor with respect to a finger, and the sensing circuit is arranged around the pixel circuit of the pixel group. | 2020-10-08 |
20200321406 | DISPLAY DEVICE - A display device includes a display substrate including a flat main region including a plurality of pixels, a flat subsidiary region, and a bending region disposed between the flat main region and the flat subsidiary region; a first layer disposed on the display substrate, the first layer including a bending opening portion in the bending region exposing the bending region of the display substrate; a bending organic layer disposed on the bending region exposed by the bending opening portion of the first layer; a plurality of light-emitting elements disposed on the first layer in the pixels, respectively, wherein the plurality of light-emitting elements includes a plurality of color filters, respectively, and wherein the bending organic layer includes the same material as at least one of the color filters. | 2020-10-08 |
20200321407 | DISPLAY SUBSTRATE, DISPLAY DEVICE AND DISPLAY METHOD THEREOF, AND MASK PLATE - A display substrate, a display device and a display method thereof, and a mask plate are provided. The display substrate includes: a plurality of pixel unit groups arranged in rows, each of the pixel unit groups including: a first-color sub-pixel unit, and a ring-shaped second-color sub-pixel unit surrounding the first-color sub-pixel unit. | 2020-10-08 |
20200321408 | ARRAY SUBSTRATE, PREPARATION METHOD THEREOF, DISPLAY PANEL AND DISPLAY DEVICE - Disclosed are an array substrate, a preparation method thereof, a display panel and a display device. The array substrate includes a base substrate, a first thin film transistor, a photosensitive sensor, and a dielectric layer. The first thin film is on the base substrate and includes a gate, a drain, a source and a conductive channel between the drain and the source. The photosensitive sensor has the drain of the first thin film transistor as an electrode of the photosensitive sensor. The dielectric layer covers the conductive channel of the first thin film transistor, where the dielectric layer is a metal oxide film. | 2020-10-08 |
20200321409 | DISPLAY PANEL, DISPLAY DEVICE AND METHOD FOR DRIVING DISPLAY PANEL - The present application provides a display panel, a display device and a method for driving the display panel. The display panel includes a control unit layer, an organic light emitting device structure and a liquid crystal display device structure, wherein the control unit layer is electrically coupled to the organic light emitting device structure and the liquid crystal display device structure, respectively, and an electrode of the organic light emitting device structure and an electrode of the liquid crystal display device structure are at least partially shared. | 2020-10-08 |
20200321410 | DISPLAY DEVICE - A display device is provided, including: a display panel including a display face and a first face opposite to the display face; an optical module configured to converge light transmitted through the display panel, the optical module being located on a side of the first face facing away from the display face; and a camera configured to receive light converged by the optical module, the camera located on a side of the optical module facing away from the first face and spaced apart from the optical module, the camera including a light incident face onto which light is incident. A projection of the optical module in a direction perpendicular to the first face of the display panel falls into display area of the display panel, and an area of the projection of the optical module is larger than an area of the light incident face of the camera. | 2020-10-08 |
20200321411 | DISPLAY PANEL AND PREPARATION METHOD THEREFOR, AND DISPLAY DEVICE - A display panel and a preparation method therefor, and a display device are disclosed. The display panel includes a first base layer; a barrier layer, disposed on the first base layer; a second base layer, disposed on the barrier layer; a first high-temperature-resistant adhesive layer, configured to adhere the first base layer to the barrier layer; and a second high-temperature-resistant adhesive layer, configured to adhere the barrier layer to the second base layer. Beneficial effects: An inorganic high-temperature-resistant adhesive layer is coated between the base layer and the barrier layer, so that the base layer can be adhered to the barrier layer more firmly, to improve bending performance of the base layer, and reduce a risk of a fracture between the base layer and the barrier layer, thereby improving a bending capability of the flexible display panel, and improving a product yield, controllability, and endurance. | 2020-10-08 |
20200321412 | SHIFT REGISTER CIRCUIT, DISPLAY PANEL, AND ELECTRONIC APPARATUS - Disclosed herein is a shift register circuit that is formed on an insulating substrate with thin film transistors having channels of the same conductivity type and includes shift stages, each of the shift stages including: a first thin film transistor; a second thin film transistor; a 3(1)-th thin film transistor; a 3(2)-th thin film transistor; a 4(1)-th thin film transistor; a 4(2)-th thin film transistor; a fifth thin film transistor; and a sixth thin film transistor. | 2020-10-08 |
20200321413 | RESONANT CAVITY STRUCTURE OF PIXEL OF OLED DISPLAY PANEL AND OLED DISPLAY PANEL - A resonant cavity structure ( | 2020-10-08 |
20200321414 | DISPLAY DEVICE - The disclosure provides a display device, including a substrate, a plurality of power lines and a pixel define layer. The plurality of power lines disposed on the substrate. The pixel define layer is disposed on the substrate, wherein the pixel define layer includes a first opening region and a second opening region. In a top view, the first opening region is adjacent to the second opening region, the first opening region overlaps a first power line of the plurality of power lines to define a first overlapping area, the second opening region overlaps a second power line of the plurality of power lines to define a second overlapping area, and the first overlapping area is different from the second overlapping area. | 2020-10-08 |
20200321415 | ORGANIC LIGHT-EMITTING DISPLAY APPARATUS HAVING PROTECTED EMISSION LAYER - An organic light-emitting display apparatus prevents the quality of an image being displayed thereon from being deteriorated as a result of contamination of an organic emission layer. The display apparatus includes a substrate with a display area and a periphery area. A first insulating layer, disposed over the substrate, has a first opening in the periphery area. A first electrode is disposed within the display area, over the first insulating layer. A first bank is disposed over the first insulating layer and has a second opening through which a center of the first electrode is exposed. A second bank is disposed over the first insulating layer and is separated from the first bank. The first opening is disposed between the first bank and the second bank. An intermediate layer is disposed over the first electrode. A second electrode is disposed over the intermediate layer and the first bank. | 2020-10-08 |
20200321416 | LIGHT EMITTING ELEMENT AND DISPLAY DEVICE INCLUDING LIGHT EMITTING ELEMENT - A light emitting element | 2020-10-08 |
20200321417 | DISPLAY PANEL AND METHOD FOR MANUFACTURING THE SAME, DISPLAY DEVICE - A display panel includes an array substrate and a package substrate disposed opposite to each other, wherein, the array substrate includes a plurality of pixel units arranged in an array, and at least one of the pixel units includes a driving transistor. Further, the package substrate includes a first electrode and a second electrode disposed opposite to each other and an insulating layer located between the two electrodes. Wherein, the first electrode is electrically connected to the first terminal of the driving transistor, and the second electrode is electrically connected to the control terminal of the driving transistor. | 2020-10-08 |
20200321418 | DISPLAY DEVICE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS - There is provided a display device including: a light emitting element; and a drive transistor (DRTr) that includes a coupling section (W | 2020-10-08 |
20200321419 | LIGHT EMITTING ELEMENT DISPLAY DEVICE - A display device includes two or more transistors in one pixel, and the two or more transistors include a first transistor of which a channel semiconductor layer is polycrystalline silicon, and a second transistor of which a channel semiconductor layer is an oxide semiconductor. | 2020-10-08 |
20200321420 | ARRAY SUBSTRATE, CONTROL METHOD THEREOF, MANUFACTURING METHOD THEREOF, DISPLAY PANEL AND DISPLAY DEVICE - An array substrate, including: a base substrate including a display area and a non-display area; a first transistor in the display area; a second transistor in the non-display area; and a substrate electrode, the substrate electrode including: a first substrate electrode between the first transistor and the base substrate; and a second substrate electrode between the second transistor and the base substrate, wherein the first substrate electrode and the second substrate electrode are configured to adjust threshold voltages of the first transistor and the second transistor, respectively, there is an open circuit between the first substrate electrode and the second substrate electrode, the first substrate electrode is supplied with a first adjustment voltage, the second substrate electrode is supplied with a second adjustment voltage, and an absolute value of the first adjustment voltage is different from an absolute value of the second adjustment voltage. | 2020-10-08 |
20200321421 | DISPLAY DEVICE - A display device includes: a substrate including a display area, a peripheral area, and a pad area, a plurality of pixels in the display area, and the peripheral area surrounding the display area; a plurality of fan-out lines extending from the pad area to the display area; a first metal layer covering at least a portion of the plurality of fan-out lines in the peripheral area; a second metal layer overlapping at least a portion of the first metal layer, the second metal layer being over the first metal layer; a third metal layer over the second metal layer in the peripheral area; a first insulating layer between the first metal layer and the second metal layer and including first contact holes; and a second insulating layer between the second metal layer and the third metal layer and including second contact holes. | 2020-10-08 |
20200321422 | ORGANIC ELECTROLUMINESCENT DEVICE AND ELECTRONIC APPARATUS - An organic electroluminescent device includes a first transistor, a power supply line layer connected to one current terminal of the first transistor, a capacitive element including a first capacitive electrode connected to a gate of the first transistor, and a second capacitive electrode, a signal line, and a pixel electrode connected to the other current terminal of the first transistor, the first capacitive electrode is provided on a layer over the gate of the first transistor, and the power supply line layer is provided on a layer between the first capacitive electrode and the signal line. | 2020-10-08 |
20200321423 | DISPLAY APPARATUS - Provided is a display apparatus, including a substrate; a plurality of pixels that are on the substrate and include at least one display device; a separation area that is on the substrate and between two adjacent pixels from among the plurality of pixels; and a penetrating portion that is in the separation area and penetrates the substrate. | 2020-10-08 |
20200321424 | DISPLAY DEVICE HAVING CONDUCTIVE PATTERNS WITH REDUCED DISPLAY ELEMENT OVERLAP - A display device includes a substrate including a pixel region and a peripheral region. A plurality of pixels is disposed in the pixel region of the substrate. Each of the plurality of pixels includes a light emitting element. Data lines and scan lines are connected to each of the plurality of pixels. A power line is configured to supply power to the plurality of pixels. The power line includes a plurality of first conductive lines and a plurality of second conductive lines intersecting the plurality of first conductive lines. The plurality of second conductive lines is arranged in a region between adjacent light emitting elements of the plurality of pixels. At least some of the plurality of second conductive lines extend in a direction oblique to a direction of extension of the data lines or the scan lines. | 2020-10-08 |
20200321425 | DISPLAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME AND DISPLAY DEVICE - Embodiments of the present disclosure provide a display substrate, a method for manufacturing the same, and a display device, and relate to the field of display technology. The contact area between a first conductive pattern and a second conductive pattern may be increased. The display substrate includes a display area and a peripheral area surrounding the display area. The peripheral area includes a first conductive pattern including at least two first hollow areas as alignment marks, an insulation layer disposed on the first conductive pattern, the insulation layer including a first insulating pattern, the first insulating pattern covering the first hollow area, and the first insulating pattern being incompletely covering space between adjacent first hollow areas, a second conductive pattern disposed on the insulating layer, the second conductive pattern penetrating through the hollow area on the first insulating pattern and electrically connected to the first conductive pattern. | 2020-10-08 |
20200321426 | ORGANIC LIGHT EMITTING DIODE DISPLAY - The present invention provides an organic light emitting diode (OLED) display, which includes a substrate, a light emitting layer and an encapsulation layer. Wherein at least one connecting terminal and a first connection end are disposed on a rear surface of the substrate, and the connecting terminal is provided with a signal line electrically connected to the first connection end. An edge of the substrate is provided with an extension substrate, the extension substrate is provided with a second connection end, and the first connection end and the second connection end are electrically connected through a flexible circuit board. | 2020-10-08 |
20200321427 | DISPLAY DEVICE - A display device includes a substrate, a metal layer disposed on the substrate, a first conductive layer including a lower pattern disposed on the metal layer, an active layer disposed on the first conductive layer, a second conductive layer disposed on the active layer and including a first gate electrode, a pixel electrode disposed on the second conductive layer, and an emission layer and a common electrode disposed on the pixel electrode. | 2020-10-08 |
20200321428 | DISPLAY DEVICE HAVING INTERSECTING INITIALIZATION POWER LINE PORTIONS - A display device may including: a substrate including a pixel area and a peripheral area; pixels provided in the pixel area of the substrate, each of the pixels including a light-emitting element provided with a pixel electrode; scan lines and data lines coupled to the pixels; a power line configured to supply driving power to the light-emitting elements, and extending in one direction; and an initialization power line configured to supply initialization power to the light-emitting elements. The power line and the initialization power line may be provided on different layers. The initialization power line may include: first conductive lines extending in a direction oblique to the scan lines and the data lines; and conductive lines intersecting the first conductive lines. The first and second conductive lines may be disposed in areas between the pixel electrodes of adjacent light-emitting elements. | 2020-10-08 |
20200321429 | DISPLAY PANEL AND DISPLAY DEVICE - The disclosure discloses a display panel and a display device, and the display panel includes: a substrate; a display area, including a plurality of signal lines on a first side of the substrate; a bending area, including a plurality of connection lines on a second side of the substrate; and a wiring area, including a plurality of lead wires for transmitting display signals on a third side of the substrate; where the plurality of connection lines electrically connects the plurality of signal lines and the plurality of lead wires; the bending area includes fourth sides of the substrate; and the second side of the substrate is intersected with the fourth sides of the substrate; where the fourth sides of the substrate includes at least one transitional side, and the at least one transitional side is concaved toward the connection lines of the bending area. | 2020-10-08 |
20200321430 | SEMICONDUCTOR SUBSTRATE WITH INTEGRATED INDUCTIVE COMPONENT - In an integrated circuit (IC), a semiconductor substrate has a first side and an opposite second side. The second side has a trench. Circuitry is on the first side. An inductive structure is within the trench. The inductive structure is connected to the circuitry through vias in the semiconductor substrate. The semiconductor substrate is mounted on a package substrate. At least a portion of the inductive structure contacts the package substrate. The circuitry is coupled to the inductive structure through wires to the package substrate. | 2020-10-08 |
20200321431 | SEMICONDUCTOR DEVICE STRUCTURE WITH MAGNETIC ELEMENT - A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a magnetic element over the semiconductor substrate. The semiconductor device structure also includes an isolation element over the magnetic element. The isolation element partially covers a top surface of the magnetic element. The semiconductor device structure further includes a conductive line over the isolation element. In addition, the semiconductor device structure includes a dielectric layer over the conductive line and the magnetic element. | 2020-10-08 |
20200321432 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR APPARATUS AND METHOD OF MANUFACTURING THE SAME - A semiconductor apparatus includes a plurality of semiconductor devices with a single substrate, a plurality of trench regions, each trench region including a trench, wherein the single substrate includes a substrate layer, a first epitaxial layer of a first conductivity type, disposed on the substrate layer, and a second epitaxial layer of a second conductivity type, disposed on the first epitaxial layer, wherein each trench of the plurality of trench regions extends through the second epitaxial layer and into the first epitaxial layer, thereby isolating adjacent semiconductor devices of the plurality of semiconductor devices. | 2020-10-08 |
20200321433 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device having an active region and a voltage withstand region comprises a first semiconductor layer of a first conductive type, a second semiconductor region of a second conductive type, disposed selectively on the front side of the first semiconductor layer, a plurality of first trench contact (TC) sections disposed at a peripheral section of the active region in the second semiconductor region, being apart from one another and extending in a first direction, a second trench contact (TC) disposed at the peripheral section of the active region in the second semiconductor region, extending in the first direction and being further from the voltage withstand region than the plurality of first trench contact sections, an electric conductor layer electrically connecting together the plurality of first TC sections, and a conductive connection region disposed between the first TC sections and second TC section, having a lower resistivity than the second semiconductor region, and electrically connecting the first TC sections and second TC section. | 2020-10-08 |
20200321434 | GATE-ALL-AROUND FIELD EFFECT TRANSISTOR HAVING STACKED U SHAPED CHANNELS CONFIGURED TO IMPROVE THE EFFECTIVE WIDTH OF THE TRANSISTOR - A method of fabricating a semiconductor device is described. The method includes forming a stack of sacrificial layers on a substrate. A U-shaped trench is formed in the stack of the sacrificial layers. A first U-shaped channel layer is deposited in the U-shaped trench. A first U-shaped sacrificial layer is conformally formed covering the U-shaped channel layer. A second U-shaped channel layer is conformally deposited covering the first U-shaped sacrificial layer. A gate is formed around the first and the second U-shaped channel layers. | 2020-10-08 |
20200321435 | FIELD EFFECT TRANSISTORS WITH GATE ELECTRODE SELF-ALIGNED TO SEMICONDUCTOR FIN - Monolithic FETs including a fin of a first semiconductor composition disposed on a sub-fin of a second composition. In some examples, an InGaAs fin is grown over GaAs sub-fin. The sub-fin may be epitaxially grown from a seeding surface disposed within a trench defined in an isolation dielectric. The sub-fin may be planarized with the isolation dielectric. The fin may then be epitaxially grown from the planarized surface of the sub-fin. A gate stack may be disposed over the fin with the gate stack contacting the planarized surface of the isolation dielectric so as to be self-aligned with the interface between the fin and sub-fin. Other embodiments may be described and/or claimed. | 2020-10-08 |
20200321436 | HEXAGONAL ARRAYS FOR QUANTUM DOT DEVICES - Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gates above the quantum well stack; and a plurality of second gates above the quantum well stack; wherein the plurality of first gates are arranged in electrically continuous first rows and the plurality of second gates are arranged in electrically continuous second rows parallel to the first rows. Quantum dot devices according to various embodiments of the present disclosure are based on arranging first and second gates in hexagonal/honeycomb arrays. | 2020-10-08 |
20200321437 | SILICON CARBIDE EPITAXIAL WAFER, METHOD FOR MANUFACTURING SILICON CARBIDE EPITAXIAL WAFER, AND POWER CONVERTER - A silicon carbide epitaxial wafer includes a silicon carbide substrate and silicon carbide epitaxial layers formed on the silicon carbide substrate. Each of the silicon carbide epitaxial layers has a triangular defect. The silicon carbide epitaxial layer each have a step inside the triangular defect in the surface morphology of the triangular defect. | 2020-10-08 |
20200321438 | GALLIUM NITRIDE SUBSTRATE AND MANUFACTURING METHOD OF NITRIDE SEMICONDUCTOR CRYSTAL - A gallium nitride substrate comprising a first main surface and a second main surface opposite thereto, wherein the first main surface is a non-polar or semi-polar plane, a dislocation density measured by a room-temperature cathode luminescence method in the first main surface is 1×10 | 2020-10-08 |
20200321439 | HIGH-MOBILITY FIELD EFFECT TRANSISTORS WITH WIDE BANDGAP FIN CLADDING - Monolithic FETs including a fin of a first III-V semiconductor material offering high carrier mobility is clad with a second III-V semiconductor material having a wider bandgap. The wider bandgap cladding may advantageously reduce band-to-band tunneling (BTBT) leakage current while transistor is in an off-state while the lower bandgap core material may advantageously provide high current conduction while transistor is in an on-state. | 2020-10-08 |
20200321440 | SEMICONDUCTOR DEVICE - Disclosed in an embodiment is a semiconductor device comprising a semiconductor structure, which comprises a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer, wherein: the first conductive semiconductor layer comprises a first super lattice layer comprising a plurality of first sub layers and a plurality of second sub layers, the first and second sub layers being alternately arranged; the semiconductor structure emits ions of indium, aluminum, and a first and second dopant during a primary ion irradiation; the intensity of indium ions emitted from the active layer includes a maximum indium intensity peak; the doping concentration of the first dopant emitted from the first conductive semiconductor layer includes a maximum concentration peak; the maximum indium intensity peak is disposed to be spaced from the maximum concentration peak in a first direction; the intensity of indium ions emitted from the plurality of first sub layers has a plurality of first indium intensity peaks; the doping concentration of the first dopant emitted from the plurality of first sub layers has a plurality of first concentration peaks; and the plurality of first indium intensity peaks and the plurality of first concentration peaks are disposed between the maximum indium intensity peak and the maximum concentration peak. | 2020-10-08 |
20200321441 | MINIATURE FIELD PLATE T-GATE AND METHOD OF FABRICATING THE SAME - A method of fabricating a gate with a mini field plate includes forming a dielectric passivation layer over an epitaxy layer on a substrate, coating the dielectric passivation layer with a first resist layer, etching the first resist layer and the dielectric passivation layer to form a first opening in the dielectric passivation layer, removing the first resist layer; and forming a tri-layer gate having a gate foot in the first opening, the gate foot having a first width, a gate neck extending from the gate foot and extending for a length over the dielectric passivation layer on both sides of the first opening, the gate neck having a second width wider than the first width of the gate foot, and a gate head extending from the gate neck, the gate head having a third width wider than the second width of the gate neck. | 2020-10-08 |
20200321442 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate having a first region and a second region and a gate structure on the first region and the second region of the substrate. The gate structure includes a first bottom barrier metal (BBM) layer on the first region and the second region, a first work function metal (WFM) layer on the first region; and a diffusion barrier layer on a top surface and a sidewall of the first WFM layer on the first region and the first BBM layer on the second region. Preferably, a thickness of the first BBM layer on the second region is less than a thickness of the first BBM layer on the first region. | 2020-10-08 |
20200321443 | Transistor with Multi-Metal Gate - A transistor includes a gate electrode with multiple metals distributed along the width of the gate electrode. Each of the metals in the gate electrode has different work functions. Such a compound gate provides higher linearity when, e.g., operated as a radio frequency transistor. | 2020-10-08 |
20200321444 | CHARGE STORAGE MEMORY DEVICE INCLUDING FERROELECTRIC LAYER BETWEEN CONTROL GATE ELECTRODE LAYERS AND METHODS OF MAKING THE SAME - A memory device includes a channel, a control gate electrode, and at least one charge storage element located between the channel and the control gate electrode. The control gate electrode includes a first electrically conductive layer, a second electrically conductive layer and a ferroelectric material layer located between the first electrically conductive layer and the second electrically conductive layer. | 2020-10-08 |
20200321445 | FERROELECTRIC-BASED FIELD-EFFECT TRANSISTOR WITH THRESHOLD VOLTAGE SWITCHING FOR ENHANCED ON-STATE AND OFF-STATE PERFORMANCE - Techniques are disclosed herein for ferroelectric-based field-effect transistors (FETs) with threshold voltage (VT) switching for enhanced RF switch transistor on-state and off-state performance. Employing a ferroelectric gate dielectric layer that can switch between two ferroelectric states enables a higher VT during the transistor off-state (VT,hi) and a lower VT during the transistor on-state (VT,lo). Accordingly, the transistor on-state resistance (Ron) can be maintained low due to the available relatively high gate overdrive (Vg,on−VT,lo) while still handling a relatively high maximum RF power in the transistor off-state due to the high VT,hi −Vg,off value. Thus, the Ron of an RF switch transistor can be improved without sacrificing maximum RF power, and/or vice versa, the maximum RF power can be improved without sacrificing the Ron. A ferroelectric layer (e.g., including Hf | 2020-10-08 |
20200321446 | FIELD EFFECT TRANSISTORS HAVING FERROELECTRIC OR ANTIFERROELECTRIC GATE DIELECTRIC STRUCTURE - Field effect transistors having a ferroelectric or antiferroelectric gate dielectric structure are described. In an example, an integrated circuit structure includes a semiconductor channel structure includes a monocrystalline material. A gate dielectric is over the semiconductor channel structure. The gate dielectric includes a ferroelectric or antiferroelectric polycrystalline material layer. A gate electrode has a conductive layer on the ferroelectric or antiferroelectric polycrystalline material layer, the conductive layer including a metal. A first source or drain structure is at a first side of the gate electrode. A second source or drain structure is at a second side | 2020-10-08 |
20200321447 | Group III Nitride-Based Transistor Device and Method of Fabricating a Gate Structure for a Group III Nitride-Based Transistor Device - In an embodiment, a Group III nitride-based transistor device, includes a first. Group III nitride barrier layer arranged on a Group III nitride channel layer, the first Group III nitride barrier layer and the Group III nitride channel layer having differing bandgaps and forming a heterojunction. capable of supporting a two-dimensional charge gas. A source, a gate and a drain are on an upper surface of the first Group III nitride barrier layer. A gate recess extends from the upper surface of the first. Group III nitride barrier layer into the first Group III nitride barrier layer. A p-doped Group III nitride material arranged in the gate recess has a first extension extending on the upper surface of the first Group III nitride barrier layer towards the drain. The first extension has a length l | 2020-10-08 |
20200321448 | VERTICAL FIELD-EFFECT TRANSISTOR LATE GATE RECESS PROCESS WITH IMPROVED INTER-LAYER DIELECTRIC PROTECTION - A method for forming a semiconductor device is disclosed. The method includes receiving a substrate stack including at least one semiconductor fin, the substrate stack including: a bottom source/drain epi region directly below the semiconductor fin; a vertical gate structure directly above the bottom source/drain epi region and in contact with the semiconductor fin; a first inter-layer dielectric in contact with a sidewall of the vertical gate structure; and a second interlayer-layer dielectric directly above and contacting a top surface of the first inter-layer dielectric. The method further including: etching a top region of the semiconductor fin and the gate structure thereby creating a recess directly above the top region of the semiconductor fin and the vertical gate structure; and forming in the recess a top source/drain epi region directly above, and contacting, a top surface of the semiconductor fin. A novel semiconductor device structure is also disclosed. | 2020-10-08 |
20200321449 | DUAL METAL GATE STRUCTURES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION - Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a semiconductor substrate comprising an N well region having a semiconductor fin protruding therefrom. A trench isolation layer is on the semiconductor substrate around the semiconductor fin, wherein the semiconductor fin extends above the trench isolation layer. A gate dielectric layer is over the semiconductor fin. A conductive layer is over the gate dielectric layer over the semiconductor fin, the conductive layer comprising titanium, nitrogen and oxygen. A P-type metal gate layer is over the conductive layer over the semiconductor fin. | 2020-10-08 |
20200321450 | METHOD OF FORMING EPITAXIAL FIN STRUCTURES OF FINFET - A method of forming a semiconductor device having first and second fin structures on a substrate includes forming a first epitaxial region of the first fin structure and forming a second epitaxial region of the second fin structure. The method further includes forming a buffer region on the first epitaxial region of the first fin structure and performing an etch process to etch back a portion of the second epitaxial region. The buffer region helps to prevents etch back of a top surface of the first epitaxial region during the etch process. Further, a capping region is formed on the buffer region and the etched second epitaxial region. | 2020-10-08 |
20200321451 | SEMICONDUCTOR DEVICE HAVING A GATE INSULATING FILM HAVING A HIGH DIELECTRIC CONSTANT PORTION FOR RELAXING AN ELECTRIC FIELD GENERATED IN THE GATE INSULATING FILM - A method for producing a semiconductor power device, includes forming a gate trench from a surface of a semiconductor layer toward an inside thereof. A first insulation film is formed on an inner surface of the gate trench. The method also includes removing a part on a bottom surface of the gate trench in the first insulation film. A second insulation film having a dielectric constant higher than SiO | 2020-10-08 |
20200321452 | ELECTRONIC DEVICE INCLUDING AT LEAST ONE NANO-OBJECT - An electronic device is provided, including a transistor, a substrate surmounted by first, second, and third elements, the second arranged between the first and the third and including a nano-object, a channel area of the transistor formed by part of the nano-object, the nano-object including first and second opposite ends along a reference axis passing through the ends, the first end connected to the first element via a first electrode including a first part and a second part formed on the first part, the second end connected to the third element via a second electrode including a first part and a second part formed on the first part, the first parts formed of a first material and the second parts formed of a second material, a lattice parameter of the second material suited to that of the first material to induce a stress in the nano-object along the reference axis. | 2020-10-08 |
20200321453 | FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME - A fin field effect transistor device structure includes a first fin structure formed over a substrate. The structure also includes a fin top layer formed over a top portion of the first fin structure. The structure also includes a first oxide layer formed across the first fin structure and the fin top layer. The structure also includes a first gate structure formed over the first oxide layer across the first fin structure. | 2020-10-08 |
20200321454 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - To provide a semiconductor device with favorable electrical characteristics. To provide a method for manufacturing a semiconductor device with high productivity. To reduce the temperatures in a manufacturing process of a semiconductor device. An island-like oxide semiconductor layer is formed over a first insulating film; a second insulating film and a first conductive film are formed in this order, covering the oxide semiconductor layer; oxygen is supplied to the second insulating film through the first conductive film; a metal oxide film is formed over the second insulating film in an atmosphere containing oxygen; a first gate electrode is formed by processing the metal oxide film; a third insulating film is formed, covering the first gate electrode and the second insulating film; and first heat treatment is performed. The second insulating film and the third insulating film each include oxide. The highest temperature in the above steps is 340° C. or lower. | 2020-10-08 |
20200321455 | DOUBLE-SIDED VERTICAL POWER TRANSISTOR STRUCTURE - Power semiconductor devices can often be expensive to produce and/or expensive to operate (i.e. inefficient). The present structure seeks to overcome these problems by providing a double-sided vertical power transistor structure that poses a unipolar path and a second parallel bipolar path. | 2020-10-08 |
20200321456 | TWO-DIMENSIONAL ELECTRON GAS (2DEG)-CONFINED DEVICES AND METHODS - Embodiments are directed to two-dimensional electron gas (2DEG)-confined 2DEG devices and methods. One such device includes a substrate and a heterostructure on the substrate. The heterostructure includes a first semiconductor layer, a second semiconductor layer, and a 2DEG layer between the first and second semiconductor layers. The device further includes a 2DEG device having a conduction channel in the 2DEG layer. An isolation electrode overlies the heterostructure and at least partially surrounds a periphery of the 2DEG device. The isolation electrode, in use, interrupts the 2DEG layer in response to an applied voltage. | 2020-10-08 |
20200321457 | ELECTRICALLY CONFINED BALLISTIC DEVICES AND METHODS - Embodiments are directed to electrically confined ballistic devices, circuits, and networks. One such device includes a heterostructure that has a first semiconductor layer, a second semiconductor layer, and a two-dimensional electrode gas (2DEG) layer between the first and second semiconductor layers. The device further includes an input electrode electrically coupled to the 2DEG layer and an output electrode electrically coupled to the 2DEG layer. A first confinement electrode is positioned on the heterostructure. The first confinement electrode, in use, generates first space charge regions which at least partially define a boundary of the ballistic device within the 2DEG layer between the input electrode and the output electrode in response to a first voltage. | 2020-10-08 |
20200321458 | BYPASSED GATE TRANSISTORS HAVING IMPROVED STABILITY - A transistor includes a plurality of gate fingers that extend in a first direction and are spaced apart from each other in a second direction, each of the gate fingers comprising at least spaced-apart and generally collinear first and second gate finger segments that are electrically connected to each other. The first gate finger segments are separated from the second gate finger segments in the first direction by a gap region that extends in the second direction. A resistor is disposed in the gap region. | 2020-10-08 |
20200321459 | FINFET DEVICE AND METHOD FOR FABRICATING SAME - Methods are disclosed herein for fabricating integrated circuit devices, such as fin-like field-effect transistors (FinFETs), and disclosed are the associated devices. An exemplary method includes forming a first semiconductor material layer over a fin portion of a substrate; forming a second semiconductor material layer over the first semiconductor material layer; and converting a portion of the first semiconductor material layer to a first semiconductor oxide layer. The fin portion of the substrate, the first semiconductor material layer, the first semiconductor oxide layer, and the second semiconductor material layer form a fin. The method further includes forming a gate stack overwrapping the fin. | 2020-10-08 |
20200321460 | VIA STRUCTURE WITH LOW RESISTIVITY AND METHOD FOR FORMING THE SAME - A semiconductor device structure is provided. The semiconductor device structure includes an insulating layer over a substrate, a gate stack formed in the insulating layer, and an insulating capping layer formed in the insulating layer to cover the gate stack. The semiconductor device structure also includes a source/drain contact structure adjacent to the gate stack. The source/drain contact structure has a sidewall that is in direct contact with a sidewall of the insulating capping layer, and an upper surface that is substantially level with an upper surface of the insulating capping layer and an upper surface of the insulating layer. In addition, the semiconductor device structure includes a first via structure above and electrically connected to the gate stack and a second via structure above and electrically connected to the source/drain contact structure. | 2020-10-08 |
20200321461 | FinFETs with Source/Drain Cladding - A device includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate. A semiconductor fin is between opposite portions of the isolation regions, wherein the semiconductor fin is over top surfaces of the isolation regions. A gate stack overlaps the semiconductor fin. A source/drain region is on a side of the gate stack and connected to the semiconductor fin. The source/drain region includes an inner portion thinner than the semiconductor fin, and an outer portion outside the inner portion. The semiconductor fin and the inner portion of the source/drain region have a same composition of group IV semiconductors. | 2020-10-08 |
20200321462 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND POWER CONVERTER - In SiC-MOSFETs including Schottky diodes, passage of a bipolar current to a second well region formed in a terminal portion sometimes reduces a breakdown voltage. In a SiC-MOSFET including Schottky diodes according to the present invention, the second well region formed in the terminal portion has a non-ohmic connection to a source electrode, and a field limiting layer lower in impurity concentration than the second well region is formed in a surface layer area of the second well region which is a region facing a gate electrode through a gate insulating film. | 2020-10-08 |
20200321463 | Semiconductor Device - A semiconductor device includes a semiconductor body comprising a first surface, a second surface opposite to the first surface, an active region, and an edge region surrounding the active region in a horizontal plane. The semiconductor device further includes a plurality of transistor cells at least partly integrated in the active region. Each transistor cell includes a drift region separated from a source region by a body region, and a gate electrode dielectrically insulated from the body region. The semiconductor device also includes a sensor device having a first sensor region of a first doping type integrated in the edge region. The first sensor region is electrically coupled to a first contact pad and to a second contact pad. Each contact pad is arranged either on the first surface or on the second surface. The sensor device at least partially extends around the active region. | 2020-10-08 |
20200321464 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a deep trench DTC reaching a predetermined depth from a first main surface of a semiconductor substrate SUB, a plurality of columnar conductors CCB including plugs PUG and field plates FP are formed. A p type impurity layer PIL is formed along the side wall surface of the deep trench DTC. Between the bottom of the plug PUG and the bottom of the p type impurity layer PIL, the field plate FP and the p type impurity layer PIL are positioned to face each other via an insulating film FIF interposed therebetween. Between the bottom of the p type impurity layer PIL and the bottom of the field plate FP, the field plate FP and an n-type drift layer NDL of the semiconductor substrate SUB are positioned to face each other via the insulating film FIF interposed therebetween. | 2020-10-08 |
20200321465 | Semiconductor Device and Method - In accordance with some embodiments, a method is provided. The method includes: forming a semiconductor fin protruding from a substrate; depositing a spacer layer over the semiconductor fin; after the depositing the spacer layer over the semiconductor fin, implanting a first dopant in the spacer layer and depositing a dopant layer of the first dopant on the spacer layer in alternating repeating steps; removing the dopant layer; and performing a thermal anneal process to drive the first dopant into the semiconductor fin from the spacer layer. | 2020-10-08 |
20200321466 | ASYMMETRIC FET FOR FDSOI DEVICES - The present disclosure relates generally to semiconductor structures, and more particularly to asymmetric field effect transistors (FET) on fully depleted silicon on insulator (FDSOI) semiconductor devices for high frequency and high voltage applications and their method of manufacture. The semiconductor device of the present disclosure includes a semiconductor-on-insulator (SOI) layer disposed above a substrate, the SOI layer having a source region, a channel region, a drift region and a drain region, where the drift region adjoins the drain region and the channel region, a gate structure disposed on the channel region, a multilayer drain spacer disposed on a drain-facing sidewall of the gate structure and covering the drift region, and a source spacer disposed on a source-facing sidewall of the gate structure, where the source and drain spacers are asymmetric with each other. | 2020-10-08 |
20200321467 | METHOD AND APPARATUS FOR USE IN IMPROVING LINEARITY OF MOSFETS USING AN ACCUMULATED CHARGE SINK-HARMONIC WRINKLE REDUCTION - A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink. | 2020-10-08 |
20200321468 | Structure of S/D Contact and Method of Making Same - A semiconductor device includes a fin feature in a substrate, a stack of semiconductor layers over the fin feature. Each of the semiconductor layers does not contact each other. The device also includes a semiconductor oxide layer interposed between the fin feature and the stack of the semiconductor layers. A surface of the semiconductor oxide layer contacts the fin feature and an opposite surface of the semiconductor oxide layer contacts a bottom layer of the stack of semiconductor layers. The device also includes a conductive material layer encircling each of the semiconductor layers and filling in spaces between each of two semiconductor layers. | 2020-10-08 |
20200321469 | SEMICONDUCTOR DEVICE AND DISPLAY APPARATUS - A semiconductor device includes a gate electrode, a semiconductor film, and a conductive film. The semiconductor film includes an oxide semiconductor material. The semiconductor film includes a channel region, a low-resistance region, and an intermediate region. The channel region is opposed to the gate electrode. The low-resistance region has a lower electric resistance than the channel region. The intermediate region is provided between the low-resistance region and the channel region. The conductive film is provided selectively in contact with the low-resistance region of the semiconductor film. | 2020-10-08 |
20200321470 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - It is an object to provide a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a semiconductor device including an inverted staggered thin film transistor whose semiconductor layer is an oxide semiconductor layer, a buffer layer is provided over the oxide semiconductor layer. The buffer layer is in contact with a channel formation region of the semiconductor layer and source and drain electrode layers. A film of the buffer layer has resistance distribution. A region provided over the channel formation region of the semiconductor layer has lower electrical conductivity than the channel formation region of the semiconductor layer, and a region in contact with the source and drain electrode layers has higher electrical conductivity than the channel formation region of the semiconductor layer. | 2020-10-08 |
20200321471 | FIELD EFFECT TRANSISTOR HAVING SOURCE CONTROL ELECTRODE, MANUFACTURING METHOD THEREOF AND ELECTRONIC DEVICE - A field effect transistor, a method of manufacturing the field effect transistor, and an electronic device are provided, wherein the field effect transistor comprises: a source ( | 2020-10-08 |
20200321472 | DOPED POLAR LAYERS AND SEMICONDUCTOR DEVICE INCORPORATING SAME - The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor, which in turn comprises a polar layer comprising a crystalline base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen, wherein the dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The capacitor additionally comprises first and second crystalline conductive or semiconductive oxide electrodes on opposing sides of the polar layer, wherein the polar layer has a lattice constant that is matched within about 20% of a lattice constant of one or both of the first and second crystalline conductive or semiconductive oxide electrodes. The first crystalline conductive or semiconductive oxide electrode serves as a template for growing the polar layer thereon, such that at least a portion of the polar layer is pseudomorphically formed on the first crystalline conductive or semiconductive oxide electrode. | 2020-10-08 |
20200321473 | DOPED POLAR LAYERS AND SEMICONDUCTOR DEVICE INCORPORATING SAME - The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a capacitor comprises a crystalline polar layer comprising a base polar material substitutionally doped with a dopant. The base polar material comprises one or more metal elements and one or both of oxygen or nitrogen. The dopant comprises a metal element of one of 4d series, 5d series, 4f series or 5f series that is different from the one or more metal elements, such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. | 2020-10-08 |
20200321474 | DOPED POLAR LAYERS AND SEMICONDUCTOR DEVICE INCORPORATING SAME - The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a transistor formed on a silicon substrate and a capacitor electrically connected to the transistor by a conductive via. The capacitor comprises upper and lower conductive oxide electrodes on opposing sides of a polar layer, wherein the lower conductive oxide electrode is electrically connected to a drain of the transistor. The capacitor additionally comprises a polar layer comprising a base polar material doped with a dopant, wherein the base polar material includes one or more metal elements and one or both of oxygen or nitrogen, wherein the dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The semiconductor device additionally comprises a lower barrier layer comprising a refractory metal or an intermetallic compound between the lower conductive oxide electrode and the conductive via. | 2020-10-08 |
20200321475 | MANUFACTURING METHOD FOR LTPS TFT SUBSTRATE - A manufacturing method for LTPS TFT substrate is disclosed. Through performing two etchings on the gate metal layer, ion heavy doping and ion light doping of the polysilicon active layer are performed in a self-aligned manner such that the LDD structure of the polysilicon active layer is symmetrically distributed on two sides of the gate electrode, which is beneficial to improve device characteristics, is more stable and reliable than the conventional technology, and can reduce the number of process masks, save mask cost, operation cost, material cost and the time cost. The thinning process of the gate insulation layer can reduce the thickness of the gate insulation layer corresponding to the heavily doped region of the polysilicon active layer, so that the ion implantation efficiency can be effectively improved. | 2020-10-08 |
20200321476 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE - A semiconductor device includes a non-volatile memory (NVM) cell. The NVM cell includes a semiconductor wire disposed over an insulating layer disposed on a substrate. The NVM cell includes a select transistor and a control transistor. The select transistor includes a gate dielectric layer disposed around the semiconductor wire and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the semiconductor wire and a control gate electrode disposed on the stacked dielectric layer. The stacked dielectric layer includes a charge trapping layer. The select gate electrode is disposed adjacent to the control gate electrode with the stacked dielectric layer interposed therebetween. | 2020-10-08 |
20200321477 | MULTI-SCHOTTKY-LAYER TRENCH JUNCTION BARRIER SCHOTTKY DIODE AND MANUFACTURING METHOD THEREOF - A Schottky diode may include a substrate; an epitaxial layer deposited on top of the substrate; one or more trenches formed on top of the epitaxial layer; an implantation region at a bottom portion of each trench; an ohmic contact metal on the other side of the substrate; a first Schottky contact metal deposited onto the implantation region in each trench to form a first Schottky junction between the first Schottky contact metal and the epitaxial layer at a lower trench sidewall; a second Schottky contact metal filling each trench and extending a predetermined length to each corner of mesas on the epitaxial layer to form a second Schottky junction between the second Schottky contact metal and the epitaxial layer at an upper trench sidewall; and a third Schottky contact metal covering the second Schottky contact metal and the epitaxial layer to form a third Schottky junction. | 2020-10-08 |
20200321478 | TRENCH JUNCTION BARRIER SCHOTTKY DIODE WITH VOLTAGE REDUCING LAYER AND MANUFACTURING METHOD THEREOF - In one aspect, a method for manufacturing a silicon carbide (SiC) multi-Schottky-layer trench junction barrier Schottky diode may include steps of providing a substrate; forming an epitaxial layer on top of the substrate; forming one or more trenches on the epitaxial layer; generating a first implantation region at a bottom portion of each trench; providing an ohmic contact metal on an opposite of the substrate; generating a second implantation region at each corner near a top portion of each trench; and forming a Schottky contact metal to fill in each trench and on top of the epitaxial layer. | 2020-10-08 |
20200321479 | Apparatus and Method for a Low Loss Coupling Capacitor - Embodiments are provided herein for low loss coupling capacitor structures. The embodiments include a n-type varactor (NVAR) configuration and p-type varactor (PVAR) configuration. The structure in the NVAR configuration comprises a p-doped semiconductor substrate (Psub), a deep n-doped semiconductor well (DNW) in the Psub, and a p-doped semiconductor well (P well) in the DNW. The circuit structure further comprises a source terminal of a p-doped semiconductor material within P well, and a drain terminal of the p-doped semiconductor material within the P well. Additionally, the circuit structure comprises an insulated gate on the surface of the P well, a metal pattern comprising a plurality of layers of metal lines, and a plurality of vias through the metal lines. The vias are contacts connecting the metal lines to the gate, the source terminal, and the drain terminal. | 2020-10-08 |
20200321480 | LASER-TEXTURED THIN-FILM SEMICONDUCTORS BY MELTING AND ABLATION - A photovoltaic device and a method of making the photovoltaic device are disclosed. The photovoltaic device may include a semiconductor layer epitaxially grown using a compound semiconductor material, such as a group III-V semiconductor material, wherein a surface of the semiconductor layer is textured via one or more laser pulses of a laser. The photovoltaic device may also include a dielectric layer deposited over the textured surface of the semiconductor layer, and a back metal reflector provided on the dielectric layer. The textured surface extends a path of light traveling through the photovoltaic device to increase absorption of the light within the photovoltaic device. | 2020-10-08 |
20200321481 | Photonic Detector Coupled with a Dielectric Resonator Antenna - An apparatus for light detection includes a light, or photon, detector assembly and a dielectric resonator layer coupled to the detector assembly. The dielectric resonator layer is configured to receive transmission of incident light that is directed into the detector assembly by the dielectric resonator layer. The dielectric resonator layer resonates with a range of wavelengths of the incident light. | 2020-10-08 |
20200321482 | OUTPUT VOLTAGE CONTROL CIRCUIT DEVICE FOR PLURALITY OF POWER SUPPLY CELLS CONNECTED IN SERIES - An output voltage control circuit device includes a rectifying unit configured to permit a flow of a current from a negative electrode side to a positive electrode side of a power supply cell, a voltage generation unit, through which a current is able to flow in both directions between both ends inserted between a negative electrode of an odd-numbered power supply cell counted from the negative electrode side of the power supply cells and an anode of the rectifying unit, and a generated voltage between both ends is able to be cyclically inverted; a voltage holding capacitor, and a voltage control circuit unit configured to generate a voltage, a direction of which is cyclically inverted, between both ends of the voltage generation unit on the negative electrode side of the power supply cells. | 2020-10-08 |
20200321483 | SHINGLED SOLAR CELLS OVERLAPPING ALONG NON-LINEAR EDGES - Solar devices and methods for producing solar devices are disclosed. In some examples, a solar device includes solar cells arranged in a shingled manner such that adjacent long edges of adjacent ones of the solar cells overlap. The adjacent long edges have a non-linear shape that has protruding portions. The solar device includes contact pads arranged in the protruding portions of the adjacent long edges such that the contact pads of the adjacent ones of the solar cells are electrically connected. | 2020-10-08 |
20200321484 | PN JUNCTION AND PREPARATION METHOD AND USE THEREOF - The patent application relates to a PN junction as well as the preparation method and use thereof. Said PN junction comprises a p-type CIGS semiconductor thin film layer and an n-type CIGS semiconductor thin film layer, wherein the n-type CIGS semiconductor thin film layer comprises or consists essentially of elements Cu, In, Ga and Se, where the Cu to In molar ratio is within the range of 1.1 to 1.5, and has a chemical formula of Cu(In | 2020-10-08 |
20200321485 | Graphic Layers and Related Methods for Incorporation of Graphic Layers into Solar Modules - In some aspects, graphic layers for depicting a visible representation of an image along a surface of a photovoltaic module can include a plurality of substantially opaque isolated regions; and at least one substantially transparent contiguous region surrounding the substantially opaque isolated regions, wherein an outer surface of the at least one substantially transparent contiguous region comprises a matte surface finish. | 2020-10-08 |
20200321486 | OPTICAL SEMICONDUCTOR DEVICE AND OPTICAL TRANSMISSION APPARATUS - An apparatus includes a first semiconductor layer including a first bandgap; and a second semiconductor layer of a first polarity including a second bandgap smaller than the first bandgap and formed over the first semiconductor layer. The first semiconductor layer includes a first conductive region of the first polarity, a second conductive region of a second polarity, and a non-conductive region between the first conductive region and the second conductive region, and the second semiconductor layer is in contact with the first conductive region and the non-conductive region. | 2020-10-08 |
20200321487 | METHOD OF SELECTIVELY TRANSFERRING SEMICONDUCTOR DEVICE - A method of transferring semiconductor devices from a first substrate to a second substrate, including providing the semiconductor devices which are between the first substrate and the second substrate. The semiconductor devices include a first semiconductor device and a second semiconductor device, and the first semiconductor device and the second semiconductor device have a first gap between thereof. The first semiconductor device and the second semiconductor device are moved from the first substrate by a picking unit. The picking unit, the first semiconductor device, and the second semiconductor device are moved close to the second substrate. The picking unit has a space apart from the second substrate. The first semiconductor device and the second semiconductor device are transferred from the picking unit to the second substrate. The he first semiconductor device and the second semiconductor device on the second substrate have a second gap between thereof. The first gap and the second gap are different. | 2020-10-08 |
20200321488 | DISPLAY PANEL AND MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE - The present disclosure provides a display panel, a manufacturing method thereof, and a display device. The method includes: providing a first substrate; forming first via holes into a first surface; forming a first metal layer on the first surface and in the first via holes; patterning the first metal layer to form first portions, including first sub-portions in the first via holes; forming second via holes into a second surface; forming a second metal layer on the second surface and in the second via holes; patterning the second metal layer to form second portions and pads, that the second portions and the pads are electrically connected, the second portions includes second sub-portions in the second via holes, and the first sub-portions and the second sub-portions are electrically connected; and bonding and electrically connecting electronic components with the plurality of pads. | 2020-10-08 |
20200321489 | Method for manufacturing electronic device - The present disclosure provides a method for manufacturing an electronic device. First, a plurality of light-emitting elements is provided on a first substrate. Then, at least one of the plurality of light-emitting elements is transferred from the first substrate to a second substrate by a transferring head. The transferring head includes an electrode and a cantilever supporting the electrode, and the cantilever includes a U-shaped portion. | 2020-10-08 |
20200321490 | METAL OXIDE NANOPARTICLES SURFACE-TREATED WITH METAL ION, QUANTUM DOT-LIGHT-EMITTING DEVICE COMPRISING THE SAME AND METHOD FOR FABRICATING THE SAME - The metal oxide nanoparticle includes a Zn-containing metal Me | 2020-10-08 |
20200321491 | NITRIDE SEMICONDUCTOR ULTRAVIOLET LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - Provided is an ultraviolet light emitting device having high quality and high reliability that prevents deterioration in electrical characteristics caused by a photochemical reaction of a non-bonding amorphous fluororesin, decomposition or the like of the amorphous fluororesin, and peeling off of the amorphous fluororesin. A nitride semiconductor ultraviolet light emitting device | 2020-10-08 |
20200321492 | LIGHT-EMITTING ELEMENT - A light-emitting element includes: a semiconductor stacked body; an insulating film located on a p-type semiconductor layer; a p-side electrode located on the insulating film, the p-side electrode comprising a pad portion and an extension portion, the extension portion being continuous with the pad portion in a first direction; a light-transmissive conductive film located on the p-type semiconductor layer and on the insulating film, the light-transmissive conductive film having an opening that is continuous along the extension portion on the insulating film; and a reflective film located between the insulating film and the p-side electrode in the opening. The opening includes a first opening and a second opening. In the second direction, the light-transmissive conductive film is electrically connected to the extension portion of the p-side electrode at a portion adjacent to a region where the first opening is located. | 2020-10-08 |
20200321493 | UV SOLID STATE OUTPUT DEVICE - A solid state UV output device package comprises a base which defines a chamber in which electrical components are housed. At least two spring contacts are mounted in the chamber. A lid over the chamber has a UV transparent or translucent window, electrical connection tracks mounted over the inside of the window and a UV output arrangement mounted over the electrical connection tracks. The electrical connection tracks of the lid make electrical contact with the spring contacts. This provides a two-layer structure which provides improved thermal management. | 2020-10-08 |
20200321494 | RED PHOSPHOR, WHITE LIGHT EMITTING DIODE, AND BACKLIGHT MODULE - A red phosphor comprising a first red phosphor and a second red phosphor having adjustable wavelength. The first red phosphor is made from a substance having structure formula M | 2020-10-08 |
20200321495 | LIGHT-EMITTING DIODE AND LIGHT-EMITTING MODULE - A light-emitting module and a light-emitting diode are provided. The light-emitting diode includes an epitaxial light-emitting structure to generate a light beam with a broadband blue spectrum. A spectrum waveform of the broadband blue spectrum has a full width at half maximum (FWHM) larger than or equal to 30 nm. The spectrum waveform has a plurality of peak inflection points, and a difference between two wavelength values to which any two adjacent ones of the peak inflection points respectively correspond is less than or equal to 18 nm. | 2020-10-08 |
20200321496 | METHODS FOR PRODUCING A CONVERSION ELEMENT AND AN OPTOELECTRONIC COMPONENT - The invention relates to a method for producing a conversion element for an optoelectronic component comprising the steps of: A) Producing a first layer, for that purpose: A1) Providing a polysiloxane precursor material, which is liquid, A2) Mixing a phosphor to the polysiloxane precursor material, wherein the phosphor is suitable for conversion of radiation, A3) Curing the arrangement produced under step A2) to produce a first layer having a phosphor mixed in a cured polysiloxane material, which comprises a three-dimensional crosslinking network based primarily on T-units, where the ratio of T-units to all units is greater than 80%, B) Producing a phosphor-free second layer, for that purpose: B1) Providing the polysiloxane precursor material, which is liquid, B2) Mixing a filler to the polysiloxane precursor material, wherein the filler is in a cured and powdered form, wherein the filler has a refractive index, which is equal to the refractive index of the cured polysiloxane material, B3) Curing the arrangement produced under step B2) to produce a second layer having a filler mixed in the cured polysiloxane material, which comprises a three-dimensional crosslinking network based primarily on T-units, wherein the produced conversion element is formed as a plate having a thickness of at least 100 μm. | 2020-10-08 |
20200321497 | METHOD OF MANUFACTURING LIGHT EMITTING DEVICE - A method of manufacturing a light emitting device, the method includes: preparing an intermediate structure including a supporter, a plurality of light emitting elements arranged on the supporter, a covering layer arranged on the supporter and surrounding the light emitting elements, and wiring electrodes each arranged on and straddling the covering layer and a corresponding one of the light emitting elements: preparing a board including light-reflective resin arranged on a surface of the board; pressing the intermediate structure against the light-reflective resin arranged on the board, with the wiring electrodes facing the light-reflective resin; curing the light-reflective resin to form a light-reflective resin layer; and removing the supporter. | 2020-10-08 |
20200321498 | PHOTON EXTRACTION FROM NITRIDE ULTRAVIOLET LIGHT-EMITTING DEVICES - In various embodiments, a rigid lens is attached to a light-emitting semiconductor die via a layer of encapsulant having a thickness insufficient to prevent propagation of thermal expansion mismatch-induced strain between the rigid lens and the semiconductor die. | 2020-10-08 |
20200321499 | JUNCTION STRUCTURE - A bonding structure is a bonding structure which bonds a light emitting element and a substrate and includes a first electrode formed on the light emitting element, a second electrode formed on the substrate, and a bonding layer which bonds the first electrode and the second electrode, and the bonding layer contains a first bonding metal component and a second bonding metal component different from the first bonding metal component. | 2020-10-08 |
20200321500 | LS Grid Core LED Connector System and Manufacturing Method - A new method, system and apparatus for mounting mechanically, thermally and electrically light emitting diode (LED), crystals, arrays or packages. The above provides an LED assembly having reduced number of components and costs, superior heat dissipation, mechanical properties and a compact structure. The use of a grid or mesh allows for more efficient and inexpensive removal of heat from one or more LEDs within an LED fixture. | 2020-10-08 |
20200321501 | LIGHT EMITTING DEVICE - A light emitting device includes a substrate including a base member including a front surface, a rear surface opposite to the front surface, a bottom surface perpendicular to the front surface, and a top surface opposite to the bottom surface, a first wiring portion located on the front surface, and a second wiring portion located on the rear surface; a light emitting element electrically connected with the first wiring portion; and a first reflective member covering a lateral surface of the light emitting element and the front surface of the base member. The base member has a recessed portion opened on the rear surface and the bottom surface. The substrate includes a third wiring portion covering an inner wall of the recessed portion and electrically connected with the second wiring portion, and a via in contact with the first wiring portion, the second wiring portion and the third wiring portion. | 2020-10-08 |