41st week of 2008 patent applcation highlights part 25 |
Patent application number | Title | Published |
20080247201 | Power-maximizing electrical energy generation system - An electrical energy generation system comprising:
| 2008-10-09 |
20080247202 | METHOD AND APPARATUS FOR SENSING MULTIPLE VOLTAGE VALUES FROM A SINGLE TERMINAL OF A POWER CONVERTER CONTROLLER - An example controller for a power converter according to aspects of the present invention includes a switching control that switches a power switch to regulate an output of a power converter. The controller also includes a sensor coupled to receive a signal from a single terminal of the controller. The signal from the single terminal is representative of a line input voltage of the power converter during at least a portion of an on time of the power switch. The signal from the single terminal is also representative of an output voltage of the power converter during at least a portion of an off time of the power switch. The switching control is responsive to the sensor. | 2008-10-09 |
20080247203 | Energy Efficient Power Converter - There is disclosed a power supply and method. The power supply may include a power converter for converting AC primary power into DC power, the power converter having a normal operating mode and a low power quiescent operating mode. A DC power plug may be adapted to deliver DC power from the power converter to a load. The normal operating mode and the low power quiescent operating mode of the power converter may be selected by a switch integrated into the DC power plug. | 2008-10-09 |
20080247204 | Regulator Device for a Three-Phase Ac Machine - A regulating apparatus for a three-phase AC machine has a DC controller and an inverter. An input of the inverter is coupled to the DC controller and an output of the inverter can be coupled to the AC machine. | 2008-10-09 |
20080247205 | Controlling apparatus of an AC LED string - The invention relates to a controlling apparatus of an AC LED string, which includes a controller to control the string being capable of flickering or totally unflickering very easily. The apparatus can also connect an adjustable resistance for application on a string with various numbers of LEDs. The apparatus includes at least one set of a pair of slots with different shapes or sizes at output ends for connecting with the LED string correctively that obtains improvement and utilization. | 2008-10-09 |
20080247206 | Energy transfer element and converter including the same - An energy transfer element includes a first winding coupled to an input circuit and a second winding coupled to an output circuit. The first winding has a first unit and a second unit, and the second winding is wound between the first unit of the first winding and the second unit of the first winding. The energy transfer element further includes a third winding provided between the first unit of the first winding and the second winding. The third winding is used to supply a bias voltage of the input circuit, and a winding width of the third winding is greater than a winding width of the first unit of the first winding and a width of the second winding. | 2008-10-09 |
20080247207 | SYSTEM FOR RECTIFYING AND LIMITING CURRENT AND REDUCING VOLTAGE - A system for reducing and limiting current and reducing voltage for a light string system. The system includes: an input terminal connected to a rectifying circuit; the rectifying circuit being connected between the input terminal and a voltage-reducing and current-limiting circuit; the voltage-reducing and current-limiting circuit being connected between the rectifying circuit and the input terminal; and an output terminal being connected to the device for rectifying current, reducing voltage and limiting current. | 2008-10-09 |
20080247208 | Semiconductor Device - A semiconductor device is provided, which comprises a rectifier circuit configured to generate a first voltage from a first signal inputted from an input terminal, a comparing circuit configured to compare a reference voltage and the first voltage inputted from the rectifier circuit and to output a second signal to a switch, and a voltage generation circuit configured to generate a second voltage from the first signal inputted from the input terminal. The rectifier circuit includes a transistor including at least a control terminal, and the voltage generation circuit inputs the second voltage to the control terminal when the switch is turned on in accordance with the second signal. | 2008-10-09 |
20080247209 | INTEGRATED SYNCHRONOUS RECTIFIER PACKAGE - A controller for controlling a controlled switching device functioning as a synchronous rectifier of alternating current, the controller comprising a control circuit for sensing the direction of current through the controlled switching device, the controlled switching device comprising a MOSFET having a conduction channel and a parasitic body diode and having two main current carrying terminals and a control terminal, the control circuit generating a control signal provided to the control terminal to turn on the controlled switching device approximately when current begins to flow in a first direction through the controlled switching device and turn off the controlled switching device approximately when current begins to flow in a second opposite direction through the controlled switching device, further wherein the control circuit for sensing the direction of current through the controlled switching device main current carrying terminals comprises a sensing circuit coupled across the controlled switching device for comparing a voltage across the controlled switching device to first and second thresholds, the sensing circuit causing the control signal to be generated to turn off the controlled switching device at the first threshold and to turn on the controlled switching device at the second threshold. | 2008-10-09 |
20080247210 | Resonant Inverter - A resonant inverter includes inductive elements (L | 2008-10-09 |
20080247211 | Active generator control sequence - A method for operating a matrix converter to convert n phases of a generator into alternating voltage with n | 2008-10-09 |
20080247212 | MEMORY SYSTEM HAVING POINT-TO-POINT (PTP) AND POINT-TO-TWO-POINT (PTTP) LINKS BETWEEN DEVICES - A memory system has first and second primary memories and first and second secondary memories coupled to the first and second primary memories, respectively, the coupling comprising at least one point-to-point connection. A memory module includes at least two of the first and second primary and first and second secondary memories. A first connection element, such as a connector or solder, connects the memory module to a mother board. A second connection element, such as a connector or solder, connects at least one other of the first and second primary and first and second secondary memories to the mother board. At least one of the memories on the first memory module is coupled to at least one of the other memories. The memory system also includes a memory controller which is connected to the primary memories by a point-to-two-point link. | 2008-10-09 |
20080247213 | Memory Device for Protecting Memory Cells during Programming - Improved circuitry and methods for programming memory cells of a memory device are disclosed. The improved circuitry and methods operate to protect the memory cells from potentially damaging electrical energy that can be imposed during programming of the memory cells. Additionally, the improved circuitry and methods operate to detect when programming of the memory cells has been achieved. The improved circuitry and methods are particularly useful for programming non-volatile memory cells. In one embodiment, the memory device pertains to a semiconductor memory product, such as a semiconductor memory chip or a portable memory card. | 2008-10-09 |
20080247214 | INTEGRATED MEMORY - In one aspect, a resistive memory device may be implemented in an embedded system. A resistive memory may comprise a resistive switchable medium that may be electrically connected to a first and a second electrode. In one aspect the first and the second electrode may comprise a via conductor and an interconnection line of an embedded structure. | 2008-10-09 |
20080247215 | RESISTIVE SWITCHING ELEMENT - According to one aspect, a switching element may comprise a first electrode, a second electrode, and a resistive switching region extending from the first electrode to the second electrode and comprising transition metal oxinitride. | 2008-10-09 |
20080247216 | METHOD AND APPARATUS FOR IMPLEMENTING IMPROVED WRITE PERFORMANCE FOR PCRAM DEVICES - A method of implementing a write operation for a programmable resistive random access memory array includes coupling a current source to a bit line associated with a programmable resistive memory element; prior to activating a word line associated with the memory element, precharging the bit line by passing current the bit line and through a dummy path selectively coupled to the bit line; and upon achieving a desired operating point of bit line current and bit line voltage, decoupling the dummy path from the bit line and activating the word line associated with the memory element so as to cause current from the bit line to flow for a period of time selected to program the memory element to one of a low resistance state and a high resistance state. | 2008-10-09 |
20080247217 | Integrated circuit, memory cell array, memory module, method of operating an integrated circuit, and computing system - An integrated circuit includes a plurality of resistivity changing memory cells and a plurality of resistivity changing reference cells. The integrated circuit is arranged such that each memory cell is switchable between N resistance levels, N being an integer greater than or equal to 2. To each of at least two possible resistance levels of a memory cell an individual reference cell as assigned. A resistance level of a memory cell is determined or set depending on the resistance level of the reference cell which is assigned to the resistance level of the memory cell. | 2008-10-09 |
20080247218 | DESIGN STRUCTURE FOR IMPLEMENTING IMPROVED WRITE PERFORMANCE FOR PCRAM DEVICES - A design structure embodied in a machine readable medium used in a design process includes a circuit for implementing a write operation for a programmable resistive random access memory array, the circuit including a current source coupled to a bit line associated with a programmable resistive memory element; a dummy path configured for selective coupling to the bit line prior to activation of a word line associated with the memory element, wherein the passage of current through the bit line and dummy path precharges the bit line; and control circuitry for decoupling the dummy path from the bit line and for activating the word line associated with the memory element upon achieving a desired operating point of bit line current and bit line voltage, so as to cause current from the bit line to flow for a period of time selected to program the memory element to one of a low resistance state and a high resistance state. | 2008-10-09 |
20080247219 | Resistive Random Access Memory Devices Including Sidewall Resistive Layers and Related Methods - A resistive random access memory (RRAM) device may include a first metal pattern on a substrate, a first insulating layer on the first metal pattern and on the substrate, an electrode, a second insulating layer on the first insulating layer, a resistive memory layer, and a second metal pattern. Portions of the first metal pattern may be between the substrate and the first insulating layer, and the first insulating layer may have a first opening therein exposing a portion of the first metal pattern. The electrode may be in the opening with the electrode being electrically coupled with the exposed portion of the first metal pattern. The first insulating layer may be between the second insulating layer and the substrate, and the second insulating layer may have a second opening therein exposing a portion of the electrode. The resistive memory layer may be on side faces of the second opening and on portions of the electrode, and the second metal pattern may be in the second opening with the resistive memory layer between the second metal pattern and the side faces of the second opening and between the second metal pattern and the electrode. Related methods are also discussed. | 2008-10-09 |
20080247220 | SEMICONDUCTOR MEMORY DEVICE WITH MEMORY CELLS OPERATED BY BOOSTED VOLTAGE - A memory using an SRAM memory cell intended for low-voltage operation is designed to decrease the threshold value of MOS transistors constituting the memory cell without substantial decrease in the static noise margin, which is the operational margin of the memory cell. To this end, a voltage Vdd′ higher than a power supply voltage Vdd of a power supply line for peripheral circuits is supplied from a power supply line for memory cells as a power supply voltage for memory cells. Since the conductance of driver MOS transistors is in-creased, the threshold voltage of the MOS transistors within the memory cells can be reduced without reducing the static noise margin. Further the ratio of width between the driver MOS transistor and a transfer MOS transistor can be set to 1, thereby allowing a reduction in the memory cell area. | 2008-10-09 |
20080247221 | 8T SRAM CELL WITH HIGHER VOLTAGE ON THE READ WL - The present invention provides circuitry for writing to and reading from an SRAM cell core, an SRAM cell, and an SRAM device. In one aspect, the circuitry includes a write circuit coupled to the SRAM cell core that includes a write transistor gated by a write word line. The circuitry also includes a read buffer circuit coupled to the SRAM cell core to read the cell without disturbing the state of the cell. The read buffer circuit includes a read transistor gated by a read word line, the read transistor coupled between a read bit-line and a read driver transistor that is further coupled to a voltage source Vss. The read driver transistor and a first driver transistor of the cell core are both gated by one output of the cell core. The read transistor has an electrical characteristic that differs from that of the core cell first driver transistor. | 2008-10-09 |
20080247222 | Spin Transfer Torque Magnetoresistive Random Access Memory and Design Methods - Systems, circuits and methods for determining read and write voltages for a given word line transistor in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. A first voltage can be supplied to the write operations so that the write operations occur in the saturation region of the word line transistor. A second voltage, which is less than the first voltage, can be supplied for read operations so that the read operations occur in the linear region of the word line transistor. | 2008-10-09 |
20080247223 | SPIN-INJECTION MAGNETIC RANDOM ACCESS MEMORY - A spin-injection magnetic random access memory of an aspect of the present invention includes a magnetoresistive element, a unit which writes data into the magnetoresistive element by use of spin-polarized electrons generated by a spin-injection current and which applies, to the magnetoresistive element, a magnetic field of a direction of a hard magnetization of the magnetoresistive element during the writing. | 2008-10-09 |
20080247224 | Phase Change Memory Bridge Cell with Diode Isolation Device - Memory cells are described along with arrays and methods for manufacturing. An embodiment of a memory cell as described herein includes a second doped semiconductor region on a first doped semiconductor region and defining a pn junction therebetween. A first electrode on the second doped semiconductor region. An insulating member between the first electrode and a second electrode, the insulating member having a thickness between the first and second electrodes. A bridge of memory material across the insulating member, the bridge having a bottom surface and contacting the first and second electrodes on the bottom surface, and defining an inter-electrode path between the first and second electrodes across the insulating member, the inter-electrode path having a path length defined by the thickness of the insulating member, wherein the memory material has at least two solid phases. | 2008-10-09 |
20080247225 | Variable resistance memory with lattice array using enclosing transistors - A variable resistance memory array, programming a variable resistance memory element and methods of forming the array. A variable resistance memory array is formed with a plurality of word line transistors surrounding each phase change memory element. To program a selected variable resistance memory element, all of the bitlines are grounded or biased at the same voltage. A top electrode select line that is in contact with the selected variable resistance memory element is selected. The word line having the word line transistors surrounding the selected variable resistance memory element are turned on to supply programming current to the element. Current flows from the selected top electrode select line through the variable resistance memory element into the common source/drain region of the surrounding word line transistors, across the transistors to the nearest bitline contacts. The word lines are patterned in various lattice configurations. | 2008-10-09 |
20080247226 | Memory devices having electrodes comprising nanowires, systems including same and methods of forming same - Memory devices having memory cells comprising variable resistance material include an electrode comprising a single nanowire. Various methods may be used to form such memory devices, and such methods may comprise establishing contact between one end of a single nanowire and a volume of variable resistance material in a memory cell. Electronic systems include such memory devices. | 2008-10-09 |
20080247227 | SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF - A semiconductor memory device includes: plural bit lines connected with plural memory cells, respectively; plural transfer lines allocated in common to the plural bit lines; sense amplifiers (SA | 2008-10-09 |
20080247228 | NON-VOLATILE STORAGE WITH CURRENT SENSING OF NEGATIVE THRESHOLD VOLTAGES - A non-volatile storage device in which current sensing is performed for a non-volatile storage element with a negative threshold voltage. A control gate read voltage is applied to a selected word line of a non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectively, associated with the non-volatile storage element. The source and p-well voltages exceed the control gate read voltage so that a positive control gate read voltage can be used. There is no need for a negative charge pump to apply a negative word line voltage even for sensing a negative threshold voltage. A programming condition of the non-volatile storage element is determined by sensing a voltage drop which is tied to a fixed current which flows in a NAND string of the non-volatile storage element. | 2008-10-09 |
20080247229 | NON-VOLATILE STORAGE USING CURRENT SENSING WITH BIASING OF SOURCE AND P-Well - A non-volatile storage device in which current sensing is performed for a non-volatile storage element. A voltage is applied to a selected word line of the first non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectively, associated with the non-volatile storage element. The source and p-well voltages are regulated at respective positive DC levels to avoid a ground bounce, or voltage fluctuation, which would occur if the source voltage at least was regulated at a ground voltage. A programming condition of the non-volatile storage element is determined by sensing a current in a NAND string of the non-volatile storage element. The sensing can occur quickly since there is no delay in waiting for the ground bounce to settle. | 2008-10-09 |
20080247230 | Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout - A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost. | 2008-10-09 |
20080247231 | NAND FLASH MEMORY DEVICE - A NAND flash memory device includes: a memory cell array that includes a plurality of NAND memory cell units each including a connection element having a plurality of electrically-rewritable memory cells; a plurality of word lines that are connected to the plurality of memory cells; a plurality of bit lines that are connected to the plurality of memory cells; and a read-write control section that applies a voltage selectively to the plurality of word lines and the plurality of bit lines, wherein each of the plurality of NAND memory cell units includes a first select gate transistor and a second select gate transistor; and wherein the read-write control section sets an voltage level applied to word lines, so that the voltage level becomes lower than a predetermined voltage level applied to other word lines connected to control gate electrodes of memory cells. | 2008-10-09 |
20080247232 | SEMICONDUCTOR STORAGE DEVICE AND ELECTRONIC EQUIPMENT THEREFOR - A semiconductor storage device includes a first memory cell for storing two kinds of states, a second memory cell for storing two kinds of states, and a sense amplifier for detecting a potential difference between voltages equivalent to readout currents of the first and second memory cells, respectively. Either one of information data “0” or data “1”, which is stored in combination of the first and second memory cells, is read out by detecting the potential difference equivalent to the readout current difference between the first and second memory cells. | 2008-10-09 |
20080247233 | NON-VOLATILE MEMORY DEVICE, NON-VOLATILE MEMORY SYSTEM AND CONTROL METHOD FOR THE NON-VOLATILE MEMORY DEVICE - A nonvolatile memory device which can reduce consumption current and shorten access time and a control method thereof is provided. The nonvolatile memory device | 2008-10-09 |
20080247234 | FLASH MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A flash memory device includes a plurality of memory cell blocks, an operating voltage generator, a block switching unit and a voltage supply circuit. Each of the plurality of memory cell blocks includes select lines and word lines, and has pass word lines included between the select lines and the word lines. The operating voltage generator outputs operating voltages to global select lines, global word lines and global pass word lines. The block switching unit connects the global word lines to the word lines and the select lines in response to a block select signal. The voltage supply circuit is connected to the select line and the pass word line, and is configured to supply the select line and the pass word line with a ground voltage in response to a block select inverse signal. | 2008-10-09 |
20080247235 | FLASH MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - Provided are a flash memory device and a method of driving the same for reading set information and stably storing the read set information in a latch. The method of driving the flash memory device includes applying power to the flash memory device, which includes a memory cell array for storing set information used to set an operating environment of the flash memory device. An initial read operation of the memory cell array is performed to read the set information. The set information read in the initial read operation is stored in a latch. It is determined whether the set information is normally stored in the latch based on set data input to the latch and set data output from the latch. | 2008-10-09 |
20080247236 | PROGRAM METHOD OF FLASH MEMORY DEVICE - A method for operating a flash memory device includes applying a first program voltage Vp | 2008-10-09 |
20080247237 | SEMICONDUCTOR MEMORY DEVICE IN WHICH SENSE TIMING OF SENSE AMPLIFIER CAN BE CONTROLLED BY CONSTANT CURRENT CHARGE - A semiconductor memory device includes a plurality of sense amplifiers which read data from a plurality of memory cells of a memory cell array, and a sense time generation circuit which controls the sense time of the plurality of sense amplifiers, the sense time generation circuit including a dummy capacitor having substantially the same size as that of a capacitor provided in each of the plurality of sense amplifiers, a control transistor connected to one electrode of the dummy capacitor and a constant-current discharge circuit which controls the control transistor to discharge the dummy capacitor with a constant current. The constant-current discharge circuit includes first and second nMOS transistors which are connected in series and a mirror circuit which generates gate voltage to operate the first and second nMOS transistors in a saturated region by use of the lowest voltage. | 2008-10-09 |
20080247238 | METHOD FOR SENSING NEGATIVE THRESHOLD VOLTAGES IN NON-VOLATILE STORAGE USING CURRENT SENSING - Current sensing is performed in a non-volatile storage device for a selected non-volatile storage element with a negative threshold voltage. A control gate read voltage is applied to a selected word line of a non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectively, associated with the non-volatile storage element. The source and p-well voltages exceed the control gate read voltage so that a positive control gate read voltage can be used. There is no need for a negative charge pump to apply a negative word line voltage even for sensing a negative threshold voltage. A programming condition of the non-volatile storage element is determined by sensing a voltage drop which is tied to a fixed current which flows in a NAND string of the non-volatile storage element. | 2008-10-09 |
20080247239 | METHOD FOR CURRENT SENSING WITH BIASING OF SOURCE AND P-WELL IN NON-VOLATILE STORAGE - Current sensing is performed in a non-volatile storage device for a non-volatile storage element. A voltage is applied to a selected word line of the first non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectively, associated with the non-volatile storage element. The source and p-well voltages are regulated at respective positive DC levels to avoid a ground bounce, or voltage fluctuation, which would occur if the source voltage at least was regulated at a ground voltage. A programming condition of the non-volatile storage element is determined by sensing a current in a NAND string of the non-volatile storage element. The sensing can occur quickly since there is no delay in waiting for the ground bounce to settle. | 2008-10-09 |
20080247240 | ERASE VERIFYING METHOD OF NAND FLASH MEMORY DEVICE - In an erase verifying method of a NAND flash memory device, a power supply voltage (Vcc) is applied to a second bit line while precharging a first bit line to a first positive voltage. Select transistors are turned on, and a ground voltage is applied to word lines of memory cell transistors. A second positive voltage is applied to source lines to which sources of the select transistors and the memory cell transistors are connected. An erased state of the memory cell transistor is verified according to whether charges accumulated in the first bit line are discharged. | 2008-10-09 |
20080247241 | SENSING IN NON-VOLATILE STORAGE USING PULLDOWN TO REGULATED SOURCE VOLTAGE TO REMOVE SYSTEM NOISE - A pull down circuit pulls a bit line voltage to a regulated source voltage in a non-volatile storage device during a sense operation such as a verify operation which occurs during programming. The storage device may include NAND strings which have associated bit lines and sense components, and a common source line. When a selected storage element of a NAND string has been programmed to its intended state, the bit line is locked out during subsequent verify operations which occur for other NAND strings which are not yet locked out. The pull down device is coupled to each bit line and to the common source line, whose voltage is regulated at a positive DC level, to prevent coupling of system power bus (V | 2008-10-09 |
20080247242 | Method Using a One-Time Programmable Memory Cell - A one-time programmable device includes a controller, a protection system, a static storage element and a latch, which can be referred to as a latch-based one-time programmable (OTP) element. In one example, the static storage element includes a thin gate-oxide that acts as a resistance element, which, depending on whether its blown, sets the latch into one of two states. | 2008-10-09 |
20080247243 | Semiconductor memory device including post package repair control circuit and post package repair method - Provided are a semiconductor memory device having a post package repair control circuit and a post package repair method. In the semiconductor memory device and the post package repair method, in a post package repair mode, a second memory bank is used as a fail bit map memory for storing failed bit information regarding a first memory bank, and the first memory bank is used as a fail bit map memory for storing failed bit information regarding the second memory bank. | 2008-10-09 |
20080247244 | Reading circuitry in memory - A reading circuit in a memory having a first memory cell coupled to a first bit line and a second bit line and a second memory cell coupled to the second bit line and a third bit line, is provided. The reading circuitry comprises a source side sensing circuit, a drain side bias circuit, a first selection circuit and a second selection circuit. The drain side bias circuit provides a drain side bias. The first selection circuit connects the second bit line and the third bit line to the drain side bias circuit in a read operation mode. The second selection circuit connects the first bit line to the source side sensing circuit so that a source current of the first memory cell is sensed. | 2008-10-09 |
20080247245 | WRITE CONTROL METHOD FOR A MEMORY ARRAY CONFIGURED WITH MULTIPLE MEMORY SUBARRAYS - Write control circuitry and control method are provided for a memory array configured with multiple memory subarrays. The write control circuitry includes multiple subarray write controllers associated with the multiple memory subarrays, each subarray write controller selectively enabling a local write control signal to its associated memory subarray. The selectively enabling is responsive to a received subarray select signal, wherein only one subarray select signal is active at a time. At least some subarray write controllers are powered at least in part via a switched power node, wherein powering of the switched power node is distributively implemented among the subarray write controllers. In one example, the distributively implemented powering of the switched power node is accomplished via multiple inverters distributed among the subarray write controllers, each inverter having an output coupled to the switched power node, and an input coupled to receive a global write enable signal. | 2008-10-09 |
20080247246 | METHODS AND APPARATUS FOR READ/WRITE CONTROL AND BIT SELECTION WITH FALSE READ SUPPRESSION IN AN SRAM - Methods and apparatus are provided for read/write control and bit selection with false read suppression in an SRAM. According to one aspect of the invention, a bit select circuit is provided for an SRAM. The disclosed bit select circuit comprises one or more transistors controlled by a write control gate signal to prevent data from being read from one or more data cells during a write operation. The transistors can comprise, for example, a pair of gated transistors controlled by the write control gate signal. The write control gate signal prevents data from being read from one or more data cells while the write control gate signal is in a predefined state. | 2008-10-09 |
20080247247 | FLASH MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - Provided are a flash memory device and a method of driving the same for improving reliability of stored set information. The method of driving the flash memory device includes applying power to the flash memory device, the flash memory device having a memory cell array for storing set information regarding operation environment settings, where the set information includes at least one bit. The method further includes performing an initial read operation on the memory cell array and judging a status of data, corresponding to the set information, read during the initial read operation to determine whether the initial read operation has passed or failed. Each bit of the set information is extended to n bits (where n is an integer equal to or greater than 2). The n bits are respectively stored in different input/output regions in the memory cell array. | 2008-10-09 |
20080247248 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - A semiconductor memory device includes: a driving voltage supplying unit configured to detect a simultaneous activation of banks and selectively supply one of a high voltage and an external voltage lower than the high voltage as a driving voltage; a flag detecting unit configured to detect inputs of flag signals activated in response to an active command and generate a precharge control signal; and a signal generating unit configured to generate a bit line precharge signal swinging between the driving voltage and a ground voltage in response to the precharge control signal. | 2008-10-09 |
20080247249 | Circuit and method for a sense amplifier - A circuit and method for providing a sense amplifier for a DRAM memory with reduced distortion in a control signal, the sense amplifier particularly useful for embedding DRAM memory with other logic and memory functions in an integrated circuit. A sense enable circuit is provided for a differential sensing latch in a sense amplifier having a cascade coupled pair of transistors, each transistor receiving a separate control signal. The separate control signals are provided by a control circuit with a delayed overlap. Differential sensing is enabled when the delayed overlap exists between the separate control signals. An array of DRAM memory cells are coupled to a plurality of the sense amplifiers. The DRAM memory incorporating the sense amplifiers may be embedded with other circuitry in an integrated circuit. Methods for providing the control signals and for laying out the DRAM memory with the sense amplifiers are provided. | 2008-10-09 |
20080247250 | Semiconductor memory device with two-stage input buffer - A semiconductor memory device includes: a pre-amplifying unit configured to amplify a difference between an input signal and a reference signal to output a pre-output signal; a delaying unit configured to delay the input signal to output a delayed input signal; and a main amplifying unit configured to receive the pre-output signal and the delayed input signal as differential inputs to output an output signal. | 2008-10-09 |
20080247251 | MEMORY DEVICE THAT TAKES LEAKAGE CURRENTS INTO ACCOUNT IN ACTIVATING THE READ AMPLIFIERS - A memory device is proved that includes memory cells situated at the intersection of lines and columns, and a dummy path including a first dummy column having two bit lines to which there are connected dummy memory cells, and a circuit adapted to select at least one of the dummy memory cells to discharge one of the dummy bit lines. The dummy path also includes at least one second dummy column adapted to generate a dummy leakage current (representing a leakage current of a column of the memory device selected in read mode), and a circuit adapted to copy the dummy leakage current to the one dummy bit line, so that the discharge of the one dummy bit line also depends on the dummy leakage current. | 2008-10-09 |
20080247252 | Semiconductor Memory Device with Temperature Control - A memory device in a semiconductor substrate includes at least one temperature sensor to provide a temperature dependent signal and at least one circuit to dissipate heat in response to a control signal. A control circuit is coupled to the at least one circuit and is operable to generate the control signal in response to the temperature dependent signal. | 2008-10-09 |
20080247253 | NON-VOLATILE STORAGE WITH TEMPERATURE COMPENSATION FOR BIT LINE DURING SENSE OPERATIONS - A non-volatile storage system in which temperature compensation of a bit line voltage is provided during a sense operation of a non-volatile storage element. A gate voltage of a transistor which couples a bit line associated with the non-volatile storage element to a sense module is temperature-compensated so that it is higher when temperature is higher to compensate for variations with temperature of the bit line voltage. The bit line voltage, in turn, varies due to variations in temperature of a threshold voltage of the non-volatile storage element. The sense module determines a programming condition of the non-volatile storage element, which may be provided in a NAND string, by sensing a voltage. The sense operation may be a read operation, verify operation, or erase-verify operation, for instance. Further, the threshold voltage of the non-volatile storage element may be positive or negative. In another aspect, a source voltage is temperature compensated. | 2008-10-09 |
20080247254 | METHOD FOR TEMPERATURE COMPENSATING BIT LINE DURING SENSE OPERATIONS IN NON-VOLATILE STORAGE - Temperature-compensation is provided during a sense operation of a non-volatile storage element. A gate voltage of a transistor which couples a bit line associated with the non-volatile storage element to a sense module is temperature-compensated so that it is higher when temperature is higher to compensate for variations with temperature of the bit line voltage. The bit line voltage, in turn, varies due to variations in temperature of a threshold voltage of the non-volatile storage element. The sense module determines a programming condition of the non-volatile storage element, which may be provided in a NAND string, by sensing a voltage. The sense operation may be a read operation, verify operation, or erase-verify operation, for instance. Further, the threshold voltage of the non-volatile storage element may be positive or negative. In another aspect, a source voltage is temperature compensated. | 2008-10-09 |
20080247255 | ELECTRONIC DEVICE INCLUDING A NONVOLATILE MEMORY ARRAY AND METHODS OF USING THE SAME - An electronic device can include a first memory cell and a second memory cell. The first memory cell can include a first source, and a second memory cell can include a second source. The first memory cell and the second memory cell can lie within a same sector of a memory array. In one embodiment, erasing the electronic device can include erasing the first memory cell while inhibiting the erase of the second memory cell. A third memory cell can have a third source and lie within another sector. In another embodiment, inhibiting the erase of the first memory cell can include placing the first source and the third source at a same potential. In a particular embodiment, the first source can be electrically insulated from the second source. | 2008-10-09 |
20080247256 | REFRESH SIGNAL GENERATOR OF SEMICONDUCTOR MEMORY DEVICE - A refresh signal generator generates an internal refresh signal to conduct a refresh with an interval controlled based on PVT fluctuations. The refresh signal generator includes a temperature sensing unit for sensing an internal temperature and activating a corresponding signal of a plurality of temperature sensing signals in response to a temperature sense driving signal, a power supply selecting unit for driving a driving voltage supply terminal to one of different voltage levels according to the plurality of temperature sensing signals, and an internal refresh signal generating unit for receiving a driving voltage from the power supply selecting unit and producing internal refresh signals at a constant interval. | 2008-10-09 |
20080247257 | MEMORY DATA INVERSION ARCHITECTURE FOR MINIMIZING POWER CONSUMPTION - A method for conserving power in a device is disclosed. The method generally includes the steps of (A) storing a plurality of data items in a plurality of bit cells in the device such that a majority of the bit cells holding the data items have a first logic state, wherein reading one of the bit cells having the first logic state consumes less power than reading one of the bit cells having a second logic state; (B) generating a polarity signal by analyzing the data items, the polarity signal indicating that the data items are stored in one of (i) an inverted condition and (ii) a non-inverted condition relative to a normal condition; and (C) driving at least one of the data items onto an external interface of the device in the normal condition during a read operation based on the polarity signal. | 2008-10-09 |
20080247258 | SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A leakage current of the MOS transistor of a power control section at a standby time is drastically reduced and the reduction of the consumption power is achieved. A memory module is provided with power control sections. When either of the memory mats is not selected, the power control sections stop the power supply voltage to a non-selected memory mat, a word driver, an input-output circuit, a control circuit and an output circuit. At the standby time of the memory module, the power control section stops a power supply to power control sections, a control circuit, a predecoder circuit, and an input circuit. In this manner, the leakage current of the MOS transistor of the power control sections at the standby time can be drastically reduced. | 2008-10-09 |
20080247259 | Configurable Memory Data Path - A data path in a memory device is configured by selecting a data path configuration configured to at least partially maintain data bit order between the memory device and a chip carrier. The memory data path is arranged based on the data path configuration for memory operations where maintaining data bit order between the memory device and the chip carrier is required. | 2008-10-09 |
20080247260 | Semiconductor memory device for independently selecting mode of memory bank and method of controlling thereof - A semiconductor memory device in which a mode of a memory bank may be independently selected and a method of controlling the semiconductor memory device may be provided. The semiconductor memory device with a plurality of banks may include a plurality of bank groups that each may have at least one bank from among the plurality of banks, and a memory controller that may control a read/write operation to be performed on a bank belonging to a bank group from among the plurality of bank groups, in response to a control signal, where different modes or the same mode may be applied to the bank groups. Accordingly, different modes or the same mode may be applied to the banks so that the read/write operation may be performed on a bank having a mode that is advantageous to the type of data, thereby minimizing consumption of power and a time delay. | 2008-10-09 |
20080247261 | SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF - A semiconductor memory device includes: a command latch circuit that latches a command signal; an address latch circuit that latches an address signal; a mode latch circuit that latches a mode signal; and a command decoder that selects the address latch circuit in response to the latch of a normal command by the command latch circuit, and selects the mode latch circuit in response to the latch of an adjustment command. With this arrangement, the mode signal can be dynamically received without performing a mode register set. Therefore, when a sufficiently large latch margin of the mode latch circuit is secured, there is no risk that it becomes impossible to input the mode signal. | 2008-10-09 |
20080247262 | BONE CEMENT CARTRIDGE WITH A RELEASABLY LOCKED DRIVE PISTON, THE PISTON CONFIGURED TO BE UNLOCKED BY A DELIVERY DEVICE - A bone cement mixing and delivery system is provided. The system includes a mixing cartridge for receiving liquid and powder components of bone cement, a mixing blade for mixing the components, and a delivery gun for discharging the bone cement from the mixing cartridge. The mixing cartridge comprises a cylinder having proximal and distal ends with a cylinder wall extending between the ends. A piston is locked at the distal end by a locking member that includes a pair of locking tabs protruding into slots in the cylinder wall. With the piston in the locked position, the mixing blade mixes the components. After mixing, the cartridge is placed in the delivery gun and release buttons on the locking member are engaged by a release mechanism on the delivery gun to release the piston from the locked position. | 2008-10-09 |
20080247263 | Method to Increase Production Rate of a Continuous Mixer or Extruder - Compounding or extrusion rates can be increased by splitting the polymer solid feed. Melting of additional solid polymer is significantly assisted by excess enthalpy from incoming melt from a primary mixing stage. Depending on resin rheology and melting characteristics, rate increases were achieved of from up to about 55 to about 100% rate increase over the use of a single feed at the same rotor speed. The net result is a decrease in the overall SEI (specific energy input to the polymer) and thus melt temperatures. | 2008-10-09 |
20080247264 | Apparatus and Method For Moving a Liquid by Means of a Piezoelectric Transducer - An apparatus having a device for moving a liquid comprises a piezoacoustic resonator element ( | 2008-10-09 |
20080247265 | Volumetric based chemical mixing system - The present invention provides an apparatus for the mixing or dilution of chemicals from one more sources that have been analyzed using laboratory analysis or an insitu-analyzer for concentration or molarity. The chemical is then transferred to a series of precisely calibrated vessels each of have a volume 10% of the next vessel. For example the main vessel may be 1 L in volume and the second vessel is 0.1 L in volume, the third is 0.01 L in volume and the fourth is 0.001 L in volume. The present system utilizes these two or more metered vessels which are connected to bulk chemical sources via intake lines. Each metered vessel contains an overflow tube, which drains any excess chemical by gravity flow from the metered vessel so as to adjust the chemical amount to a pre-calibrated desired level. As the chemicals exit the angle pipes, sensors located at the end of the overflow tube sense the chemical being discharged and trigger the feed pump and valve to shut off, whereby the excess chemicals will continue to drain out until the chemical levels reach the same level as the vent port of the pipe attached to the metered vessels. The excess chemicals are then drained into a recovery vessel which then can be transferred back to the bulk sources via a feed pump or pressure mechanism. The chemicals in the calibrated vessels are then dispensed by gravity lines to the mix tank vessel for mixing and subsequently delivered to a qualification vessel which may be verified using titration or online Ion Chromatography. | 2008-10-09 |
20080247266 | Metering device - A metering device for the feeding of additives to a gooey fluid or a pasty composition, in particular to a plastic melt, includes a passage section receiving the fluid and which contains at least one metering element for the injection of an additive into the plastic melt. The passage section has a recess for the reception of the metering element that is bounded at all sides by the passage section. The metering element is made of a porous structure or with a capillary structure for the passage of the additive. | 2008-10-09 |
20080247267 | Method and apparatus for cleaning rotary mixing device - In a method of cleaning a rotary mixing device having a mixer portion and a driving shaft, a shield is located over at least the mixer portion. The mixing device is rotated, expelling material clinging to or trapped by the mixing portion, such as paint, from the mixer portion of the mixing device. This material is blocked or caught by the shield. In one embodiment, the shield is cylindrical in shape and has a base with an opening through which the shaft of the mixing device may extend, and an open second end leading to an interior area for containing the mixer portion of the mixing device. | 2008-10-09 |
20080247268 | Autonomous Depth Control For Wellbore Equipment - A method for tracking a wellbore tool includes: obtaining a first image of the wellbore using an imager associated with the tool; obtaining a second image of the wellbore using the imager after a selected time period; matching the first image with the second image by shifting one of the first and second images; determining an amount of the shifting; and comparing the amount of the shifting with a reference distance to determine a distance of tool movement. A method for tracking a wellbore tool includes: obtaining an image of a wellbore feature using a first imager associated with the tool; moving the tool in the wellbore; and registering a distance of tool movement when the image of the wellbore feature is detected by a second imager spaced apart from the first imager, wherein the distance of tool movement equals a spacing between the first and second imagers. | 2008-10-09 |
20080247269 | Analysis of Uncertainty of Hypocenter Location Using the Combination of a VSP and a Subsurface Array - Acoustic signals resulting from microseismic events in the subsurface are received in a first array of detectors deployed in a borehole and in a second array of detectors at or near the surface of the earth. The signals are converted to give the locations of the microseismic events. | 2008-10-09 |
20080247270 | Resistivity Measurement Through Metal Casing Using Magnetic Field and Magnetoacoustic Phenomena - Measurements of acoustic velocities are made through a case borehole in the absence and presence of an applied magnetic field. A formation resistivity parameter may be estimated from differences in the acoustic velocities. | 2008-10-09 |
20080247271 | SEISMIC SENSOR WITH RAIN NOISE SHIELD - A seismic sensor includes a seismic energy detector having a case configured to be affixed to the ground. A portion of the case above the ground surface is exposed. An energy distributing shield is affixed directly to the exposed portion of the case. A method for seismic data acquisition includes affixing a plurality of spaced apart seismic sensors to the ground surface. Each of the sensors includes a shield affixed directly to an exposed portion of the sensor. The shield is made from an energy distributing material. At selected times a seismic energy source is actuated. Signals generated by each of the seismic sensors are recorded individually. | 2008-10-09 |
20080247272 | Method for reducing 3-D migration operator to 2-D migration operator for inhomogeneous media - Time slices of seismic data are transformed from rectangular space-time domain to cylindrical space-time domain. 2-D seismic migration is performed on the transformed data for each radial direction. Slices of the migrated data are inverse transformed back to the rectangular space-time domain, generated migrated 3-D data for generally inhomogeneous media. | 2008-10-09 |
20080247273 | APPARATUS AND METHODS FOR SELF-POWERED COMMUNICATION AND SENSOR NETWORK - A system for communicating between a first location and a second location comprises a jointed tubular string having a first section and a second section connected at a connection joint, with the tubular string having a fluid in an internal passage thereof. A first acoustic transducer is mounted in the internal passage of the first section proximate the connection joint, and a second acoustic transducer is mounted in the internal passage of the second section proximate the connection joint. A signal transmitted from the first location to the second location is transmitted across the connection joint as an acoustic signal in the fluid from the first acoustic transducer to the second acoustic transducer. | 2008-10-09 |
20080247274 | SENSOR ARRAY POST-FILTER FOR TRACKING SPATIAL DISTRIBUTIONS OF SIGNALS AND NOISE - A “Sensor Array Post-Filter” provides an adaptive post-filter that accurately models and suppresses both diffuse and directional noise sources as well as interfering speech sources. The post-filter is applied to an output signal produced by a beamformer used to process signals produced by a sensor array. As a result, the Sensor Array Post-Filter operates to improve the signal-to-noise ratio (SNR) of beamformer output signals by providing adaptive post-filtering of the output signals. The post-filter is generated based on a generative statistical model for modeling signal and noise sources at distinct regions in a signal field that considers prior distributions trained to model an instantaneous direction of arrival for signals captured by sensors in the array. | 2008-10-09 |
20080247275 | Underwater detection apparatus - An underwater detection apparatus for detecting a target by transmitting and receiving an ultrasound signal is provided. The apparatus includes a replica memory module for storing the typical amplitude evolution of a seawall echo during a predetermined time period as a template-replica beforehand, a correlator module for determining a correlation between the amplitude evolution of an echo signal reflected from the target and the template-replica, a seawall detector module for detecting a seawall position based on the correlation, and a seawall display processor module for displaying the seawall on its position in an indicator. | 2008-10-09 |
20080247276 | DEVICE AND METHOD FOR MANAGING TIME INFORMATION - Disclosed is a device and method for managing time information in a mobile communication terminal. To this end, the present invention provides a plan in which time information of a terminal can be automatically set with the local time of a corresponding time zone as a reference in accordance with a user's selection in a communication network, and a schedule can be exchanged with the universal time as a reference when it is necessary to share the schedule containing time information between terminals in different time zones. | 2008-10-09 |
20080247277 | CORRECTION DEVICE FOR TIMEPIECE DISPLAY MECHANISM AND WHEEL FITTED THERETO - The invention concerns a correction device ( | 2008-10-09 |
20080247278 | PROGRAMMABLE WATCH WINDER - An automatic watch winder that is user-programmable via USB (Universal Serial Bus) and/or wireless IrDA (Infrared), IEEE 802.11, or IEEE 802.15 connections to a computer, such as a laptop or notebook computer. The watch winder also includes a user programmable, high intensity LED illuminator used to charge the luminous material on a watch | 2008-10-09 |
20080247279 | EXTERNAL LOAD PORT MAGAZINE AND STORAGE SYSTEM AND METHOD OF USING SAME - An external load port magazine for use with a storage unit includes a casing detachably mountable on an exterior of the storage unit and defining therein a space for holding at least one item to be loaded into the storage unit. An opening is formed in the casing for enabling automatic withdrawal or insertion of the at least one item from or into the space when the casing is mounted on the exterior of the storage unit. A mechanism is provided for moving the at least one stored item towards the opening. | 2008-10-09 |
20080247280 | Optical Drive with Constant Radial Bandwidth - The invention relates to an optical drive for e.g. CD, DVD, HD-DVD or BD disks. A radial servomechanism controls the radial position of a laser beam in response to a push pull signal (PP). The radial servomechanism has an amplifier (VGA, | 2008-10-09 |
20080247281 | Data Recording Device, Data Recording Method, and Computer Program - It is possible to manage an empty region in a disc partition while satisfying an inhibit matter of the ROM standard not recording a space bit map describer (SBD). The SBD is recorded upon disc initialization and additional recording into the partition is performed by using the SBD regardless of the access type in the device. When ejecting the disc, pointer information to the SBD recorded in the partition describer (PD) is hacked up in the SBD pointer information save file or save data and then the pointer information is erased. Upon disc recognition, the existence of the save file/data is confirmed and the SBD is restored. | 2008-10-09 |
20080247282 | Method of Data Protection - A method of data protection is used in a data processing system having a storage device. According to the method, when the data processing system reads a damaged storage block in the storage device, it finds the surrounding storage blocks of the damaged block and determines in sequence whether any of the surrounding blocks is damaged. If none of them is damaged, then the data processing system determines whether those surrounding blocks are not in use. If they are not in use, then the data processing system defines them as being in use. If they are already in use, then the data processing system searches unused storage blocks in the storage device, duplicates the data in the surrounding blocks to the unused blocks, and then define the unused blocks as being in use. Finally, the data processing system establishes a correspondence relation between the surrounding blocks and the unused blocks. Therefore, when the data processing system accesses the surrounding blocks, it obtains data stored in the unused blocks through the correspondence relation. | 2008-10-09 |
20080247283 | APPARATUS FOR ASSIGNING SPARE AREAS FOR DEFECT MANAGEMENT AND APPARATUS FOR HANDLING FRAGMENTED ECC BLOCKS - A recording medium having a spare area for defect management, and a method and apparatus for allocating and assigning the spare area. A plurality of zones are formed as one group without prescribing the relationship between a zone and a group. Spare areas include a spare area for slipping replacement and a spare area for linear replacement. The spare are for slipping replacement is first allocated, and the spare area for linear replacement is allocated according to the size of an area remaining after the spare area for slipping replacement is used and the purpose for which a disc is used. When the spare area for linear replacement becomes deficient during use of the disc, a supplementary spare area for linear replacement is allocated in sequence from the rearmost of a logical file area, such that the spare area can be more flexibly and effectively allocated. | 2008-10-09 |
20080247284 | RECORDING APPARATUS FOR OPTICAL DISK DRIVE - A recording method for an optical disk drive is implemented as follows. First, at least one of the level of the focusing error signal, the level of the tracking error signal, a wobble synchronization pattern loss, the error rate of demodulating a wobble signal, the frequency of buffer under-run occurrence, the temperature of the drive, the wobble jitter and the level of write power is detected. If at least one detected value exceeds the preset value, the recording will be ceased. Then, the rotation speed of the optical disk drive is decreased, and the recording is resumed with the decreased rotation speed. If at least one of the temperature of the drive, the wobble jitter and the estimated write power exceeds the reset value before recording starts, the rotation speed of the optical disk drive is decreased before recording. | 2008-10-09 |
20080247285 | INFORMATION RECORDING MEDIUM, RECORDING APPARATUS, REPRODUCTION APPARATUS, RECORDING METHOD, AND REPRODUCTION METHOD - An information recording medium is provided, which comprises a plurality of recording layers and a first disc information area for storing parameters relating to access to the plurality of recording layers and formats relating to the plurality of recording layers. The first disc information area is provided in a first recording layer which is one of the plurality of recording layers. | 2008-10-09 |
20080247286 | Apparatus and method for producing optical recording medium, optical recording medium, apparatus and method for reproduction and apparatus and method for recording - An optical recording medium having a plural number of recording layers includes a n-th recording layer ( | 2008-10-09 |
20080247287 | Disc Tilt Detecting Device - The invention relates to a device ( | 2008-10-09 |
20080247288 | Optical Disk Drive and Tracking Error Detection Method For an Optical Disk Drive - The present invention relates to a tracking error detection method for an optical storage system wherein an optical disk comprises a plurality of adjacent track portions with a radial track pattern in which a number n>2 of adjacent track portions repeatedly exhibit non-uniform radial track distances (TP | 2008-10-09 |
20080247289 | Copy protection of optical discs - The more effective is the copy protection provided on a DVD, the greater is the likelihood that the copy protection will adversely interfere with legitimate uses of the disc. In a disc where the content is arranged in physical sectors, it is now proposed to provide subversive regions on the disc having a similar structure to genuine regions. A subversive region and a genuine region will each extend over one or more physical sectors. The subversive region will be provided with physical sector addresses which coincide with addresses of the genuine region. Navigational data will ensure that it is the genuine, rather than the subversive, region which will be accessed during normal play, but the subversive region will effectively hide the genuine region during copying. | 2008-10-09 |
20080247290 | Optical disc drive, optical storage medium, optical storage medium inspection apparatus, and optical storage medium inspection method - This optical disc drive has an optical pickup head that emits a light beam to an optical storage medium, detects the light beam reflected from the optical storage medium, and outputs a signal based on the received reflected light; a jitter measuring unit for measuring jitter in signals output from the optical pickup head; and an evaluation unit for determining from the measured jitter if the optical storage medium is good or defective. The jitter measuring unit measures jitter in a train of 3T or longer marks or spaces from an optical storage medium to which digital information is recorded as a train of marks or spaces of length kT based on a period T and an integer k of two or more. | 2008-10-09 |
20080247291 | Optical disc type determining method and optical disc device - Whether an optical disc is a first optical disc or not is determined with reference to at least one of first and second focus error signal amplitude values. Then, if a sum value of the addition of a first focus balance signal value (CD-FBAL signal value) to a second focus balance signal value (DVD-FBAL signal value) is equal to or more than a predetermined threshold value, the signal surface of the optical disc is determined to be a CD signal surface of a dual disc. On the other hand, if the sum value is smaller than the predetermined threshold value, the signal surface of the optical disc is determined to be a DVD signal surface of a DVD or a DVD signal surface of a dual disc. | 2008-10-09 |
20080247292 | METHOD AND APPARATUS FOR WRITING DATA ON A STORAGE MEDIUM - A data recording method according to the present invention is a method for recording data as edge position information, including marks and spaces of multiple different lengths, on a storage medium by irradiating the storage medium with a pulsed energy beam. The method includes the steps of: (A) generating a write code sequence based on the data to be recorded; (B) determining a write pulse waveform, defining the power modulation of the energy beam, according to the code lengths of respective codes included in the write code sequence; and (C) modulating the power of the energy beam based on the write pulse waveform. If the shortest code length of the write code sequence is n (which is an integer equal to or greater than one), a write pulse waveform that has only one write pulse is assigned to recording mark making periods corresponding to codes with code lengths x of n, n+1 and n+2, and a write pulse waveform that has multiple write pulses Pw is assigned to recording mark making periods corresponding to codes with code lengths x of n+3 or more. | 2008-10-09 |
20080247293 | METHOD AND APPARATUS FOR WRITING DATA ON A STORAGE MEDIUM - A data recording method according to the present invention is a method for recording data as edge position information, including marks and spaces of multiple different lengths, on a storage medium by irradiating the storage medium with a pulsed energy beam. The method includes the steps of: (A) generating a write code sequence based on the data to be recorded; (B) determining a write pulse waveform, defining the power modulation of the energy beam, according to the code lengths of respective codes included in the write code sequence; and (C) modulating the power of the energy beam based on the write pulse waveform. If the shortest code length of the write code sequence is n (which is an integer equal to or greater than one), a write pulse waveform that has only one write pulse is assigned to recording mark making periods corresponding to codes with code lengths x of n, n+1 and n+2, and a write pulse waveform that has multiple write pulses Pw is assigned to recording mark making periods corresponding to codes with code lengths x of n+3 or more. | 2008-10-09 |
20080247294 | Data reading method - A data reading method used in a reading device for reading a holographic storage medium is provided. The holographic storage medium has several data areas. Each data area has several data pages, and each data page forms a data image that has at least one reserved block pattern on the reading device. The reserved block pattern of the data image corresponding to a first data page is searched within a first searching region to obtain a first pattern position. The reserved block pattern of the data image corresponding to a second data page is searched within a second searching region to obtain a second pattern position. A third searching position is then determined according to the first and second pattern positions. The reserved block pattern of the data image corresponding to a third data page is searched within a third searching region whose center is at the third searching position. | 2008-10-09 |
20080247295 | FIRST-SIDE DUAL-LAYER OPTICAL DATA STORAGE DISK AND METHOD OF MANUFACTURING THE SAME - An optical data storage disk includes a central substrate and on each side of the substrate a pair of metal/alloy recording layers separated by a transparent layer. | 2008-10-09 |
20080247296 | Optical Storage Disk and System Comprising a Disk with Non-Uniformly Spaced Tracks - The present invention relates to an optical storage disk for both read-only and (re-)writable applications comprising a plurality of adjacent track portions with a radial track pattern in which a number of n≧2 adjacent track portions repeatedly exhibit non-uniform radial track distances TP | 2008-10-09 |
20080247297 | Optical pickup - An optical pickup includes: a slide base, having: a first surface; and a second surface; a first substrate fixed to the first surface; a standing frame disposed on the second surface; a second substrate facing the standing frame; a laser diode operable to emit a laser beam to the disk and disposed in the standing frame; an optical, element supported by the second substrate and adapted to receive a reflected beam; a flexible flat cable. The flexible flat cable is bent so that one end portion of the flexible flat cable is connected to the second substrate. A curved portion is formed with a slit elongated in a longitudinal direction of the flexible flat cable and defines an outer portion and an inner portion. A width of the inner portion is narrower than a width of the outer portion. | 2008-10-09 |
20080247298 | Optical System, Optical Pickup Apparatus, and Optical Disk Apparatus - The present invention discloses an optical system for extracting signal light components from a beam including the signal light components and stray light components. The optical system includes a condensing optical element situated on an optical path of the beam for condensing the beam, a polarization changing unit for changing the state of polarization of at least one of the signal light components and the stray light components included in the incident beam transmitted through the condensing optical element, and an extracting element for extracting the signal light components included in the beam transmitted through the polarization changing unit. | 2008-10-09 |
20080247299 | RECORDING MEDIUM, RECORDING METHOD, REPRODUCTION METHOD, RECORDING APPARATUS AND REPRODUCTION APPARATUS - A recording medium comprising a recording area, the recording area includes a first area and a second area, the first area includes a frame area, the frame area includes an area in which a second synchronization code sequence and at least a portion of data are to be recorded, and the second area includes an area in which a third synchronization code sequence and a fourth synchronization code sequence are to be recorded. | 2008-10-09 |
20080247300 | STORAGE DEVICE AND METHOD FOR SCANNING A STORAGE MEDIUM - A storage device and a method for scanning a storage medium. A storage medium for storing data in the form of marks is scanned by an array of probes for mark detecting purposes in a scanning mode. The storage medium has fields with each field to be scanned by an associated one of the probes. At least one of the fields has marks representing operational data for operating the scanning mode. Scanning parameters are computed from the operational data and the scanning mode is adjusted according to the computed parameters. | 2008-10-09 |