41st week of 2014 patent applcation highlights part 14 |
Patent application number | Title | Published |
20140299856 | ORGANIC ELECTROLUMINESCENCE ELEMENT - An organic electroluminescent element having a small reduction rate in the luminance immediately after the start of light emission is provided. The organic electroluminescent element includes a substrate, a pair of electrodes including an anode and a cathode, disposed on the substrate, a light emitting layer disposed between the electrodes, and at least one organic layer disposed between the light emitting layer and the anode, in which at least one kind of a specific compound including a fluorene structure is contained in at least one organic layer between the light emitting layer and the anode, and at least one kind of a specific compound including a carbazole structure or a fluorene structure is contained as a light emitting material in the light emitting layer. | 2014-10-09 |
20140299857 | COMPLEX COMPOUND, DRYING AGENT, SEALING STRUCTURE AND ORGANIC EL ELEMENT - A complex compound obtained by reacting a compound represented by the following formula (1) and a polyol having an ether bond in a molecule and having 4 to 12 carbon atoms or a branch polyol having 5 to 7 carbon atoms: | 2014-10-09 |
20140299858 | PLANARIZING AGENTS AND DEVICES - Use of certain materials in hole injection layer and/or hole transport layer can improve operational lifetimes in organic devices. Polymers having fused aromatic side groups such as polyvinylnaphthol polymers can be used in conjunction with conjugated polymers. Inks can be formulated and cast as films in organic electronic devices including OLEDs, SMOLEDs, and PLEDs. One embodiment provides a composition comprising: at least one conjugated polymer, and at least one second polymer different from the conjugated polymer comprising at least one optionally substituted fused aromatic hydrocarbon side group. The substituent can be hydroxyl. Aqueous-based inks can be formulated. | 2014-10-09 |
20140299859 | METHOD FOR HYBRID ENCAPSULATION OF AN ORGANIC LIGHT EMITTING DIODE - Methods and apparatus for encapsulating organic light emitting diode (OLED) structures disposed on a substrate using a hybrid layer of material are provided. The processing parameters used during deposition of the hybrid layer of material allow control of the characteristics of the deposited hybrid layer. The hybrid layer may be deposited such that the layer has characteristics of an inorganic material in some sublayers of the hybrid layer and characteristics of an organic material in other sublayers of the hybrid layer. Use of the hybrid material allows OLED encapsulation using a single hard mask for the complete encapsulating process with low cost and without alignment issues present in conventional processes. | 2014-10-09 |
20140299860 | METHOD OF MANUFACTURING THIN FILM TRANSISTOR,THIN FILM TRANSISTOR MANUFACTURED BY USING THE METHOD, METHOD OF MANUFACTURING ORGANIC LIGHT-EMITTING DISPLAY APPARATUS, AND ORGANIC LIGHT-EMITTING DISPLAY APPARATUS MANUFACTURED BY USING THE METHOD - A method of manufacturing a thin film transistor (TFT) comprises forming a buffer layer, an amorphous silicon layer, and an insulating layer on a substrate; crystallizing the amorphous silicon layer as a polycrystalline silicon layer; forming a semiconductor layer and a gate insulating layer which have a predetermined shape by simultaneously patterning the polycrystalline silicon layer and the insulating layer; forming a gate electrode including a first portion and a second portion by forming and patterning a metal layer on the gate insulating layer. The first portion is formed on the gate insulating layer and overlaps a channel region of a semiconductor layer, and the second portion contacts the semiconductor layer. A source region and a drain region are formed on the semiconductor layer by doping a region of the semiconductor layer. The region excludes the channel region overlapping the gate electrode and constitutes a region which does not overlap the gate electrode. An interlayer insulating layer is formed on the gate electrode so as to cover the gate insulating layer; contact holes are formed on the interlayer insulating layer and the gate insulating layer so as to expose the source region and the drain region, and simultaneously an opening for exposing the second portion is formed. A source electrode and a drain electrode are formed by patterning a conductive layer on the interlayer insulating layer. The source electrode and the drain electrode are electrically connected to the source region and the drain region via the contact holes, and simultaneously the second portion exposed via the opening is removed. | 2014-10-09 |
20140299861 | Heterocyclic Compound, Light-Emitting Element, Light-Emitting Device, Electronic Device, and Lighting Device - A substance having a hole-transport property and a wide band gap is provided. A heterocyclic compound represented by a general formula (G1) is provided. In the formula, α | 2014-10-09 |
20140299862 | ORGANIC LIGHT-EMITTING DISPLAY SYSTEM AND METHOD OF MANUFACTURING THE SAME - An organic light-emitting display system and a method of manufacturing the same are disclosed. In one aspect, the organic light-emitting display system includes a substrate, a display unit that defines an active area on the substrate and includes a plurality of thin film transistor (TFTs), and an encapsulation layer that seals the display unit and has a stacked structure in which at least a first inorganic film, a first organic film, and a second inorganic film are sequentially stacked. The TFTs includes an active layer, a gate electrode, a source electrode, a drain electrode, and an interlayer insulating film that is disposed between the gate electrode and the source electrode and between the gate electrode and the drain electrode, wherein the second inorganic film directly contacts the interlayer insulating film outside the active area. Accordingly, in various embodiments, since an inorganic layer of a thin film encapsulation layer is prevented from being cracked, penetration of external moisture or oxygen into the active area of the display can be reduced or prevents. | 2014-10-09 |
20140299863 | TOUCH-RESPONSIVE DISPLAY ASSEMBLY - A touch-responsive display assembly includes a touch panel. The touch panel includes: an anode, a cathode disposed over the anode, and an organic layered structure disposed between the anode and the cathode and including an organic electroluminescent layer that is emissive When a voltage is applied across the anode and the cathode. At least one of the anode and the cathode is made of a flexible film of a conductive nanomaterial that contains interconnected nanounits. | 2014-10-09 |
20140299864 | POLYMERS CONTAINING THERMALLY DISSOCIABLE AND SOLUBLE GROUPS AND THE USE OF SUCH POLYMERS AS ORGANIC ELECTROLUMINESCENT MATERIALS - A polymer, a luminescent material, and the likes are provided, wherein a film can be formed by a wet film-forming method, the film formed has a high stability, and is capable of being laminated with other layers by a wet film-forming method or another method, which are less decrease in charge transportation efficiency or luminescent efficiency, and attain an excellent driving stability. The polymer has a thermally dissociable and soluble group. | 2014-10-09 |
20140299865 | ORGANIC ELECTROLUMINESCENCE ELEMENT AND MATERIAL FOR ORGANIC ELECTROLUMINESCENCE ELEMENT - An organic electroluminescence device includes an anode, a cathode and at least an emitting layer interposed between the anode and the cathode. The emitting layer contains a first host material, a second host material and a phosphorescent dopant material. The first host material is a compound represented by the following formula (1). The second host material is a compound represented by the following formula (3). | 2014-10-09 |
20140299866 | OLED DEVICE AND METHOD OF PRODUCING AN OLED DEVICE - The invention describes an OLED device ( | 2014-10-09 |
20140299867 | ORGANIC ELECTROLUMINESCENCE DISPLAY PANEL AND ORGANIC ELECTROLUMINESCENCE DISPLAY APPARATUS - An organic electroluminescence (EL) display panel includes a cathode electrode formed above a bank and formed opposite to a plurality of anode electrodes, and a charge functional layer commonly formed for each of the organic light-emitting layers across a plurality of aperture areas formed in the bank. A distance from the center of the display region to the end of the cathode electrode is shorter than a distance from the center of the display region to the end of the charge functional layer. | 2014-10-09 |
20140299868 | Compound, Device and Method of Making Same - An organic light-emitting device comprises an anode, a cathode and a light-emitting layer between the anode and the cathode. The light-emitting layer comprises a compound of formula (I): | 2014-10-09 |
20140299869 | Organic Electronic Device And Method Of Manufacture - A method of forming an organic electronic device comprising the steps of: forming a surface modification layer comprising a partially fluorinated fullerene on at least part of a surface of at least one electrode of the device by depositing a solution comprising the partially fluorinated fullerene and at least one solvent onto the electrode surface; and forming an organic semiconductor layer comprising at least one organic semiconductor on the surface modification layer. The partially fluorinated fullerene is a partially fluorinated Buckminster fullerene, optionally a partially fluorinated C | 2014-10-09 |
20140299870 | ORGANIC TRANSISTOR AND METHOD FOR MANUFACTURING SAME - A method for manufacturing an organic transistor includes laminating a base insulating layer on a substrate; forming source/drain electrodes on the base insulating layer; laminating an organic semiconductor layer to cover the electrodes and be in contact with the base insulating layer; laminating a gate insulating layer on the organic semiconductor layer; forming a gate electrode on the gate insulating layer; and performing, before the organic semiconductor layer is formed, surface treatment on the surface of the base insulating layer which is in contact with the organic semiconductor layer. The surface treatment is performed such that, when W1 represents the work of adhesion between two laminated layers using the same material of the organic semiconductor layer, the work of adhesion W2 between the base insulating layer and the organic semiconductor layer when the organic semiconductor layer is formed on the surface-treated base insulating layer satisfies the relationship W1≧W2. | 2014-10-09 |
20140299871 | ORGANIC FIELD EFFECT TRANSISTOR - The present invention provides an electronic component or device comprising a gate electrode, a source electrode and a drain electrode, wherein said component or device further comprising an organic semiconducting (OSC) material that is provided between the source and drain electrode, wherein the OSC material comprises (a) a polymer represented by formula: (I), and (b) a compound of formula (II). High quality OFETs can be fabricated by the choice of a semiconductor material, which is comprised of a polymer represented by formula I and (b) a compound of formula II. | 2014-10-09 |
20140299872 | HETEROGENEOUS INTERGRATION OF GROUP III-V OR II-VI MATERIALS WITH SILICON OR GERMANIUM - Substrates for an electronic circuit and device manufacturing methods are disclosed. According to an embodiment, the substrate comprises: a silicon or germanium wafer impregnated with impurities that form one or more deep energy levels within the band gap of the material forming the wafer, wherein at least one of said deep energy levels is positioned at least 0.3 eV away from the conduction band if the level is a donor level or at least 0.3 eV away from the valence band if the level is an acceptor level; and a device layer formed on a surface of said wafer, said device layer comprising electronically functional components formed in a layer of Periodic Table Group III-V or II-VI material. The wafer may be formed from Cz silicon or Cz germanium, for example. | 2014-10-09 |
20140299873 | SINGLE-CRYSTAL OXIDE SEMICONDUCTOR, THIN FILM, OXIDE STACK, AND FORMATION METHOD THEREOF - To provide a metal oxide film including a single-crystal region. An oxide semiconductor film including indium and zinc is formed by a sputtering method by using a c-axis-aligned polycrystalline sputtering target at a substrate temperature of 200° C. or higher and 500° C. or lower. In this case, the oxide semiconductor film is formed over a c-axis-aligned zinc oxide film with a thickness of 0.1 nm or more and 5 nm or less. Consequently, it is possible to form an island-shaped single crystal with an average thickness of 0.5 μm or less, preferably 5 nm or more and 0.1 μm or less and an area of 5 μm | 2014-10-09 |
20140299874 | Semiconductor Device - To provide a semiconductor device including, over the same substrate, a transistor and a resistor each including an oxide semiconductor. A semiconductor device includes a resistor having a first oxide semiconductor layer covered with a nitride insulating layer containing hydrogen and a transistor having a second oxide semiconductor layer which is covered with an oxide insulating layer, has the same composition as the first oxide semiconductor layer, and has a different carrier density from the first oxide semiconductor layer. The first oxide semiconductor layer has higher carrier density than the second oxide semiconductor layer by treatment for increasing an impurity concentration. The treatment is performed on an entire surface of the first oxide semiconductor layer processed into an island shape. Therefore, in the first oxide semiconductor layer, regions contacting the nitride insulating layer and regions contacting electrode layers in contact holes of the nitride insulating layer have the same conductivity. | 2014-10-09 |
20140299875 | DISPLAY DEVICE AND DRIVING METHOD OF THE SAME - A first capacitor obtains a gate-source voltage of a first transistor in accordance with a programming current flowing through the first transistor, and a second capacitor obtains a threshold voltage of a second transistor. Then, the electric charges held in the first capacitor and the second capacitor are capacitively coupled. By using the voltage obtained with the capacitively coupling as a gate-source voltage of the first transistor, constant current in accordance with the programming current can be supplied to a light emitting element. | 2014-10-09 |
20140299876 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device which is miniaturized and has sufficient electrical characteristics to function as a transistor is provided. In a semiconductor device including a transistor in which a semiconductor layer, a gate insulating layer, and a gate electrode layer are stacked in that order, an oxide semiconductor film which contains at least four kinds of elements of indium, gallium, zinc, and oxygen, and in which the percentage of the indium is twice or more as large as each of the percentage of the gallium and the percentage of the zinc when the composition of the four elements is expressed in atomic percentage is used as the semiconductor layer. In the semiconductor device, the oxide semiconductor film is a film to which oxygen is introduced in the manufacturing process and contains a large amount of oxygen, and an insulating layer including an aluminum oxide film is provided to cover the transistor. | 2014-10-09 |
20140299877 | COATING LIQUID FOR FORMING METAL OXIDE THIN FILM, METAL OXIDE THIN FILM, FIELD-EFFECT TRANSISTOR, AND METHOD FOR MANUFACTURING FIELD-EFFECT TRANSISTOR - A coating liquid for forming a metal oxide thin film includes: an inorganic indium compound; an inorganic calcium compound or an inorganic strontium compound, or both thereof; and an organic solvent. | 2014-10-09 |
20140299878 | SEMICONDUCTOR DEVICE AND STACKED SEMICONDUCTOR DEVICE - A semiconductor device includes a package substrate, and a stack of semiconductor chips over the package substrate, each of the semiconductor chips including first and second surfaces, each of the semiconductor chips including a first through electrode that extends through each of the semiconductor chips, a first surface electrode positioned on the first surface of each of the semiconductor chips, the first surface electrode being coupled to a first end of the first through electrode, a second surface electrode positioned on the second surface of each of the semiconductor chips, the second surface electrode being coupled to a second end of the first through electrode, a second through electrode that extends through each of the semiconductor chips, the second through electrode having third and fourth ends, and a third surface electrode positioned on the second surface of the first semiconductor chip. | 2014-10-09 |
20140299879 | SEMICONDUCTOR DEVICE - A semiconductor device is provided, which includes a display portion and a driver circuit portion configured to drive the display portion. The display portion includes a first pixel electrode, a second pixel electrode, a plurality of photo sensors between the first pixel electrode and the second pixel electrode, and a plurality of color filters. The driver circuit portion includes a transistor including a single crystal semiconductor layer. | 2014-10-09 |
20140299880 | LAYER FORMATION WITH REDUCED CHANNEL LOSS - Insulating layers can be formed over a semiconductor device region and etched in a manner that substantially reduces or prevents the amount of etching of the underlying channel region. A first insulating layer can be formed over a gate region and a semiconductor device region. A second insulating layer can be formed over the first insulating layer. A third insulating layer can be formed over the second insulating layer. A portion of the third insulating layer can be etched using a first etching process. A portion of the first and second insulating layers beneath the etched portion of the third insulating layer can be etched using at least a second etching process different from the first etching process. | 2014-10-09 |
20140299881 | TFT ARRAY SUBSTRATE AND METHOD FOR PRODUCING THE SAME - A TFT array substrate has an organic insulating film formed of a photosensitive organic resin material. A common electrode and a lead-out wiring are formed on the organic insulating film, and a pixel electrode is formed above the common electrode with an interlayer insulating film provided between them. The pixel electrode is connected to the lead-out wiring through a contact hole formed in the interlayer insulating film. The lead-out wiring and the common electrode are connected to a drain electrode and a common wiring, respectively, through contact holes formed in the organic insulating film. A metal cap film is provided on each of the lead-out wiring and the common electrode in the contact holes formed in the organic insulating film. | 2014-10-09 |
20140299882 | INTEGRATED FIN AND STRAP STRUCTURE FOR AN ACCESS TRANSISTOR OF A TRENCH CAPACITOR - At least one dielectric pad layer is formed on a semiconductor-on-insulator (SOI) substrate. A deep trench is formed in the SOI substrate, and a combination of an outer electrode, a node dielectric, and an inner electrode are formed such that the top surface of the inner electrode is recessed below the top surface of a buried insulator layer of the SOI substrate. Selective epitaxy is performed to fill a cavity overlying the inner electrode with an epitaxial semiconductor material portion. A top semiconductor material layer and the epitaxial semiconductor material portion are patterned to form a fin structure including a portion of the top semiconductor material layer and a portion of the epitaxial semiconductor material portion. The epitaxial semiconductor material portion functions as a conductive strap structure between the inner electrode and a semiconductor device to be formed on the fin structure. | 2014-10-09 |
20140299883 | PRINTED, SELF-ALIGNED, TOP GATE THIN FILM TRANSISTOR - A self-aligned top-gate thin film transistor (TFT) and a method of forming such a thin film transistor, by forming a semiconductor thin film layer; printing a doped glass pattern thereon, a gap in the doped glass pattern defining a channel region of the TFT; forming a gate electrode on or over the channel region, the gate electrode comprising a gate dielectric film and a gate conductor thereon; and diffusing a dopant from the doped glass pattern into the semiconductor thin film layer. | 2014-10-09 |
20140299884 | Flexible Display With Bent Edge Regions - An electronic device may have a flexible display with portions that are bent along a bend axis. The display may have display circuitry such as an array of display pixels in an active area. Contact pads may be formed in an inactive area of the display. Signal lines may couple the display pixels to the contact pads. The signal lines may overlap the bend axis in the inactive area of the display. During fabrication, an etch stop may be formed on the display that overlaps the bend axis. The etch stop may prevent over etching of dielectric such as a buffer layer on a polymer flexible display substrate. A layer of polymer that serves as a neutral stress plane adjustment layer may be formed over the signal lines in the inactive area of the display. Upon bending, the neutral stress plane adjustment layer helps prevent stress in the signal lines. | 2014-10-09 |
20140299885 | SUBSTRATE STRUCTURES AND SEMICONDUCTOR DEVICES EMPLOYING THE SAME - A substrate structure includes a substrate, a nucleation layer on the substrate and including a group III-V compound semiconductor material having a lattice constant that is different from that of the substrate by less than 1%, and a buffer layer on the nucleation layer and including first and second layers, wherein the first and second layers include group III-V compound semiconductor materials having lattice constants that are greater than that of the nucleation layer by 4% or more. | 2014-10-09 |
20140299886 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A silicon carbide semiconductor device includes: a semiconductor substrate made of silicon carbide single crystal and having a principal surface and a backside; and an ohmic electrode contacting one of the principal surface and the backside of the semiconductor substrate in an ohmic manner. A boundary between the ohmic electrode and the one of the principal surface and the backside of the semiconductor substrate is terminated with an element, which has a Pauling electronegativity larger than silicon and a binding energy with silicon larger than a binding energy of Si—H. | 2014-10-09 |
20140299887 | SEMICONDUCTOR DEVICES COMPRISING GETTER LAYERS AND METHODS OF MAKING AND USING THE SAME - Semiconductor devices comprising a getter material are described. The getter material can be located in or over the active region of the device and/or in or over a termination region of the device. The getter material can be a conductive or an insulating material. The getter material can be present as a continuous or discontinuous film. The device can be a SiC semiconductor device such as a SiC vertical MOSFET. Methods of making the devices are also described. | 2014-10-09 |
20140299888 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A SiC semiconductor device capable of increasing a switching speed without destroying a gate insulating film. In addition, in a SiC-MOSFET including an n-type semiconductor substrate formed of SiC, a p-type semiconductor layer is entirely or partially provided on an upper surface of a p-type well layer that has a largest area of the transverse plane among a plurality of p-type well layers provided in an n-type drift layer and is arranged on an outermost periphery immediately below a gate electrode pad. It is preferable that a concentration of an impurity contained in the p-type semiconductor layer be larger than that of the p-type well layer. | 2014-10-09 |
20140299889 | SEMICONDUCTOR DEVICES - A semiconductor device includes a first gate structure on a first region of a substrate and a second gate structure on a second region of the substrate, a first impurity region on an upper portion of the substrate adjacent to the first gate structure and a second impurity region on an upper portion of the substrate adjacent to the second gate structure, a first metal silicide layer on the first impurity region, a Fermi level pinning layer on the second impurity region, a second metal silicide layer on the Fermi level pinning layer, and a first contact plug on the first metal silicide layer and a second contact plug on the second metal silicide layer. The Fermi level pinning layer pins a Fermi level of the second metal silicide layer to a given energy level. | 2014-10-09 |
20140299890 | SEMICONDUCTOR DEVICES COMPRISING GETTER LAYERS AND METHODS OF MAKING AND USING THE SAME - Semiconductor devices comprising a getter material are described. The getter material can be located in or over the active region of the device and/or in or over a termination region of the device. The getter material can be a conductive or an insulating material. The getter material can be present as a continuous or discontinuous film. The device can be a SiC semiconductor device such as a SiC vertical MOSFET. Methods of making the devices are also described. | 2014-10-09 |
20140299891 | SEMICONDUCTOR DEVICE - A semiconductor device that can improve reliability while suppressing increase of a conduction loss or a switching loss. In the semiconductor device, when a two-dimensional shape on a main surface of the semiconductor substrate is an unit cell, the shape being a repeating unit of a plurality of well regions periodically disposed in a surface layer of a drift layer, one unit cell and another unit cell adjacent in an x-axis direction are disposed misaligned in a y-axis direction, and one unit cell and another unit cell adjacent in the y-axis direction are disposed misaligned in the x-axis direction. | 2014-10-09 |
20140299892 | OPTOELECTRONIC SEMICONDUCTOR STRUCTURE AND METHOD FOR TRANSPORTING CHARGE CARRIERS - An optoelectronic semiconductor structure ( | 2014-10-09 |
20140299893 | Conductive Connector For Use With Circuit Board, and LED Module Having the Same - A conductive connector for use with circuit boards is characterized in that a conductive connection plug and a conductive connection socket are disposed on two circuit boards, respectively. The conductive connection plug has an inserting portion protruding from the edge of the first circuit board. The conductive connection socket has a clamping portion for clamping and securing the inserting portion of the conductive connection plug. The conductive connection plug is plugged into the conductive connection socket to enable the two circuit boards to be put together easily and quickly and reduce required space. An LED module is characterized in that the conductive connector connects circuit boards each having at least one LED component to enable the circuit boards to be put together easily and quickly, taken apart easily, and changed easily. | 2014-10-09 |
20140299894 | LIGHT EMITTING DIODE PACKAGE - A light emitting diode (LED) package including a substrate unit, a light emitting unit and an encapsulant. The substrate unit includes a metal substrate and a circuit board. The metal substrate has a first carrier portion and a second carrier portion. The second carrier portion is projected from the first carrier portion. The first carrier portion has a first carrier face. The second carrier portion has a second carrier face located higher than the first carrier face. The circuit board is disposed on the first carrier face, and the second carrier portion passes through the circuit board. The light emitting unit includes at least one LED chip disposed on the second carrier face of the second carrier portion, and the LED chip electrically connected to the circuit board. The encapsulant encapsulates the LED chip. | 2014-10-09 |
20140299895 | LIGHT EMITTING DEVICE WITH PHOSPHOR WAVELENGTH CONVERSION - A light emitting device comprises a substantially planar light transmissive substrate having a light emitting surface and an opposite surface. The substrate is configured as a light guiding medium. The light emitting device also comprises at least one phosphor material disposed as a layer on the light emitting surface with a plurality of window areas and at least one source of excitation radiation of a first wavelength positioned adjacent to at least one peripheral edge of the substrate. The source is configured to couple excitation radiation into the substrate such that it is waveguided within the substrate by total internal reflection. Additionally, the light emitted by the device from the light emitting surface comprises first wavelength radiation and second, longer wavelength photoluminescent light emitted by the phosphor layer as a result of excitation by the source. | 2014-10-09 |
20140299896 | SURFACE-TEXTURED ENCAPSULATIONS FOR USE WITH LIGHT EMITTING DIODES - Surface-textured encapsulations for use with light emitting diodes. In an aspect, a light emitting diode (LED) array apparatus includes a plurality of LEDs mounted to a substrate and an encapsulation covering the LEDs and having a surface texturing configured to extract light, wherein the surface texturing is includes at least one light extracting feature having a diameter larger than two or more of the LEDs. | 2014-10-09 |
20140299897 | High Efficient and High Power LED Light Source,LED Lamp Which Uses Light Source and the Application of the Lamp - A light module includes a plurality of LEDs coupled on a circuit board, a condenser unit including a plurality of condensers integrally coupled with each other and supported on the circuit board, and a plurality of converging lenses supported within the light cavities of said condensers respectively. Each LED is located at a focal point of the condenser and is located at a focal point of the converging lens. A first portion of light from the LED is directly project toward the converging lens and is diverged by the converging lens to parallelly project out of the condenser. A second portion of light from the LED is reflected by a light reflecting wall of the condenser to parallelly project out of the condenser. Therefore, the first and second portions of light form collimated light beams out of a light opening of the condenser. | 2014-10-09 |
20140299898 | LIGHT EMITTING DEVICE MODULE AND METHOD OF MANUFACTURING THE SAME - A light emitting device (LED) module, and manufacturing method of the same, which may be applied to various applications is provided. The LED module may be miniaturized by directly mounting an LED and a lens unit on a substrate, and price competitiveness may be enhanced by lowering a fraction defective and increasing yield of the LED module. In a method of manufacturing an LED module, an operation may be minimized and simplified by directly mounting LEDs and a plurality of lens units having various shapes, collectively forming the plurality of lens units, and by performing the operation on a wafer level. A heat radiation characteristic may be enhanced through use of a metallic material as a substrate and a bump. | 2014-10-09 |
20140299899 | DISPLAY DEVICE, ELECTRONIC APPARATUS, AND METHOD OF FABRICATING THE DISPLAY DEVICE - It is an object of the invention to provide a technique to manufacture a display device with high image quality and high reliability at low cost with high yield. The invention has spacers over a pixel electrode layer in a pixel region and over an insulating layer functioning as a partition which covers the periphery of the pixel electrode layer. When forming a light emitting material over a pixel electrode layer, a mask for selective formation is supported by the spacers, thereby preventing the mask from contacting the pixel electrode layer due to a twist and deflection thereof. Accordingly, such damage as a crack by the mask does not occur in the pixel electrode layer. Thus, the pixel electrode layer does not have a defect in shapes, thereby a display device which performs a high resolution display with high reliability can be manufactured. | 2014-10-09 |
20140299900 | INTERDIGITATED MULTIPLE PIXEL ARRAYS OF LIGHT-EMITTING DEVICES - The present invention discloses a plurality of interdigitated pixels arranged in an array, having a very low series-resistances with improved current spreading and improved heat-sinking Each pixel is a square with sides of dimension 1. The series resistance is minimized by increasing the perimeter of an active region for the pixels. The series resistance is also minimized by shrinking the space between a mesa and n-contact for each pixel. | 2014-10-09 |
20140299901 | LIGHT EMITTING DIODE AND MANUFACTURING METHOD THEREOF - A light-emitting diode, comprising: a substrate, the substrate comprising an upper surface, a bottom surface opposite to the upper surface, and a side surface; a first type semiconductor layer on the upper surface, wherein the first type semiconductor layer comprises a first portion and a second portion, and the second portion comprises an edge surrounding the first portion; a light-emitting layer on the first portion; and a second type semiconductor layer on the light-emitting layer, wherein the second portion comprising a first surface and a second surface, and a first distance is between the first surface and the upper surface, and a second distance is between the second surface and the upper surface and is smaller than the first distance; wherein the first surface is rougher than the second surface, and the second surface is located at the edge. | 2014-10-09 |
20140299902 | Articles and methods for rapid manufacturing of solid state light sources - Rapid manufacturing processes and designs based on solid luminescent elements form solid state light sources. Direct attach, as well as other LED types, are embedded or affixed to the solid luminescent elements to form low cost solid state light sources. | 2014-10-09 |
20140299903 | DOUBLE-CHIP LIGHT EMITTING DIODE - Disclosed is a double-chip LED including a leadframe, a green chip, a blue chip, a transparent colloid and a red fluorescent layer. The green chip is installed at the bottom of the leadframe; the blue chip is installed at the bottom of the leadframe and adjacent to the green chip; the transparent colloid is sprayed or coated onto the green chip and the blue chip; and the red fluorescent layer is disposed on the transparent colloid and excited by a green light source or a blue light source to produce a mixed light source. The red fluorescent layer can be a red fluorescent plate or red fluorescent powder. In the present double-chip LED, the green chip and the blue chip excite the red fluorescent plate or red fluorescent powder to produce a better white light mixing effect. | 2014-10-09 |
20140299904 | LIGHT EMITTING DEVICE - A light emitting device according to embodiments includes a light emitting element emitting light having a peak wavelength of 425 nm or more and 465 nm or less, a first phosphor emitting light having a peak wavelength of 485 nm or more and 530 nm or less, a second phosphor emitting light having a peak wavelength longer than that of the first phosphor, and a third phosphor emitting light having a peak wavelength longer than that of the second phosphor. Then, when the peak wavelength of the light emitting element is λ | 2014-10-09 |
20140299905 | LIGHT EMITTING DIODE WITH IMPROVED LUMINOUS EFFICIENCY - A light-emitting diode includes a substrate, and a light-emitting structure disposed on the substrate. The light-emitting structure includes a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer. A transparent electrode layer including concave portions and convex portions is disposed on the second conductivity-type semiconductor layer. Micro-lenses are disposed on the transparent electrode layer and completely cover the concave portions, and only partially cover the convex portions that are disposed between the micro-lenses. | 2014-10-09 |
20140299906 | LIGHT EMITTING DIODE, MANUFACTURING METHOD THEREOF, LIGHT EMITTING DIODE MODULE, AND MANUFACTURING METHOD THEREOF - A manufacturing method of a light emitting diode (LED) and a manufacturing method of an LED module are provided. The manufacturing method of the LED may include manufacturing a plurality of LED chips, manufacturing a phosphor pre-form including a plurality of mounting areas for mounting the plurality of LED chips, applying an adhesive inside the phosphor pre-form, mounting each of the plurality of LED chips in each of the plurality of mounting areas, and cutting the phosphor pre-form to which the plurality of LED chips are mounted, into units including individual LED chips. | 2014-10-09 |
20140299907 | Reflector for Light-Emitting Devices - Polymer compositions are described that are well suited for producing reflectors for light-emitting devices, such as light-emitting diodes. In one embodiment, the polymer composition contains a polymer resin and a stabilizer comprising a phosphonate compound and/or a phosphate compound and optionally a white pigment. The polymer resin may comprise, for instance, a poly(1,4-cyclohexanedimethanol terephthalate). The phosphate stabilizer has been found to significantly improve the stability of the polymer composition without interfering with the ability of the composition to bond to other polymer materials, such as silicone resins. Silicone resins, for instance, are typically used as an encapsulant for light-emitting diode assemblies. | 2014-10-09 |
20140299908 | LIGHT EMITTING DIODE PACKAGE AND METHOD OF FABRICATING THE SAME - A light emitting diode package and a method of fabricating the same. The package includes a light emitting diode chip having a first surface and a second surface opposing the first surface, a metal frame (or TAB tape) having leads connected to the light emitting diode chip, and a light-pervious encapsulant encapsulating the light emitting diode chip, wherein the second surface of the chip is exposed from the first light-pervious encapsulant. The metal frame (or TAB tape) connects the light emitting diode chip to an external circuit board. The LED package does not need wire-bonding process. A method of fabricating a light emitting diode package is also provided. | 2014-10-09 |
20140299909 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD OF FORMING THE SAME - A semiconductor light-emitting device has a first principal surface, a second principal surface formed on a side opposite to the first principal surface, and a light-emitting layer. A p-electrode on the second principal surface is in the region of the light-emitting layer and surrounds an n-electrode. An insulating layer on the side of the semiconductor layer surrounds the p-and the n-electrodes. A p-metal pillar creates an electrical connection for the p-electrode, and an n-metal pillar creates an electrical connection for the n-electrode. A resin layer surrounds the end portions of the p-and the n-metal pillars, and also covers the side surface of the semiconductor layer, the second principal surface, the p-electrode, the n-electrode, the insulating layer, the p-metal pillar and the n-metal pillar. | 2014-10-09 |
20140299910 | LIGHT EMITTING DIODE PACKAGE AND LIGHT EMITTING MODULE COMPRISING THE SAME - The present invention provides a light emitting diode package including a light emitting diode chip, a lead frame having a chip area on which the light emitting diode chip is disposed, and a package body having a cavity and supporting the lead frame. The chip area is exposed through the cavity. The lead frame includes a first terminal group disposed at a first side of the chip area and a second terminal group disposed at a second side of the chip area. The first terminal group and the second terminal group each include a first terminal connected to the chip area and a second terminal separated from the chip area. The second terminal of the first terminal group is exposed through the cavity, and the second terminal of the second terminal group is buried in the package body. | 2014-10-09 |
20140299911 | Method for Producing Optoelectronic Semiconductor Components, Lead Frame Composite, and Optoelectronic Semiconductor Component - A method for producing a packaged component is disclosed. In one embodiment, a lead frame composite has first lead frame parts, second lead frame parts and test contacts, electrically connecting via first electrical connections the first lead frame parts to the other first lead frame parts. A potting body is formed on the lead frame composite thereby mechanically connecting the first lead frame parts to the second lead frame parts and encapsulating the first electrical connections. First semiconductor components are placed on the first lead frame parts after forming the potting body. The first semiconductor components are electrically connected to the second lead frame parts via second electrical connections. The first semiconductor components are electrically tested at the test contacts prior to singulating the lead frame composite and the potting body. The lead frame composite and the potting body are singulated thereby forming the packaged semiconductor components. | 2014-10-09 |
20140299912 | SILICON-CONTROLLED-RECTIFIER WITH ADJUSTABLE HOLDING VOLTAGE - In a silicon-controlled-rectifier (SCR) with adjustable holding voltage, an epitaxial layer is formed on a heavily doped semiconductor layer. A first N-well having a first P-heavily doped area is formed in the epitaxial layer. A first P-well is formed in the epitaxial layer. Besides, a first N-heavily doped area is formed in the first P-well. At least one deep isolation trench is formed in the epitaxial layer, having a depth greater than the depth of the first N-type well and located between the first P-heavily doped area and the first N-heavily doped area. A distance between the deep isolation trench and the heavily doped semiconductor layer is larger than zero. | 2014-10-09 |
20140299913 | INTEGRATED CIRCUITS USING GUARD RINGS FOR ESD SYSTEMS, AND METHODS FOR FORMING THE INTEGRATED CIRCUITS - An integrated circuit includes at least one transistor over a substrate, and a first guard ring disposed around the at least one transistor. The integrated circuit further includes a second guard ring disposed around the first guard ring. The integrated circuit further includes a first doped region disposed adjacent to the first guard ring, the first doped region having a first dopant type. The integrated circuit further includes a second doped region disposed adjacent to the second guard ring, the second doped region having a second dopant type. | 2014-10-09 |
20140299914 | NANOTUBE SEMICONDUCTOR DEVICES - Semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In one embodiment, a semiconductor device is formed in a second semiconductor layer disposed on a first semiconductor layer of opposite conductivity type and having trenches formed therein where the trenches extend from the top surface to the bottom surface of the second semiconductor layer. The semiconductor device includes a first epitaxial layer formed on sidewalls of the trenches where the first epitaxial layer is substantially charge balanced with adjacent semiconductor regions. The semiconductor device further includes a first dielectric layer formed in the trenches adjacent the first epitaxial layer and a gate electrode disposed in an upper portion of at least some of the trenches above the first dielectric layer and insulated from the sidewalls of the trenches by a gate dielectric layer. | 2014-10-09 |
20140299915 | SEMICONDUCTOR DEVICE - In a semiconductor device having a vertical semiconductor element configured to pass an electric current between an upper electrode and a lower electrode, a field stop layer includes a phosphorus/arsenic layer doped with phosphorus or arsenic and a proton layer doped with proton. The phosphorus/arsenic layer is formed from a back side of a semiconductor substrate to a predetermined depth. The proton layer is deeper than the phosphorus/arsenic layer. An impurity concentration of the proton layer peaks inside the phosphorus/arsenic layer and gradually, continuously decreases at a depth greater than the phosphorus/arsenic layer. | 2014-10-09 |
20140299916 | MONOLITHIC CELL FOR AN INTEGRATED CIRCUIT AND ESPECIALLY A MONOLITHIC SWITCHING CELL - A cell includes at least two semiconductor structures of the same nature, these two structures both employing voltages and currents that are unidirectional, each structure having an anode ( | 2014-10-09 |
20140299917 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first conductive type semiconductor substrate, a second conductive type active region formed on a top surface side of the semiconductor substrate, a second conductive type inside VLD region formed to contact the active region on the top surface side in a plan view, and a second conductive type well region formed to contact a portion opposite to the portion contacting the active region of the inside VLD region on the top surface side in a plan view. The well region is formed to be deeper than the active region. The inside VLD region has the same depth as that of the active region in the portion contacting the active region, the depth gradually increasing from the active region toward the well region and becoming the same as the depth of the well region in the portion contacting the well region. | 2014-10-09 |
20140299918 | SEMICONDUCTOR SUBSTRATE AND FABRICATION METHOD THEREOF, AND SEMICONDUCTOR APPARATUS USING THE SAME AND FABRICATION METHOD THEREOF - A semiconductor substrate and a fabrication method thereof, and a semiconductor apparatus using the same and a fabrication method thereof are provided. The semiconductor substrate includes a semiconductor wafer, a silicon germanium (SiGe)-based impurity doping region formed on the semiconductor wafer, and a protection layer formed on the SiGe-based impurity doping region. | 2014-10-09 |
20140299919 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are provided. In one embodiment, the method comprises: growing a first epitaxial layer on a substrate; forming a sacrificial gate stack on the first epitaxial layer; selectively etching the first epitaxial layer; growing and in-situ doping a second epitaxial layer on the substrate; forming a spacer on opposite sides of the sacrificial gate stack; and forming source/drain regions with the spacer as a mask. | 2014-10-09 |
20140299920 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - The present disclosure provides a layout of a semiconductor integrated circuit device that can assure a lot of substrate contact regions, and can surely suppress latch-up without increasing an area of a whole semiconductor integrated circuit and without significantly decreasing a decoupling capacitance element. In a margin region, a transistor serving as a decoupling capacitance and a substrate contact are disposed as a pair on a P-type well. In the margin region, a transistor serving as a decoupling capacitance and a substrate contact are disposed as a pair on an N | 2014-10-09 |
20140299921 | SOLID-STATE IMAGING DEVICE WITH CHANNEL STOP REGION WITH MULTIPLE IMPURITY REGIONS IN DEPTH DIRECTION AND METHOD FOR MANUFACTURING THE SAME - Channel stop sections formed by multiple times of impurity ion implanting processes. Four-layer impurity regions are formed across the depth of a semiconductor substrate (across the depth of the bulk), so that a P-type impurity region is formed deep in the semiconductor substrate; thus, incorrect movement of electric charges is prevented. Other four-layer impurity regions of another channel stop section are decreased in width step by step across the depth of the substrate, so that the reduction of a charge storage region of a light receiving section due to the dispersion of P-type impurity in the channel stop section is prevented in the depth of the substrate. | 2014-10-09 |
20140299922 | HIGH-K METAL GATE DEVICE STRUCTURE FOR HUMAN BLOOD GAS SENSING - A device structure for detecting partial pressure of oxygen in blood includes a semiconductor substrate including a source region and a drain region. A multi-layer gate structure is formed on the semiconductor substrate. The multi-layer gate structure includes an oxide layer formed over the semiconductor substrate, a high-k layer formed over the oxide layer, a metal gate layer formed over the high-k layer, and a polysilicon layer formed over the metal gate layer. A receiving area holds a blood sample in contact with the multi-layer gate structure. The high-k layer is exposed to contact the blood sample in the receiving area. | 2014-10-09 |
20140299923 | FIELD EFFECT TRANSISTOR - A field effect transistor includes a semiconductor substrate having a protrusion with at least one inclined surface, a gate insulator disposed at least on a portion of the inclined surface, and a gate conductor disposed on the gate insulator, wherein the semiconductor substrate comprises doped regions sandwiching a channel region, wherein the at least one inclined surface has a first crystal orientation in the channel region, and the inclined surface has an included angle to a vertical plane with a second crystal orientation. The hole mobility and the electron mobility are substantially the same in the channel region having a crystalline orientation off from the (110) crystal orientation. | 2014-10-09 |
20140299924 | FORMATION OF THE DIELECTRIC CAP LAYER FOR A REPLACEMENT GATE STRUCTURE - Gate to contact shorts are reduced by forming dielectric caps in replaced gate structures. Embodiments include forming a replaced gate structure on a substrate, the replaced gate structure including an ILD having a cavity, a first metal on a top surface of the ILD and lining the cavity, and a second metal on the first metal and filling the cavity, planarizing the first and second metals, forming an oxide on the second metal, removing the oxide, recessing the first and second metals in the cavity, forming a recess, and filling the recess with a dielectric material. Embodiments further include dielectric caps having vertical sidewalls, a trapezoidal shape, a T-shape, or a Y-shape. | 2014-10-09 |
20140299925 | CMOS IMAGE SENSOR WITH RESET SHIELD LINE - Techniques and mechanisms to improve potential well characteristics in a pixel cell. In an embodiment, a coupling portion of a pixel cell couples a reset transistor of the pixel cell to a floating diffusion node of the pixel cell, the reset transistor to reset a voltage of the floating diffusion node. In another embodiment, the pixel cell includes a shield line which extends athwart the coupling portion, where the shield line is to reduce a parasitic capacitance of the reset transistor to the floating diffusion node. | 2014-10-09 |
20140299926 | Semiconductor Device and Method for Manufacturing the Same - A method for manufacturing a semiconductor device comprises forming a first layer on an impurity diffusion region in a semiconductor substrate by a selective epitaxial growth method, forming a second layer on the first layer by the selective epitaxial growth method, forming a contact hole penetrating an interlayer insulating film in a thickness direction thereof and reaching the second layer, and filling a conductive material into the contact hole to form a contact plug including the first and second layers and the conductive material. | 2014-10-09 |
20140299927 | Digital Circuit Having Correcting Circuit and Electronic Apparatus Thereof - Provided is a digital circuit ( | 2014-10-09 |
20140299928 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device may include, but is not limited to, a semiconductor substrate having a first gate groove; a first fin structure underneath the first gate groove; a first diffusion region in the semiconductor substrate, the first diffusion region covering an upper portion of a first side of the first gate groove; and a second diffusion region in the semiconductor substrate. The second diffusion region covers a second side of the first gate groove. The second diffusion region has a bottom which is deeper than a top of the first fin structure. | 2014-10-09 |
20140299929 | DRAM CELL BASED ON CONDUCTIVE NANOCHANNEL PLATE - A capacitor is formed in nano channels in a conductive body. Embodiments include forming a source contact through a first inter layer dielectric (ILD), forming a conductive body on the first ILD, forming a second ILD on the conductive body, forming drain and gate contacts through the second ILD, conductive body, and first ILD, forming nano channels in the conductive body, forming an insulating layer in the channels, and metalizing the channels. An embodiment includes forming the nano channels by forming a mask on the second ILD, the mask having features with a pitch of 50 nanometers (nm) to 100 nm, etching the second ILD through the mask, etching the conductive body through the mask to a depth of 80% to 90% of the thickness of the conductive body, and removing the mask. | 2014-10-09 |
20140299930 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes a gate structure including a select gate formed over a substrate and a memory gate formed on one sidewall of the select gate and having a P-type channel, a drain region formed in the substrate at one sidewall of the gate structure and overlapping a part of the memory gate, and a source region formed in the substrate at the other sidewall of the gate structure and overlapping a part of the select gate. The memory gates include a grid of rows and columns with bits of 1's and 0's selectively forming a memory in a nonvolatile memory device. | 2014-10-09 |
20140299931 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a substrate comprising a first word line formation area, a second word line formation area, and a support area interposed between the first and second word line formation areas; a first stacked structure disposed over the substrate of each of the first and second word line formation areas and having a plurality of interlayer dielectric layers and a plurality of conductive layers that are alternately stacked therein; a second stacked structure disposed over the substrate of the support area and having the plurality of interlayer dielectric layers and a plurality of spaces that are alternately stacked therein; a channel layer disposed in the first stacked structure; and a memory layer interposed between the channel layer and each of the plurality of conductive layers. | 2014-10-09 |
20140299932 | Semiconductor Device Including a Gate Trench and a Source Trench - A semiconductor device includes a source trench extending into a semiconductor body from a first surface of the semiconductor body. A source trench dielectric and a source trench electrode are in the source trench. A gate trench dielectric and a gate trench electrode are in a gate trench extending into the semiconductor body from the first surface. A body region of a first conductivity type is between the gate and source trenches. A source region of a second conductivity type different from the first conductivity type is between the gate and source trenches. An interconnection electrically couples the body region and the source trench electrode. The interconnection adjoins a lateral face of the source trench electrode and the body region. A source contact is on the source trench electrode at the first surface. | 2014-10-09 |
20140299933 | Semiconductor Component Having a Semiconductor Body with a Cutout - A semiconductor component includes a semiconductor body having a surface and a cutout in the semiconductor body. The cutout extends from the surface of the semiconductor body into the semiconductor body in a direction perpendicular to the surface. The cutout has a base and at least one sidewall. The component further includes a layer on the surface of the semiconductor body and in the cutout. The layer forms a well above the cutout. The well has a well base, a well edge and at least one well sidewall. The at least one well sidewall forms an angle α in the range of 20° to 80° with respect to the surface of the semiconductor body. The layer has at least one edge which, proceeding from the well edge, extends in the direction of the surface of the semiconductor body. | 2014-10-09 |
20140299934 | Semiconductor Device and Method for Fabricating the Same - Provided is a semiconductor device. The semiconductor device includes a fin on a substrate; a gate electrode cross the fin on the substrate; a source/drain formed on at least one of both sides of the gate electrode, and including a first film and a second film; and a stress film arranged between an isolation film on the substrate and the source/drain, and formed on a side surface of the fin. | 2014-10-09 |
20140299935 | SHALLOW TRENCH ISOLATION FOR SOI STRUCTURES COMBINING SIDEWALL SPACER AND BOTTOM LINER - A method for making a semiconductor device is provided which includes (a) providing a layer stack comprising a semiconductor layer ( | 2014-10-09 |
20140299936 | INTEGRATED CIRCUIT DEVICES AND FABRICATION TECHNIQUES - Integrated circuit devices and fabrication techniques. A semiconductor device fabrication method may include doping, in a same processing step, first and second portions of a substrate of an integrated circuit. The first portion corresponds to a doped region of a semiconductor device. The second portion corresponds to a via contact. The method may further include, after the doping, forming the gate of the semiconductor device. | 2014-10-09 |
20140299937 | SPACER STRUCTURES OF A SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes forming a first set of gate electrodes over a substrate, adjacent gate electrodes of the first set of gate electrodes being separated by a first gap width. Each gate electrode of the first set of gate electrodes has a first gate width. The method further includes forming a second set of gate electrodes over the substrate, adjacent gate electrodes of the second set of gate electrodes being separated by a second gap width less than the first gap width. Each gate electrode of the second set of gate electrodes has a second gate width greater than the first gate width. | 2014-10-09 |
20140299938 | METHODS AND DEVICES FOR ENHANCING MOBILITY OF CHARGE CARRIERS - Methods and devices for enhancing mobility of charge carriers. An integrated circuit may include semiconductor devices of two types. The first type of device may include a metallic gate and a channel strained in a first manner. The second type of device may include a metallic gate and a channel strained in a second manner. The gates may include, collectively, three or fewer metallic materials. The gates may share a same metallic material. A method of forming the semiconductor devices on an integrated circuit may include depositing first and second metallic layers in first and second regions of the integrated circuit corresponding to the first and second gates, respectively. | 2014-10-09 |
20140299939 | Semiconductor Device - Provided are a semiconductor device and a fabricating method of the semiconductor device. The semiconductor device may include an interlayer dielectric film formed on a substrate and including a trench, a gate insulating film formed in the trench, a first work function control film formed on the gate insulating film of the trench along bottom and sidewalls of the trench, a first metal gate pattern formed on the first work function control film of the trench and filling a portion of the trench, and a second metal gate pattern formed on the first metal gate pattern of the trench, the second metal gate pattern different from the first metal gate pattern. | 2014-10-09 |
20140299940 | SEMICONDUCTOR ELECTRONIC COMPONENTS WITH INTEGRATED CURRENT LIMITERS - An electronic component includes a high-voltage depletion-mode transistor and a low-voltage enhancement-mode transistor. A source electrode of the high-voltage depletion-mode transistor is electrically connected to a drain electrode of the low-voltage enhancement-mode transistor, and a gate electrode of the high-voltage depletion-mode transistor is electrically coupled to the source electrode of the low-voltage enhancement-mode transistor. The on-resistance of the enhancement-mode transistor is less than the on-resistance of the depletion-mode transistor, and the maximum current level of the enhancement-mode transistor is smaller than the maximum current level of the depletion-mode transistor. | 2014-10-09 |
20140299941 | SRAM CELL WITH REDUCED VOLTAGE DROOP - A mesh circuit for the VSS supply voltage of a SRAM device is disclosed. Embodiments also provide a SRAM bitcell design comprising a VSS mesh disposed in two different metal layers. One metal layer includes horizontal VSS lines, while another metal layer includes vertical VSS lines. A via layer disposed between the first metal layer and second metal layer connects the two metal layers together. | 2014-10-09 |
20140299942 | SEMICONDUCTOR DEVICE HAVING FIN STRUCTURE AND METHOD OF MANUFACTURING THE SAME - In a semiconductor device, a thin wall oxide film formed over sidewalls of an active region is formed, and a portion of the wall oxide film adjacent to a gate region is removed. A gate insulating film is formed where the portion of wall oxide film was removed to prevent a parasitic transistorfrom being generated by the wall oxide film. | 2014-10-09 |
20140299943 | FinFET-Based ESD Devices and Methods for Forming the Same - A device includes a plurality of STI regions, a plurality of semiconductor strips between the STI regions and parallel to each other, and a plurality of semiconductor fins over the semiconductor strips. A gate stack is disposed over and crossing the plurality of semiconductor fins. A drain epitaxy semiconductor region is disposed on a side of the gate stack and connected to the plurality of semiconductor fins. The drain epitaxy semiconductor region includes a first portion adjoining the semiconductor fins, wherein the first portion forms a continuous region over and aligned to the plurality of semiconductor strips. The drain epitaxy semiconductor region further includes second portions farther away from the gate stack than the first portion. Each of the second portions is over and aligned to one of the semiconductor strips. The second portions are parallel to each other, and are separated from each other by a dielectric material. | 2014-10-09 |
20140299944 | GRAPHENE DEVICES AND METHODS OF FABRICATING THE SAME - A graphene device includes: a semiconductor substrate having a first region and a second region; a graphene layer on the first region, but not on the second region of the semiconductor substrate; a first electrode on a first portion of the graphene layer; a second electrode on a second portion of the graphene layer; an insulating layer between the graphene layer and the second electrode; and a third electrode on the second region of the semiconductor substrate. The semiconductor substrate has a tunable Schottky barrier formed by junction of the first electrode, the graphene layer, and the semiconductor substrate. | 2014-10-09 |
20140299945 | INTEGRATED CIRCUITS HAVING SOURCE/DRAIN STRUCTURE - An integrated circuit includes a gate structure over a substrate. A silicon-containing material structure is in each of recesses that are adjacent to the gate structure. The silicon-containing material structure has a first region and a second region, the second region is closer to the gate structure than the first region, and the first region is thicker than the second region. | 2014-10-09 |
20140299946 | SEMICONDUCTOR DEVICE - A semiconductor device concerning an embodiment is provided with a semiconductor layer, an impurity-doped layer selectively formed on the semiconductor layer, and a drain electrode formed on the impurity-doped layer. The semiconductor device is further provided with a source electrode which is formed and isolated from the drain electrode, and a gate electrode which is formed between the source electrode and the drain electrode. The semiconductor device is provided with an insulating film which is formed between the gate electrode and the drain electrode, and a shielding plate which is formed on the insulating film and is electrically connected to the source electrode. At least a part of the shielding plate is formed above an extending portion of the impurity-doped layer which extends in the direction to the gate electrode from the drain electrode. | 2014-10-09 |
20140299947 | INERTIAL ANGULAR SENSOR OF BALANCED MEMS TYPE AND METHOD FOR BALANCING SUCH A SENSOR - An inertial angular sensor of MEMS type has a support of at least two masses which are mounted movably with respect to the support, at least one electrostatic actuator and at least one electrostatic detector. The masses are suspended in a frame itself connected by suspension means to the support. The actuator and the detector are designed to respectively produce and detect a vibration of the masses, and a method for balancing such a sensor provided with at least one load detector mounted between the frame and the support and with at least one electrostatic spring placed between the frame and one of the masses and slaved so as to ensure dynamic balancing of the sensor as a function of a measurement signal of the load sensor. | 2014-10-09 |
20140299948 | SILICON BASED MEMS MICROPHONE, A SYSTEM AND A PACKAGE WITH THE SAME - The present invention relates to a silicon based MEMS microphone, comprising a silicon substrate and an acoustic sensing part supported on the silicon substrate, wherein a mesh-structured back hole is formed in the substrate and aligned with the acoustic sensing part, the mesh-structured back hole includes a plurality of mesh beams which are interconnected with each other and supported on the side wall of the mesh-structure back hole, the plurality of mesh beams and the side wall define a plurality of mesh holes which all have a tapered profile and merge into one hole in the vicinity of the acoustic sensing part at the top side of the silicon substrate. The mesh-structured back hole can help to streamline the air pressure pulse caused, for example, in a drop test and thus reduce the impact on the acoustic sensing part of the microphone, and also serve as a protection filter to prevent alien substances such as particles entering the microphone. | 2014-10-09 |
20140299949 | ASSEMBLY OF A CAPACITIVE ACOUSTIC TRANSDUCER OF THE MICROELECTROMECHANICAL TYPE AND PACKAGE THEREOF - A microelectromechanical-acoustic-transducer assembly has: a first die integrating a MEMS sensing structure having a membrane, which has a first surface in fluid communication with a front chamber and a second surface, opposite to the first surface, in fluid communication with a back chamber of the microelectromechanical acoustic transducer, is able to undergo deformation as a function of incident acoustic-pressure waves, and faces a rigid electrode so as to form a variable-capacitance capacitor; a second die, integrating an electronic reading circuit operatively coupled to the MEMS sensing structure and supplying an electrical output signal as a function of the capacitive variation; and a package, housing the first die and the second die and having a base substrate with external electrical contacts. The first and second dice are stacked in the package and directly connected together mechanically and electrically; the package delimits at least one of the front and back chambers. | 2014-10-09 |
20140299950 | ELECTRONIC DEVICES HAVING SEMICONDUCTOR MEMORY UNITS - Disclosed are electronic devices comprising a semiconductor memory unit capable of reducing the switching current of a variable resistance element for switching between different resistance states. One implementation of a disclosed electronic device may include a first magnetic layer having an easy magnetization axis in a first direction and having a variable magnetization direction, a third magnetic layer having a magnetization direction pinned in the first direction, a second magnetic layer interposed between the first magnetic layer and the third magnetic layer, and having a magnetization direction pinned in a second direction different from the first direction, a tunnel barrier layer interposed between the first magnetic layer and the second magnetic layer, and a non-magnetic layer interposed between the second magnetic layer and the third magnetic layer. | 2014-10-09 |
20140299951 | NOVEL HYBRID METHOD OF PATTERNING MTJ STACK - This invention comprises a method to make small MTJ element using hybrid etching and oxygen plasma immersion ion implantation. The method has no removal of the magnetic free layer (or memory layer) and hence prevents any possible physical damage near the free layer edges. After photolithography patterning, alternative Ta, Ru, Ta etchings are performed before it stops on an MgO intermediate layer above the free layer. Then an oxygen plasma immersion ion implantation is performed to completely oxidize the exposed portion of the free layer, leaving the hard mask covered portion unchanged which define the lateral width of the MTJ element. | 2014-10-09 |
20140299952 | MAGNETIC TUNNEL JUNCTION DEVICE AND METHOD FOR FABRICATING THE SAME - A magnetic tunnel junction device includes a first electrode having a curved top surface, a magnetic tunnel junction layer formed along the top surface of the first electrode, and a second electrode formed on the magnetic tunnel junction layer. | 2014-10-09 |
20140299953 | WRITE CURRENT REDUCTION IN SPIN TRANSFER TORQUE MEMORY DEVICES - The present disclosure relates to the fabrication of spin transfer torque memory elements for non-volatile microelectronic memory devices. The spin transfer torque memory element may include a magnetic tunneling junction connected with specifically sized and/or shaped fixed magnetic layer that can be positioned in a specific location adjacent a free magnetic layer. The shaped fixed magnetic layer may concentrate current in the free magnetic layer, which may result in a reduction in the critical current needed to switch a bit cell in the spin transfer torque memory element. | 2014-10-09 |
20140299954 | SOLID-STATE IMAGE PICKUP ELEMENT AND IMAGE PICKUP APPARATUS - Disclosed herein is a solid-state image pickup element, including: a photoelectric conversion region; a transistor; an isolation region of a first conductivity type configured to isolate the photoelectric conversion region and the transistor from each other; a well region of the first conductivity type having the photoelectric conversion region, the transistor, and the isolation region of the first conductivity type formed therein; a contact portion configured to supply an electric potential used to fix the well region to a given electric potential; and an impurity region of the first conductivity type formed so as to extend in a depth direction from a surface of the isolation region of the first conductivity type in the isolation region of the first conductivity type between the contact portion and the photoelectric conversion region, and having a sufficiently higher impurity concentration than that of the isolation region of the first conductivity type. | 2014-10-09 |
20140299955 | SLOPED STRUCTURE, METHOD FOR MANUFACTURING SLOPED STRUCTURE, AND SPECTRUM SENSOR - A method for manufacturing a sloped structure is disclosed. The method includes the steps of: (a) forming a sacrificial film above a substrate; (b) forming a first film above the sacrificial film, the first film having a first portion connected to the substrate, a second portion located above the sacrificial film, a third portion located between the first portion and the second portion, and a thin region in a portion of the third portion or in a boundary section between the second portion and the third portion and having a thickness smaller than the first portion; (c) removing the sacrificial film; and (d) bending the first film in the thin region, after the step (c), thereby sloping the second portion of the first film with respect to the substrate. | 2014-10-09 |