41st week of 2019 patent applcation highlights part 50 |
Patent application number | Title | Published |
20190311972 | METHOD FOR THE INTEGRATION OF POWER CHIPS AND BUS-BARS FORMING HEAT SINKS - The method comprises: 1) producing a preform (EB | 2019-10-10 |
20190311973 | SYSTEMS AND METHODS FOR IMPROVED THROUGH-SILICON-VIAS - A semiconductor structure is described. The semiconductor structure includes a semiconductor substrate and a through-silicon via (TSV). The TSV is disposed between a first surface of the semiconductor substrate and an interconnection layer disposed on a second surface of the semiconductor substrate, where the first surface of the semiconductor substrate is opposite to the second surface. The TSV has an external surface that interfaces with the semiconductor substrate. In one embodiment, the external surface includes a protrusion that extends into the semiconductor substrate. In another embodiment, the TSV includes one or more voids. In yet another embodiment, the TSV includes both protrusions and voids. The protrusions and/or the one or more voids may reduce thermal expansion stress. Other embodiments may be described and/or claimed. | 2019-10-10 |
20190311974 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A chip mounting portion included in a semiconductor device has a region including a semiconductor chip in plan view. When an average surface roughness of the region is “Ra”, 0.8 μm≤Ra≤3.0 μm holds. | 2019-10-10 |
20190311975 | LOW-COST SEMICONDUCTOR PACKAGE USING CONDUCTIVE METAL STRUCTURE - A low-cost semiconductor package using a conductive metal structure includes a lead frame including a pad and a lead, a semiconductor chip attached onto the pad of the lead frame, an Aluminum (Al) pad formed on the semiconductor chip, a clip structure having one side adhered to the Al pad and the other side adhered to the lead of the lead frame, and a sealing member formed to surround the semiconductor chip and the clip structure via molding, wherein the semiconductor chip is adhered directly to a junction of the lead frame through a first adhesive layer formed of a solder or epoxy resin-based material and is adhered directly to a junction of the Al pad and the clip structure through a second adhesive layer formed of a solder-based material. | 2019-10-10 |
20190311976 | SEMICONDUCTOR POWER DEVICE WITH CORRESPONDING PACKAGE AND RELATED MANUFACTURING PROCESS - A semiconductor power device has: a die, with a front surface and a rear surface, and with an arrangement of projecting regions on the front surface, which define between them windows arranged within which are contact regions; and a package, which houses the die inside it. A metal frame has a top surface and a bottom surface; the die is carried by the frame on the top surface; an encapsulation coating coats the frame and the die. A first insulation multilayer is arranged above the die and is formed by an upper metal layer, a lower metal layer, and an intermediate insulating layer; the lower metal layer is shaped according to an arrangement of the projecting regions and has contact projections, which extend so as to electrically contact the contact regions, and insulation regions, interposed between the contact projections, in positions corresponding to the projecting regions. | 2019-10-10 |
20190311977 | High Performance Multi-Component Electronics Power Module - Methods are provided for forming an IC power package including a power MOSFET device, a microprocessor/driver, and/or other discrete electronics. A lead frame may be etched to form a half-etch lead frame defining component attach structures at the top side of the lead frame. A power MOSFET may be mounted to a die attach pad defined in the half-etch lead frame, and the structure may be overmolded. The top of the overmolded structure may be grinded to reduce a thickness of the power MOSFET and expose a top surface of the MOSFET through the surrounding mold compound. A conductive contact may be formed on a top surface of the MOSFET. Selected portions of the half-etch lead frame may be etched from the bottom-up to separate the MOSFET from other package components, and to define a plurality of package posts for solder-mounting the package to a PCB. | 2019-10-10 |
20190311978 | COMPOSITE STACKED INTERCONNECTS FOR HIGH-SPEED APPLICATIONS AND METHODS OF ASSEMBLING SAME - A semiconductor package substrate includes a composite and stacked vertical interconnect on a land side of the substrate. The composite and stacked vertical interconnect includes a smaller contact end against the semiconductor package substrate, and a larger contact end for board mounting. | 2019-10-10 |
20190311979 | SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor substrate includes a first dielectric structure and a first circuit layer. The first circuit layer is embedded in the first dielectric structure. The first circuit layer does not protrude from a first surface of the first dielectric structure. The first circuit layer includes at least one conductive segment. The conductive segment includes a first portion adjacent to the first surface of the first dielectric structure and a second portion opposite to the first portion. A width of the first portion of the conductive segment is different from a width of the second portion of the conductive segment. | 2019-10-10 |
20190311980 | MICROELECTRONIC ASSEMBLIES HAVING SUBSTRATE-INTEGRATED PEROVSKITE LAYERS - Disclosed herein are microelectronic assemblies with integrated perovskite layers, and related devices and methods. For example, in some embodiments, a microelectronic assembly may include an organic package substrate portion having a surface with a conductive layer, and a perovskite conductive layer on the conductive layer. In some embodiments, a microelectronic assembly may include an organic package substrate portion having a surface with a conductive layer, a perovskite conductive layer having a first crystalline structure on the conductive layer, and a perovskite dielectric layer having a second crystalline structure on the perovskite conductive layer. In some embodiments, the first and second crystalline structures have a same orientation. | 2019-10-10 |
20190311981 | POWER ELECTRONICS PACKAGE AND METHOD OF MANUFACTURING THEREOF - An electronics package is disclosed herein that includes a glass substrate having an exterior portion surrounding an interior portion thereof, wherein the interior portion has a first thickness and the exterior portion has a second thickness larger than the first thickness. An adhesive layer is formed on a lower surface of the interior portion of the glass substrate. A semiconductor device having an upper surface is coupled to the adhesive layer, the semiconductor device having at least one contact pad disposed on the upper surface thereof. A first metallization layer is coupled to an upper surface of the glass substrate and extends through a first via formed through the first thickness of the glass substrate to couple with the at least one contact pad of the semiconductor device. | 2019-10-10 |
20190311982 | WIRING BOARD AND SEMICONDUCTOR PACKAGE - A wiring board includes: a Cu pad; an insulating layer covering the Cu pad and having an opening portion; a first metallic layer formed on the Cu pad in the opening portion; and a connecting terminal formed on the first metallic layer to extend from the opening portion to above an upper surface of the insulating layer. The connecting terminal includes: a seed layer formed on the first metallic layer; and a second metallic layer formed on the seed layer. A stacked body is formed of the first metallic layer and the connecting terminal and includes a constricted portion. The constricted portion is located in a certain position of the first metallic layer in a thickness direction of the first metallic layer, and a sectional area of the stacked body is the smallest at the constricted portion. | 2019-10-10 |
20190311983 | STACKING MULTIPLE DIES HAVING DISSIMILAR INTERCONNECT STRUCTURE LAYOUT AND PITCH - An apparatus is provided comprising: first die, wherein a first plurality of interconnect structures is formed on the first die; one or more layers, wherein a first surface of the one or more layers is attached to the first plurality of interconnect structures; a second plurality of interconnect structures formed on a second surface of the one or more layers; and a second die, wherein a third plurality of interconnect structures is formed on the second die, wherein a first interconnect structure of the first plurality of interconnect structures is electrically connected to a second interconnect structure of the second plurality of interconnect structures through the one or more layers, and wherein the first die is mounted on the second die such that the second interconnect structure of the second plurality of interconnect structures is attached to a third interconnect structure of the third plurality of interconnect structures. | 2019-10-10 |
20190311984 | SELF-ALIGNED VIA - There is disclosed in an example an integrated circuit, including: a first layer having a dielectric, a first conductive interconnect and a second conductive interconnect; a second layer having a third conductive interconnect; a conductive via between the first layer and the second layer to electrically couple the second conductive interconnect to the third conductive interconnect; a dielectric plug disposed vertically between the first layer and second layer and disposed to prevent the via from electrically shorting to the first conductive interconnect; and a dielectric cap covering the dielectric plug. | 2019-10-10 |
20190311985 | ADVANCED INTERCONNECTS CONTAINING AN IMT LINER - An interconnect structure is provided that includes a liner located between an electrically conductive structure and an interconnect dielectric material layer. The liner is composed of a phase change material that is insulating at a first temperature, and becomes conductive at a second temperature that is higher than the first temperature. The liner that is composed of such a phase change material is referred to as an “insulator-to/from metal transition (IMT)” liner. In the present application, an entirety of, or a portion of, the IMT liner may be changed from an insulating phase to a conductive phase by increasing the temperature (i.e., heating) of the liner so as to provide a redundancy path in which electrons can flow. | 2019-10-10 |
20190311986 | FORMING DUAL METALLIZATION INTERCONNECT STRUCTURES IN SINGLE METALLIZATION LEVEL - Techniques are provided to fabricate metallic interconnect structures in a single metallization level, wherein different width metallic interconnect structures are formed of different metallic materials to eliminate or minimize void formation in the metallic interconnect structures. For example, a semiconductor device includes an insulating layer disposed on a substrate, and a first metallic line and a second metallic line formed in the insulating layer. The first metallic line has a first width, and the second metallic line has a second width which is greater than the first width. The first metallic line is formed of a first metallic material, and the second metallic line is formed of a second metallic material, which is different from the first metallic material. For example, the first metallic material is cobalt or ruthenium, and the second metallic material is copper. | 2019-10-10 |
20190311987 | Through-Core Via - A package substrate for connecting together semiconductor devices with other semiconductor device packages. The package substrate includes an exposed core layer with at least one via exposing a conductive layer of the package substrate. A first portion of the package substrate may include a solder mask on top and bottom surfaces. A first semiconductor device may be connected to the first portion of the package substrate. Layers of a second portion of the package substrate are removed to expose a core layer and vias are created in the exposed core layer to expose the conductive layer. Conducive material at least partially filling the vias may be used to connect a semiconductor device package to the second portion of the package substrate. The semiconductor device packages may communicate through conductive layers in the package substrate. The package substrate may be used to connect the semiconductor packages to a motherboard. | 2019-10-10 |
20190311988 | Method of Forming Semiconductor Packages Having Through Package Vias - A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias. | 2019-10-10 |
20190311989 | METHODS AND DEVICES FOR SOLDERLESS INTEGRATION OF MULTIPLE SEMICONDUCTOR DIES ON FLEXIBLE SUBSTRATES - Methods and devices for solderless integration of multiple semiconductor dies on flexible substrates. In some embodiments, a method for solderless integration of multiple semiconductor dies on flexible substrates includes arranging one or a plurality of semiconductor dies on a first carrier, active side down, and then depositing a sacrificial material over them. In some embodiments, the method further includes removing the first carrier and then building a wafer-level redistribution layer (RDL) over the active side of the one or plurality of semiconductor dies and the sacrificial material. In some embodiments, the method includes patterning the wafer-level RDL to form an outline of a final module footprint and then applying a second carrier to the wafer-level RDL. In some embodiments, the method can also include removing the sacrificial material from the one or plurality of semiconductor dies and the wafer-level RDL to achieve an integration of the one or plurality of semiconductor dies. | 2019-10-10 |
20190311990 | WIRING SUBSTRATE AND ELECTRONIC DEVICE - A wiring substrate includes a first substrate including a wiring layer and a solder resist layer that partially covers the wiring layer. The solder resist layer includes a circular opening partially exposing the wiring layer and a support partially covering the wiring layer within the opening. The wiring layer includes a first connection pad exposed in the opening and formed by a portion of the wiring layer located at an outer side of the support. The wiring substrate further includes a cylindrical connection pin and a bonding member that bonds a first end surface of the connection pin and the first connection pad located in the opening. | 2019-10-10 |
20190311991 | SEMICONDUCTOR DEVICE WITH EMBEDDED SEMICONDUCTOR DIE AND SUBSTRATE-TO-SUBSTRATE INTERCONNECTS - A semiconductor device having an embedded semiconductor die and substrate-to-substrate interconnects is disclosed and may include a substrate with a top surface and a bottom surface, a semiconductor die bonded to the top surface of the substrate, a first mold material encapsulating the semiconductor die and at least a portion of the top surface of the substrate, and a first conductive bump that is on the top surface of the substrate and is at least partially encapsulated by the first mold material. An extended substrate may be coupled to the substrate utilizing the first conductive bump. A second conductive bump may be formed on the bottom surface of the substrate, and a second mold material may encapsulate at least a portion of the second conductive bump and at least a portion of the bottom surface of the substrate. A third mold material may be formed between the first mold material and the extended substrate. | 2019-10-10 |
20190311992 | INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME - An integrated circuit device includes a metal film and a complex capping layer covering a top surface of the metal film. The metal film includes a first metal, and penetrates at least a portion of an insulating film formed over a substrate. The complex capping layer includes a conductive alloy capping layer covering the top surface of the metal film, and an insulating capping layer covering a top surface of the conductive alloy capping layer and a top surface of the insulating film. The conductive alloy capping layer includes a semiconductor element and a second metal different from the first metal. The insulating capping layer includes a third metal. | 2019-10-10 |
20190311993 | Schemes for Forming Barrier Layers for Copper in Interconnect Structures - A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided. | 2019-10-10 |
20190311994 | ELECTRONIC DEVICE MODULE - An electronic device module includes a substrate, at least one first component and at least one second component disposed on one surface of the substrate, a shielding wall disposed between the at least one first component and the at least one second component, and disposed on the substrate, and a sealing portion having the at least one first component, the at least one second component and the shielding wall embedded therein, and disposed on the substrate. The shielding wall includes at least one insulating layer and at least one conductive layer disposed on the insulating layer. | 2019-10-10 |
20190311995 | WARPING REDUCTION IN SILICON WAFERS - Techniques for reducing stress in an integrated circuit wafer are disclosed. A silicon substrate may include multiple integrated circuit chips and multiple scribe regions situated between the one of the multiple integrated circuit chips. A particular scribe region includes a plurality of layers and a stress reduction structure that includes, at a particular layer of the plurality of layers, a material whose coefficient of thermal expansion of materials is greater than a coefficient of thermal expansion of the silicon wafer. | 2019-10-10 |
20190311996 | High-Reliability Electronic Packaging Structure, Circuit Board, and Device - A high-reliability electronic packaging structure includes a plurality of packaging layers and mechanical support layers. An electrically functional solder joint is provided in a first area of each of the packaging layers, and any two adjacent packaging layers are coupled using electrically functional solder joints. A mechanical support layer is disposed in a second area of each of the packaging layers, and the mechanical support layer is configured to support the two adjacent packaging layers. The first area is provided on a periphery of the second area. Hence, a problem that an internal silicon chip at an upper packaging layer or a lower packaging layer fractures and fails when the upper packaging layer or the lower packaging layer is subject to a mechanical load can be resolved. | 2019-10-10 |
20190311997 | SECURE ASSEMBLY OF DOCUMENTS OR MEDIA - The invention relates to a method for producing a security document, wherein a body is created that comprises two superimposed layers, a circuit which is electric and/or has an electronic chip arranged on the interface between the two layers, and a first adhesive between the two layers, which adheres to the two layers and/or the circuit. The method includes a step of depositing a second adhesive which is different from, or has a different behaviour from, the first adhesive in relation to the solvents or the temperature and partially adheres to at least one of the two layers and/or the circuit. | 2019-10-10 |
20190311998 | HIGH FREQUENCY MODULE AND METHOD OF MANUFACTURING THE SAME - A high frequency module includes: a package section including a semiconductor chip, a first portion of a backshort being integrated with the semiconductor chip by a first resin, and a first rewiring line electrically coupled to the semiconductor chip and including a portion to be an antenna coupler; and a waveguide with which a second portion of the backshort is integrated, wherein the package section and the waveguide are integrated by a second resin, to position the portion to be the antenna coupler between the waveguide and the backshort. | 2019-10-10 |
20190311999 | SEMICONDUCTOR DEVICE AND WAFER-LEVEL PACKAGE EACH HAVING REDISTRIBUTION STRUCTURE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device having a redistribution structure includes a redistribution layer provided on a semiconductor chip, and a passivation layer covering the redistribution layer while partially exposing the redistribution layer. The passivation layer has a thickness less than that of the redistribution layer. | 2019-10-10 |
20190312000 | RELIABLE PASSIVATION FOR INTEGRATED CIRCUITS - Device and method for forming a device are presented. A substrate having circuit component and a back-end-of-line (BEOL) dielectric layer with interconnects is provided. A pad dielectric layer is formed over the BEOL dielectric layer. The pad dielectric layer includes a pad via opening which exposes a surface of one of the interconnects in the BEOL dielectric layer. A pad interconnect is formed on the pad dielectric layer and the pad interconnect is coupled to one of the interconnect in the BEOL dielectric by a pad via contact in the pad via opening. The pad interconnect comprises a pad interconnect pattern which is devoid of 90° angles and any angled structures contained in the pad interconnect pattern less than 90°. A passivation layer is formed on the substrate. The passivation layer lines the pad interconnect and covers an exposed surface of the pad dielectric layer. | 2019-10-10 |
20190312001 | IMPROVING MECHANICAL AND THERMAL RELIABILITY IN VARYING FORM FACTORS - A system for packaging integrated circuits includes an integrated circuit having one or more integrated circuit terminals. The system for packaging integrated circuits also includes a substrate having one or more substrate terminals. The system for packaging integrated circuits further includes an electrically conductive adhesive in communication with the integrated circuit terminals and the substrate terminals. The electrically conductive adhesive establishes an electrical connection between each of the one or more integrated circuit terminals and the one or more substrate terminals. The electrical connection between each of the one or more integrated circuit terminals and the one or more substrate terminals are enclosed in a dielectric. The system for packaging integrated circuits includes a second adhesive in communication with the integrated circuit and the substrate, wherein the second adhesive couples the integrated circuit and substrate together. | 2019-10-10 |
20190312002 | HIGH BANDWIDTH MEMORY PACKAGE FOR HIGH PERFORMANCE PROCESSORS - Integrated component packages and methods of assembling integrated component packages are provided. The integrated component package can comprise a bump pitch relaxing layer. A high-bandwidth memory component directly mechanically coupled to the bump pitch relaxing layer on a first side of the bump pitch relaxing layer via a first set of bump bond connections. The high-bandwidth memory component directly electrically coupled to the bump pitch relaxing layer on the first side of the bump pitch relaxing layer via the first set of bump bond connections. The bump pitch relaxing layer mechanically coupled to a first side of a substrate via second set of bump bond connections. The high-bandwidth memory component electrically coupled to the substrate via the bump-pitch relaxing layer and the second set of bump bond connections, and a bump pitch of the second set of bump bond connections is larger than the first set of bump bond connections. | 2019-10-10 |
20190312003 | WIRING BOARD AND SEMICONDUCTOR DEVICE - A wiring board includes an insulator layer, and a connection terminal having a first surface and a side surface intersecting the first surface. The first surface is exposed from the insulator layer, and the insulator layer includes a gap formed along at least a part of the side surface. | 2019-10-10 |
20190312004 | PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME - A package structure including at least one semiconductor die, an insulating encapsulant, an insulating layer, conductive pillars, a dummy pillar, a first seed layer and a redistribution layer is provided. The semiconductor die have a first surface and a second surface opposite to the first surface. The insulating encapsulant is encapsulating the semiconductor die. The insulating layer is disposed on the first surface of the semiconductor die and on the insulating encapsulant. The conductive pillars are located on the semiconductor die. The dummy pillar is located on the insulating encapsulant. The first seed layer is embedded in the insulating layer, wherein the first seed layer is located in between the conductive pillars and the semiconductor die, and located in between the dummy pillar and the insulating encapsulant. The redistribution layer is disposed over the insulating layer and is electrically connected to the semiconductor die through the conductive pillars. | 2019-10-10 |
20190312005 | DECOUPLING CAPACITOR MOUNTED ON AN INTEGRATED CIRCUIT DIE, AND METHOD OF MANUFACTURING THE SAME - Electronic device package technology is disclosed. In one example, an electronic device comprises a die ( | 2019-10-10 |
20190312006 | BONDING APPARATUS, BONDING SYSTEM, BONDING METHOD, AND RECORDING MEDIUM - A bonding apparatus configured to bond substrates includes a first holder configured to vacuum-exhaust a first substrate to attract and hold the first substrate on a bottom surface thereof; a second holder disposed under the first holder and configured to vacuum-exhaust a second substrate to attract and hold the second substrate on a top surface thereof; a rotator configured to rotate the first holder and the second holder relatively; a moving device configured to move the first holder and the second holder relatively in a horizontal direction; three position measurement devices disposed at the first holder or the second holder rotated by the rotator and configured to measure a position of the first holder or the second holder; and a controller configured to control the rotator and the moving device based on measurement results of the three position measurement devices. | 2019-10-10 |
20190312007 | BONDING SYSTEM AND BONDING METHOD - A bonding system includes a surface modifying apparatus, a surface hydrophilizing apparatus and a bonding apparatus. The surface modifying apparatus is configured to modify a bonding surface of a first substrate and a bonding surface of a second substrate with plasma. The surface hydrophilizing apparatus is configured to hydrophilize the modified bonding surfaces of the first substrate and the second substrate. The bonding apparatus includes a condensation suppressing gas discharge unit, and is configured to bond the hydrophilized bonding surfaces of the first substrate and the second substrate by an intermolecular force. The condensation suppressing gas discharge unit is configured to discharge a condensation suppressing gas toward a space between a peripheral portion of the bonding surface of the first substrate and a peripheral portion of the bonding surface of the second substrate facing each other. | 2019-10-10 |
20190312008 | Arrangements and Method for Providing a Bond Connection - A method comprises heating a first electrically conductive layer that is to be electrically contacted, and that is arranged on a first element, and pressing a first end of a bonding wire on the first electrically conductive layer by exerting pressure to the first end of the bonding wire, and further by exposing the first end of the bonding wire to ultrasonic energy, thereby deforming the first end of the bonding wire and creating a permanent substance-to-substance bond between the first end of the bonding wire and the first electrically conductive layer. The bonding wire either comprises a rounded cross section with a diameter of at least 125 μm or a rectangular cross section with a first width of at least 500 μm and a first height of at least 50 μm. | 2019-10-10 |
20190312009 | CARRIER AND INTEGRATED MEMORY - An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip. | 2019-10-10 |
20190312010 | CARRIER AND INTEGRATED MEMORY - An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip. | 2019-10-10 |
20190312011 | CARRIER AND INTEGRATED MEMORY - An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip. | 2019-10-10 |
20190312012 | MEMORY DEVICE - A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug. | 2019-10-10 |
20190312013 | SEMICONDUCTOR PACKAGE - A semiconductor package includes: a first semiconductor chip in which a through-electrode is provided; a second semiconductor chip connected to a top surface of the first semiconductor chip; a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer, and a second connection hump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer. | 2019-10-10 |
20190312014 | SEMICONDUCTOR DEVICE AND STRUCTURE - A 3D semiconductor device and structure, including: a first die including first transistors and first interconnect, overlaid by a second die including second transistors and second interconnect, where the first die has a first die area and the second die has a second die area, where the first die area is at least 10% larger than the second die area, where the second die is aligned to the first die with less than 400 nm alignment error, and where the second die has a thickness of less than four microns. | 2019-10-10 |
20190312015 | LED BACKPLANE HAVING PLANAR BONDING SURFACES AND METHOD OF MAKING THEREOF - A backplane can have a non-planar top surface. Insulating material portions including planar top surface regions located within a same horizontal plane are formed over the backplane. A two- dimensional array of metal plate clusters is formed over the insulating material portions. Each of the metal plate clusters includes a plurality of metal plates. Each metal plate includes a horizontal metal plate portion overlying a planar top surface region and a connection metal portion connected to a respective metal interconnect structure in the backplane. A two- dimensional array of light emitting device clusters is bonded to the backplane through respective bonding structures. Each light emitting device cluster includes a plurality of light emitting devices overlying a respective metal plate cluster. | 2019-10-10 |
20190312016 | FAN OUT PACKAGING POP MECHANICAL ATTACH METHOD - Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a mold over and around a first die and a first via. The semiconductor package has a conductive pad of a first redistribution layer disposed on a top surface of the first die and/or a top surface of the mold. The semiconductor package includes a second die having a solder ball coupled to a die pad on a bottom surface of the second die, where the solder ball of the second die is coupled to the first redistribution layer. The first redistribution layer couples the second die to the first die, where the second die has a first edge and a second edge, and where the first edge is positioned within a footprint of the first die and the second edge is positioned outside the footprint of the first die. | 2019-10-10 |
20190312017 | Optoelectronic Component and Method for Producing an Optoelectronic Component - The invention relates to an optoelectronic component comprising
| 2019-10-10 |
20190312018 | Multi-Chip Semiconductor Package - A semiconductor package includes a first die; a first redistribution structure over the first die, the first redistribution structure being conterminous with the first die; a second die over the first die, a first portion of the first die extending beyond a lateral extent of the second die; a conductive pillar over the first portion of the first die and laterally adjacent to the second die, the conductive pillar electrically coupled to first die; a molding material around the first die, the second die, and the conductive pillar; and a second redistribution structure over the molding material, the second redistribution structure electrically coupled to the conductive pillar and the second die. | 2019-10-10 |
20190312019 | TECHNIQUES FOR DIE TILING - Techniques are provided for fine node heterogeneous-chip packages. In an example, a method of making a heterogeneous-chip package can include coupling electrical terminals of a first side of a first base die to electrical terminals of a first side of a second base die using a silicon bridge, forming an organic substrate about the silicon bridge and adjacent the first sides of the first and second base dies, and coupling a fine node die to a second side of at least one of the first base die or the second base die. | 2019-10-10 |
20190312020 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND MOUNTING DEVICE - The disclosure is provided with: a temporary crimping step in which one or more semiconductor chips | 2019-10-10 |
20190312021 | Method of Manufacturing a Package-on-Package Type Semiconductor Package - A method for manufacturing a semiconductor package, for example a package-on-package type semiconductor device package. As non-limiting examples, various aspects of this disclosure provide high-yield methods for manufacturing a package-on-package type semiconductor package, or a portion thereof. | 2019-10-10 |
20190312022 | SEMICONDUCTOR COMPONENT, PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A package manufacturing having a semiconductor substrate, a bonding layer, at least one semiconductor device, a redistribution circuit structure and an insulating encapsulation. The bonding layer is disposed on the semiconductor substrate. The semiconductor device is disposed on and in contact with a portion of the bonding layer, wherein the bonding layer is located between the semiconductor substrate and the semiconductor device and adheres the semiconductor device onto the semiconductor substrate. The redistribution circuit structure is disposed on and electrically connected to the semiconductor device, wherein the semiconductor device is located between the redistribution circuit structure and the bonding layer. The insulating encapsulation wraps a sidewall of the semiconductor device, wherein a sidewall of the bonding layer is aligned with a sidewall of the insulating encapsulation and a sidewall of the redistribution circuit structure. | 2019-10-10 |
20190312023 | INTEGRATED CIRCUIT DEVICE WITH CRENELLATED METAL TRACE LAYOUT - Integrated circuit (IC) cell architectures including a crenellated interconnect trace layout. A crenellated trace layout may be employed where an IC cell includes transistor having a source/drain terminal interconnected through a back-side (3D) routing scheme that reduces front-side routing density for a given transistor footprint. In the crenellated layout, adjacent interconnect traces or tracks may have their ends staggered according to a crenellation phase for the cell. Crenellated tracks may intersect one cell boundary with adjacent tracks intersecting an opposite cell boundary. Track ends may be offset by at least the width of an underlying orthogonal interconnect trace. Crenellated track ends may be offset by the width of an underlying orthogonal interconnect trace and half a spacing between adjacent orthogonal interconnect traces. | 2019-10-10 |
20190312024 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first circuit, a second circuit, a first power supply line, a second power supply line coupled to the first circuit, a third power supply line, a fourth power supply line coupled to the second circuit, a first switch circuit including a first switch transistor and a well tap, the first switch transistor including one source or drain end coupled to the first power supply line and another source or drain end coupled to the second power supply line, the well tap being electrically coupled to the second power supply line, and a second switch circuit including a second switch transistor including one source or drain end coupled to the third power supply line and another source or drain end coupled to the fourth power supply line, the second switch circuit including no well tap electrically coupled to the fourth power supply line. | 2019-10-10 |
20190312025 | SYSTEMS AND METHODS FOR FABRICATION OF GATED DIODES WITH SELECTIVE EPITAXIAL GROWTH - An integrated circuit (IC) is fabricated with transistors and gated diodes having selected epitaxial growth. The transistors may be Field-Effect Transistors (FETs) for example, and more specifically, may be fin-based FETs (finFETs) where fins are fabricated, in part, using an epitaxial growth process. The IC is further fabricated with gated diodes. Selected gated diodes within the IC are fabricated using the epitaxial growth process on the fins of the gated diode to form an anode and a cathode. Other selected gated diodes are fabricated without using epitaxial growth processes to form the anode and the cathode. In still another aspect, selected gated diodes are fabricated with epitaxial growth processes on either the anode or the cathode, but not both. In an exemplary aspect, the other selected gated diodes are part of electrostatic discharge (ESD) protection circuits in an input/output (I/O) region of the IC. | 2019-10-10 |
20190312026 | ESD PROTECTION DEVICE, SEMICONDUCTOR DEVICE THAT INCLUDES AN ESD PROTECTION DEVICE, AND METHOD OF MANUFACTURING SAME - An ESD protection device for protecting an integrated circuit (IC) against an ESD event includes a first terminal coupled to an input/output pad of the IC, a second terminal coupled to a reference or ground voltage, a silicon-controlled rectifier (SCR) device having an anode connected to the first terminal and a cathode connected to the reference or ground voltage, and a pnp transistor coupled in parallel with the SCR device. The pnp transistor has an emitter coupled to the first terminal, a collector coupled to the second terminal, and a base coupled to a gate of the SCR. The pnp transistor includes a contact region formed at a first side of a substrate, the first contact region being surrounded by an STI layer formed at the first side of the substrate. An insulation structure is formed at an intersection of the first contact region and the STI layer. | 2019-10-10 |
20190312027 | MONOLITHIC SINGLE CHIP INTEGRATED RADIO FREQUENCY FRONT END MODULE CONFIGURED WITH SINGLE CRYSTAL ACOUSTIC FILTER DEVICES - A method of manufacture and structure for a monolithic single chip single crystal device. The method can include forming a first single crystal epitaxial layer overlying the substrate and forming one or more second single crystal epitaxial layers overlying the first single crystal epitaxial layer. The first single crystal epitaxial layer and the one or more second single crystal epitaxial layers can be processed to form one or more active or passive device components. Through this process, the resulting device includes a monolithic epitaxial stack integrating multiple circuit functions. | 2019-10-10 |
20190312028 | ON-CHIP METAL-INSULATOR-METAL (MIM) CAPACITOR AND METHODS AND SYSTEMS FOR FORMING SAME - We report a semiconductor device, containing a semiconductor substrate; an isolation feature on the substrate; a plurality of gates on the isolation feature, wherein each gate comprises a gate electrode and a high-k dielectric layer disposed between the gate electrode and the isolation feature and disposed on and in contact with at least one side of the gate electrode; and a fill metal between the plurality of gates on the isolation feature. We also report methods of forming such a device, and a system for manufacturing such a device. | 2019-10-10 |
20190312029 | SEMICONDUCTOR DEVICE - An IGBT region in which an IGBT is disposed and a FWD region in which a FWD connected in antiparallel to the IGBT is disposed are provided in an active region of a semiconductor chip. In the active region, the FWD region is provided in plural separated from each other. The IGBT region is a continuous region between the FWD regions. In the IGBT region and the FWD region, first and second gate trenches are disposed in striped-shape layouts that are parallel to a front surface of the semiconductor chip and extend along a same first direction. The second gate trenches of the FWDs of the FWD regions are disposed separated from the first gate trenches of the IGBT in the IGBT region. This structure enables degradation of element characteristics to be prevented, and heat dissipation of the semiconductor chip and the degrees of freedom in design to be enhanced. | 2019-10-10 |
20190312030 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - Semiconductor device having less defects in a gate insulating film and improved reliability and methods of forming the semiconductor devices are provided. The semiconductor devices may include a gate insulating film on a substrate and a gate electrode structure on the gate insulating film. The gate electrode structure may include a lower conductive film, a silicon oxide film, and an upper conductive film sequentially stacked on the gate insulating film. The lower conductive film may include a barrier metal layer. | 2019-10-10 |
20190312031 | ROM Chip Manufacturing Structures Having Shared Gate Electrodes - An integrated circuit (IC) chip embodiment includes first and second ROM cells arranged in a same row of a ROM array. The first and second ROM cells include first portions of first and second gate structures, respectively. The IC chip further includes a strap cell disposed between the first and second ROM cells. The strap cell includes second portions of the first and second gate structures. The first gate structure is physically separated from the second gate structure. | 2019-10-10 |
20190312032 | SEMICONDUCTOR DEVICE - A semiconductor device is provided, which includes a first and second multichannel active patterns spaced apart from one another and extending in a first direction. The semiconductor device also includes first and second gate structures on the first and second multichannel active patterns, extending in a second direction and including first and second gate insulating films, respectively. Sidewalls of the first multichannel active pattern include first portions in contact with the first gate insulating film, second portions not in contact with the first gate insulating film, third portions in contact with the second gate insulating film, and fourth portions not in contact with the second gate insulating film. Additionally, a height of the first portions of the first multichannel active pattern is greater than a height of the third portions of the first multichannel active pattern. | 2019-10-10 |
20190312033 | POWER DEVICE STRUCTURE WITH IMPROVED RELIABILITY AND EFFICIENCY - Systems and methods according to one or more embodiments are provided for improved reliability and efficiency of high side power stage output drivers used in switching amplifiers. In one example, a system includes a power device structure comprising an nwell structure formed within a semiconductor p substrate and a pwell structure formed within the nwell structure. The system further includes one or more NMOS electronic power devices formed on the pwell structure and a pwell guardring formed on the pwell structure configured to surround the one or more NMOS electronic power devices. The system further includes an nwell guardring formed on the nwell structure configured to surround the pwell structure and a p+ guardring formed on the nwell structure configured to surround the nwell guardring. | 2019-10-10 |
20190312034 | INTEGRATED CIRCUIT DEVICE - An integrated circuit device includes a first fin separation insulating portion over the first device region; a pair of first fin-type active regions apart from each other with the first fin separation insulating portion therebetween and collinearly extending in a first horizontal direction; a first dummy gate structure vertically overlapping the first fin separation insulating portion; a second fin separation insulating portion apart from the first fin separation insulating portion and arranged over the second device region; and a plurality of second fin-type active regions apart from each other with the second fin separation insulating portion therebetween in the second device region and collinearly extending in the first horizontal direction, wherein a vertical level of a lowermost surface of the second fin separation insulating portion is equal to or lower than a vertical level of a lowermost surface of the first fin separation insulating portion. | 2019-10-10 |
20190312035 | METHOD FOR FORMING HYDROGEN-PASSIVATED SEMICONDUCTOR CHANNELS IN A THREE-DIMENSIONAL MEMORY DEVICE - A method of forming a three-dimensional memory device includes forming memory stack structures vertically extending through an alternating stack of insulating layers and electrically conductive layers over a substrate, such that each of the memory stack structures includes a memory film and a vertical semiconductor channel laterally surrounded by the memory film. The method also includes forming a stack of a first silicon nitride layer and a second silicon nitride layer over the memory stack structures, such that the first silicon nitride layer has a higher hydrogen-to-nitrogen ratio than the second silicon nitride layer, performing an anneal process at an elevated temperature to diffuse hydrogen from the first silicon nitride layer into the memory stack structures, and removing the first and second silicon nitride layers. | 2019-10-10 |
20190312036 | METHOD FOR FORMING SEMICONDUCTOR DEVICE HAVING A MULTI-THICKNESS GATE TRENCH DIELECTRIC LAYER - A semiconductor device includes a semiconductor substrate having a gate trench including of an upper trench and a lower trench. The upper trench is wider than the lower trench. A gate is embedded in the gate trench. The gate includes an upper portion and a lower portion. A first gate dielectric layer is between the upper portion and a sidewall of the upper trench. The first gate dielectric layer has a first thickness. A second gate dielectric layer is between the lower portion and a sidewall of the lower trench and between the lower portion and a bottom surface of the lower trench. The second gate dielectric layer has a second thickness that is smaller than the first thickness. | 2019-10-10 |
20190312037 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are provided. The method includes forming a plurality of bit line structures on a semiconductor substrate, wherein there is a plurality of trenches between the bit line structures. The method also includes forming a first oxide layer conformally covering the bit line structures and the trenches, and forming a photoresist material layer in the trenches and on the first oxide layer, wherein the photoresist material layer has an etch selectivity that is higher than that of the first oxide layer. The method further includes removing the photoresist material layer to form a plurality of capacitor contact holes between the bit line structures, and forming a capacitor contact in the capacitor contact holes. | 2019-10-10 |
20190312038 | SEMICONDUCTOR DEVICE INCLUDING FDSOI TRANSISTORS WITH COMPACT GROUND CONNECTION VIA BACK GATE - The present disclosure provides manufacturing techniques and semiconductor devices in which a contact element at the source side of a pull-down transistor in a RAM cell may connect to the back gate region in a fully depleted SOI transistor architecture. In this manner, the complexity of at least some metallization layers may be reduced, thereby providing the potential of reducing parasitic bit line capacitance. Furthermore, in some illustrative embodiments, the contact regime for connecting the back gate region to a reference potential may be omitted, thereby reducing overall floor space of respective designs. | 2019-10-10 |
20190312039 | 3D SRAM CIRCUIT WITH DOUBLE GATE TRANSISTORS WITH IMPROVED LAYOUT - The application relates to an integrated circuit with SRAM memory and provided with several superimposed levels of transistors, the integrated circuit including SRAM cells provided with a first transistor and a second transistor belonging to an upper level of transistors and each having a double gate composed of an upper electrode and a lower electrode laid out on either side of a semiconductor layer, a lower gate electrode of the first transistor being connected to a lower gate electrode of the second transistor. | 2019-10-10 |
20190312040 | SRAM Circuits with Aligned Gate Electrodes - A device includes a Static Random Access Memory (SRAM) array, and an SRAM cell edge region abutting the SRAM array. The SRAM array and the SRAM cell edge region in combination include first gate electrodes having a uniform pitch. A word line driver abuts the SRAM cell edge region. The word line driver includes second gate electrodes, and the first gate electrodes have lengthwise directions aligned to lengthwise directions of respective ones of the second gate electrodes. | 2019-10-10 |
20190312041 | SEMICONDUCTOR DEVICES INCLUDING SI/GE ACTIVE REGIONS WITH DIFFERENT GE CONCENTRATIONS - In semiconductor devices, some active regions may frequently have to be formed on the basis of a silicon/germanium (Si/Ge) mixture in order to appropriately adjust transistor characteristics, for instance, for P-type transistors. To this end, the present disclosure provides manufacturing techniques and respective devices in which at least two different types of active regions, including Si/Ge material, may be provided with a high degree of compatibility with conventional process strategies. Due to the provision of different germanium concentrations, increased flexibility in adjusting characteristics of transistor elements that require Si/Ge material in their active regions may be achieved. | 2019-10-10 |
20190312042 | METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING SILICON/GERMANIUM ACTIVE REGIONS WITH DIFFERENT GERMANIUM CONCENTRATIONS - A semiconductor device includes a first transistor element having a first channel region and a second transistor element having a second channel region, wherein the first channel region includes a first crystalline silicon/germanium (Si/Ge) material mixture having a first germanium concentration, and wherein the second channel region includes a second crystalline Si/Ge material mixture having a second germanium concentration that is higher than the first germanium concentration. | 2019-10-10 |
20190312043 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided is an inexpensive high-performance split gate MONOS memory. In a manufacturing process of a split gate MONOS memory, a protective layer is formed in an upper part of a control gate electrode before metal substitution of a memory gate electrode. | 2019-10-10 |
20190312044 | HIGH DENSITY PROGRAMMABLE E-FUSE CO-INTEGRATED WITH VERTICAL FETS - A method for integrating vertical transistors and electric fuses includes forming fins through a dielectric layer and a dummy gate stack on a substrate; thinning top portions of the fins by an etch process; epitaxially growing top source/drain regions on thinned portions of the fins in a transistor region and top cathode/anode regions on the thinned portions of the fins in a fuse region; and removing the dummy gate layer and exposing sidewalls of the fins. The fuse region is blocked to form a gate structure in the transistor region. The transistor region is blocked and the fuse region is exposed to conformally deposit a metal on exposed sidewalls of the fins. The metal is annealed to form silicided fins. Portions of the substrate are separated to form bottom source/drain regions for vertical transistors in the transistor region and bottom cathode/anode regions for fuses in the fuse region. | 2019-10-10 |
20190312045 | PARTIALLY DISPOSED GATE LAYER INTO THE TRENCHES - In accordance with some examples, a system comprises a substrate layer having an outer surface. The system also comprises a plurality of trenches extending from the outer surface into the substrate layer. The system then comprises a plurality of active regions with each active region positioned between a different pair of consecutive trenches of the plurality of trenches. The system also comprises a dielectric layer disposed in each of the plurality of trenches and on each of the plurality of active regions. The system then comprises a floating gate layer disposed on the dielectric layer and extending at least partially into each of the plurality of trenches. | 2019-10-10 |
20190312046 | METHOD FOR MAKING NON-VOLATILE MEMORY DEVICE - Method for forming a memory device are disclosed. Embodiments include forming memory cells over a substrate, each memory cell includes a control gate (CG) formed over a floating gate (FG) and a select gate (SG) formed adjacent to a first side of the CG and FG, wherein a vertical oxide layer is formed between the SG and the CG and FG, forming an implant mask layer over a portion of the SG, CG and vertical oxide of each memory cell; and implanting dopants into the substrate using the implant mask to form source drain (S/D) regions between the memory cells. | 2019-10-10 |
20190312047 | Integrated Structures Containing Vertically-Stacked Memory Cells - Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, and having vertically-stacked memory cells within the conductive levels. An opening extends through the stack. Channel material is within the opening and along the memory cells. At least some of the channel material contains germanium. | 2019-10-10 |
20190312048 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - To provide, in an increased production yield, a reliability-improved semiconductor product having both a planar type transistor and a fin type transistor. A semiconductor device having both a planar type transistor and a fin type transistor is manufactured by decreasing the thickness of a hard mask for the formation of element isolation in the planar type transistor region prior to formation of element isolation in the fin type transistor region. | 2019-10-10 |
20190312049 | VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A vertical memory device includes a gate structure including a first gate electrode on a peripheral circuit region of a substrate, the substrate containing a cell region and the peripheral circuit region, a plurality of second gate electrodes sequentially stacked on the cell region of the substrate, the plurality of second gate electrodes spaced apart from each other in a vertical direction to an upper surface of the substrate, a channel extending in the vertical direction on the cell region of the substrate and extending through at least one of the second gate electrodes, and a first insulating interlayer covering the gate structure on the peripheral circuit region of the substrate, a cross-section in one direction of an upper surface of a portion of the first insulating interlayer overlapping the gate structure in the vertical direction having a shape of a portion of a polygon. | 2019-10-10 |
20190312050 | STRING SELECT LINE GATE OXIDE METHOD FOR 3D VERTICAL CHANNEL NAND MEMORY - A memory device includes a stack of conductive strips in a plurality of first levels with a first opening and a conductive strip in the second level with a second opening, both openings exposing sidewalls. Data storage structures are formed on the sidewalls of the conductive strips in the plurality of first levels. A first vertical channel structure including vertical channel films is disposed in the first opening, the vertical channel films in contact with the data storage structures. The second opening is aligned with the first vertical channel structure. A gate dielectric layer is disposed on the sidewall of the conductive strip in the second level. A second vertical channel structure including vertical channel films is disposed in the second opening in contact with the gate dielectric layer on the sidewall of the conductive strip in the second level. | 2019-10-10 |
20190312051 | SEMICONDUCTOR MEMORY DEVICE - Disclosed is a semiconductor memory device comprising a peripheral circuit structure on a first substrate, a second substrate on the peripheral circuit structure, a stack structure on the second substrate and comprising a plurality of gate electrodes, a through dielectric pattern penetrating the stack structure and the second substrate, and a vertical supporter on a top surface of the second substrate and vertically extending from the top surface of the second substrate and penetrating the stack structure and the through dielectric pattern. | 2019-10-10 |
20190312052 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - Provided are three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor memory device includes a plurality of electrode structures provided on a substrate and extending in parallel to each other in one direction and each including electrodes and insulating layers alternately stacked on the substrate, a plurality of vertical structures penetrating the plurality of electrode structures, and an electrode separation structure disposed between two of the plurality of electrode structures adjacent to each other. Each of the electrodes includes an outer portion adjacent to the electrode separation structure, and an inner portion adjacent to the plurality of vertical structures. A thickness of the outer portion is smaller than a thickness of the inner portion. | 2019-10-10 |
20190312053 | NOR FLASH MEMORY AND METHOD OF FABRICATING THE SAME - NOR flash memory that includes three-dimensional memory cells is provided. In the NOR flash memory of the present disclosure, one memory cell includes one memory transistor and one selection transistor. A common source | 2019-10-10 |
20190312054 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICE - A three-dimensional semiconductor device and method of fabrication is provided. The three-dimensional semiconductor device includes a stacked structure on a lower structure. The stacked structure includes interlayer insulating layers and gate electrodes. The device also includes a channel structure on the lower structure, with the channel structure including a horizontal portion between the stacked structure and the lower structure. The channel structure also includes a plurality of vertical portions extended in a vertical direction. The device also includes support patterns on the lower structure. In addition, the device includes a gate dielectric structure having a lower portion and upper portions. The method of fabrication includes forming the stacked structure with holes. The method also includes removing a sacrificial layer from a horizontal area above the lower structure and forming a channel structure within the holes and within a horizontal space made by removal of the sacrificial layer. | 2019-10-10 |
20190312055 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device includes lower gate electrodes on a substrate in a first direction substantially perpendicular to a top surface of the substrate, upper gate electrodes on the lower gate electrodes in the first direction, and channel structures extending through the lower and upper gate electrodes in the first direction. Each channel structure includes a lower channel structure, an upper channel structure, and a landing pad interconnecting the lower and upper channel structures. The first channel structure includes a first landing pad having a horizontal width substantially greater than that of the lower channel structure of the first channel structure at a first vertical level. The second channel structure located closest to the first channel structure includes a second landing pad having a horizontal width substantially greater than that of the lower channel structure of the second channel structure at a second vertical level lower than the first vertical level. | 2019-10-10 |
20190312056 | Elevationally-Extending Strings Of Memory Cells Individually Comprising A Programmable Charge Storage Transistor And Methods Of Processing Silicon Nitride-Comprising Materials - A method comprises forming material to be etched over a substrate. An etch mask comprising a silicon nitride-comprising region is formed elevationally over the material. The etch mask comprises an elevationally-extending mask opening in the silicon nitride-comprising region that has a minimum horizontal open dimension that is greater in an elevationally-innermost portion of the region than in an elevationally-outermost portion of the region. The elevationally-outermost portion has a greater etch rate in at least one of HF and H | 2019-10-10 |
20190312057 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device may be provided. The method may include forming stacks including interlayer insulating layers and separated by a slit, the interlayer insulating layers surrounding a channel layer and stacked to be spaced apart from one another with an interlayer space interposed therebetween. The method may include forming a conductive pattern filling the interlayer space. The method may include forming an isolation layer on a surface of the conductive pattern by oxidizing a portion of the conductive pattern by performing an oxidizing process. | 2019-10-10 |
20190312058 | VOID FORMATION FOR CHARGE TRAP STRUCTURES - Various embodiments include methods and apparatus having a number of charge trap structures, where each charge trap structure includes a dielectric barrier between a gate and a blocking dielectric region, the blocking dielectric region located on a charge trap region of the charge trap structure. At least a portion of the gate can be separated by a void from a region which the charge trap structure is directly disposed. Additional apparatus, systems, and methods are disclosed. | 2019-10-10 |
20190312059 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a substrate; an insulator layer provided on the substrate; a first transistor provided on the insulator layer; a semiconductor layer including a plurality of impurity regions of a first conduction type, the impurity regions forming a part of the first transistor; a heat dissipation layer; a thermal conductive layer linking the semiconductor layer and the heat dissipation layer; and an interruption structure configured to interrupt a flow of a current between the first transistor and the thermal conductive layer. | 2019-10-10 |
20190312060 | ARRAY SUBSTRATES, DISPLAY DEVICES AND METHODS OF MANUFACTURING ARRAY SUBSTRATES - The present application provides an array substrate and a display device. The array substrate includes a substrate provided with a display region and a non-display region. The display region is configured to display. The non-display region includes a groove region. The groove region has a light transmittance greater than that of the display region. The display device includes the above-described array substrate. | 2019-10-10 |
20190312061 | DISPLAY APPARATUS AND METHOD OF MANUFACTRING THE SAME - A display apparatus includes a base substrate, a polysilicon active pattern disposed on the base substrate, including polycrystalline silicon, including a source region and a drain region each doped with impurities and a channel region between the source region and the drain region, and including indium, a first gate electrode overlapping the channel region, and a source electrode electrically connected to the source region and a drain electrode electrically connected to the drain region. | 2019-10-10 |
20190312062 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - One embodiment of the invention is characterized as follows. A display device comprising: a display area including a plurality of pixels, each of the pixels has a first TFT and a second TFT, the first TFT and the second TFT comprise an oxide semiconductor, the first TFT and the second TFT are covered by an interlayer insulating film, a first through hole is formed in the in the interlayer insulating film to connect a drain of the first TFT, wherein a distance d1 between a center of the first through hole and an edge of a channel of the first TFT is shorter than a distance d2 between a center of the first through hole and an edge of a channel of the second TFT, a channel length of the first TFT is shorter than a channel length of the second TFT. | 2019-10-10 |
20190312063 | ANALOG CIRCUIT AND SEMICONDUCTOR DEVICE - An object is to obtain a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range, using a thin film transistor in which an oxide semiconductor layer is used. An analog circuit is formed with the use of a thin film transistor including an oxide semiconductor which has a function as a channel formation layer, has a hydrogen concentration of 5×10 | 2019-10-10 |
20190312064 | SEMICONDUCTOR DEVICE - A semiconductor device includes a oxide semiconductor layer, a gate electrode arranged above the oxide semiconductor layer, a gate insulation layer between the oxide semiconductor layer and the gate electrode, a first insulation layer arranged above the oxide semiconductor layer and arranged with a first aperture part, wiring including an aluminum layer arranged above the first insulation layer, the wiring being electrically connected to the oxide semiconductor layer via the first aperture part, a barrier layer including aluminum oxide above the first insulation layer, above the wiring and covering a side surface of the wiring, and an organic insulation layer arranged above the barrier layer. | 2019-10-10 |
20190312065 | Switching Element, Manufacturing Method Thereof, Array Substrate and Display Device - A switching element, a manufacturing method thereof, an array substrate and a display device are provided. The switching element includes: a base substrate; a first thin-film transistor (TFT), disposed on the base substrate; and a second TFT, disposed on the first TFT, wherein the first TFT includes a first electrode and a second electrode, and the first TFT and the second TFT share the first electrode and the second electrode. | 2019-10-10 |
20190312066 | THIN-FILM NEGATIVE DIFFERENTIAL RESISTANCE AND NEURONAL CIRCUIT - A method is presented for forming a monolithically integrated semiconductor device. The method includes forming a first device including first hydrogenated silicon-based contacts formed on a first portion of a semiconductor material of an insulating substrate and forming a second device including second hydrogenated silicon-based contacts formed on a second portion of the semiconductor material of the insulating substrate. Source and drain contacts of the first device are formed before a gate contact of the first device and a gate contact of the second device is formed before the emitter and collector contacts of the second device. The first device can be a heterojunction field effect transistor (HJFET) and the second device can be a (heterojunction bipolar transistor) HBT. The HJFET and the HBT are integrated in a neuronal circuit and create negative differential resistance by forming a lambda diode. | 2019-10-10 |
20190312067 | SYSTEMS AND METHODS FOR REDUCING SUBSTRATE SURFACE DISRUPTION DURING VIA FORMATION - Embodiments are related to systems and methods for forming vias in a substrate, and more particularly to systems and methods for reducing substrate surface disruption during via formation. | 2019-10-10 |
20190312068 | DISPLAY DEVICE AND ACTIVE ARRAY SWITCH SUBSTRATE THEREOF - This application provides a display device and an active array switch substrate thereof. The active array switch substrate includes: a substrate; active array switches, formed on the substrate, where the active array switch includes a source electrode; at least one solar structure, disposed on the source electrode, where the solar structure includes a solar cell; and a transparent electrode, covered on the solar cell. The solar cell includes an N-type layer, an I-type layer of a microcrystalline silicon structure, and a P-type layer sequentially stacked in a direction away from the source electrode. | 2019-10-10 |
20190312069 | OPTOELECTRONIC DEVICE - An optoelectronic device. The optoelectronic device comprising a substrate having a three-dimensional array of peaks and troughs. Each peak having a first and a second face. The troughs containing a first semiconductor material. The first face of each peak coated with a conductor material and the second face of each peak coated with a second semiconductor material. | 2019-10-10 |
20190312070 | SEMICONDUCTOR DEVICE AND SENSOR INCLUDING A SINGLE PHOTON AVALANCHE DIODE (SPAD) STRUCTURE - A semiconductor device, sensor, and array of SPAD cubes are described. One example of the disclosed sensor includes at least one Single Photon Avalanche Diode (SPAD) cube established in a substrate, the at least one SPAD cube including a photosensitive area that is configured to produce an electrical signal in response to light impacting the photosensitive area, where the photosensitive area is positioned at a first side of the at least one SPAD cube, a contact that receives the electrical signal, where the contact is positioned at a second side of the at least one SPAD cube that opposes the first side of the at least one SPAD cube, and at least one trench that spans an entire thickness of the substrate thereby electrically and optically isolating the at least one SPAD cube from adjacent SPAD cubes. | 2019-10-10 |
20190312071 | IMAGING DEVICE - An imaging device is used that has: a substrate; a first electrode layer disposed on the substrate, and having a first electrode; a first photoelectric conversion film disposed on the first electrode layer; a pixel electrode layer disposed on the first photoelectric conversion film, and having a pixel electrode; a second photoelectric conversion film disposed on the pixel electrode layer; and a second electrode layer disposed on the second photoelectric conversion film, and having a second electrode, wherein at least part of a period from among a first accumulation period during which a signal of the first photoelectric conversion film is accumulated, and a second accumulation period during which a signal of the second photoelectric conversion film is accumulated, does not overlap the other from among the first accumulation period and the second accumulation period. | 2019-10-10 |