41st week of 2012 patent applcation highlights part 12 |
Patent application number | Title | Published |
20120256195 | SEMICONDUCTOR DEVICE - A semiconductor device capable of decreasing a reverse leakage current and a forward voltage is provided. In the semiconductor device, an anode electrode undergoes Schottky junction by being connected to a surface of an SiC epitaxial layer that has the surface, a back surface, and trapezoidal trenches formed on the side of the surface each having side walls and a bottom wall. Furthermore, an edge portion of the bottom wall of each of the trapezoidal trenches is formed to be in the shape bent towards the outside of the trapezoidal trench in the manner that a radius of curvature R satisfies 0.012012-10-11 | |
20120256196 | SCHOTTKY DIODE - A semiconductor system of a Schottky diode is described having an integrated PN diode as a clamping element, which is suitable in particular as a Zener diode having a breakdown voltage of approximately 20 V for use in motor vehicle generator systems. The semiconductor system of the Schottky diode includes a combination of a Schottky diode and a PN diode. The breakdown voltage of the PN diode is much lower than the breakdown voltage of the Schottky diode, the semiconductor system being able to be operated using high currents during breakdown operation. | 2012-10-11 |
20120256197 | ORGANIC ELECTROLUMINESCENCE ELEMENT - The organic electroluminescence device includes an anode, a cathode, a first electron injection layer, an electron transport layer, and a light emitting layer. The first electron injection layer is made of alkali metal and is formed between the anode and the cathode. The electron transport layer is formed between the first electron injection layer and the anode. The light emitting layer is formed between the electron transport layer and the anode. The organic electroluminescence element further includes a second electron injection layer. The second electron injection layer is formed between the first electron injection layer and the electron transport layer. The second electron injection layer is made of amorphous inorganic material. | 2012-10-11 |
20120256198 | LED PACKAGE STRUCTURE FOR INCREASING THE LIGHT UNIFORMING EFFECT - A LED package structure for increasing the light uniforming effect includes a substrate unit, a light emitting unit, a first package unit, and a second package unit. The substrate unit includes at least one substrate body. The light emitting unit includes at least one light emitting element disposed on the at least one substrate body and electrically connected to the at least one substrate body. The first package unit includes a first package resin body formed on the at least one substrate body to cover the at least one light emitting element. The second package unit includes a second package resin body formed on the at least one substrate body to cover the first package resin body. The second package resin body is a light uniforming resin body having a light diffusing material mixed therein, and the second package resin body has an exposed light uniforming surface formed thereon. | 2012-10-11 |
20120256199 | DISPLAY DEVICE AND A METHOD OF MANUFACTURING THE SAME - A display device includes an array substrate, a driving film and an adhesive member. The array substrate includes a first base substrate, a plurality of first signal pads formed on the first base substrate and a first dummy pad formed adjacent to the first signal pads. The driving film includes a base film, a plurality of output terminals formed on the base film and a first alignment mark formed adjacent to the output terminals. The adhesive member adheres the first signal pads to the output terminals, and adheres the first dummy pad to the first alignment mark. | 2012-10-11 |
20120256200 | HIGH EFFICIENCY LEDS - A light emitting device and method of fabricating the same is disclosed that comprises at least one light emitter comprising an active region which emits light. The device further comprising a submount arranged such that the at least one light emitter is mounted to the submount such that the active region is angled in relation to the submount. | 2012-10-11 |
20120256201 | ORGANIC LIGHT EMITTING DIODE DISPLAY AND MANUFACTURING METHOD THEREOF - An OLED display includes: a substrate; an organic light emitting element formed on the substrate and including a first electrode, an emission layer, and a second electrode; and an encapsulation layer formed on the substrate while covering the organic light emitting element. The encapsulation layer includes an organic layer and an inorganic layer, and a protrusion and depression structure is formed in an interface between the organic layer and the inorganic layer. | 2012-10-11 |
20120256202 | ORGANIC LIGHT EMITTING DIODE DISPLAY AND MANUFACTURING METHOD THEREOF - An organic light emitting diode (OLED) display a includes: a substrate; an organic light emitting element on the substrate and including a first electrode, a light emission layer, and a second electrode; and an encapsulation layer on the substrate while covering the organic light emitting element. The encapsulation layer includes an organic layer and an inorganic layer. A mixed area, where organic materials forming the organic layer and inorganic materials forming the inorganic layer co-exist along a plane direction of the encapsulation layer, is formed at the boundary between the organic layer and the inorganic layer. | 2012-10-11 |
20120256203 | ORGANIC LIGHT EMITTING DIODE DISPLAY - An organic light emitting diode display includes a substrate, a display portion on the substrate, and a sealing substrate fixed on the substrate and sealingly engaging the display portion. The sealing substrate is fixed by an adhesive layer that surrounds the display portion. The sealing substrate includes a composite member, at least one conductive portion, and an insulation sheet. The composite member includes a resin base layer and a plurality of carbon fibers. The at least one conductive portion extends over inner and outer sides of the composite member and penetrates the composite member. The at least one conductive portion includes a double-layered structure having a metal foil layer and a plating layer. The insulation sheet is on the outer side of the composite member and the insulation sheet covers the at least one conductive portion | 2012-10-11 |
20120256204 | Light-Emitting Device and a Method of Manufacturing Light-Emitting Device - To provide a highly reliable light-emitting device and especially a light-emitting device which can be formed without use of a metal mask and includes a plurality of light-emitting elements. A structural body at least an end of which has an acute-angled shape is provided so that the end can pass downward through an electrically conductive film formed over the insulating layer and can be at least in contact with an insulating layer having elasticity, thereby physically separating the electrically conductive film, and the electrically conductive films are thus electrically insulated from each other. Such a structure may be provided between adjacent light-emitting elements so that the light-emitting elements can be electrically insulated from each other in the light-emitting device. | 2012-10-11 |
20120256205 | LED LIGHTING MODULE WITH UNIFORM LIGHT OUTPUT - The invention relates to a light emitting diode (LED) module that is characterized by a thermally conductive substrate which is used as the base of the module; and a plurality of cavities positioned on the module; and a plurality of LED semiconductors chips are mounted within each cavity. Within each cavity; secondary cavities are formed and a plurality of LED semiconductors chips are mounted within each of the secondary cavity. A multiple layer configuration of encapsulation is used to fill the cavities to help mix and diffuse the light from the LED chips and ensure that we achieve a uniform light output from the light emitting surface of the module. | 2012-10-11 |
20120256206 | LED MODULE WITH COOLING PASSAGE - An LED module with a cooling passage is disclosed. The LED module includes a light source unit having a plurality of LED's which provide light through an appropriate power supply, and one or more cooling units which form said cooling passage, which combine heat generated from the LEDs with ambient heat and discharges the combined heat in an opposite direction. | 2012-10-11 |
20120256207 | ILLUMINATION DEVICE AND DISPLAY APPARATUS - An illumination device includes: a substrate; a first transparent electrode covering approximately an entire surface of a display region of the substrate; a second transparent electrode which overlaps with the first transparent electrode when seen in plan view and covers approximately the entire surface of the display region; and a plurality of island shaped light emitting elements disposed between the first transparent electrode and the second transparent electrode. The first and second transparent electrodes are formed as single continuous films. | 2012-10-11 |
20120256208 | Light-Emitting Device, Electronic Appliance, and Lighting Device - A light-emitting device and a lighting device each of which includes a plurality of light-emitting elements exhibiting light with different wavelengths are provided. The light-emitting device and the lighting device each have an element structure in which each of the light-emitting elements emits only light with a desired wavelength, and thus the light-emitting elements have favorable color purity. In the light-emitting element emitting light (λ | 2012-10-11 |
20120256209 | Organic Light Emitting Element and Display Device Using the Element - A hole transporting region made of a hole transporting material, an electron transporting region made of an electron transporting material, and a mixed region (light emitting region) in which both the hole transporting material and the electron transporting material are mixed and which is doped with a triplet light emitting material for red color are provided in an organic compound film, whereby interfaces between respective layers which exist in a conventional lamination structure are eliminated, and respective functions of hole transportation, electron transportation, and light emission are exhibited. In accordance with the above-mentioned method, the organic light emitting element for red color can be obtained in which power consumption is low and a life thereof is long. Thus, the display device and the electric device are manufactured by using the organic light emitting element. | 2012-10-11 |
20120256210 | LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE PACKAGE HAVING THE SAME - Disclosed are a light emitting device. The light emitting device includes a light emitting structure including a first and second conductive semiconductors, and an active layer; an insulating layer on a lateral surface of the light emitting structure; an electrode on the first conductive semiconductor layer; an electrode layer under the second conductive semiconductor layer; and a protective layer including a first portion between the light emitting structure and the electrode layer and a second portion extending outward beyond a lower surface of the light emitting structure, wherein the first conductive semiconductor layer includes a first top surface including a roughness on a first region, and a second top surface lower than the first region and being closer the lateral surface of the light emitting structure than the first region, wherein the second top surface is disposed on an edge portion of the first conductive semiconductor layer. | 2012-10-11 |
20120256211 | METHODS OF FABRICATING LIGHT EMITTING DEVICES INCLUDING MULTIPLE SEQUENCED LUMINOPHORIC LAYERS, AND DEVICES SO FABRICATED - An LED includes a first pedestal and may be fabricated by coating a first phosphor layer on the LED, thinning the first phosphor layer to expose the first pedestal, forming a second pedestal on the first pedestal, coating a second phosphor layer and thinning the second phosphor layer to expose the second pedestal. Alternatively, an LED having a pedestal is coated with a first phosphor layer, coated with a second phosphor layer and then planarized to expose the pedestal. Related structures are also provided. | 2012-10-11 |
20120256212 | TUNABLE PHOSPHOR FOR LUMINESCENT - The present disclosure provides an illuminating system including a light emitting diode (LED); and a tunable luminescent material disposed approximate the light-emitting diode, wherein the tunable luminescent material includes alkaline earth metal (AE) and silicon aluminum nitride doped by a rare earth element (RE), formulated as (AE)Si | 2012-10-11 |
20120256213 | LED STRUCTURE AND MANUFACTURING METHOD THEREOF - The present invention discloses an LED structure and a manufacturing method thereof. The LED structure has a housing, an LED chip and a transparent encapsulant. The housing has a recess and at least one protruded wall. The LED chip is received in the recess. The transparent encapsulant is formed by dispensing a molding compound into the recess by an adhesive dispenser. The transparent encapsulant has an edge matched with an edge of the recess to encapsulate the LED chip in the recess, and has a height smaller than that of the protruded wall. The LED chip of the LED structure of the present invention can emit light through the spherical surface of the transparent encapsulant based on a greater visual angle, and thus enhance the light extraction efficiency. | 2012-10-11 |
20120256214 | LED PACKAGE STRUCTURE - The present invention discloses an LED package structure which has a housing, an LED chip and a transparent encapsulant. The housing has a recess and a plurality of protrusions. The LED chip is mounted in the recess of the housing, and covered in the recess by the transparent encapsulant. The protrusions are formed in the recess or on the edge of the housing. The protrusions of the present invention can form the uneven shape of the surface of the transparent encapsulant, so as to increase the diffusion angle of the light and enhance the light extraction efficiency. | 2012-10-11 |
20120256215 | PACKAGE HAVING LIGHT-EMITTING ELEMENT AND FABRICATION METHOD THEREOF - A package having a light-emitting element includes a substrate having a light-emitting element disposed thereon, an insulating layer formed on the substrate and having an opening for exposing the light-emitting element, a florescent layer formed in the opening of the insulating layer for encapsulating the light-emitting element, and a transparent material formed on the florescent layer and the insulating layer. As such, a specific space can be defined by the insulating layer for exposing the light-emitting element and forming the fluorescent layer, thereby overcoming the problem of non-uniform coating of phosphor powder as encountered in prior techniques. | 2012-10-11 |
20120256216 | ORGANIC LIGHT EMITTING DIODE DEVICE - An organic light emitting diode device is disclosed. The organic light emitting diode device includes a substrate, a first electrode layer, a first insulating layer, at least one controlling electrode layer, a second insulating layer, at least one light emitting layer, a third insulating layer, and a second electrode layer. The first electrode layer is formed on the substrate and includes a first area and a second area adjacent to the first area. The first insulating layer, the controlling electrode layer, and the second insulating layer are sequentially formed on the first area. The light emitting layer is formed on the second area. The second electrode layer is formed on the light emitting layer. In the present invention, the controlling electrode layer controls a recombination region of electron-hole pair so as to achieve an objective of adjusting a color temperature. | 2012-10-11 |
20120256217 | LIGHT-EMITTING DIODE PACKAGE - A light-emitting diode (LED) package including a substrate, an LED chip, a polarizer, and a supporter is provided. The LED chip is disposed on the substrate. The polarizer is disposed above the LED chip. The supporter is disposed on the substrate for supporting the polarizer. | 2012-10-11 |
20120256218 | ORGANIC LIGHT EMITTING DIODE DISPLAY - An organic light-emitting diode (OLED) display according to an exemplary embodiment may include: a substrate and an organic light emitting element on the substrate; a thin film encapsulation layer on the substrate and covering the organic light emitting element; and one or more scattering materials dispersed in the thin film encapsulation layer. According to the exemplary embodiment, light efficiency may be improved by dispersing scattering materials in at least one of an organic layer or an inorganic layer forming a thin film encapsulation layer with a large refractive index difference. | 2012-10-11 |
20120256219 | LIGHT EMITTING DIODE PACKAGE AND METHOD OF MANUFACTURING THE SAME - An LED package includes a substrate, an electrode layer, a light-emitting chip, a reflection cup and an encapsulation. The substrate includes a first surface, an opposite second surface, and two side surfaces. The electrode layer is consisted of a positive electrode and a negative electrode, each of which extends from the first surface to the second surface via a respective side surface. The light-emitting chip is located on the first surface of the substrate and electrically connected to the electrode layer. The reflection cup comprises a first part covering the electrode layer on the side surfaces of the substrate, a second part with a bowl-like shape on the first surface of the substrate and surrounding the light-emitting chip. The encapsulation is filled in the second part of the reflection cup. | 2012-10-11 |
20120256220 | ENCAPSULATING SHEET, LIGHT EMITTING DIODE DEVICE, AND A METHOD FOR PRODUCING THE SAME - An encapsulating sheet is stuck to a substrate mounted with a light emitting diode to encapsulate the light emitting diode. The encapsulating sheet includes an encapsulating material layer in which an embedding region is defined, the embedding region for embedding the light emitting diode from one side surface of the encapsulating material layer; a first phosphor layer laminated on the other side surface of the encapsulating material layer; and a second phosphor layer laminated on one side surface of the encapsulating material layer so as to be spaced apart from the embedding region. | 2012-10-11 |
20120256221 | LIFE-IMPROVED SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device includes first and second semiconductor layers, an active region, a transparent electrically-conducting layer | 2012-10-11 |
20120256222 | PHOSPHOR AND LIGHT-EMITTING DEVICE - A phosphor has the general formula (M | 2012-10-11 |
20120256223 | LIGHT EMISSION DEVICE - Disclosed are a light emission device comprising an LED element and a wavelength conversion section, the LED element emitting light of a specific wavelength and the wavelength conversion section converting the light emitted from the LED element to light of a specific wavelength, featured in that the wavelength conversion section is composed of a ceramic layer which has been formed employing, as a raw material, polysilazane containing a phosphor and inorganic fine particles with a particle size smaller than the phosphor. | 2012-10-11 |
20120256224 | INSULATED SUBSTRATE, PROCESS FOR PRODUCTION OF INSULATED SUBSTRATE, PROCESS FOR FORMATION OF WIRING LINE, WIRING SUBSTRATE, AND LIGHT-EMITTING ELEMENT - Provided is an insulating substrate which includes an aluminum substrate and an anodized film covering a whole surface of the aluminum substrate and in which the anodized film contains intermetallic compound particles with a circle equivalent diameter of 1 μm or more in an amount of up to 2,000 pcs/mm | 2012-10-11 |
20120256225 | SEMICONDUCTOR DEVICE PACKAGE INCLUDING A PASTE MEMBER - A semiconductor device package is provided. The semiconductor device package comprises a package body; a plurality of electrodes comprising a first electrode on the package body; a paste member on the first electrode and comprising inorganic fillers and metal powder; and a semiconductor device die-bonded on the paste member, wherein a die-bonding region of the first electrode comprises a paste groove having a predetermined depth and the paste member is formed in the paste groove. | 2012-10-11 |
20120256226 | LIGHT EMITTING DEVICE, LIGHT EMITTING DEVICE PACKAGE AND LIGHTING SYSTEM INCLUDING THE SAME - A light emitting device including a second conductive type semiconductor layer; an active layer over the second conductive type semiconductor layer; a first conductive type semiconductor layer over the active layer; a second electrode in a first region under the second conductive type semiconductor layer; a current blocking layer including a metal; and a first electrode over the first conductive type semiconductor layer. Further, the first electrode has at least one portion that vertically overlaps the current blocking layer. | 2012-10-11 |
20120256227 | Light Emitting Device and Method for Manufacturing Thereof - A conductive layer serving as an auxiliary wiring is formed under a first electrode with a first insulating layer interposed therebetween, and the conductive layer and a second electrode are electrically connected to each other through an opening in the first insulating layer and the first electrode. A second insulating layer is formed over a sidewall of the opening so that the first electrode is not directly in contact with the second electrode in the opening. An EL layer is formed by evaporation in a state where a deposition target substrate is inclined to an evaporation source, so that the second insulating layer serves as an obstacle and a region where the EL layer is not formed by the evaporation and the conductive layer is exposed is formed in part of the opening in a self-aligned manner. | 2012-10-11 |
20120256228 | DIE-BONDED LED - An LED includes a first intermetallic layer, a first metal thin film layer, an LED chip, a substrate, a second metal thin film layer, and a second intermetallic layer. The first metal thin film layer is located on the first intermetallic layer. The LED chip is located on the first metal thin film layer. The second metal thin film layer is located on the substrate. The second intermetallic layer is located on the second metal thin film layer, and the first intermetallic layer is located on the second intermetallic layer. Materials of the first and the second metal thin film layer are selected from a group consisting of Au, Ag, Cu, and Ni. Materials of the intermetallic layers are selected from a group consisting of a Cu—In—Sn intermetallics, an Ni—In—Sn intermetallics, an Ni—Bi intermetallics, an Au—In intermetallics, an Ag—In intermetallics, an Ag—Sn intermetallics, and an Au—Bi intermetallics. | 2012-10-11 |
20120256229 | Electrostatic discharge protection device and Electrostatic discharge protection circuit thereof - The ESD protection device includes a substrate, a well, a first doped region and a second doped region. The substrate has a first conductive type, and the substrate is electrically connected to a first power node. The well has a second conductive type, and is disposed in the substrate. The first doped region has the first conductive type, and is disposed in the well. The first doped region and the well are electrically connected to a second power node. The second doped region has the second conductive type, and is disposed in the substrate. The second doped region is in a floating state. | 2012-10-11 |
20120256230 | POWER DEVICE WITH TRENCHED GATE STRUCTURE AND METHOD OF FABRICATING THE SAME - A power device with trenched gate structure, includes: a substrate having a first face and a second face opposing to the first face, a body region of a first conductivity type disposed in the substrate, a base region of a second conductivity type disposed in the body region, a cathode region of the first conductivity type disposed in the base region, an anode region of the second conductivity type disposed in the substrate at the second face a trench disposed in the substrate and extending from the first face into the body region, and the cathode region encompassing the trench, wherein the trench has a wavelike sidewall, a gate structure disposed in the trench and an accumulation region disposed in the body region and along the wavelike sidewall. The wavelike sidewall can increase the base current of the bipolar transistor and increase the performance of the IGBT. | 2012-10-11 |
20120256231 | LOW VOLTAGE PNPN PROTECTION DEVICE - A low voltage protection device that includes a silicon substrate comprises an inner layer of a first dopant type. The device also includes a first outer layer of a second dopant type disposed adjacent a first surface of the inner layer and a second outer layer of the second dopant type disposed adjacent a second surface of the inner layer opposite the first surface. The device further includes a first mesa region disposed in a peripheral region of a first side of the low voltage protection device. The first mesa region includes a first area that includes a peripheral portion of a cathode of the low voltage protection device, the cathode formed by diffusing a high concentration of dopant species of the first type on a first surface of the silicon substrate, and a second area comprising a high concentration of diffused dopant species of the second type. | 2012-10-11 |
20120256232 | Multilayer Rare Earth Device - Examples of device structures utilizing layers of rare earth oxides to perform the tasks of strain engineering in transitioning between semiconductor layers of different composition and/or lattice orientation and size are given. A structure comprising a plurality of semiconductor layers separated by transition layer(s) comprising two or more rare earth compounds operable as a sink for structural defects is disclosed. | 2012-10-11 |
20120256233 | ELECTROSTATIC DISCHARGE SHUNTING CIRCUIT - An integrated electrostatic discharge (ESD) shunting circuit includes a III-V semiconductor layer, and a first drain-less high electron mobility transistor (HEMT) or a metal-semiconductor FET (MESFET) transistor having a first gate and at least a second drain-less HEMT or MESFET having a second gate formed in the substrate. The HEMTs or MESFETs include a donor layer on the semiconductor layer, no drains, and a source including an ohmic contact layer on the donor layer. | 2012-10-11 |
20120256234 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - First, second, and third power wirings and plurality of first signal wirings are formed on the upper layer of a semiconductor substrate, and at least one second signal wiring is formed on the upper layer of the plurality of first signal wirings. First and second power wirings are mutually separated in the cell height direction and extended in the cell width direction. Third power wiring extends between the first and second power wirings in the cell width direction. The plurality of first signal wirings are separated from first, second, and third power wirings, and electrically connected to at least one of the plurality of circuit elements. At least one second signal wiring extends in the cell width direction, and electrically connected to at least one of the plurality of circuit elements and the plurality of first signal wirings. | 2012-10-11 |
20120256235 | LAYOUT SCHEME AND METHOD FOR FORMING DEVICE CELLS IN SEMICONDUCTOR DEVICES - A method and layout for forming word line decoder devices and other devices having word line decoder cells provides for forming metal interconnect layers using non-DPL photolithography operations and provides for stitching distally disposed transistors using a lower or intermediate metal layer or a subjacent conductive material. The transistors may be disposed in or adjacent longitudinally arranged word line decoder or other cells and the conductive coupling using the metal or conductive material lowers gate resistance between transistors and avoids RC signal delays. | 2012-10-11 |
20120256236 | INTEGRATED CMOS POROUS SENSOR - A single chip wireless sensor comprises a microcontroller connected by a transmit/receive interface to a wireless antenna. The microcontroller is also connected to an 8 kB RAM, a USB interface, an RS232 interface, 64 kB flash memory, and a 32 kHz crystal. The device senses humidity and temperature, and a humidity sensor is connected by an 18 bit ΣΔ A-to-D converter to the microcontroller and a temperature sensor is connected by a 12 bit SAR A-to-D converter to the microcontroller. The device is an integrated chip manufactured in a single process in which both the electronics and sensor components are manufactured using standard CMOS processing techniques, applied to achieve both electronic and sensing components in an integrated process. | 2012-10-11 |
20120256237 | EMBEDDED MEMS SENSORS AND RELATED METHODS - Embodiments of embedded MEMS sensors and related methods are described herein. Other embodiments and related methods are also disclosed herein. | 2012-10-11 |
20120256238 | Junction Field Effect Transistor With An Epitaxially Grown Gate Structure - A method of fabricating a semiconductor device that includes forming a replacement gate structure on a portion of a semiconductor substrate, wherein source regions and drain regions are formed in opposing sides of the replacement gate structure. A dielectric is formed on the semiconductor substrate having an upper surface that is coplanar with an upper surface of the replacement gate structure. The replacement gate structure is removed to provide an opening to an exposed portion of the semiconductor substrate. A functional gate conductor is epitaxially grown within the opening in direct contact with the exposed portion of the semiconductor substrate. The method is applicable to planar metal oxide semiconductor field effect transistors (MOSFETs) and fin field effect transistors (finFETs). | 2012-10-11 |
20120256239 | Ultra-Thin Power Transistor and Synchronous Buck Converter Having Customized Footprint - A packaged power transistor device ( | 2012-10-11 |
20120256240 | METHOD FOR INCREASING PENETRATION DEPTH OF DRAIN AND SOURCE IMPLANTATION SPECIES FOR A GIVEN GATE HEIGHT - The thickness of drain and source areas may be reduced by a cavity etch used for refilling the cavities with an appropriate semiconductor material, wherein, prior to the epitaxial growth, an implantation process may be performed so as to allow the formation of deep drain and source areas without contributing to unwanted channel doping for a given critical gate height. In other cases, the effective ion blocking length of the gate electrode structure may be enhanced by performing a tilted implantation step for incorporating deep drain and source regions. | 2012-10-11 |
20120256241 | Semiconductor Device and Method of Driving the Same - To provide a semiconductor device and a driving method of the same that is capable of enlarging a signal amplitude value as well as increasing a range in which a linear input/output relationship operates while preventing a signal writing-in time from becoming long. The semiconductor device having an amplifying transistor and a biasing transistor and the driving method thereof, wherein an electric discharging transistor is provided and pre-discharge is performed. | 2012-10-11 |
20120256242 | SEMICONDUCTOR NANOWIRE STRUCTURE REUSING SUSPENSION PADS - An integrated circuit apparatus is provided and includes first and second silicon-on-insulator (SOI) pads formed on an insulator substrate, each of the first and second SOI pads including an active area formed thereon, a nanowire suspended between the first and second SOI pads over the insulator substrate, one or more field effect transistors (FETs) operably disposed along the nanowire and a planar device operably disposed on at least one of the respective active areas formed on each of the first and second SOI pads. | 2012-10-11 |
20120256243 | SEMICONDUCTOR DEVICE FOR REDUCING INTERCONNECT PITCH - A semiconductor device includes a plurality of transistors formed on a semiconductor substrate, a first local wiring which is electrically connected to at least one of the plurality of transistors and extending in a first direction, a second local wiring which is formed above the first local wiring and which electrically connects to at least one of the plurality of transistors and extends in a second direction, a plurality of first wirings which are formed above the second local wiring and which extend in a third direction, at least each of the plurality of first wirings being electrically connected to the first local wiring and the second local wiring, respectively, and a second wiring which is formed above the first wiring and which electrically connects to at least one of the plurality of first wirings and extends in a fourth direction. | 2012-10-11 |
20120256244 | Methods of Forming Field Effect Transistors, Pluralities of Field Effect Transistors, and DRAM Circuitry Comprising a Plurality of Individual Memory Cells - A method of forming a field effect transistor includes forming trench isolation material within a semiconductor substrate and on opposing sides of a semiconductor material channel region along a length of the channel region. The trench isolation material is formed to comprise opposing insulative projections extending toward one another partially under the channel region along the channel length and with semiconductor material being received over the projections. The trench isolation material is etched to expose opposing sides of the semiconductor material along the channel length. The exposed opposing sides of the semiconductor material are etched along the channel length to form a channel fin projecting upwardly relative to the projections. A gate is formed over a top and opposing sides of the fin along the channel length. Other methods and structures are disclosed. | 2012-10-11 |
20120256245 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device in accordance with one embodiment of the invention can include a semiconductor substrate having a groove, a bit line, a pocket implantation region, a bottom insulating membrane, and a charge accumulation region. The bit line is formed on a side of the groove in the semiconductor substrate and acts as a source and a drain. The pocket implantation region is formed to touch (or contact) the bit line, has a similar conductivity type as the semiconductor substrate, and has a dopant concentration higher than that of the semiconductor substrate. The bottom insulating membrane is formed on and touches (or contacts) a side surface of the groove. The charge accumulation layer is formed on and touches (or contacts) a side surface of the bottom insulating membrane. | 2012-10-11 |
20120256246 | SEMICONDUCTOR DEVICE INCLUDING A FLOATING GATE - A semiconductor device includes a semiconductor layer with a trench dug downward from its surface, a source region formed on a surface layer portion adjacent to a first side of the trench in a prescribed direction, a drain region formed on the surface layer portion, adjacent to a second side of the trench opposite to the first side in the prescribed direction, a first insulating film on the bottom surface and the side surface of the trench, a floating gate stacked on the first insulating film and opposed to the bottom surface and the side surface of the trench through the first insulating film, a second insulating film formed on the floating gate, and a control gate at least partially embedded in the trench so that the portion embedded in the trench is opposed to the floating gate through the second insulating film. | 2012-10-11 |
20120256247 | 3D Vertical NAND and Method of Making Thereof by Front and Back Side Processing - Monolithic three dimensional NAND strings and methods of making. The method includes both front side and back side processing. Using the combination of front side and back side processing, a NAND string can be formed that includes an air gap between the floating gates in the NAND string. The NAND string may be formed with a single vertical channel. Alternatively, the NAND string may have a U shape with two vertical channels connected with a horizontal channel. | 2012-10-11 |
20120256248 | STRUCTURE AND FABRICATION METHOD OF TUNNEL FIELD EFFECT TRANSISTOR WITH INCREASED DRIVE CURRENT AND REDUCED GATE INDUCED DRAIN LEAKAGE (GIDL) - Gate induced drain leakage in a tunnel field effect transistor is reduced while drive current is increased by orienting adjacent semiconductor bodies, based on their respective crystal orientations or axes, to optimize band-to-band tunneling at junctions. Maximizing band-to-band tunneling at a source-channel junction increases drive current, while minimizing band-to-band tunneling at a channel-drain junction decreases GIDL. GIDL can be reduced by an order of magnitude in an embodiment. Power consumption for a given frequency can also be reduced by an order of magnitude. | 2012-10-11 |
20120256249 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A MONOS type non-volatile semiconductor memory device which is capable of electrically writing, erasing, reading and retaining data, the memory device including source/drain regions, a first gate insulating layer, a first charge trapping layer formed on the first gate insulating layer, a second gate insulating layer formed on the first charge trapping layer, and a controlling electrode formed on the second gate insulating layer. The first charge trapping layer includes an insulating film containing Al and O as major elements and having a defect pair formed of a complex of an interstitial O atom and a tetravalent cationic atom substituting for an Al atom, the insulating film also having electron unoccupied levels within the range of 2 eV-6 eV as measured from the valence band maximum of Al | 2012-10-11 |
20120256250 | Power Transistor Device Vertical Integration - A semiconductor component includes a sequence of layers, the sequence of layers including a first insulator layer, a first semiconductor layer disposed on the first insulator layer, a second insulator layer disposed on the first semiconductor layer, and a second semiconductor layer disposed on the second insulator layer. The semiconductor component also includes a plurality of devices at least partly formed in the first semiconductor layer. A first one of the plurality of devices is a power transistor formed in a first region of the first semiconductor layer and a first region of the second semiconductor layer. The first region of the first and second semiconductor layers are in electrical contact with one another through a first opening in the second insulator layer. | 2012-10-11 |
20120256251 | SEMICONDUCTOR DEVICE - An ESD protection element is disclosed in which LOCOS oxide films are formed at both ends of a gate electrode, and a conductivity type of a diffusion layer formed below one of the LOCOS oxide films which is not located on a drain side is set to a p-type, to thereby limit an amount of a current flowing in a portion below a source-side n-type high concentration diffusion layer, the current being generated due to surface breakdown of a drain. With this structure, even in a case of protecting a high withstanding voltage element, it is possible to maintain an off-state during a steady state, while operating, upon application of a surge or noise to a semiconductor device, so as not to reach a breakage of an internal element, discharging a generated large current, and then returning to the off-state again. | 2012-10-11 |
20120256252 | COMPATIBLE VERTICAL DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR TRANSISTOR AND LATERAL DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR TRANSISTOR AND MANUFACTURE METHOD THEREOF - A method for manufacturing compatible vertical double diffused metal oxide semiconductor (VDMOS) transistor and lateral double diffused metal oxide semiconductor (LDMOS) transistor includes: providing a substrate having an LDMOS transistor region and a VDMOS transistor region; forming an N-buried region in the substrate; forming an epitaxial layer on the N-buried layer region; forming isolation regions in the LDMOS transistor region and the VDMOS transistor region; forming a drift region in the LDMOS transistor region; forming gates in the LDMOS transistor region and the VDMOS transistor region; forming PBODY regions in the LDMOS transistor region and the VDMOS transistor region; forming an N-type GRADE region in the LDMOS transistor region; forming an NSINK region in the VDMOS transistor region, where the NSINK region is in contact with the N-buried layer region; forming sources and drains in the LDMOS transistor region and the VDMOS transistor region; and forming a P+ region in the LDMOS transistor region, where the P+ region is in contact with the source. | 2012-10-11 |
20120256253 | Vertical Memory Devices - Vertical memory devices include a channel, a ground selection line (GSL), a word line, a string selection line (SSL), a pad and an etch-stop layer. The channel extends in a first direction on a substrate. The channel includes an impurity region and the first direction is perpendicular to a top surface of the substrate. At least one GSL, a plurality of the word lines and at least one SSL are spaced apart from each other in the first direction on a sidewall of the channel. The pad is disposed on a top surface of the channel. The etch-stop layer contacts the pad. | 2012-10-11 |
20120256254 | STRUCTURE AND FABRICATION PROCESS OF SUPER JUNCTION MOSFET - This invention discloses a specific superjunction MOSFET structure and its fabrication process. Such structure includes: a drain, a substrate, an EPI, a source, a side-wall isolation structure, a gate, a gate isolation layer and source. There is an isolation layer inside the active area underneath the source. Along the side-wall of this isolation layer, a buffer layer with same doping type as body can be introduced & source can be extended down too to form field plate. Such buffer layer & field plate can make the EPI doping much higher than convention device which results in lower Rdson, better performance, shorter gate so that to reduce both gate charge Qg and gate-to-drain charge Qgd. The process to make such structure is simpler and more cost effective. | 2012-10-11 |
20120256255 | RECESSED TRENCH GATE STRUCTURE AND METHOD OF FABRICATING THE SAME - A recessed trench gate structure is provided. The recessed trench gate structure includes a substrate with a recessed trench, a gate dielectric layer disposed around an inner surface of the recessed trench, a lower gate conductor disposed at a lower portion of the recessed trench and on the gate dielectric layer. Specially, the lower gate conductor has a convex top surface. A spacer is disposed along an inner side wall of a upper portion of the recessed trench and a upper gate conductor is disposed on the lower gate conductor. The convex top surface can prevent the electric field from distributing not uniformly, so that the GIDL can be prevented. | 2012-10-11 |
20120256256 | RECESSED GATE TRANSISTOR WITH CYLINDRICAL FINS - A recessed gate transistor with cylindrical fins is disclosed. The recessed gate transistor is disposed in an active region of a semiconductor substrate. Two isolation regions disposed in the semiconductor substrate to define an active region therebetween. The recessed gate transistor includes a gate structure, a source doping region and a drain doping region. The gate structure has at least three fins forms a concave and convex bottom of the gate structure. The front fin is disposed in one of the two isolation regions, the middle fin is disposed in the active region and a last fin disposed in the other one of the two isolation regions. The front fin and the last fin are both cylindrical. A lower part of the gate structure is M-shaped when view from the source doping region to the drain doping region direction. | 2012-10-11 |
20120256257 | TRANSISTOR WITH BURIED FINS - The present invention disclosed a recessed gate transistor with buried fins. The recessed gate transistor with buried fins is disposed in an active region on a semiconductor substrate. Two isolation regions disposed in the semiconductor substrate, and sandwich the active region. A gate structure is disposed in the semiconductor substrate, wherein the gate structure includes: an upper part and a lower part. The upper part is disposed in the active region and a lower part having a front fin disposed in one of the two isolation regions, at least one middle fin disposed in the active region, and a last fin disposed in the other one of the two isolation regions, wherein the front fin are both elliptic cylindrical. | 2012-10-11 |
20120256258 | TRENCH POWER MOSFET STRUCTURE WITH HIGH CELL DENSITY AND FABRICATION METHOD THEREOF - A fabrication method of a high cell density trench power MOSFET structure is provided. Form at least a gate trench in a silicon substrate and a gate dielectric layer on the silicon substrate. Form a gate polysilicon structure in the gate trench and cover by a passivation layer. Form a first-conductive-type body region in the silicon substrate and implant impurities with a second conductive type thereof to form a source doped region. Expose the gate polysilicon structure and the source doped region. Form a dielectric spacer having a predetermined thickness on a sidewall of the gate trench. Deposit metal on the gate polysilicon structure and the source doped region. A first and a second self-aligned silicide layer are respectively formed on the gate polysilicon structure and the source doped region. The dielectric spacer forms an appropriate distance between the first and the second self-aligned silicide layer. | 2012-10-11 |
20120256259 | SINGLE-SIDED ACCESS DEVICE AND FABRICATION METHOD THEREOF - The present invention provides a single-sided access device including an active fin structure comprising a source region and a drain region; an insulating layer interposed between the source region and the drain region; a trench isolation structure disposed at one side of the active fin structure; a single-sided sidewall gate electrode disposed on the other side of the active fin structure opposite to the trench isolation structure so that the active fin structure is sandwiched by trench isolation structure and the single-sided sidewall gate electrode; and a gate protrusion laterally and electrically extended from the single-sided sidewall gate electrode and embedded between the source region and the drain region under the insulating layer. | 2012-10-11 |
20120256260 | DUAL-DEPTH SELF-ALIGNED ISOLATION STRUCTURE FOR A BACK GATE ELECTRODE - Doped semiconductor back gate regions self-aligned to active regions are formed by first patterning a top semiconductor layer and a buried insulator layer to form stacks of a buried insulator portion and a semiconductor portion. Oxygen is implanted into an underlying semiconductor layer at an angle so that oxygen-implanted regions are formed in areas that are not shaded by the stack or masking structures thereupon. The oxygen implanted portions are converted into deep trench isolation structures that are self-aligned to sidewalls of the active regions, which are the semiconductor portions in the stacks. Dopant ions are implanted into the portions of the underlying semiconductor layer between the deep trench isolation structures to form doped semiconductor back gate regions. A shallow trench isolation structure is formed on the deep trench isolation structures and between the stacks. | 2012-10-11 |
20120256261 | SEMICONDUCTOR DEVICE AND METHOD FOR MAKING SAME - A semiconductor device including a substrate having at least one nitride material lined isolation cavity; and a hafnium containing dielectric fill at least partially contained in and at least partially covering at least a portion of the at least one nitride lined isolation cavity. | 2012-10-11 |
20120256262 | FIELD EFFECT TRANSISTOR WITH OFFSET COUNTER-ELECTRODE CONTACT - The field effect transistor comprises a substrate successively comprising an electrically conducting support substrate, an electrically insulating layer and a semiconductor material layer. The counter-electrode is formed in a first portion of the support substrate facing the semi-conductor material layer. The insulating pattern surrounds the semi-conductor material layer to delineate a first active area and it penetrates partially into the support layer to delineate the first portion. An electrically conducting contact passes through the insulating pattern from a first lateral surface in contact with the counter-electrode through to a second surface. The contact is electrically connected to the counter-electrode. | 2012-10-11 |
20120256263 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor storage device includes an interlayer insulating film provided between select gate electrodes, a first fill material extending along upper portions of memory cell gate electrodes so as to cover air gaps residing between the memory cell gate electrodes, the first fill material extending along sidewalls of the select gate electrodes and sidewalls of the interlayer insulating film so as to define a recess above the first fill material extending along the sidewalls of the select gate electrodes and the sidewalls of the interlayer insulating film, a second fill material filling the recess above the first fill material, and a plurality of contacts formed through the interlayer insulating film, the contacts physically contacting each of device areas formed in a semiconductor substrate. | 2012-10-11 |
20120256264 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD - A semiconductor device includes a semiconductor substrate including a well having a first conductivity type defined by a device isolation region, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film and including a first side surface and a second side surface facing the first side surface, and a first side wall insulating film formed on the first side surface and a second side wall insulating film formed on the second side surface. | 2012-10-11 |
20120256265 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A first source/drain region is formed outside a first insulating sidewall spacer, as viewed from a first gate electrode, in a semiconductor substrate. A second source/drain region is formed outside a second insulating sidewall spacer, as viewed from a second gate electrode, in the semiconductor substrate. The second source/drain region includes a silicon mixed-crystal layer. The second gate electrode has a lower height than the first gate electrode. | 2012-10-11 |
20120256266 | SEMICONDUCTOR DEVICE - A semiconductor device has a first MIS transistor. The first MIS transistor includes a first source/drain region of a first conductivity type which includes a silicon compound layer causing a first stress in a gate length direction of a channel region in a first active region, and a stress insulating film which is formed on the first active region to cover a first gate electrode, a first sidewall, and the first source/drain region, and which causes a second stress opposite to the first stress. An uppermost surface of the silicon compound layer is located higher than a surface of a semiconductor substrate located directly under the first gate electrode. A first stress-relief film is formed in a space between the silicon compound layer and the first sidewall. | 2012-10-11 |
20120256267 | Electrical Fuse Formed By Replacement Metal Gate Process - A method is provided for fabricating an electrical fuse and a field effect transistor having a metal gate which includes removing material from first and second openings in a dielectric region overlying a substrate, wherein the first opening is aligned with an active semiconductor region of the substrate, and the second opening is aligned with an isolation region of the substrate, and the active semiconductor region including a source region and a drain region adjacent edges of the first opening. An electrical fuse can be formed which has a fuse element filling the second opening, the fuse element being a monolithic region of a single conductive material being a metal or a conductive compound of a metal. A metal gate can be formed which extends within the first opening to define a field effect transistor (“FET”) which includes the metal gate and the active semiconductor region. | 2012-10-11 |
20120256268 | INTEGRATED CIRCUIT STRUCTURE HAVING SUBSTANTIALLY PLANAR N-P STEP HEIGHT AND METHODS OF FORMING - Solutions for forming an integrated circuit structure having a substantially planar N-P step height are disclosed. In one embodiment, a method includes: providing a structure having an n-type field effect transistor (NFET) region and a p-type field effect transistor (PFET) region; forming a mask over the PFET region to leave the NFET region exposed; performing dilute hydrogen-flouride (DHF) cleaning on the exposed NFET region to substantially lower an STI profile of the NFET region; and forming a silicon germanium (SiGE) channel in the PFET region after the performing of the DHF. | 2012-10-11 |
20120256269 | SEMICONDUCTOR DEVICES INCLUDING DUAL GATE STRUCTURES AND METHODS OF FABRICATION - Semiconductor devices including dual gate structures and methods of forming such semiconductor devices are disclosed. For example, semiconductor devices are disclosed that include a first gate stack that may include a first conductive gate structure formed from a first material, and a second gate stack that may include a dielectric structure formed from an oxide of the first material. For another example, methods including forming a high-K dielectric material layer over a semiconductor substrate, forming a first conductive material layer over the high-K dielectric material layer, oxidizing a portion of the first conductive material layer to convert the portion of the first conductive material layer to a dielectric material layer, and forming a second conductive material layer over both the conductive material layer and the dielectric material layer are also disclosed. | 2012-10-11 |
20120256270 | DUAL METAL GATES USING ONE METAL TO ALTER WORK FUNCTION OF ANOTHER METAL - Methods of forming dual metal gates and the gates so formed are disclosed. A method may include forming a first metal (e.g., NMOS metal) layer on a gate dielectric layer and a second metal (e.g., PMOS metal) layer on the first metal layer, whereby the second metal layer alters a work function of the first metal layer (to form PMOS metal). The method may remove a portion of the second metal layer to expose the first metal layer in a first region; form a silicon layer on the exposed first metal layer in the first region and on the second metal layer in a second region; and form the dual metal gates in the first and second regions. Since the gate dielectric layer is continuously covered with the first metal, it is not exposed to the damage from the metal etch process. | 2012-10-11 |
20120256271 | Method and Apparatus for Modeling Multi-terminal MOS Device for LVS and PDK - An apparatus comprises two n-type metal oxide semiconductor (MOS) devices formed next to each other. Each n-type MOS device further includes a pair of face-to-face diodes formed in an isolation ring. A method of modeling the apparatus comprises reusing four-terminal MOS device models in standard cell libraries and combining the four-terminal MOS device model and the isolation ring model into a 4T MOS plus isolation ring model. The method of modeling the apparatus further comprises adding a dummy device between a body contact of the first n-type MOS device and a body contact of the second n-type MOS device. | 2012-10-11 |
20120256272 | MEMORY DEVICE COMPRISING AN ARRAY PORTION AND A LOGIC PORTION - In an embodiment of the present invention, a method comprises patterning a first plurality of semiconductor structures in an array portion of a semiconductor substrate using a first photolithographic mask. The method further comprises patterning a second plurality of semiconductor structures over a logic portion of a semiconductor substrate using a second photolithographic mask. The method further comprises patterning a sacrificial layer over the first plurality of semiconductor structures using the second photolithographic mask. The sacrificial layer is patterned simultaneously with the second plurality of semiconductor structures. | 2012-10-11 |
20120256273 | METHOD OF UNIFYING DEVICE PERFORMANCE WITHIN DIE - A method of unifying device performance within an integrated circuit die includes providing a layout of an integrated circuit die with multiple functional circuit blocks; filling a field between the multiple functional circuit blocks with dummy diffusion patterns; and filling the field between the multiple functional circuit blocks with dummy gate patterns such that the dummy gate patterns and the dummy diffusion patterns are completely overlapped. | 2012-10-11 |
20120256274 | Schottky Diodes Having Metal Gate Electrodes And Methods of Formation Thereof - In one embodiment, the semiconductor device includes a first doped region disposed in a first region of a substrate. A first metal electrode having a first portion of a metal layer is disposed over and contacts the first doped region. A second doped region is disposed in a second region of the substrate. A dielectric layer is disposed on the second doped region. A second metal electrode having a second portion of the metal layer is disposed over the dielectric layer. The second metal electrode is capacitively coupled to the second doped region. | 2012-10-11 |
20120256275 | METAL GATE STRUCTURE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a metal gate structure includes first providing a substrate having a dummy gate formed thereon. The dummy gate includes a high-K gate dielectric layer, a bottom barrier layer, a first etch stop layer and a sacrificial layer sequentially and upwardly stacked on the substrate. Then, the sacrificial layer is removed to form a gate trench with the first etch stop layer exposed on the bottom of the gate trench. After forming the gate trench, a first work function metal layer is formed in the gate trench. | 2012-10-11 |
20120256276 | Metal Gate and Fabricating Method Thereof - A method of manufacturing a metal gate is provided. The method includes providing a substrate. Then, a gate dielectric layer is formed on the substrate. A multi-layered stack structure having a work function metal layer is formed on the gate dielectric layer. An O | 2012-10-11 |
20120256277 | SEMICONDUCTOR DEVICE EXHIBITING REDUCED PARASITICS AND METHOD FOR MAKING SAME - A semiconductor device includes a substrate and a gate stack disposed on the substrate. An upper layer of the gate stack is a metal gate conductor and a lower layer of the gate stack is a gate dielectric. A gate contact is in direct contact with the metal gate conductor. | 2012-10-11 |
20120256278 | Method of Removing High-K Dielectric Layer on Sidewalls of Gate Structure - A semiconductor structure, and method of forming a semiconductor structure, that includes a gate structure on a semiconductor substrate, in which the gate structure includes a gate conductor and a high-k gate dielectric layer. The high-k gate dielectric layer is in contact with the base of the gate conductor and is present on the sidewalls of the gate conductor for a dimension that is less than ¼ the gate structure's height. The semiconductor structure also includes source regions and drain regions present in the semiconductor substrate on opposing sides of the gate structure. | 2012-10-11 |
20120256279 | METHOD OF GATE WORK FUNCTION ADJUSTMENT AND METAL GATE TRANSISTOR - A method of gate work function adjustment includes the steps as follow. First, a substrate is provided, wherein a metal gate is disposed on the substrate, a source doping region and a drain doping region are disposed in the substrate at opposite sites of the metal gate, wherein the metal gate is divided into a source side adjacent to the source doping region, and a drain side adjacent to the drain doping region. Later, a mask layer is formed to cover the source doping region and the drain doping region. After that, an implantation process is performed to implant nitrogen into the metal gate so as to make a first nitrogen concentration of the source side higher than a second nitrogen concentration of the drain side. Finally, the mask layer is removed. | 2012-10-11 |
20120256280 | PACKAGING FOR FINGERPRINT SENSORS AND METHODS OF MANUFACTURE - A fingerprint sensor package, including a sensing side for sensing fingerprint information and a separate connection side for electrically connecting the fingerprint sensor package to a host device, is disclosed. The fingerprint sensor package can also include a sensor integrated circuit facing the sensing side and substantially surrounded by a fill material. The fill material includes vias at peripheral locations around the sensor integrated circuit. The fingerprint sensor package can further include a redistribution layer on the sensing side which redistributes connections of the sensor integrated circuit to the vias. The connections can further be directed through the vias to a ball grid array on the connection side. Some aspects also include electrostatic discharge traces positioned at least partially around a perimeter of the connection side. Methods of manufacturing arc also disclosed. | 2012-10-11 |
20120256281 | SEMICONDUCTOR DEVICES HAVING NANOCHANNELS CONFINED BY NANOMETER-SPACED ELECTRODES - Semiconductor devices having integrated nanochannels confined by nanometer spaced electrodes, and VLSI (very large scale integration) planar fabrication methods for making the devices. A semiconductor device includes a bulk substrate and a first metal layer formed on the bulk substrate, wherein the first metal layer comprises a first electrode. A nanochannel is formed over the first metal layer, and extends in a longitudinal direction in parallel with a plane of the bulk substrate. A second metal layer is formed over the nanochannel, wherein the second metal layer comprises a second electrode. A top wall of the nanochannel is defined at least in part by a surface of the second electrode and a bottom wall of the nanochannel is defined by a surface of the first electrode. | 2012-10-11 |
20120256282 | MEMS SENSOR DEVICE WITH MULTI-STIMULUS SENSING | 2012-10-11 |
20120256283 | INTEGRATED PASSIVE COMPONENT - An integrated passive component having a semiconductor body, arranged on a metal substrate and having a first surface, and a plurality of metal surfaces formed on the surface, and an integrated circuit formed on the surface of the semiconductor body, whereby the integrated circuit is connected by traces to the metal surfaces, and having a dielectric passivation layer formed on the surface, and the metal surfaces are connected to pins by bonding wires, and a first coil former, formed above the dielectric layer, with a winding, whereby the winding has a first connector and a second connector, and whereby the winding is formed as a wire or litz wire and the first connector of the winding is connected to a first metal surface and the second connector to a second metal surface. | 2012-10-11 |
20120256284 | IMAGING DEVICE AND CAMERA MODULE - An imaging device includes: an optical sensor including a light receiving unit capable of forming an object image; a seal material for protecting the light receiving unit of the optical sensor; an intermediate layer formed at least between the light receiving unit and an opposite surface of the seal material facing the light receiving unit; and a control film arranged between the intermediate layer and the opposite surface of the seal material, wherein, in the control film, a cutoff wavelength is shifted to a shortwave side in accordance with an incident angle of light which is obliquely incident on the film. | 2012-10-11 |
20120256285 | SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS - A solid-state imaging device includes: a light-receiving element; and a multilayer film which is disposed on a side of a light-receiving surface of the light-receiving element and is formed by laminating a plurality of layers made of materials having different refractive indices, in which a defect layer is included in at least one of the laminated layers, wherein in the defect layer, a plurality of kinds of materials having different refractive indices coexist in a surface parallel to the light-receiving surface. | 2012-10-11 |
20120256286 | PHOTOELECTRIC CONVERSION DEVICE AND ELECTRONIC DEVICE, AND METHOD FOR MANUFACTURING PHOTOELECTRIC CONVERSION DEVICE - A photoelectric conversion device includes: a first substrate of which end portions are cut off so as to slope or with a groove shape; a photodiode and an amplifier circuit over the first substrate; a first electrode electrically connected to the photodiode and provided over one end portion of the first substrate; a second electrode electrically connected to the amplifier circuit and provided over an another end portion of the first substrate; and a second substrate having third and fourth electrodes thereon. The first and second electrodes are attached to the third and fourth electrodes, respectively, with a conductive material provided not only at the surfaces of the first, second, third, and fourth electrodes facing each other but also at the side surfaces of the first and second electrodes to increase the adhesiveness between a photoelectric conversion device and a member on which the photoelectric conversion device is mounted. | 2012-10-11 |
20120256287 | BACK-ILLUMINATED SOLID-STATE IMAGE PICKUP DEVICE - In a back-illuminated solid-state image pickup device including a semiconductor substrate | 2012-10-11 |
20120256288 | Schottky Diode and Method for Making It - A Schottky diode and a method for making one. The method includes the following steps: providing a semiconductor base body, preferably in the form of a wafer, having a high dopant concentration and having a first main surface, which forms the first electrical contact surface of the Schottky diode; epitaxially depositing a semiconductor layer having the same conductivity and a lower dopant concentration on that surface of the semiconductor base body which lies opposite the first main surface; arranging a first metal layer on the semiconductor layer with the formation of a Schottky contact between the first metal layer and the semiconductor layer; connecting a planar contact body to the first metal layer by means of a connecting means; forming at least one individual Schottky diode; and arranging a passivation layer in the edge region of the at least one Schottky diode. | 2012-10-11 |
20120256289 | Forming High Aspect Ratio Isolation Structures - An isolation structure, such as a trench isolation structure, may be formed by forming an aperture in a semiconductor substrate and then filling the aperture with boron. In some embodiments, the aperture filling may use atomic layer deposition. In some cases, the boron may be amorphous boron. The aperture may be a high aspect ratio aperture, such as a trench, in some embodiments. | 2012-10-11 |
20120256290 | MICROSTRUCTURE DEVICE COMPRISING A FACE TO FACE ELECTROMAGNETIC NEAR FIELD COUPLING BETWEEN STACKED DEVICE PORTIONS AND METHOD OF FORMING THE DEVICE - A galvanic-isolated coupling of circuit portions is accomplished on the basis of a stacked chip configuration. The semiconductor chips thus can be fabricated on the basis of any appropriate process technology, thereby incorporating one or more coupling elements, such as primary or secondary coils of a micro transformer, wherein the final characteristics of the micro transformer are adjusted during the wafer bond process. | 2012-10-11 |
20120256291 | SEMICONDUCTOR DEVICE - The cell size is reduced and device reliability is improved for a semiconductor device including plural transistors making up a multi-channel output circuit. In a multi-channel circuit configuration, a group of transistors having a common function of plural channels are surrounded by a common trench for insulated isolation from another group of transistors having another function. The collectors of mutually adjacent transistors on the high side are commonly connected to a VH power supply, whereas the emitters of mutually adjacent transistors on the low side are commonly connected to a GND power supply. | 2012-10-11 |
20120256292 | Diodes with Embedded Dummy Gate Electrodes - A circuit structure includes a first isolation region, and a first dummy gate electrode over and vertically overlapping the first isolation region. First pickup regions of a diode are formed on opposite sides of the first isolation region, wherein sidewalls of the first pickup regions contact opposite sidewalls of the first isolation region. Second pickup regions of the diode are formed on opposite sides of a combined region of the first pickup regions and the first isolation region, wherein the first and the second pickup regions are of opposite conductive types. A well region is under the first and the second pickup regions and the first isolation region, wherein the well region is of a same conductivity type as the second pickup regions. | 2012-10-11 |
20120256293 | ONE-TIME PROGRAMMABLE DEVICES AND METHODS OF FORMING THE SAME - A one-time programmable (OTP) device includes at least one transistor that is electrically coupled with a fuse. The fuse includes a silicon-containing line continuously extending between a first node and a second node of the fuse. A first silicide-containing portion is disposed over the silicon-containing line. A second silicide-containing portion is disposed over the silicon-containing line. The second silicide-containing portion is separated from the first silicide-containing portion by a predetermined distance. The predetermined distance is substantially equal to or less than a length of the silicon-containing line. | 2012-10-11 |
20120256294 | Nanopillar Decoupling Capacitor - Techniques for incorporating nanotechnology into decoupling capacitor designs are provided. In one aspect, a decoupling capacitor is provided. The decoupling capacitor comprises a first electrode; an intermediate layer adjacent to the first electrode having a plurality of nanochannels therein; a conformal dielectric layer formed over the intermediate layer and lining the nanochannels; and a second electrode at least a portion of which is formed from an array of nanopillars that fill the nanochannels in the intermediate layer. Methods for fabricating the decoupling capacitor are also provided, as are semiconductor devices incorporating the decoupling capacitor design. | 2012-10-11 |