41st week of 2021 patent applcation highlights part 50 |
Patent application number | Title | Published |
20210320049 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes a housing, an interface substrate attached to the housing, an insulating substrate in the housing, a first flexible substrate connecting the insulating substrate and the interface substrate, a first integrated circuit on a first surface of the insulating substrate, and a first heat conductor arranged on a second surface of the insulating substrate that is opposite to the first surface, and contacting a first inner surface of the housing. | 2021-10-14 |
20210320050 | LIQUID-BASED HEAT EXCHANGER - A liquid cooled thermal heat sink is provided. A plurality of jet orifices provide an exit for pressurised liquid to exit a plenum chamber and impinge on a thermal surface whereby they effect a cooling of the thermal surface, the heated liquid being transferred through an exit channel to dissipate heat away from the thermal surface. | 2021-10-14 |
20210320051 | MICRO THROUGH-SILICON VIA FOR TRANSISTOR DENSITY SCALING - An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer. | 2021-10-14 |
20210320052 | SHIELD STRUCTURE FOR BACKSIDE THROUGH SUBSTRATE VIAS (TSVS) - Various embodiments of the present application are directed towards an integrated circuit (IC) in which a shield structure blocks the migration of charge to a semiconductor device from proximate a through substrate via (TSV). In some embodiments, the IC comprises a substrate, an interconnect structure, the semiconductor device, the TSV, and the shield structure. The interconnect structure is on a frontside of the substrate and comprises a wire. The semiconductor device is on the frontside of the substrate, between the substrate and the interconnect structure. The TSV extends completely through the substrate, from a backside of the substrate to the wire, and comprises metal. The shield structure comprises a PN junction extending completely through the substrate and directly between the semiconductor device and the TSV. | 2021-10-14 |
20210320053 | DISTRIBUTED INDUCTANCE INTEGRATED FIELD EFFECT TRANSISTOR STRUCTURE - A distributed inductance integrated field effect transistor (FET) structure, comprising a plurality of FETs. Each FET comprises a plurality of source regions, a gate region having a plurality of gate fingers extending from a gate bus bar, a drain region having a plurality of drain finger extending from a drain bus bar between the plurality of gate fingers, wherein the gate region controls current flow in a conductive channel between the drain region and source region. A first distributed inductor connects the gate regions of adjacent ones of the plurality of FETs; and a second distributed inductor connects the drain regions of adjacent ones of the plurality of FETs. | 2021-10-14 |
20210320054 | HEATSINK FOR THERMAL RESPONSE CONTROL FOR INTEGRATED CIRCUITS - A semiconductor device package includes a leadframe, and a heatsink bonded to the leadframe. A semiconductor device may be mounted using the leadframe and positioned such that heat generated by the semiconductor device is conducted by the heatsink, with molding that encapsulates the leadframe, the heatsink, and the semiconductor device. | 2021-10-14 |
20210320055 | SEMICONDUCTOR MODULE - A semiconductor module includes a base member including a circuit board on which a positive electrode pad and a negative electrode pad are provided and on which a semiconductor device is mounted to be electrically coupled to the positive electrode pad and the negative electrode pad, a housing that is attached to the base member so as to surround the positive electrode pad and the negative electrode pad, the housing being formed in a frame shape, a first electrode plate that is electrically coupled to the positive electrode pad, the first electrode plate having a flat plate portion, and a second electrode plate that is electrically coupled to the negative electrode pad, the second electrode plate having a flat plate portion. The flat plate portion of the first electrode plate and the flat plate portion of the second electrode plate are arranged in a parallel-plate configuration within the housing. | 2021-10-14 |
20210320056 | ENLARGED CONDUCTIVE PAD STRUCTURES FOR ENHANCED CHIP BOND ASSEMBLY YIELD - An electrical device includes an electrically insulating body having an insulating body surface and a conductive pad array, a small conductive pad arranged on the insulating body surface and within the conductive pad array, and an enlarged conductive pad. The enlarged conductive pad is arranged on the insulating body and within the conductive pad array, wherein the enlarged conductive pad is spaced apart from the small conductive pad and is larger than the small conductive pad. C4 assemblies and methods of making C4 assemblies including the electrical device are also described. | 2021-10-14 |
20210320057 | POWER DELIVERY DEVICE AND METHOD - A power delivery device includes a printed circuit board (PCB), a package device, and a chip connecting device. The PCB is configured to receive a first reference voltage and a second reference voltage. The package device is coupled to the PCB, and includes a bump array. The chip connecting device is coupled to the bump array of the package device, and configured to output a first supply voltage and a second supply voltage. The bump array includes first bumps and second bumps. The first bumps are configured to transmit the first reference voltage. The second bumps are configured to transmit the second reference voltage. The first bumps and the second bumps are disposed in parallel. | 2021-10-14 |
20210320058 | SEMICONDUCTOR PACKAGE - A method includes forming a first package structure including a first connection member including a first redistribution layer, a first frame having a first through-portion, a first semiconductor chip having a connection pad electrically connected to the first redistribution layer, and a first encapsulant covering a portion of each of the first frame and the first semiconductor chip, forming a second package structure including a second connection member including a second redistribution layer, a second semiconductor chip having a second connection pad, and a second encapsulant covering a portion of the second semiconductor chip, forming a first through-via, the first through-via electrically connecting to the second redistribution layer, and laminating the first package structure on the second package structure. After the laminating, the first through-via penetrates through the first frame, the first encapsulant, and a portion of the first connection member, and is electrically connected to the first redistribution layer. | 2021-10-14 |
20210320059 | HYBRID BACK-END-OF-LINE (BEOL) DIELECTRIC FOR HIGH CAPACITANCE DENSITY METAL-OXIDE-METAL (MOM) CAPACITOR - Certain aspects of the present disclosure generally relate to a hybrid back-end-of-line (BEOL) dielectric for a high capacitance density metal-oxide-metal (MOM) capacitor, especially in lower BEOL layers. One example semiconductor device includes an active layer and a first metal layer disposed above the active layer. The first metal layer generally includes: a first electrode; a second electrode, wherein the first and second electrodes have interdigitated fingers; a first dielectric material disposed at least partially between at least two adjacent fingers of the first and second electrodes; and a second dielectric material, wherein the second dielectric material is different from the first dielectric material and wherein the first electrode, the second electrode, and the first dielectric material compose a portion of a metal-oxide-metal (MOM) capacitor. | 2021-10-14 |
20210320060 | ELECTRODE-VIA STRUCTURE - A via structure and methods for forming a via structure generally includes a via opening in a dielectric layer. A conformal barrier layer is in the via opening; and a conductive metal on the barrier layer in the via opening. The conductive metal includes a recessed top surface. A conductive planarization stop layer is on the recessed top surface and extends about a shoulder portion formed in the dielectric layer, wherein the shoulder portion extends about a perimeter of the via opening. A fill material including an insulator material or a conductor material is on the conductive planarization stop layer within the recessed top surface, wherein the conductive planarization stop layer on the shoulder portion is coplanar to the insulator material or the conductor material. Also described are methods of fabricating the via structure. | 2021-10-14 |
20210320061 | CONTACT FORMATION METHOD AND RELATED STRUCTURE - A method and structure for forming semiconductor device includes forming a contact via opening in a first dielectric layer, where the contact via opening exposes a first portion of a contact etch stop layer (CESL). The method further includes etching both the first portion of the CESL exposed by the contact via opening and adjacent lateral portions of the CESL to expose a source/drain contact and form an enlarged contact via opening having cavities disposed on either side of a bottom portion of the enlarged contact via opening. The method further includes forming a passivation layer on sidewall surfaces of the enlarged contact via opening including on sidewall surfaces of the cavities. The method further includes depositing a first metal layer within the enlarged contact via opening and within the cavities to provide a contact via in contact with the exposed source/drain contact. | 2021-10-14 |
20210320062 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a semiconductor device, an interconnect structure, a capacitor, and a plurality of pads. The semiconductor device is disposed at the substrate. The interconnect structure is disposed on the substrate and electrically connected to the semiconductor device. The capacitor is disposed on the interconnect structure and electrically connected to the interconnect structure. The capacitor includes a first electrode, a second electrode covering a top surface and a sidewall of the first electrode, and an insulating layer disposed between the first electrode and the second electrode. The plurality of pads are disposed on the interconnect structure and electrically connected to the interconnect structure, wherein at least one of the plurality of pads is electrically connected to the capacitor. | 2021-10-14 |
20210320063 | THIN FILM RESISTORS OF SEMICONDUCTOR DEVICES - A semiconductor device is provided. A semiconductor device includes a first and a second region, a dielectric layer, a capping layer, and a planar resistive layer. The dielectric layer is arranged over the first and second regions and the capping layer is arranged over the dielectric layer. The capping layer has a substantially planar top surface over the first and second regions. The planar resistive layer is encapsulated within the capping layer in the first device region. | 2021-10-14 |
20210320064 | METHODS AND APPARATUS FOR FORMING DUAL METAL INTERCONNECTS - Methods and apparatus for creating a dual metal interconnect on a substrate. In some embodiments, a first liner of a first nitride material is deposited into at least one 1X feature and at least one wider than 1X feature, the first liner has a thickness of less than or equal to approximately 12 angstroms; a second liner of a first metal material is deposited into the at least one 1X feature and at least one wider than 1X feature; the first metal material is reflowed such that the at least one 1X feature is filled with the first metal material and the at least one wider than 1X feature remains unfilled with the first metal material; a second metal material is deposited on the first metal material, and the second metal material is reflowed such that the at least one wider than 1X feature is filled with the second metal material. | 2021-10-14 |
20210320065 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - An inverter cell having a logical function and a filler cell having no logical function are placed adjacent to each other. Nanowires of the filler cell are placed at the same positions as nanowires of the inverter cell in the Y direction. A p-type dummy transistor and n-type dummy transistor of the filler cell are respectively placed at the same levels as a p-type transistor and n-type transistor of the inverter cell in the Z direction. | 2021-10-14 |
20210320066 | Die Interconnect Substrate, an Electrical Device and a Method for Forming a Die Interconnect Substrate - A die interconnect substrate comprises a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate comprises a multilayer substrate structure comprising a substrate interconnect. The bridge die is embedded in the multilayer substrate structure. The substrate interconnect extends from a level above the bridge die to a level below the bridge die. The multilayer substrate structure further comprises an electrically insulating layer comprising a first electrically insulating material. The multilayer substrate structure further comprises an electrically insulating filler structure located laterally between the bridge die and the electrically insulating layer, wherein the electrically insulating filler structure comprises a second electrically insulating material different from the first electrically insulating material. | 2021-10-14 |
20210320067 | SEMICONDUCTOR PACKAGE - There is provided a semiconductor package capable of preventing damage to an interposer to improve reliability. The semiconductor package includes a first substrate including a first insulating layer and first conductive patterns, an interposer disposed on a top surface of the first substrate and including a second insulating layer and second conductive patterns, first connecting members in contact with the top surface of the first substrate and a bottom surface of the interposer, and supporting members including solder parts, which are in contact with the top surface of the first substrate and the bottom surface of the interposer, and core parts, which are disposed in the solder parts and include a different material from the solder parts. The first connecting members electrically connect the first conductive patterns and the second conductive patterns, and the supporting members do not electrically connect the first conductive patterns and the second conductive patterns. | 2021-10-14 |
20210320068 | Interposer-Type Component Carrier and Method of Manufacturing the Same - An interposer-type component carrier includes a stack comprising at least one electrically conductive layer structure and at least one electrically insulating layer structure; a cavity formed in an upper portion of the stack; an active component embedded in the cavity and having at least one terminal facing upwards; and a redistribution structure having only one electrically insulating layer structure above the component. A method of manufacturing an interposer-type component carrier is also disclosed. | 2021-10-14 |
20210320069 | PACKAGE WITH FAN-OUT STRUCTURES - Structures and formation methods of chip packages are provided. The method includes disposing a semiconductor die over a carrier substrate. The method also includes disposing an interposer substrate over the carrier substrate. The interposer substrate has a recess that penetrates through opposite surfaces of the interposer substrate. The interposer substrate has interior sidewalls surrounding the semiconductor die, and the semiconductor die is as high as or higher than the interposer substrate. The method further includes forming a protective layer in the recess of the interposer substrate to surround the semiconductor die. In addition, the method includes removing the carrier substrate and stacking a package structure over the interposer substrate. | 2021-10-14 |
20210320070 | PHYSICAL UNCLONABLE FUNCTION - Methods, and devices related to authentication of chips using physical unclonable function (PUF) are disclosed. The semiconductor chip has a substrate having a major surface. The semiconductor chip has a boundary defined on the major surface in accordance with a ground rule associated with a gate cut passing (CT) fin formed on the major surface. The semiconductor chip has multiple non-planar devices fabricated on the surface at the boundary. The CT fin forms a random distribution of field effect transistors (FETs) with varying work function metal (WFM) thickness that includes some FETs that fail the ground rule and other FETs that meet the ground rule. A physical unclonable function (PUF) region is defined in accordance with the random distribution. | 2021-10-14 |
20210320071 | WARPAGE COMPENSATING RF SHIELD FRAME - An integrated circuit package shield comprising a frame comprising two or more segments, the segments to interlock with one another along a substrate and the segments comprising electrically conductive material to electrically couple to the substrate; and a lid to cover the frame, the lid comprising a conductive material to electrically couple to the substrate. | 2021-10-14 |
20210320072 | ELECTROMAGNETIC SHIELDING METAL-INSULATOR-METAL CAPACITOR STRUCTURE - The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interposer device. The semiconductor interposer device includes a substrate and a first metallization layer formed on the substrate. A first dielectric layer is formed on the first metallization layer and a second metallization layer is formed on the substrate. A first conducting line is formed in the first metallization layer and second and third conducting lines are formed in the second metallization layer. A metal-insulator-metal (MIM) capacitor is formed in the first dielectric layer and over the first conducting line. The MIM capacitor includes (i) a top capacitor electrode in the first dielectric layer and electrically coupled to the second conducting line; (ii) a bottom capacitor electrode in the first dielectric layer and above the first conducting line, wherein the bottom capacitor electrode is configured to be electrically floating; and (iii) a second dielectric layer between the top and bottom capacitor electrodes. | 2021-10-14 |
20210320073 | ELECTRONIC PACKAGE AND FABRICATION METHOD THEREOF - An electronic package is formed by disposing an electronic element and a lead frame having a plurality of conductive posts on a carrier structure having an antenna function, and encapsulating the electronic element and the lead frame with an encapsulant. The encapsulant is defined with a first encapsulating portion and a second encapsulating portion lower than the first encapsulating portion. The electronic element is positioned in the first encapsulating portion, and the plurality of conductive posts are positioned in the second encapsulating portion. End surfaces of the plurality of conductive posts are exposed from a surface of the second encapsulating portion so as to be electrically connected to a connector. | 2021-10-14 |
20210320074 | Textured Bond Pads - In some examples, a package comprises a semiconductor die and a bond pad formed upon the semiconductor die. The bond pad has a protrusion on a top surface of the bond pad. The package also comprises a metal contact and a bond wire coupled to the protrusion and to the metal contact. | 2021-10-14 |
20210320075 | BONDED ASSEMBLY CONTAINING BONDING PADS SPACED APART BY POLYMER MATERIAL, AND METHODS OF FORMING THE SAME - A first metal layer can be deposited over first dielectric material layers of a first substrate, and can be patterned into first metallic plates. First bonding pads including a respective one of the first metallic plates are formed. A first polymer material layer can be formed over the first bonding pads. A second semiconductor die including second bonding pads is bonded to the first bonding pads to form a bonded assembly. | 2021-10-14 |
20210320076 | ELECTRONIC PACKAGE, MANUFACTURING METHOD THEREOF AND CONDUCTIVE STRUCTURE - Provided is an electronic package, including a first substrate of a first conductive structure and a second substrate of a second conductive structure, where a first conductive layer, a bump body and a metal auxiliary layer of the first conductive structure are sequentially formed on the first substrate, and a metal pillar, a second conductive layer, a metal layer and a solder layer of the second conductive structure are sequentially formed on the second substrate, such that the solder layer is combined with the bump body and the metal auxiliary layer to stack the first substrate and the second substrate. Therefore, the arrangement of the bump body and the metal auxiliary layer allows complete reaction of the IMCs after reflowing the solder layer, and the volume of the conductive structures will not continue to shrink. As such, the problem of cracking of the conductive structures can be effectively averted. | 2021-10-14 |
20210320077 | SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device comprising a semiconductor substrate, an under-bump pattern on the semiconductor substrate and including a first metal, a bump pattern on the under-bump pattern, and an organic dielectric layer on the semiconductor substrate and in contact with a sidewall of the bump pattern. The bump pattern includes a support pattern in contact with the under-bump pattern and having a first width, and a solder pillar pattern on the support pattern and having a second width. The first width is greater than the second width. The support pattern includes at least one of a solder material and an intermetallic compound (IMC). The intermetallic compound includes the first metal and the solder material. | 2021-10-14 |
20210320078 | ELECTRONICS ASSEMBLIES EMPLOYING COPPER IN MULTIPLE LOCATIONS - Electronic assemblies may be fabricated with interconnects of different types present in multiple locations and comprising fused copper nanoparticles. Each interconnect or a portion thereof comprises a bulk copper matrix formed from fusion of copper nanoparticles or a reaction product formed from copper nanoparticles. The interconnects may comprise a copper-based wire bonding assembly, a copper-based flip chip connection, a copper-based hermetic seal assembly, a copper-based connector between an IC substrate and a package substrate, a copper-based component interconnect, a copper-based interconnect comprising via copper for establishing electrical communication between opposite faces of a package substrate, a copper-based interconnect defining a heat channel formed from via copper, and any combination thereof. | 2021-10-14 |
20210320079 | SEMICONDUCTOR DEVICES INCLUDING SEED STRUCTURE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICES - A semiconductor device may include a seed structure on a complex structure. The seed structure may include a first barrier layer, a first seed layer on the first barrier layer, a second barrier layer on the first seed layer, and a second seed layer on the second barrier layer. The second barrier layer may contact a side surface of at least one of the first barrier layer and the first seed layer. An electrode layer may be disposed on the seed structure. | 2021-10-14 |
20210320080 | USING ELECTRICAL CONNECTIONS THAT TRAVERSE SCRIBE LINES TO CONNECT DEVICES ON A CHIP - A chip or integrated circuit includes a layer that includes a first device and a second device. A scribe line is located between the first device and the second device and separates the first device from the second device. An electrically conductive connection traverses the scribe line and is coupled to the first device and the second device, thus connecting the first and second devices. | 2021-10-14 |
20210320081 | RADIO FREQUENCY MODULES - Packaged modules for use in wireless devices are disclosed. A substrate supports integrated circuit die including at least a portion of a baseband system and a front end system, an oscillator assembly, and an antenna. The oscillator assembly includes an enclosure to enclose the oscillator and conductive pillars formed at least partially within a side of the enclosure to conduct signals between the top and bottom surfaces of the oscillator assembly. Components can be vertically integrated to save space and reduce trace length. Vertical integration provides an overhang volume that can include discrete components. Radio frequency shielding and ground planes within the substrate shield the front end system and antenna from radio frequency interference. Stacked filter assemblies include passive surface mount devices to filter radio frequency signals. | 2021-10-14 |
20210320082 | INTERCONNECTION OF COPPER SURFACES USING COPPER SINTERING MATERIAL - A method for interconnecting a first conductor and a second conductor includes forming a layer of substantially pure copper on the first conductor, applying a copper sintering material to the first conductor, the second conductor, or both, and interconnecting the first conductor and the second conductor by sintering the copper sintering material so as to form a copper-copper interface that includes the layer of substantially pure copper, the second conductor, and the copper sintering material. | 2021-10-14 |
20210320083 | MANUFACTURING METHOD OF POWER SEMICONDUCTOR DEVICE, POWER SEMICONDUCTOR DEVICE, AND POWER CONVERTER - A power semiconductor element and a support member are stacked with an intermediate structure being interposed between the power semiconductor element and the support member. The intermediate structure includes a first metal paste layer and at least one first penetrating member. The first metal paste layer contains a plurality of first metal particles. The at least one first penetrating member penetrates the first metal paste layer. At least one first vibrator attached to the at least one first penetrating member penetrating the first metal paste layer is vibrated. The first metal paste layer is heated so that the plurality of first metal particles are sintered or fused. | 2021-10-14 |
20210320084 | ELECTRONIC SYSTEM, DIE ASSEMBLY AND DEVICE DIE - The present disclosure provides a device die, a die assembly and an electronic system. The device die includes a package and a plurality of transfer pads disposed on a functional surface of the package. The transfer pads are divided into a plurality of segments electrically isolated from each other. In an adjacent pair of transfer pads, there is only one electrical connection between the transfer pads, comprising one segment in one transfer pad electrically connected to one segment in the other transfer pad. The die assembly includes a pair of device dies stacked in a stepped configuration. The electronic system includes a supporting member having at least one metallic layer, and a plurality of device dies disposed on the supporting member and mechanically and electrically coupled to the metallic layer by a plurality of conductive strings. | 2021-10-14 |
20210320085 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a first substrate, a first semiconductor die, a second semiconductor die, a second substrate, at least one first solder ball, at least one second solder ball, and at least one third solder ball. The first semiconductor die is disposed on the first substrate. The second semiconductor die is disposed on the first semiconductor die. The second substrate is disposed on the second semiconductor die. The first solder ball is vertically between the first substrate and the first semiconductor die. The second solder ball is vertically between the second substrate and the second semiconductor die. The third solder ball is vertically between the first substrate and the second substrate. | 2021-10-14 |
20210320086 | SEMICONDUCTOR PACKAGE INCLUDING EMBEDDED SOLDER CONNECTION STRUCTURE - A semiconductor package includes a first semiconductor chip including a first chip body portion and a first chip rear bump disposed in a region recessed into the first chip body portion, and a second semiconductor chip stacked on the first semiconductor chip and including a second chip body portion and a second chip front bump protruding from the second chip body portion. The first chip rear bump includes a lower metal layer and a solder layer disposed on the lower metal layer. The second chip front bump is bonded to the solder layer. The second chip front bump is disposed to cover at least the solder layer on a bonding surface of the second chip front bump and the solder layer. | 2021-10-14 |
20210320087 | SURFACE EMITTING LIGHT SOURCE - A surface-emitting light source includes a plurality of light-emitting regions each of which includes light sources, wherein each of the plurality of light-emitting regions can be turned on individually. Each of the light-emitting regions is adjacent to each other and includes a light-guide portion that is provided in adjacent light-emitting regions and covers the light sources, and a light-reflective member disposed below the light-guide portion. The light-reflective member has a first wall portion disposed at the outer periphery of each of the light-emitting regions. The first wall portion includes one or more unit first wall portions each of which corresponds to a respective one of the light sources located at the outer periphery of each of the light-emitting regions. The unit first wall portion located at the two adjacent light-emitting regions has a central portion having a height smaller than a height of both end portions. | 2021-10-14 |
20210320088 | LED CHIP INITIAL STRUCTURE, SUBSTRATE STRUCTURE, CHIP TRANSFERRING METHOD AND IMAGE DISPLAY DEVICE - An LED chip initial structure, a substrate structure for carrying the LED chip initial structure, a chip transferring method using the LED chip initial structure, and an LED image display device manufactured by the LED chip transferring method are provided. The LED chip initial structure includes an LED chip main body and a conductive electrode. One of a top side and a bottom side of the LED chip main body is a temporary electrodeless side, another one of the top side and the bottom side of the LED chip main body is a connecting electrode side, and the temporary electrodeless side has an unoccupied surface. The conductive electrode is disposed on the connecting electrode side of the LED chip main body so as to electrically connect to the LED chip main body. The LED chip initial structure is adhered to a hot-melt material through the conductive electrode. | 2021-10-14 |
20210320089 | APPARATUS AND METHOD FOR MANUFACTURING LIGHT-EMITTING DISPLAY DEVICE - An apparatus for manufacturing a light emitting display device includes a substrate transfer stage including a plurality of support plates arranged at an interval in a first direction, each of the plurality of support plates extending in a second direction; and at least one electric-field application module disposed on at least one side of the substrate transfer stage. The at least one electric-field application module includes a probe head including at least one probe pin; and a driver connected to the probe head to move the probe head at least up and down. | 2021-10-14 |
20210320090 | MANUFACTURING METHOD OF MICRO LIGHT EMITTING DIODE DEVICE - A method for manufacturing a micro light emitting diode device is provided. A plurality of first type epitaxial structures are formed on a first substrate and the first type epitaxial structures are separated from each other. A first connection layer and a first adhesive layer are configured between the first type epitaxial structures and the first substrate. The first connection layer is connected to the first type epitaxial structures. The first adhesive layer is located between the first connection layer and the first type epitaxial substrate. The Young's modulus of the first connection layer is larger than the Young's modulus of the first adhesive layer. The first connection layer located between any two adjacent first type epitaxial structures is removed so as to form a plurality of first connection portions separated from each other. Each of the first connection portions is connected to the corresponding first type epitaxial structure. | 2021-10-14 |
20210320091 | PANEL FOR DISPLAY BY MICRO LED AND METHOD FOR MAKING SAME - A method for making a micro LED display panel not requiring high-accuracy or individual positioning includes providing a carrier substrate with micro LEDs, providing a TFT substrate including a driving circuit, and forming a conductive connecting element, an insulating layer, and a contact electrode layer on the TFT substrate. The insulating layer and the contact electrode layer are patterned to define a through hole, the first electrode is placed against the contact electrode layer, and different voltages Vref and Vdd are applied to the contact electrode layer and to the conductive connecting element respectively, creating an electrostatic attraction. The micro LEDs and the first electrode are transferred from the carrier substrate onto the TFT substrate; and the conductive connecting element is bonded to the first electrode. The method of making is simple. A micro LED display panel made by the method is also provided. | 2021-10-14 |
20210320092 | METHOD FOR MAKING INKJET-PRINTED ENCAPSULATED QUANTUM DOTS, LIGHT CONVERSION UNIT, AND MICRO LED DISPLAY PANEL - A method for making inkjet-printed encapsulated quantum dots and a light conversion unit using the inkjet-printed encapsulated quantum dots are disclosed. The light conversion unit comprises: a substrate, a light convertor carrying layer having several accommodating grooves, several first micro encapsulated QD structures, and several second micro encapsulated QD structures. In case of letting the substrate has a hydrophobic surface, at least one inkjet-printing nozzle is utilized for injecting a first QDs solution and a second QDs solution into the accommodating grooves by a form of droplet, such that one third of the accommodating grooves are formed with the first micro encapsulated QD structure, and another one third of the accommodating grooves formed with the second micro encapsulated QD structure. Moreover, a micro LED display panel having the light conversion unit exhibits a color gamut that is approximately 110% NTSC. | 2021-10-14 |
20210320093 | Stacked Die Multichip Module Package - A multichip module (MCM) power package includes a multilayer routable leadframe substrate (MRLF) substrate including a first and a second RLF layer. A multilayer extending via extends from the first into the second RLF layer. A first vertical FET has a side flipchip attached to a bottom side of the second RLF. A second vertical FET has a side flipchip attached to a bottom side of the second RLF layer, and contacts the multilayer extending via. A controller integrated circuit (IC) is flipchip attached a top side of the MRLF substrate at least partially over the first vertical FET. A top mold compound is on a top side of the MRLF substrate lateral to the controller IC that is lateral to a metal pad on the multilayer extending via. A bottom side of the first and second vertical FET are exposed by a bottom mold compound layer. | 2021-10-14 |
20210320094 | THREE-DIMENSIONAL MEMORY DEVICE WITH BACKSIDE SOURCE CONTACT - Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a peripheral circuit on the substrate, a memory stack including interleaved conductive layers and dielectric layers above the peripheral circuit, a first semiconductor layer above the memory stack, a second semiconductor layer above and in contact with the first semiconductor layer, a plurality of channel structures each extending vertically through the memory stack and the first semiconductor layer, and a source contact above the memory stack and in contact with the second semiconductor layer. | 2021-10-14 |
20210320095 | CAMERA ASSEMBLY, LENS MODULE, AND ELECTRONIC DEVICE - A camera assembly includes a photosensitive unit, including a photosensitive chip and an optical filter mounted on the photosensitive chip; functional components; and an encapsulation layer, embedded with the photosensitive unit and the functional components. The photosensitive chip and the functional components are exposed from a bottom surface of the encapsulation layer. A top surface of the encapsulation layer is higher than the photosensitive chip and functional components and exposes the optical filter. The photosensitive chip has soldering pads facing away from the bottom surface of the encapsulation layer. The functional components have soldering pads exposed from the bottom surface of the encapsulation layer. The camera assembly further includes a redistribution layer structure, disposed on the bottom surface of the encapsulation layer and electrically connecting to the soldering pads. | 2021-10-14 |
20210320096 | MANUFACTURING METHOD FOR SEMICONDUCTOR PACKAGE STRUCTURE - A manufacturing method for a semiconductor package structure, which includes the steps of providing a circuit build-up substrate, which has a first surface that exposes multiple flip-chip bonding pads and multiple first bonding pads located around the flip-chip bonding pads; forming a conductive substrate embedded with a chip and multiple conductive pillars on the first surface of the circuit build-up substrate, in which the first surface of the chip is disposed corresponding to the flip-chip bonding pads and the second end of the conductive pillars is disposed corresponding to the first bonding pads; a second surface of the chip and a first end of each conductive pillars are exposed from an upper surface of the conductive substrates; and arranging a memory module on the conductive substrate, corresponding to the first end of the conductive pillars, wherein the memory module and the chip do not overlap in an orthographic projection direction. | 2021-10-14 |
20210320097 | INTEGRATED CIRCUIT PACKAGE AND METHOD OF FORMING SAME - An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure. | 2021-10-14 |
20210320098 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a substrate, a first gate structure, a second gate structure, a third gate structure, and a first source/drain region. The first, second, and third gate structures are above the substrate and arranged in a first direction. The first, second, and third gate structures extend in a second direction different from the first direction, and the second gate structure is between the first and third gate structures. The first source/drain region is between the first and third gate structures, and the first source/drain region is at one end of the second gate structure. | 2021-10-14 |
20210320099 | METHODS OF FORMING CAPACITOR STRUCTURES - Methods of forming a capacitor structure might include forming a first and second conductive regions having first and second conductivity types, respectively, in a semiconductor material, forming a dielectric overlying the first and second conductive regions, forming a conductor overlying the dielectric, and patterning the conductor, the dielectric, and the first and second conductive regions to form a first island of the first conductive region, a second island of the first conductive region, an island of the second conductive region, a first portion of the dielectric overlying the first island of the first conductive region separated from a second portion of the dielectric overlying the second island of the first conductive region and the island of the second conductive region, and a first portion of the conductor overlying the first portion of the dielectric separated from a second portion of the conductor overlying the second portion of the dielectric. | 2021-10-14 |
20210320100 | ELECTROSTATIC DISCHARGE CIRCUIT AND METHOD FOR PREVENTING MALFUNCTIONING OF INTEGRATED CIRCUIT FROM REVERSE CONNECTION OF POWER SOURCE - Disclosed are an electrostatic discharge circuit and a method for preventing malfunctions of an integrated circuit due to a reverse connection of a power source. The electrostatic discharge circuit includes at least one MOSFET for providing an electrostatic discharging current path, and a control circuit coupled to the at least one MOSFET. When an external power supply is reversely connected, the control circuit is configured to change a potential of a base of at least one MOSFET, such that the at least one MOSFET is turned off, thereby preventing the integrated circuit from malfunctioning caused by a current generated by the reverse connection of the external power source flowing through the at least one MOSFET. | 2021-10-14 |
20210320101 | DETECTION DEVICE - A detection device comprises a substrate, a terminal part provided on the substrate and having a plurality of terminals, a first protection circuit unit provided on the substrate and having a plurality of first protection circuits, a selector unit provided on the substrate and having a plurality of selectors, a second protection circuit unit provided on the substrate and having a plurality of second protection circuits and a sensor unit provided on the substrate and having a plurality of sensors. The first protection circuit unit is provided between the terminal unit and the selector unit, and the second protection circuit unit is provided between selector unit and the sensor unit. | 2021-10-14 |
20210320102 | PASSIVE TUNABLE INTEGRATED CIRCUIT WITH ELECTRO-STATIC DISCHARGE PROTECTION - A passive tunable integrated circuit (PTIC) having an electro-static discharge (ESD) protection circuit is disclosed. The ESD protection circuit includes at least one spark gap that has a breakdown voltage determined by design parameters. The at least one spark gaps are configured to route signals above a breakdown voltage to ground in order to protect a variable capacitor. The design parameters can be based on a material (Barium Strontium Titanate), a structure, and a fabrication process of the PTIC and further based on expected ESD signals for a mobile device application. | 2021-10-14 |
20210320103 | III-Nitride Device - An integrated semiconductor device includes a silicon body that includes <111> single crystal silicon, a semiconductor device that is disposed within the silicon body, a III-nitride body disposed on the silicon body, and a III-nitride device that is disposed within the III-nitride body, wherein the semiconductor device is operatively coupled to the III-nitride device. | 2021-10-14 |
20210320104 | METHOD OF FORMING SEMICONDUCTOR STRUCTURE - A semiconductor structure includes a first semiconductor substrate, a second semiconductor substrate, a depletion layer, an isolation structure, a first gate structure, and a second gate structure. The first and second semiconductor substrates respectively have a first active region and a second active region overlapping the first active region. The depletion layer is disposed between the first active region and the second active region. The isolation structure surrounds the first and second active regions. The first gate structure is disposed in the second active region. The second gate structure is disposed in the second active region. The second active region has a portion between the first gate structure and the second gate structure. | 2021-10-14 |
20210320105 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A semiconductor device and a method of fabricating a semiconductor device, the device including a substrate; a first conductive pattern on the substrate; a second conductive pattern on the substrate and spaced apart from the first conductive pattern; an air spacer between the first conductive pattern and the second conductive pattern; and a quantum dot pattern covering an upper part of the air spacer. | 2021-10-14 |
20210320106 | DRAM CAPACITOR TO STORAGE NODE'S LANDING PAD AND BIT LINE AIRGAP - Memory devices and methods of forming memory devices are described. Specifically, dynamic random-access memory (DRAM) devices are provided with a capacitor landing pad able to connect a 6f | 2021-10-14 |
20210320107 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - The embodiments provide a semiconductor structure and a fabrication method thereof. The semiconductor structure includes: a substrate including an active region and a shallow trench isolation region spaced apart from each other; a plurality of isolation structures arranged on a surface of the substrate; a plurality of grooves arranged between the plurality of isolation structures, wherein a bottom of the groove has a first inclined plane, and the first inclined plane is formed in the active region; and a conductive plug arranged in the groove. According to embodiments of the present disclosure, it is avoidable that an air gap is formed inside a polycrystalline silicon in the fabrication process of a storage node contact (SNC) structure. | 2021-10-14 |
20210320108 | STATIC RANDOM-ACCESS MEMORY AND FABRICATION METHOD THEREOF - A static random-access memory device is provided. The static random-access memory device includes a substrate with at least one first region; first fins on a surface of the substrate, and second initial fins on the surface of the substrate. A width of the second initial fins is different from a width of the first fins. A portion of the first fins is used to form pass-gate transistors, and another portion of the first fins and the second initial fins are used to form pull-down transistors. | 2021-10-14 |
20210320109 | TEST KEY STRUCTURE - The present invention provides a test key structure, the test key structure a substrate, a plurality of test key cells disposed on the substrate, wherein each test key cell includes a first gate structure arranged along a first direction (X-axis), a first diffusion region, a second diffusion region, a connection diffusion region and a share contact arranged along a second direction (Y-axis), wherein the first gate structure crosses over the first diffusion region to form a pull-up transistor (PU), the second gate structure crosses over the second diffusion region to form a pull-down transistor (PD), and wherein the plurality of share contacts and the plurality of connection diffusion regions of the plurality of test key cells are electrically connected to each other. | 2021-10-14 |
20210320110 | MOS TRANSISTOR HAVING LOWER GATE-TO-SOURCE/DRAIN BREAKDOWN VOLTAGE AND ONE-TIME PROGRAMMABLE MEMORY DEVICE USING THE SAME - A MOS transistor includes a semiconductor substrate, a drain region and a source region in the semiconductor substrate, a channel region between the drain region and the source region, a gate electrode on the channel region, and a gate dielectric layer between the gate electrode and the semiconductor substrate. The gate dielectric layer has different thicknesses. The MOS transistor has a gate-to-source/drain breakdown voltage that is lower than a gate-to-channel breakdown voltage and a gated source/drain junction breakdown voltage. | 2021-10-14 |
20210320111 | Ferroelectric Device and Methods of Fabrication Thereof - A semiconductor device includes a first dielectric layer, a first conductive feature in the first dielectric layer, a second dielectric layer over the first dielectric layer, an ferroelectric random-access memory (FeRAM) cell in the second dielectric layer, a third dielectric layer over the second dielectric layer, and a second conductive feature in the third dielectric layer, the second conductive feature being electrically coupled to the top electrode. The FeRAM cell includes a bottom electrode contacting the first conductive feature, a ferroelectric material layer completely covering an upper surface of the bottom electrode, and a top electrode on the ferroelectric material layer. | 2021-10-14 |
20210320112 | NON-VOLATILE FLASH MEMORY DEVICE AND A MANUFACTURING METHOD THEREOF - The present disclosure provides a non-volatile flash memory device and a manufacturing method thereof. The non-volatile flash memory device comprises at least a plurality of memory cells in a memory area. The manufacturing method comprises: providing a substrate, and defining the memory area of the non-volatile flash memory device on the substrate; forming a plurality of stack gates of the plurality of memory cells on a substrate corresponding to the memory area, and the top of each stack gate is a memory control gate of the memory cell; etching the memory control gates to reduce the height of the memory control gates with the fluid photoresist filled among the plurality of stack gates of the plurality of memory cells as a mask; and removing the fluid photoresist. | 2021-10-14 |
20210320113 | METHOD OF MANUFACTURING MEMORY STURCTURE - A method of manufacturing a memory structure including the following steps is provided. A first pad layer is formed on a substrate. Isolation structures are formed in the first pad layer and the substrate. At least one shape modification treatment is performed on the isolation structures. Each shape modification treatment includes the following steps. A first etching process is performed on the first pad layer to reduce a height of the first pad layer and to form first openings exposing sidewalls of the isolation structures. After the first etching process is performed, a second etching process is performed on the isolation structures to modify shapes of the sidewalls of the isolation structures exposed by the first openings. The first pad layer is removed to form a second opening between two adjacent isolation structures. | 2021-10-14 |
20210320114 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes: a first semiconductor structure including a memory array; a second semiconductor structure spaced apart from the first semiconductor structure, the second semiconductor structure including a first transistor; a first insulating layer between the first semiconductor structure and the second semiconductor structure; a second insulating layer between the second semiconductor structure and the first insulating layer; a first bonding pad electrically connected to the memory array, the first bonding pad being located in the first insulating layer; and a second bonding pad electrically connected to the first transistor, the second bonding pad being located in the second insulating layer. The first bonding pad and the second bonding pad are in contact with each other. At least one sidewall of sidewalls of the first bonding pad and the second bonding pad includes a curved part. | 2021-10-14 |
20210320115 | THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME - Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes an insulating layer, a semiconductor layer, a memory stack including interleaved conductive layers and dielectric layers, a source contact structure extending vertically through the insulating layer from an opposite side of the insulating layer with respect to the semiconductor layer to be in contact with the semiconductor layer, and a channel structure extending vertically through the memory stack and the semiconductor layer into the insulating layer or the source contact structure. | 2021-10-14 |
20210320116 | NON-VOLATILE MEMORY - A non-volatile memory includes a first semiconductor layer vertically stacked on a second semiconductor layer and including a first memory group, a second memory group, a third memory group and a fourth memory group. The second semiconductor layer includes a first region, a second region, a third region and a fourth region respectively underlying the first memory group, second memory group, third memory group and fourth memory group. The first region includes one driving circuit connected to memory cells of one of the second memory group, third memory group and fourth memory group through a first word line, and another driving circuit connected to memory cells of the first memory group through a first bit line, wherein the first word line and first bit line extend in the same horizontal direction. | 2021-10-14 |
20210320117 | VERTICAL MEMORY STRUCTURE WITH AIR GAPS AND METHOD FOR PREPARING THE SAME - The present disclosure provides a vertical memory structure with air gaps and a method for preparing the vertical memory structure. The vertical memory structure includes a semiconductor stack including a lower semiconductor pattern structure filling a recess on a substrate and protruding from an upper surface of the substrate in a first direction substantially perpendicular to the upper surface of the substrate; a plurality of gate electrodes surrounding a sidewall of the semiconductor stack, the plurality of gate electrodes being at a plurality of levels, respectively, so as to be spaced apart from each other in the first direction; and a plurality of air gap structures disposed at outer sides of the plurality of gate electrodes respectively. | 2021-10-14 |
20210320118 | METHOD FOR FORMING THREE-DIMENSIONAL MEMORY DEVICE WITH BACKSIDE SOURCE CONTACT - Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A sacrificial layer above a second semiconductor layer at a first side of a substrate and a dielectric stack on the sacrificial layer are subsequently formed. A channel structure extending vertically through the dielectric stack and the sacrificial layer into the second semiconductor layer is formed. The sacrificial layer is replaced with a first semiconductor layer in contact with the second semiconductor layer. The dielectric stack is replaced with a memory stack, such that the channel structure extends vertically through the memory stack and the first semiconductor layer into the second semiconductor layer. A source contact is formed at a second side opposite to the first side of the substrate to be in contact with the second semiconductor layer. | 2021-10-14 |
20210320119 | THREE-DIMENSIONAL MEMORY DEVICE AND METHOD FOR FORMING THE SAME - Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a peripheral circuit on the substrate, a memory stack including interleaved conductive layers and dielectric layers above the peripheral circuit, a first semiconductor layer above the memory stack, a second semiconductor layer above and in contact with the first semiconductor layer, a plurality of channel structures each extending vertically through the memory stack and the first semiconductor layer, and an insulating structure extending vertically through the memory stack, the first semiconductor layer, and the second semiconductor layer. | 2021-10-14 |
20210320120 | THREE-DIMENSIONAL MEMORY DEVICES - Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a stop layer, a polysilicon layer, a memory stack including interleaved stack conductive layers and stack dielectric layers, and a plurality of channel structures each extending vertically through the memory stack and the polysilicon layer, stopping at the stop layer. | 2021-10-14 |
20210320121 | METHODS FOR FORMING THREE-DIMENSIONAL MEMORY DEVICES - Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A stop layer, a first polysilicon layer, a sacrificial layer, a second polysilicon layer, and a dielectric stack are sequentially formed at a first side of a substrate. A channel structure extending vertically through the dielectric stack, the second polysilicon layer, the sacrificial layer, and the first polysilicon layer, stopping at the stop layer, is formed. An opening extending vertically through the dielectric stack and the second polysilicon layer, stopping at the sacrificial layer to expose part of the sacrificial layer, is formed. The sacrificial layer is replaced, through the opening, with a third polysilicon layer between the first and second polysilicon layers. The substrate is removed from a second side opposite to the first side of the substrate, stopping at the stop layer. | 2021-10-14 |
20210320122 | THREE-DIMENSIONAL MEMORY DEVICE WITH BACKSIDE INTERCONNECT STRUCTURES - Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack including interleaved conductive layers and dielectric layers above the substrate, a plurality of channel structures each extending vertically through the memory stack, a semiconductor layer above and in contact with the plurality of channel structures, a plurality of source contacts above the memory stack and in contact with the semiconductor layer, a plurality of contacts through the semiconductor layer, and a backside interconnect layer above the semiconductor layer including a source line mesh in a plan view. The plurality of source contacts are distributed below and in contact with the source line mesh. A first set of the plurality of contacts are distributed below and in contact with the source line mesh. | 2021-10-14 |
20210320123 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - Disclosed is a three-dimensional semiconductor memory device including a carbon-containing layer on a substrate, a plurality of electrode interlayer dielectric layers and a plurality of electrode layers that are alternately stacked on the carbon-containing layer, a cell vertical pattern that penetrates at least some of the electrode interlayer dielectric layers and the electrode layers, and a semiconductor pattern between the cell vertical pattern and the carbon-containing layer. The substrate includes a plurality of first grains. The semiconductor pattern includes a plurality of second grains. An average size of the second grains is less than an average size of the first grains. | 2021-10-14 |
20210320124 | THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME - Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A first polysilicon layer, a dielectric sacrificial layer, a second polysilicon layer, and a dielectric stack are sequentially formed above a substrate. A channel structure extending vertically through the dielectric stack, the second polysilicon layer, and the dielectric sacrificial, and into the first polysilicon layer is formed. An opening extending vertically through the dielectric stack and the second polysilicon layer, and extending vertically into or through the dielectric sacrificial layer to expose part of the dielectric sacrificial layer, and a polysilicon spacer along part of a sidewall of the opening are formed. The dielectric sacrificial layer is replaced, through the opening, with a third polysilicon layer between the first and second polysilicon layers. | 2021-10-14 |
20210320125 | VERTICAL MEMORY DEVICES - A vertical memory device includes a gate electrode structure, a channel, an insulation pattern structure, an etch stop structure, and a through via. The gate electrode structure includes gate electrodes spaced apart from each other on a substrate in a first direction perpendicular to an upper surface of the substrate, and each of the gate electrodes extends in a second direction parallel to the upper surface of the substrate. The channel extends in the first direction through the gate electrode structure. The insulation pattern structure extends through the gate electrode structure. The etch stop structure extends through the gate electrode structure and surround at least a portion of a sidewall of the insulation pattern structure, and the etch stop structure includes a filling pattern and an etch stop pattern on a sidewall of the filling pattern. The through via extends in the first direction through the insulation pattern structure. | 2021-10-14 |
20210320126 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES - In a 3D semiconductor memory device, a stack structure includes electrodes and first insulating layers disposed between the electrodes. The stack structure has a stair structure on a connection region. A vertical channel structure penetrates the stack structure on a cell array region. A vertical dummy structure penetrates the stair structure on the connection region. A second insulating layer is selectively disposed on the cell array region. A maximum thickness of the second insulating layer ranges from 1.5 times to 10 times a maximum thickness of the first insulating layer on the second insulating layer. The vertical channel structure includes an abrupt diameter change at a level of a top surface of the second insulating layer. The abrupt diameter change has a surface which is parallel to the top surface of the second insulating layer and is substantially coplanar with the top surface of the second insulating layer. | 2021-10-14 |
20210320127 | DISPLAY PANEL - The present invention provides a display panel, and by means of using a plurality of sub-pixels as a sub-pixel unit, each sub-pixel unit corresponds to one gate fan-out line, such that a number of the gate fan-out lines of a pixel unit can be reduced, a width of a pixel opening area can be increased, and an aperture ratio (AR %) and response time (TR %) of the panel can be improved. | 2021-10-14 |
20210320128 | DISPLAY DEVICE - To suppress fluctuation in the threshold voltage of a transistor, to reduce the number of connections of a display panel and a driver IC, to achieve reduction in power consumption of a display device, and to achieve increase in size and high definition of the display device. A gate electrode of a transistor which easily deteriorates is connected to a wiring to which a high potential is supplied through a first switching transistor and a wiring to which a low potential is supplied through a second switching transistor; a clock signal is input to a gate electrode of the first switching transistor; and an inverted clock signal is input to a gate electrode of the second switching transistor. Thus, the high potential and the low potential are alternately applied to the gate electrode of the transistor which easily deteriorates. | 2021-10-14 |
20210320129 | DISPLAY DEVICE - By applying an AC pulse to a gate of a transistor which easily deteriorates, a shift in threshold voltage of the transistor is suppressed. However, in a case where amorphous silicon is used for a semiconductor layer of a transistor, the occurrence of a shift in threshold voltage naturally becomes a problem for a transistor which constitutes a part of circuit that generates an AC pulse. A shift in threshold voltage of a transistor which easily deteriorates and a shift in threshold voltage of a turned-on transistor are suppressed by signal input to a gate electrode of the transistor which easily deteriorates through the turned-on transistor. In other words, a structure for applying an AC pulse to a gate electrode of a transistor which easily deteriorates through a transistor to a gate electrode of which a high potential (VDD) is applied, is included. | 2021-10-14 |
20210320130 | DISPLAY SUBSTRATE AND DISPLAY APPARATUS - A display substrate has an active area which includes a photosensitive region with a light-transmitting channel. The display substrate includes a base, a pixel circuit layer, a first insulating layer and a conductive light-shielding layer. The pixel circuit layer includes pixel circuits and at least one pixel circuit includes a first thin film transistor and a second thin film transistor. The first insulating layer has a first via hole. The conductive light-shielding layer includes a conductive light-shielding pattern that has a first light-transmitting hole. Orthogonal projections of the first light-transmitting hole and of a gap region between the first thin film transistor and the second thin film transistor have a first overlapping region, which the light-transmitting channel penetrates. The conductive light-shielding pattern is coupled with a source electrode or a drain electrode of the first thin film transistor through the first via hole. | 2021-10-14 |
20210320131 | SEMICONDUCTOR STRUCTURE - The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductive substrate and an oxidation region formed on the semiconductive substrate. The oxidation region includes a stage with a first width along a horizontal direction. The semiconductor structure further includes a fin formed on a top surface of the stage. A method for forming the semiconductor structure is also provided. | 2021-10-14 |
20210320132 | Display device - The disclosed display device includes: a substrate; a gate electrode disposed on the substrate; a data line disposed on the substrate and extending along an extension direction; and a connecting member disposed on the substrate and electrically connecting to the gate electrode, wherein the connecting member includes a first part overlapped with the gate electrode and a second part not overlapped with the gate electrode, and a minimum width of the second part in a direction perpendicular to the extension direction is less than a maximum width of the first part in the direction. | 2021-10-14 |
20210320133 | ARRAY SUBSTRATE AND MOTHER-BOARD FOR ARRAY SUBSTRATES - The application discloses an array substrate and a mother-board for array substrates. The array substrate includes a display area and a non-display area on a periphery of the display area. The non-display area is provided with an interface area. The array substrate includes: multiple signal lines extending in the display area and leading to the non-display area; multiple pads located in the interface Area, and each of the multiple pads is connected to a corresponding one of the multiple signal lines; and a short-circuiting component located in the non-display area, wherein the short-circuiting component is connected with the multiple pads, the multiple signal lines connected with the pads are short-circuited, and the short-circuiting component includes a patterned first metal structure. The array substrate according to embodiments of the present application can avoid problems caused by static electricity, such as, electrostatic damage or product defects. | 2021-10-14 |
20210320134 | MONOLITHIC MULTI-METALLIC THERMAL EXPANSION STABILIZER - A monolithic multi-metallic thermal expansion stabilizer (MTES) has a coefficient of thermal expansion (CTE) differential between a first surface and a second surface, and a transition region extending between for mitigating the CTE differential. | 2021-10-14 |
20210320135 | IMAGING DEVICE AND ELECTRONIC APPARATUS - An imaging device that smoothly transfers electric charges from a photoelectric converter to a transfer destination is provided. This imaging device includes: a semiconductor layer; a photoelectric converter that generates electric charges corresponding to a received light amount; and a transfer section that includes a first trench gate and a second trench gate and transfers the electric charges from the photoelectric converter to a single transfer destination via the first trench gate and the second trench gate, the first trench gate and the second trench gate each extending from the front surface to the back surface of the semiconductor layer into the photoelectric converter. The first trench gate has a first length from the front surface to the photoelectric converter, and the second trench gate has a second length from the front surface to the photoelectric converter, the second length being shorter than the first length. | 2021-10-14 |
20210320136 | IMAGE PICKUP APPARATUS AND METHOD FOR MANUFACTURING IMAGE PICKUP APPARATUS - An image pickup apparatus includes a cover glass including a first principal surface and a second principal surface, an image pickup member which includes a light receiving surface and a rear surface and in which the light receiving surface is disposed on the second principal surface which is larger than the light receiving surface, and a first resin disposed around the image pickup member of the second principal surface, having the same external size of a cross-section orthogonal to an optical axis as an external size of a cross-section of the second principal surface, and including a trench parallel to the optical axis on a side surface, and a second resin disposed in the trench. | 2021-10-14 |
20210320137 | DETECTION MODULE AND DISPLAY DEVICE HAVING THE SAME - A detection module for a display device includes: a substrate; a detector disposed on the substrate to detect an external signal; a sensor driving circuit disposed on the substrate to drive the detector; and a light shielding layer to block an external light from entering the sensor driving circuit and to receive a light blocking voltage. | 2021-10-14 |
20210320138 | IMAGE SENSING DEVICE - An image sensing device includes a substrate, a first reflector, and at least one second reflector. The substrate includes a photoelectric conversion element corresponding to each unit pixel. The first reflector is disposed in a manner that at least some parts of the first reflector overlap with the photoelectric conversion element, and is configured to reflect incident light directed to the photoelectric conversion element in a direction away from the photoelectric conversion element. The second reflect disposed over the substrate is configured to reflect the incident light reflected by the first reflector in a direction along which the incident light moves again closer to the photoelectric conversion element. | 2021-10-14 |
20210320139 | DEVICE OVER PHOTODETECTOR PIXEL SENSOR - Various embodiments of the present application are directed towards a semiconductor-on-insulator (SOI) DoP image sensor and a method for forming the SOI DoP image sensor. In some embodiments, a semiconductor substrate comprises a floating node and a collector region. A photodetector is in the semiconductor substrate and is defined in part by a collector region. A transfer transistor is over the semiconductor substrate. The collector region and the floating node respectively define source/drain regions of the transfer transistor. A semiconductor mesa is over and spaced from the semiconductor substrate. A readout transistor is on and partially defined by the semiconductor mesa. The semiconductor mesa is between the readout transistor and the semiconductor substrate. A via extends from the floating node to a gate electrode of the readout transistor. | 2021-10-14 |
20210320140 | SOLID-STATE IMAGING DEVICE AND IMAGING DEVICE - An imaging device includes a photoelectric conversion region that converts incident light into electric charge. The imaging device includes a first readout circuit coupled to the photoelectric conversion region at a first location, and a second readout circuit including a portion coupled to the photoelectric conversion region at a second location. The second readout circuit is configured to control the first readout circuit. The first location and the second location are on a same side of the photoelectric conversion region. | 2021-10-14 |
20210320141 | SEMICONDUCTOR DEVICE AND IMAGING DEVICE - To improve the joining strength between semiconductor chips. In a semiconductor device, a first semiconductor chip includes a first joining surface including a first insulating layer, a plurality of first pads to which a first inner layer circuit insulated by the first insulating layer is electrically connected, and a linear first metal layer arranged on an outside of the plurality of first pads. A second semiconductor chip includes a second joining surface joined to the first joining surface, the second joining surface including a second insulating layer, a plurality of second pads that are arranged in positions facing the first pads and to which a second inner layer circuit insulated by the second insulating layer is electrically connected, and a linear second metal layer arranged in a position facing the first metal layer. A width of the first metal layer and the second metal layer is a width based on a joining strength between the first insulating layer and the second insulating layer and a joining strength between the first metal layer and the second metal layer in an area from an end portion of the first semiconductor chip to the first pad. | 2021-10-14 |
20210320142 | IMAGE PICKUP UNIT AND IMAGING APPARATUS - An image pickup unit includes: a printed wiring board provided with an image pickup element and having a first electrode on a surface layer; a flexible wiring substrate having a base member having first and second faces, a conductive layer provided on the first face, and an insulating layer provided on the conductive layer, wherein the conductive layer has a second electrode in which the insulating layer is not provided to one longitudinal end part; a conductive connection member that connects the first electrode to the second electrode; and a reinforcement member provided on the base member on the second face side, wherein the reinforcement member continuously covers an end part of the insulating layer on a side closer to the second electrode and an end part of the conductive connection member on a side closer to the insulating layer of a portion connected to the second electrode. | 2021-10-14 |
20210320143 | IMAGE SENSOR AND IMAGING SYSTEM COMPRISING THE SAME - The present invention relates to an image sensor and to an imaging system comprising the same. The present invention particularly relates to X-ray image sensors and imaging systems. | 2021-10-14 |
20210320144 | BACK-ILLUMINATED SENSOR AND A METHOD OF MANUFACTURING A SENSOR USING A SILICON ON INSULATOR WAFER - An image sensor is fabricated by first heavily p-type doping the thin top monocrystalline silicon substrate of an SOI wafer, then forming a relatively lightly p-doped epitaxial layer on a top surface of the top silicon substrate, where p-type doping levels during these two processes are controlled to produce a p-type dopant concentration gradient in the top silicon substrate. Sensing (circuit) elements and associated metal interconnects are fabricated on the epitaxial layer, then the handling substrate and oxide layer of the SOI wafer are at least partially removed to expose a lower surface of either the top silicon substrate or the epitaxial layer, and then a pure boron layer is formed on the exposed lower surface. The p-type dopant concentration gradient monotonically decreases from a maximum level near the top-silicon/epitaxial-layer interface to a minimum concentration level at the epitaxial layer's upper surface. | 2021-10-14 |
20210320145 | Light Emitting Diode Structure and Method for Manufacturing the Same - The LED structure includes a substrate and a plurality of LED units formed on the substrate. Each LED unit includes a bonding layer formed on the substrate, a first doping type semiconductor layer formed on the bonding layer, a second doping type semiconductor layer formed on the first doping type semiconductor layer, a passivation layer formed on the second doping type semiconductor layer and a portion of the first doping type semiconductor layer; and an electrode layer formed on a portion of the passivation layer and contacting the second doping type semiconductor layer. The plurality of LED units include a first LED unit and a second LED unit adjacent to the first LED unit. The first doping type semiconductor layer of the first LED unit horizontally extends to the first doping type semiconductor layer of the second LED unit adjacent to the first LED unit, and the first LED unit and the second LED unit are individually functionable LED units. | 2021-10-14 |
20210320146 | DISPLAY DEVICE USING SEMICONDUCTOR LIGHT-EMITTING ELEMENTS - A display device is discussed. The Display device includes a plurality of semiconductor light-emitting elements on a substrate, wherein the substrate includes: a base substrate; an insulating layer on the base substrate; and pads protruding farther than the insulating layer and enabling the semiconductor light-emitting elements to in contact, wherein the insulating layer includes inorganic particles, and at least a portion of some of the inorganic particles is formed so as to protrude from a surface of the insulating layer. | 2021-10-14 |
20210320147 | PHASE CHANGE MEMORY STRUCTURE AND MANUFACTURING METHOD FOR THE SAME - Present disclosure provides a semiconductor structure and a method for fabricating a semiconductor device. The semiconductor includes a transistor, a first metallization layer over the transistor, a phase change material over the first metallization layer, a second metallization layer over the phase change material, a heater between the first metallization layer and the second metallization layer and in contact with the phase change material, the heater including a heat insulation shell having a first heat conductivity, wherein the heat insulation shell includes a superlattice structure, and a heat conducting core contacting the heat insulation shell and having a second heat conductivity different from the first heat conductivity. | 2021-10-14 |
20210320148 | CROSSBAR ARRAY CIRCUIT WITH PARALLEL GROUNDING LINES - Technologies relating to crossbar array circuits with parallel grounding lines are disclosed. An example crossbar array circuit includes: a word line; a bit line; a first selector line; a grounding line; a first transistor including a first source terminal, a first drain terminal, a first gate terminal, and a first body terminal; and an RRAM device connected in series with the first transistor. The grounding line is connected to the first body terminal and is grounded and the grounding line parallel to the bit line. The first selector line is connected to the first gate terminal. In some implementations, the RRAM device is connected between the first transistor via the first drain terminal and the word line, and the first source terminal is connected to the bit line. | 2021-10-14 |