41st week of 2021 patent applcation highlights part 51 |
Patent application number | Title | Published |
20210320149 | PHOTOELECTRIC CONVERSION ELEMENT AND SOLID-STATE IMAGING DEVICE - A photoelectric conversion element according to an embodiment of the present disclosure includes: a first electrode and a second electrode facing each other; and a photoelectric conversion layer provided between the first electrode and the second electrode, and including a first organic semiconductor material, a second organic semiconductor material, and a third organic semiconductor material that have mother skeletons different from one another. The first organic semiconductor material is one of fullerenes and fullerene derivatives. The second organic semiconductor material in a form of a single-layer film has a higher linear absorption coefficient of a maximal light absorption wavelength in a visible light region than a single-layer film of the first organic semiconductor material and a single-layer film of the third organic semiconductor material. The third organic semiconductor material has a value equal to or higher than a HOMO level of the second organic semiconductor material. | 2021-10-14 |
20210320150 | DISPLAY DEVICE - A display device includes: a first substrate including a display area to emit a light having a peak wavelength from light emitting areas and a non-display area surrounding the display area; and a second substrate including transparent areas overlapping the light emitting areas and to convert the peak wavelength of the light or to transmit the light through the transparent areas. The second substrate includes: a base layer including the transparent areas, an inner light blocking area arranged between the transparent areas, and an outer light blocking area arranged outside the transparent areas; a color filter on the base layer; and a light blocking layer above the color filter and including an outer light blocking layer overlapping the outer light blocking area and an inner light blocking layer overlapping the inner light blocking area. | 2021-10-14 |
20210320151 | LIGHT-EMITTING DEVICE - The light-emitting device includes a light-emitting element in which a first electrode, a light-emitting layer, and a second electrode are sequentially layered toward a side of a light-emitting face. Further, the light-emitting device includes, on a side of the light-emitting face of the second electrode, a complementary color light absorption layer configured to absorb complementary color light of light emitted by the light-emitting element. | 2021-10-14 |
20210320152 | ORGANIC LIGHT-EMITTING DIODE DISPLAY SUBSTRATE AND DISPLAY DEVICE - The present disclosure provides an organic light-emitting diode display substrate, a method of preparing the same, and a display device. The organic light-emitting diode display substrate includes: a light-emitting layer, a light modulation layer, and a color conversion layer, in which the light-emitting layer is configured to emit first color light, the light modulation layer and the color conversion layer are arranged on different light-exiting paths of the light-emitting layer, the color conversion layer is configured to convert first color light into second color light and third color light, and the light modulation layer is configured to modulate an emergent direction of first color light. | 2021-10-14 |
20210320153 | DISPLAY PANEL AND DISPLAY DEVICE - A display panel and a display device are provided. The display panel includes a light-emitting layer, a first insulation layer, a first metal layer, a second insulation layer, and a second metal layer. The first metal layer includes a bridging layer and a first floating pattern. The second metal layer includes a driving electrode and a sensing electrode disposed in a same layer. This prevents a fracture structure and improves display effects and product performance of the display device. | 2021-10-14 |
20210320154 | ORGANIC LIGHT-EMITTING DEVICE - An electronic apparatus comprising:
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20210320155 | DISPLAY DEVICE - A display device includes: a first base layer; a circuit element layer on the first base layer; a pixel definition layer on the circuit element layer and comprising a plurality of light-emitting openings which are spaced apart from each other and define a plurality of light-emitting regions; a second base layer spaced apart from and facing the first base layer; a light-shielding layer on the second base layer and comprising a plurality of openings respectively overlapping the light-emitting regions, wherein on a plane of the first base layer, shapes of first to third openings along one direction among the openings are different from each other. | 2021-10-14 |
20210320156 | DISPLAY SUBSTRATE AND DISPLAY DEVICE - A display substrate and a display device are provided. The display substrate includes sub-pixels including a light emitting element and a pixel circuit, the light emitting element includes a second electrode including a main body electrode. The sub-pixels include a first color sub-pixel which includes a first connecting portion. In the first color sub-pixel, the connecting electrode is connected with the first connecting portion through a first via hole, and the first connecting portion is electrically connected with the pixel circuit through a first connecting hole; and the first via hole and the first connecting hole are not overlapped with the main body electrode, and orthographic projections of the first via hole and the first connection hole on a first straight line extending in an extension direction of the data line are overlapped. | 2021-10-14 |
20210320157 | DISPLAY PANEL AND DISPLAY DEVICE - A display panel includes a substrate, sub-pixels, and a black matrix. Each sub-pixel includes a pixel drive circuit and a light-emitting element. The light-emitting element includes an anode connected to M trace lead-out ends. At least portion of the trace lead-out end is electrically connected to pixel drive circuit through connection trace, M≥1. The black matrix has openings where the anode is exposed. The portion of the trace lead-out end exposed in the opening is a connection end. The sub-pixels include first and second sub-pixels having different light-emitting colors. In the first sub-pixel, M connection ends include at least one first connection end. In the second sub-pixel, M connection ends include at least one second connection end. Extension directions of first connection ends are parallel to extension direction of one second connection end, respectively. The first and second connection ends having parallel extension directions have similar profiles. | 2021-10-14 |
20210320158 | DISPLAY DEVICE AND SEMICONDUCTOR DEVICE - The purpose of the present invention is to increase ON current of the oxide semiconductor thin film transistor. An example of the structure that attains the purpose is:
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20210320159 | DISPLAY DEVICE HAVING A GROOVE IN A BLOCKING REGION - A display device includes a substrate including a display area and a non-display area adjacent to the display area. The non-display area includes a blocking region. An organic layer is disposed on the substrate. An emission layer is disposed in the display area of the substrate. An auxiliary pattern is disposed in the blocking region of the non-display area of the substrate. A thin film encapsulation layer is disposed on the substrate and overlaps the emission layer and the blocking region. The organic layer has a groove penetrating an entire thickness of the organic layer in the blocking region. The auxiliary pattern overlaps the groove. The auxiliary pattern includes a same material as a gate electrode disposed in the display area of the substrate. | 2021-10-14 |
20210320160 | OLED PIXEL STRUCTURE, OLED DISPLAY SCREEN, AND ELECTRONIC DEVICE - An organic light-emitting diode (OLED) pixel structure includes a substrate, a first electrode, a pixel layer, and a second electrode that are sequentially stacked, and an isolation column. The pixel layer includes a plurality of pixel points disposed in an array. Two adjacent pixel points cooperatively define a gap therebetween. Parts of the first electrode and the second electrode corresponding to the gap are hollowed out. A part of the isolation column is accommodated in the gap. The isolation column includes a first end surface facing the substrate and a second end surface facing away from the substrate. The isolation column is configured to allow the optical signal to pass in from one of the first end surface and the second end surface and pass out from the other end surface. An OLED display screen and an electronic device are also provided. | 2021-10-14 |
20210320161 | DOUBLE-SIDED E-PAPER DISPLAY PANEL, DISPLAY DEVICE AND OPERATING METHOD THEREOF - The present invention provides a double-sided e-paper display panel including a first substrate, a second substrate, a light isolation layer, a first display medium layer, a second display medium layer, a first electrode layer, and a second electrode layer. The second substrate and the first substrate are disposed opposite to each other. The light isolation layer is disposed between the first substrate and the second substrate. The first display medium layer is disposed between the first substrate and the light isolation layer. The second display medium layer is disposed between the light isolation layer and the second substrate. The first display medium layer and the second display medium layer include a fluid and a plurality of charged particles. The first electrode layer is disposed between the first substrate and the first display medium layer. The second electrode layer is disposed between the second display medium layer and the second substrate. | 2021-10-14 |
20210320162 | DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME - A display device includes a substrate, a first conductive layer on the substrate and including a lower light blocking pattern and a first signal line, a buffer layer on the first conductive layer, a semiconductor layer on the buffer layer and including a first semiconductor pattern and a second semiconductor pattern separated from the first semiconductor pattern, an insulating layer on the semiconductor layer and including an insulating layer pattern, a second conductive layer on the insulating layer and including a second signal line, a planarization layer on the second conductive layer, and a third conductive layer on the planarization layer and including an anode electrode. The first semiconductor pattern is electrically connected to the lower light blocking pattern by the anode electrode, and at least a portion of the second semiconductor pattern is isolated from and overlaps each of the first signal line and the second signal line. | 2021-10-14 |
20210320163 | DISPLAY DEVICE - A display device includes: a base part including a display area including a plurality of pixels each having at least one switching element and a light-emitting element, a non-display area surrounding the display area, and a through hole surrounded by the display area and configured to transmit light; a plurality of first lines extending in a first direction on the base part and connected to the plurality of pixels; and connection lines bypassing the through hole and extending in the display area to connect between the first lines spaced apart from one another by the through hole among the plurality of first lines. | 2021-10-14 |
20210320164 | DISPLAY PANEL AND DISPLAY DEVICE HAVING THE SAME - A display panel includes a first display area having a first light transmittance and a second display area having a second light transmittance that is higher than the first light transmittance. The display panel further comprises a plurality of first pixels disposed in the first display area and a plurality of second pixels disposed in the second display area. A first power line is connected to the plurality of first pixels. The first power line is configured to provide a first power voltage. A second power line is connected to the plurality of second pixels. The second power line is configured to provide a second power voltage having a voltage level that is different from a voltage level of the first power voltage. | 2021-10-14 |
20210320165 | DISPLAY DEVICE - A display device may include a substrate including a display area and a peripheral area adjacent to the display area, fan-out lines disposed in the peripheral area of the substrate, an insulation layer disposed on the fan-out lines, at least one first dam disposed on the insulation layer in the peripheral area, the at least one first dam surrounding the display area, a second dam disposed on the insulation layer in the peripheral area, the second dam surrounding the at least one first dam, and a blocking pattern disposed between the insulation layer and an edge of the second dam adjacent to the at least one first dam. | 2021-10-14 |
20210320166 | DISPLAY SUBSTRATE, DISPLAY PANEL AND DISPLAY APPARATUS - A display substrate includes a plurality of data lines and a plurality of columns of pixel driving circuits. A column of pixel driving circuits is connected to a corresponding data line, and each pixel driving circuit includes a driving transistor and a first transistor. The driving transistor is a P-type transistor. The first transistor includes: a first active pattern having a first channel region, and a first doped region and a second doped region on two opposite sides of the first channel region; a first gate; and a first insulating block disposed on a side of the first active pattern away from the base and having a first via. The data line is connected to a portion of the first active pattern located in the first doped region through the first via. Sizes of all first vias in the column of pixel driving circuits gradually decrease in a first direction. | 2021-10-14 |
20210320167 | DISPLAY PANEL, PREPARATION METHOD FOR DISPLAY PANEL AND DISPLAY DEVICE - The present disclosure discloses a display panel, a method for preparing the display panel, and a display device. The display panel is divided into a display area and a non-display area. The display panel in the non-display area includes: a substrate; a metal wiring layer arranged on the substrate, the metal wiring layer including metal wirings; a planarization layer covering the substrate and the metal wiring layer, the planarization layer being provided with grooves corresponding to the metal wirings, and the grooves each being located on a side, facing away from the substrate, of a metal wiring corresponding to the each groove and exposing the metal wiring; and a flexible electrode layer filling the grooves, the flexible electrode layer being coupled to the metal wiring layer located at bottoms of the grooves. | 2021-10-14 |
20210320168 | DISPLAY DEVICE AND MANUFACTURING METHOD OF DISPLAY DEVICE - A display device includes a display module and a circuit board. The display module includes a base substrate, which includes a display area and a non-display area adjacent to the display area, and a first pad positioned on the base substrate and overlapping the non-display area. The circuit board includes a first board and a second pad positioned on the first board and contacting the first pad, wherein the second pad is provided with a first metal layer of a single material. | 2021-10-14 |
20210320169 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A semiconductor structure and a method for forming the semiconductor structure are provided. The semiconductor structure includes a substrate and a dummy gate structure on the substrate. The substrate contains source-drain openings on both sides of the dummy gate structure. The semiconductor structure also includes a first stress layer formed on a sidewall of a source-drain opening of the source-drain openings. Further, the semiconductor structure includes a second stress layer formed at a bottom of the source-drain opening and on the first stress layer. The second stress layer fully fills the source-drain opening, and stress of the first stress layer is less than stress of the second stress layer. | 2021-10-14 |
20210320170 | Insulated Gate Power Semiconductor Device and Method for Manufacturing Such Device - An insulated gate power semiconductor device ( | 2021-10-14 |
20210320171 | SUPERJUNCTION SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SUPERJUNCTION SEMICONDUCTOR DEVICE - A method of manufacturing a superjunction device, including forming a first semiconductor layer of a first conductivity type on a semiconductor substrate, forming a plurality of first trenches from the first semiconductor layer, forming a second semiconductor layer of the first conductivity type on the first semiconductor layer and in the first trenches, implanting an impurity of a second conductivity type in the second semiconductor layer, thereby forming a plurality of well regions of the second conductivity type, and a parallel pn structure including first and second columns alternating one another repeatedly in a direction parallel to a surface of the semiconductor substrate, forming a plurality of second trenches penetrating through the second semiconductor layer and reaching the first columns, forming a plurality of second semiconductor regions of the second conductivity type in the well regions in the active region, and selectively forming a plurality of first semiconductor regions of the first conductivity type in the second semiconductor regions. | 2021-10-14 |
20210320172 | SEMICONDUCTOR DEVICE WITH AIR GAP AND METHOD OF FABRICATING THE SAME - A semiconductor device with an air gap includes a plurality of gate stacks disposed on a substrate; a liner layer conformally covering the gate stacks and the substrate; and a dielectric stack disposed on the liner layer on the gate stacks. The air gap is formed between the liner layer and the dielectric stack on two adjacent gate stacks. A height of the air gap is greater than heights of the two adjacent gate stacks, and the air gap includes: a lower portion between the two adjacent gate stacks, sidewalls and a bottom of the lower portion exposing the liner layer; a middle portion above the lower portion; and an upper portion above the middle portion. Sidewalls of the upper portion expose the dielectric stack, a top surface of the upper portion is covered by the dielectric stack, and the upper portion has a smaller width than the lower portion. | 2021-10-14 |
20210320173 | DEFORMABLE ELECTRONIC DEVICE AND METHOD OF MAKING A DEFORMABLE ELECTRONIC DEVICE - A method of making a deformable electronic device comprises forming a multilayer device structure comprising functional layers on a flexible substrate. At least one, some or all of the functional layers comprises a stack of 2D monolayers, and a number or proportion of misaligned interfaces within each stack of 2D monolayers is controlled to obtain a predetermined bending stiffness. Each of the misaligned interfaces comprises a twist angle and/or lattice mismatch between adjacent 2D monolayers. The functional layers may include electronically active layers and other layers having a dielectric, insulating, and/or protective function. | 2021-10-14 |
20210320174 | VERTICAL POWER SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD - A vertical power semiconductor device is proposed. The vertical power semiconductor device includes a semiconductor body having a first main surface and a second main surface opposite to the first main surface along a vertical direction. The vertical power semiconductor device further includes a drift region in the semiconductor body. The drift region includes platinum atoms. The vertical power semiconductor device further includes a field stop region in the semiconductor body between the drift region and the second main surface. The field stop region includes a plurality of impurity peaks. A first impurity peak of the plurality of impurity peaks has a larger concentration than a second impurity peak of the plurality of impurity peaks. The first impurity peak includes hydrogen and the second impurity peak includes helium. | 2021-10-14 |
20210320175 | TRANSISTOR CIRCUIT WITH ASYMMETRICAL DRAIN AND SOURCE - The parasitic capacitance of a transistor may be reduced by mismatching the source and drain. Faster low finger count transistors may be achieved with lower drain capacitance and a frequency gain on the D1 inverter as described for the examples herein. In one such example, a transistor includes a source and a drain wherein a length of the source is more than a length of the drain, a width of the source is more than a width of the drain, or a height of the source is more than a height of the drain. | 2021-10-14 |
20210320176 | SEMICONDUCTOR DEVICE - A semiconductor device with enhanced semiconductor characteristics that is useful for power devices. A semiconductor device, including: an n-type semiconductor layer; an electrode; two or more p-type semiconductors that is provided between the n-type semiconductor layer and the electrode, the n-type semiconductor layer containing gallium, a number of the two or more p-type semiconductors that is equal to or more than three, and the two or more p-type semiconductors that are embedded in the n-type semiconductor layer. | 2021-10-14 |
20210320177 | SILICON WAFER AND MANUFACTURING METHOD OF THE SAME - A silicon wafer having a layer of oxygen precipitates and method of manufacturing thereof wherein the wafer exhibiting robustness characterized as having a ratio of a first average density from a first treatment that to a second average density from a second treatment is between 0.74 to 1.02, wherein the first treatment includes heating the wafer or a portion of the wafer at about 1150° C. for about 2 minutes and then between about 950 to 1000° C. for about 16 hours, and the second treatment includes heating the wafer or a portion of the wafer at about 780° C. for about 3 hours and then between about 950 to 1000° C. for about 16 hours. The wafer exhibits heretofore unattainable uniformity wherein a ratio of an oxygen precipitate density determined from any one cubic centimeter in the BMD layer of the wafer to another oxygen precipitate density from any other one cubic centimeter in the BMD layer of the wafer is in a range of 0.77 to 1.30. | 2021-10-14 |
20210320178 | Electronic Device Including a Transistor and a Shield Electrode - An electronic device can include a substrate, an active region of a transistor, and a shield electrode. The substrate can define a trench and include a mesa adjacent to the trench, and the shield electrode can be within the trench. In an embodiment, the electronic device can further include an active region of a transistor within the mesa and an insulating layer including a thicker section and a thinner section closer to a bottom of the trench. In another embodiment, the electronic device can include a body region and a doped region within the mesa and spaced apart from the body region by a semiconductor region. The doped region can have a dopant concentration that is higher than a dopant concentration of the semiconductor region and a portion of the substrate underlying the doped region. | 2021-10-14 |
20210320179 | SEMICONDUCTOR DEVICE - A semiconductor device with enhanced semiconductor characteristics that is useful for power devices. A semiconductor device, including: an n-type semiconductor layer; one or more p-type semiconductors; an electrode, the one or more p-type semiconductors that are provided between the n-type semiconductor layer and the electrode, and at least a part of the one or more p-type semiconductors is protruded in the electrode. | 2021-10-14 |
20210320180 | Semiconductor Device and Method - In an embodiment, a device includes: a gate electrode; a epitaxial source/drain region adjacent the gate electrode; one or more inter-layer dielectric (ILD) layers over the epitaxial source/drain region; a first source/drain contact extending through the ILD layers, the first source/drain contact connected to the epitaxial source/drain region; a contact spacer surrounding the first source/drain contact; and a void disposed between the contact spacer and the ILD layers. | 2021-10-14 |
20210320181 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a source/drain region, a body region, a first gate structure, and a second gate structure. The source/drain region and the body region are in a substrate. The first and second gate structures are above the substrate. The source/drain region and the body region are on opposite sides of the first gate structure. The second gate structure is spaced apart from the first gate structure. The source/drain region, the body region, and the first gate structure are on a same side of the second gate structure. | 2021-10-14 |
20210320182 | CHARGE-TRAPPING LAYER WITH OPTIMIZED NUMBER OF CHARGE-TRAPPING SITES FOR FAST PROGRAM AND ERASE OF A MEMORY CELL IN A 3-DIMENSIONAL NOR MEMORY STRING ARRAY - A thin-film memory transistor includes a source region, a drain region, a channel region, a gate electrode, and a charge-trapping layer provided between the channel region and the gate electrode and electrically isolated therefrom, wherein the charge-trapping layer has includes a number of charge-trapping sites that is 70% occupied or evacuated using a single voltage pulse of a predetermined width of 500 nanoseconds or less and a magnitude of 15.0 volts or less. The charge-trapping layer comprises silicon-rich nitride may have a refractive index of 2.05 or greater or comprises nano-crystals of germanium (Ge), zirconium oxide (ZrO | 2021-10-14 |
20210320183 | DISTRIBUTED CURRENT LOW-RESISTANCE DIAMOND OHMIC CONTACTS - In some embodiments, a semiconductor structure can include: a diamond substrate having a surface conductive layer; a heavily doped region formed in the diamond substrate; and a metal contact positioned over the conductive surface layer such that a first portion of the heavily doped region is covered by the metal contact and a second portion of the heavily doped region is not covered by the metal contact. | 2021-10-14 |
20210320184 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND TESTING DEVICE - Provided is a semiconductor device, including: a compound semiconductor layer; a first insulating film provided on the compound semiconductor layer; a second insulating film, which is formed of a material different from the first insulating film, provided on the first insulating film; and a gate electrode provided above the second insulating film. The first insulating film may include tantalum oxynitride, and the second insulating film may include a material with a larger band gap than tantalum oxynitride. The second insulating film may include aluminum oxynitride. | 2021-10-14 |
20210320185 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a semiconductor device includes forming a fin structure comprising alternately stacked first semiconductor layers and second semiconductor layers over a substrate. A sacrificial gate structure is formed over the fin structure. Spacers are formed on either side of the sacrificial gate structure. The sacrificial gate structure is removed to form a trench between the spacers. The first semiconductor layers are removed from the trench, while leaving the second semiconductor layers suspended in the trench. A self-assembling monolayer is formed on sidewalls of the spacers in the trench. Interfacial layers are formed encircling the suspended second semiconductor layers, respectively. A high-k dielectric layer is deposited at a faster deposition rate on the interfacial layers than on the self-assembling monolayer. A metal gate structure is formed over the high-k dielectric layer. | 2021-10-14 |
20210320186 | SELF-ALIGNED UNIFORM BOTTOM SPACERS FOR VTFETS - Semiconductor devices and methods of forming the same include forming a bottom source/drain structure around a fin. A multi-layer bottom spacer is formed on the bottom source/drain structure, around the fin. Each layer of the multi-layer bottom spacer has a respective vertical height above the bottom source/drain structure, with a layer of the multi-layer bottom spacer that is farthest from the fin having a greater vertical height than a layer that is closest to the fin, to address parasitic capacitance from the bottom source/drain structure. | 2021-10-14 |
20210320187 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a first gate structure on the NMOS region and a second gate structure on the PMOS region; forming a seal layer on the first gate structure and the second gate structure; forming a first lightly doped drain (LDD) adjacent to the first gate structure; forming a second LDD adjacent to the second gate structure; and performing a soak anneal process to boost an oxygen concentration of the seal layer for reaching a saturation level. | 2021-10-14 |
20210320188 | FINFET WITH DUMMY FINS AND METHODS OF MAKING THE SAME - A semiconductor structure includes a semiconductor fin protruding from a substrate and oriented lengthwise along a first direction, a dielectric fin disposed over the substrate and oriented lengthwise along a second direction perpendicular to the first direction, where the dielectric fin defines a sidewall of the semiconductor fin along the second direction and where the dielectric fin includes a first dielectric layer disposed over a second dielectric layer that differs from the first dielectric layer in composition, and a metal gate stack disposed over the semiconductor fin and oriented lengthwise along the second direction. | 2021-10-14 |
20210320189 | METHODS OF FORMING A REPLACEMENT GATE STRUCTURE FOR A TRANSISTOR DEVICE - One illustrative IC product disclosed herein includes a transistor device formed on a semiconductor substrate, the transistor device comprising a gate structure comprising an upper surface, a polish-stop sidewall spacer positioned adjacent the gate structure, wherein, at a location above an upper surface of the semiconductor substrate, when viewed in a cross-section taken through the first polish-stop sidewall spacer in a direction corresponding to a gate length direction of the transistor, an upper surface of the gate structure is substantially coplanar with an upper surface of the polish-stop sidewall spacer. | 2021-10-14 |
20210320190 | SUBLITHOGRAPHY GATE CUT PHYSICAL UNCLONABLE FUNCTION - Methods, and devices related to authentication of chips using physical unclonable function (PUF) are disclosed. The semiconductor chip includes a substrate. The semiconductor chip includes multiple devices formed on the substrate. Each device includes multiple fins. A gate is formed on the multiple fins with a gate cut (CT) design that results in random distribution of complete gate cut and incomplete gate cut for each of the multiple devices based on a natural process variation in semiconductor manufacturing for each device. A physical unclonable function (PUF) region is defined in accordance with the random distribution. | 2021-10-14 |
20210320191 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed over a bottom fin structure. A sacrificial gate structure having sidewall spacers is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is removed. The second semiconductor layers are laterally recessed. Dielectric inner spacers are formed on lateral ends of the recessed second semiconductor layers. The first semiconductor layers are laterally recessed. A source/drain epitaxial layer is formed to contact lateral ends of the recessed first semiconductor layer. The second semiconductor layers are removed thereby releasing the first semiconductor layers in a channel region. A gate structure is formed around the first semiconductor layers. | 2021-10-14 |
20210320192 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device with high reliability is provided. The present invention relates to a method for manufacturing a transistor including an oxide semiconductor. A stacked-layer structure of an oxide semiconductor and an insulator functioning as a gate insulator is subjected to microwave-excited plasma treatment, whereby the carrier concentration of the oxide semiconductor is reduced and the barrier property of the gate insulator is improved. In addition, a conductor functioning as an electrode and the insulator functioning as a gate insulator are formed in contact with the oxide semiconductor and then the microwave-excited plasma treatment is performed, whereby a high-resistance region and a low-resistance region can be formed in the oxide semiconductor in a self-aligned manner. Moreover, the microwave-excited plasma treatment is performed under an atmosphere containing oxygen with a high pressure, whereby a transistor having favorable electrical characteristics can be provided. | 2021-10-14 |
20210320193 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device having favorable electrical characteristics is provided. A manufacturing method of the semiconductor device includes the steps of forming a first oxide over a substrate; depositing a first insulator over the first oxide; forming an opening reaching the first oxide in the first insulator; depositing a first oxide film in contact with the first oxide and the first insulator in the opening; depositing a first insulating film over the first oxide film by a PEALD method; depositing a first conductive film over the first insulating film; and removing part of the first oxide film, part of the first insulating film, and part of the first conductive film until a top surface of the first insulator is exposed to form a second oxide, a second insulator, and a first conductor. The deposition of the first insulating film is performed while the substrate is heated to higher than or equal to | 2021-10-14 |
20210320194 | HETEROJUNCTION BIPOLAR TRANSISTOR INCLUDING BALLAST RESISTOR AND SEMICONDUCTOR DEVICE - A first sub-collector layer functions as an inflow path of a collector current that flows in a collector layer of a heterojunction bipolar transistor. A collector ballast resistor layer having a lower doping concentration than the first sub-collector layer is disposed between the collector layer and the first sub-collector layer. | 2021-10-14 |
20210320195 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device that has a plurality of gate trench portions electrically connected to a gate electrode, and a plurality of dummy trench portions electrically connected to an emitter electrode, and includes a first trench group that includes one gate trench portion and two dummy trench portions adjacent to the gate trench portion and adjacent to each other, and a second trench group that includes two gate trench portions adjacent to each other. | 2021-10-14 |
20210320196 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device is provided. The semiconductor device includes a substrate; a buffer layer on the substrate; a channel layer on the buffer layer; a barrier layer on the channel layer; a doped compound semiconductor layer on a portion of the barrier layer; an un-doped first capping layer on the doped compound semiconductor layer; a gate structure on the un-doped first capping layer; and source/drain structures on opposite sides of the gate structure. There is a channel region in the channel layer that is adjacent to the interface between the channel layer and the barrier layer. | 2021-10-14 |
20210320197 | MULTI-GATE HIGH ELECTRON MOBILITY TRANSISTORS (HEMTs) EMPLOYING TUNED RECESS DEPTH GATES FOR IMPROVED DEVICE LINEARITY - A multi-gate HEMT includes at least two gates, with at least one recessed the same depth or at a deeper depth in a barrier layer than at least one other gate. Recessing a gate decreases the thickness of the barrier layer beneath the gate, reducing a density of high mobility carriers in a two-dimensional electron gas layer (2DEG) conductive channel formed at the heterojunction of a barrier layer and a buffer layer below the recessed gate. The recessed gate can increase gate control of the 2DEG conductive channel. The multi-gate HEMT has at least one gate recessed the same depth or a deeper depth into the buffer layer than another gate, which forms at least two different turn-on voltages for different gates. This can achieve improvement of transconductance linearity and a positive shift of the threshold voltage. | 2021-10-14 |
20210320198 | TRANSISTOR - A transistor includes a substrate, a semiconductor unit disposed on the substrate, a gate unit, a source electrode and a drain electrode. The gate unit includes a non-metal gate part disposed on the semiconductor unit, and a metal gate layer entirely enclosing the non-metal gate part. The drain and source electrodes are disposed respectively on two opposite sides of the gate unit. | 2021-10-14 |
20210320199 | ENHANCEMENT-MODE SEMICONDUCTOR DEVICE AND PREPARATION METHOD THEREFOR - The present invention relates to an enhancement-mode semiconductor device and a preparation method therefor. The device includes a substrate, a semiconductor epitaxial layer, a gate electrode, a source electrode, and a drain electrode. The epitaxial layer includes a nitride nucleation layer, a nitride stress buffer layer, a nitride channel layer, a primary epitaxial nitride barrier layer, a p-type nitride layer and a secondary epitaxial nitride barrier layer. By means of etching, the p-type nitride in a gate electrode region is reserved, realizing the depletion of a gate electrode channel. By means of maskless regrowth, the secondary epitaxial nitride barrier layer is grown on the primary epitaxial barrier layer and the p-type nitride layer in the gate electrode region, realizing a high-conduction access region. | 2021-10-14 |
20210320200 | TERMINATION FOR TRENCH FIELD PLATE POWER MOSFET - A semiconductor device includes a substrate having opposed first and second major surface, an active area, and a termination area. Insulated trenches extend from the first major surface toward the second major surface, each of the insulated trenches including a conductive field plate and a gate electrode overlying the conductive field plate, the gate electrode being separated from the field plate by a gate-field plate insulator. The field plate extends longitudinally in both of the active and termination areas and the gate electrode is absent in the termination area. A body region of a first conductivity type extends laterally between pairs of the insulated trenches. First and second spacer regions of a second conductivity type extend laterally between the pairs of the insulated trenches at the termination area to produce segments of the first conductivity type between the first and second spacer regions that are isolated from the body region. | 2021-10-14 |
20210320201 | SEMICONDUCTOR DEVICE WITH RECESSED ACCESS TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - The present disclosure provides a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a substrate, a word line, a plurality of first impurity regions, a second impurity region, and an isolation film. The word line is W-shaped, is disposed in the substrate, and includes a base and a pair of legs connected to the base. The first impurity regions are disposed in the substrate and on either side of the word line. The second impurity region is disposed between the legs of the word line. The isolation film is disposed in the substrate, wherein the word line is surrounded by the isolation film. | 2021-10-14 |
20210320202 | Super Shielded Gate Trench MOSFET Having Superjunction Structure - A trenched semiconductor power device is disclosed comprising a plurality of trenched gates, each including a pair of split gate electrodes and a shielded gate electrode forming an oxide charge balance region between adjacent trenched gates, and junction charge balance region below trench bottom. The trenched semiconductor power device further comprises a super junction structure including a plurality of alternating P and N regions disposed above a substrate forming a junction charge balance region below the oxide charge balance region for breakdown voltage enhancement and on-resistance reductions. | 2021-10-14 |
20210320203 | TRANSISTOR DEVICES AND METHODS OF FORMING A TRANSISTOR DEVICE - According to various embodiments, a transistor device may include a substrate. The transistor device may further include a drain terminal and a source terminal formed in the substrate, and a gate terminal formed over the substrate. The transistor device may further include an insulator structure arranged between the drain terminal and the source terminal, and at least partially under the gate terminal. The insulator structure may include an oxide member and a trench isolation region. The oxide member may be at least partially formed over the trench isolation region. | 2021-10-14 |
20210320204 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME - The semiconductor device includes: a gate electrode on a semiconductor substrate via a gate insulating film; an offset drain layer in the semiconductor substrate on one side of the gate electrode; a drain layer on the offset drain layer; and a source layer in the semiconductor substrate on another side of the gate electrode. The semiconductor device further includes: a protective film covering the semiconductor substrate; a field plate on the protective film, and having a portion above the offset drain layer; and a field plug connected to the field plate and in the protective film and above the offset drain layer, in such a manner as to avoid reaching the offset drain layer. | 2021-10-14 |
20210320205 | LOW-NOISE GATE-ALL-AROUND JUNCTION FIELD EFFECT TRANSISTOR - A Vertical Junction Field Effect Transistor (VJFET) is disclosed with reduced noise and input capacitance and high input impedance. The VJFET has a substrate; a source disposed on the substrate; a drain; and a channel. The vertical channel has one or more channel sidewall surfaces. The channel sidewall surfaces have a total or aggregate channel sidewall surface area. A semiconductor gate grown on one or more of the channel sidewall surfaces has a thickness below 10 nanometers (nm), or between 3 nm and 10 nm, that reduces transistor noise. The interface surface area between the conductive (e.g. metal) external electrical gate contact and the contacted surface of the semiconductor gate is minimized to further reduce transistor noise. | 2021-10-14 |
20210320206 | METHOD AND APPARATUS FOR USE IN IMPROVING LINEARITY OF MOSFETS USING AN ACCUMULATED CHARGE SINK-HARMONIC WRINKLE REDUCTION - A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink. | 2021-10-14 |
20210320207 | THREE PART SOURCE/DRAIN REGION STRUCTURE FOR TRANSISTOR - A structure for a field-effect transistor includes a semiconductor body, a first gate structure extending over the semiconductor body, and a second gate structure extending over the semiconductor body. A recess is in the semiconductor body between the first and second gate structures. A three part source/drain region includes a pair of spaced semiconductor spacers in the recess; a first semiconductor layer laterally between the pair of semiconductor spacers; and a second semiconductor layer over the first semiconductor layer. The pair of spaced semiconductor spacers, the first semiconductor layer and the second semiconductor layer may all have different dopant concentrations. | 2021-10-14 |
20210320208 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A semiconductor structure and a method for forming the semiconductor structure are provided. The semiconductor structure includes a substrate and a gate structure on the substrate. The substrate contains source-drain openings on both sides of the gate structure. The semiconductor structure also includes a first stress layer formed in a source-drain opening of the source-drain openings. The first stress layer is doped with first ions. In addition, the semiconductor structure includes a protection layer over the first stress layer, and an inversion layer between the first stress layer and the protection layer. The protection layer is doped with second ions, and the inversion layer is doped with third ions. A conductivity type of the third ions is opposite to a conductivity type of the second ions. | 2021-10-14 |
20210320209 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A highly reliable semiconductor device with favorable electrical characteristics is provided. The semiconductor device includes a first insulator; a first conductor and a second conductor over the first insulator; an oxide provided between the first conductor and the second conductor; a second insulator over the first conductor, the second conductor, and the oxide; and a third conductor over the second insulator. A side surface of the first conductor includes a region in contact with one side surface of the oxide, a side surface of the second conductor includes a region in contact with the other side surface of the oxide. The level of a top surface of the first conductor, the level of a top surface of the second conductor, and the level of a top surface of the oxide arc substantially the same. The conductivity of the first conductor is higher than that of the oxide, and the conductivity of the second conductor is higher than that of the oxide. | 2021-10-14 |
20210320210 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a substrate, a semiconductor layer, a gate structure, source/drain regions, a bottom isolation layer, and a bottom spacer. The semiconductor layer is above the substrate. The gate structure is above the substrate and surrounds the semiconductor layer. The source/drain regions are on opposite sides of the semiconductor layer. The bottom isolation layer is between the substrate and the semiconductor layer. The bottom spacer is on a sidewall of the bottom isolation layer. | 2021-10-14 |
20210320211 | DOPED POLAR LAYERS AND SEMICONDUCTOR DEVICE INCORPORATING SAME - The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor, which in turn comprises a polar layer comprising a crystalline base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen, wherein the dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The capacitor additionally comprises first and second crystalline conductive or semiconductive oxide electrodes on opposing sides of the polar layer, wherein the polar layer has a lattice constant that is matched within about 20% of a lattice constant of one or both of the first and second crystalline conductive or semiconductive oxide electrodes. The first crystalline conductive or semiconductive oxide electrode serves as a template for growing the polar layer thereon, such that at least a portion of the polar layer is pseudomorphically formed on the first crystalline conductive or semiconductive oxide electrode. | 2021-10-14 |
20210320212 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device having a reduced amount of oxygen vacancy in a channel formation region of an oxide semiconductor is provided. Further, a semiconductor device which includes an oxide semiconductor and has improved electric characteristics is provided. Furthermore, a methods for manufacturing the semiconductor device is provided. An oxide semiconductor film is formed; a conductive film is formed over the oxide semiconductor film at the same time as forming a low-resistance region between the oxide semiconductor film and the conductive film; the conductive film is processed to form a source electrode and a drain electrode; and oxygen is added to the low-resistance region between the source electrode and the drain electrode, so that a channel formation region having a higher resistance than the low-resistance region is formed and a first low-resistance region and a second low-resistance region between which the channel formation region is positioned are formed. | 2021-10-14 |
20210320213 | SEMICONDUCTOR DEVICE - A semiconductor device is provided. The semiconductor device includes: a first wire pattern disposed on a substrate and extending in a first direction; a first gate electrode surrounding the first wire pattern and extending in a second direction, the first direction intersecting the second direction perpendicularly; a first transistor including the first wire pattern and the first gate electrode; a second wire pattern disposed on the substrate and extending in the first direction; a second gate electrode surrounding the second wire pattern and extending in the second direction; and a second transistor including the second wire pattern and the second gate electrode, wherein a width of the first wire pattern in the second direction is different from a width of the second wire pattern in the second direction. | 2021-10-14 |
20210320214 | LOCALIZED STRAIN FIELDS IN EPITAXIAL LAYER OVER cREO - A layered structure ( | 2021-10-14 |
20210320215 | LIGHT DETECTION DEVICE - A light detection device is disclosed. A first cell and a second cell are set in the light detection device. The first cell and the second cell are mutually adjacent. The device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer provided on the first semiconductor layer, the second semiconductor layer being of a second conductivity type; a first member provided between the first cell and the second cell; a second member provided between the first member and the first cell; and a third member provided between the first member and the second cell. The first to third members are made of a material different from the first semiconductor layer and the second semiconductor layer. | 2021-10-14 |
20210320216 | PHOTODETECTION DEVICE HAVING A LATERAL CADMIUM CONCENTRATION GRADIENT IN THE SPACE CHARGE ZONE - Photo-detection device ( | 2021-10-14 |
20210320217 | AVALANCHE PHOTODIODE - The present disclosure relates to semiconductor structures and, more particularly, to an avalanche photodiode and methods of manufacture. The structure includes: a substrate material having a trench with sidewalls and a bottom composed of the substrate material; a first semiconductor material lining the sidewalls and the bottom of the trench; a photosensitive semiconductor material provided on the first semiconductor material; and a third semiconductor material provided on the photosensitive semiconductor material. | 2021-10-14 |
20210320218 | LIGHT-RECEIVING ELEMENT AND DISTANCE-MEASURING MODULE - The present technology relates to a light-receiving element and a distance-measuring module for enabling improvement of characteristics. A light-receiving element includes an on-chip lens, a wiring layer, a first substrate arranged between the on-chip lens and the wiring layer, and a second substrate bonded to the first substrate via the wiring layer, the first substrate includes a first voltage application portion to which a first voltage is applied, a second voltage application portion to which a second voltage different from the first voltage is applied, a first charge detection portion arranged around the first voltage application portion, and a second charge detection portion arranged around the second voltage application portion, and the second substrate includes a plurality of pixel transistors that performs an operation of reading charges detected in the first and second charge detection portions. The present technology can be applied to, for example, a light-receiving element that generates distance information by a ToF method. | 2021-10-14 |
20210320219 | HETEROSTRUCTURE OPTOELECTRONIC DEVICE FOR EMITTING AND DETECTING ELECTROMAGNETIC RADIATION, AND MANUFACTURING PROCESS THEREOF - An optoelectronic device with a semiconductor body that includes: a bottom cathode structure, formed by a bottom semiconductor material, and having a first type of conductivity; and a buffer region, arranged on the bottom cathode structure and formed by a buffer semiconductor material different from the bottom semiconductor material. The optoelectronic device further includes: a receiver comprising a receiver anode region, which is formed by the bottom semiconductor material, has a second type of conductivity, and extends in the bottom cathode structure; and an emitter, which is arranged on the buffer region and includes a semiconductor junction formed at least in part by a top semiconductor material, different from the bottom semiconductor material. | 2021-10-14 |
20210320220 | PHOTOVOLTAIC STRINGER AND METHOD FOR MANUFACTURING PHOTOVOLTAIC RIBBON - The present disclosure provides a photovoltaic stringer and a method for manufacturing a photovoltaic ribbon. The photovoltaic stringer includes a first clamping component to pull a ribbon from a ribbon reel, a second clamping component to coordinate with the first clamping component to stretch the ribbon, a cutting component to cut the ribbon, and, at least one first electrode and at least one second electrode to supply power to the ribbon. The method for manufacturing a photovoltaic ribbon comprises acquiring a ribbon reel and pulling a ribbon, stretching the ribbon and cutting the ribbon to obtain a cut ribbon, and performing an annealing process on the cut ribbon. | 2021-10-14 |
20210320221 | METHOD FOR MANUFACTURING AN ELECTRONIC DEVICE - A method of manufacturing an electronic device, including the successive steps of: a) performing an ion implantation of indium or of aluminum into an upper portion of a first single-crystal gallium nitride layer, to make the upper portion of the first layer amorphous and to preserve the crystal structure of a lower portion of the first layer; and b) performing a solid phase recrystallization anneal of the upper portion of the first layer, resulting in transforming the upper portion of the first layer into a crystalline indium gallium nitride or aluminum gallium nitride layer. | 2021-10-14 |
20210320222 | LED CHIP STRUCTURE, CHIP TRANSFERRING SYSTEM AND CHIP TRANSFERRING METHOD - An LED chip structure, a chip transferring system and a chip transferring method are provided. The chip transferring system includes a liquid receiving tank, an electromagnetic field generating module and a connection layer removing module. A plurality of LED chip structures are randomly distributed in the liquid substance of the liquid receiving tank. The electromagnetic field generating module movably is disposed inside or removed from the liquid receiving tank. The connection layer removing module is disposed above the circuit substrate. Each of the LED chip structures includes an LED chip, a removable connection layer and a magnetic material layer. The LED chip structure can be transferred from the liquid receiving tank onto a circuit substrate by the electromagnetic field generating module, and the magnetic material layer can be separated from the LED chip while the removable connection layer is removed by the connection layer removing module. | 2021-10-14 |
20210320223 | OPTOELECTRONIC SEMICONDUCTOR CHIP AND METHOD FOR PRODUCING AN OPTOELECTRONIC SEMICONDUCTOR CHIP - In at least one embodiment, the optoelectronic semiconductor chip ( | 2021-10-14 |
20210320224 | LIGHT-EMITTING DEVICE - A light-emitting device according to one embodiment of the present disclosure includes: a substrate; a first quantum well layer including Al | 2021-10-14 |
20210320225 | CHIP TRANSFERRING METHOD AND LED CHIP STRUCTURE - A chip transferring method and an LED chip structure are provided. The chip transferring method includes distributing a plurality of LED chip structures in a liquid substance of a liquid receiving tank, each LED chip structure including an LED chip, a metal material layer and a removable connection layer; placing a carrier substrate in the liquid receiving tank, the carrier substrate including a carrier body for carrying a plurality of hot-melt material layers and a plurality of micro heaters disposed on the carrier body; respectively melting the hot-melt material layers by the micro heaters, so that the metal material layer of each LED chip structure is adhered to the corresponding hot-melt material layer that has been melted; separating the carrier substrate with the LED chip structures from the liquid receiving tank; and transferring the LED chip structures from the carrier substrate to an adhesive substrate. | 2021-10-14 |
20210320226 | LIGHT-EMITTING ELEMENT AND ELECTRONIC APPARATUS - A light-emitting element and an electronic apparatus capable of reducing the element area and realizing a stable electrical connection. A light-emitting element according to the present technology includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer laminated in this order, and a light-emitting surface, a non-light-emitting surface, and a side surface connecting the light-emitting surface and the non-light-emitting surface. The side surface is inclined. A first electrode is in a concave portion in the light-emitting surface at a periphery of the first semiconductor layer. A second electrode is on a non-light-emitting surface side of the laminate. A third electrode is on the non-light-emitting surface side of the laminate and is insulated from the second electrode. The side wiring electrically connects the first electrode and the third electrode via the side surface. | 2021-10-14 |
20210320227 | MICRO LED DEVICE AND METHOD FOR MANUFACTURING SAME - A micro-LED device of the present disclosure includes a crystal growth substrate ( | 2021-10-14 |
20210320228 | TRANSPARENT MICRO DISPLAY DEVICE - Discussed herein is a transparent light emitting diode (LED) display device. A capacitor of a pixel-driving circuit is integrated with an LED, and thus that the area of the pixel-driving circuit is reduced, and the transmission area is increased. In this manner, it is possible to achieve high transmittance without compromising the display quality. | 2021-10-14 |
20210320229 | LIGHT EMITTING DIODE STRUCTURE HAVING RESONANT CAVITY AND METHOD FOR MANUFACTURING THE SAME - A LED structure includes a substrate, a LED unit formed on the substrate, a first reflector layer formed between the substrate and the LED unit, and a second reflector layer formed on the LED unit. A common anode layer of the LED unit is formed on the first reflector layer. The first reflector layer, the LED unit and the second reflector layer are configured to collectively provide a resonant cavity. | 2021-10-14 |
20210320230 | DUV LED Module Structure - A deep ultraviolet (DUV) light-emitting diode (LED) module structure contains: a holder configured to accommodate a substrate. The holder including a receiving cup mounted therein and a transparent layer mounted on a top of the receiving cup. The holder includes a DUV LED chip adhered on the substrate, and the holder, the substrate, and the DUV LED chip are connected and packaged. The substrate is electrically connected with a drive circuit, and the drive circuit is configured to turn on/off the DUV LED chip. Thereby, the DUV LED module structure enhances DUV radiation intensity, reduces a loss of optical path, and slows down deterioration because of DUV irradiation. | 2021-10-14 |
20210320231 | LIGHT-EMITTING DEVICE AND DISPLAY DEVICE COMPRISING SAME - A light emitting device may include: a substrate; a light emitting element located on the substrate and configured to emit light; a first electrode and a second electrode spaced from each other with the light emitting element interposed therebetween; a color conversion layer located on the substrate and configured to convert light emitted from the light emitting element into light having a specific color; a first contact electrode configured to electrically couple the first electrode with a first end of the light emitting element; and a second contact electrode configured to electrically couple the second electrode with a second end of the light emitting element. In a plan view, the color conversion layer may be spaced from the light emitting element and overlaps with at least one of the first and the second contact electrodes. | 2021-10-14 |
20210320232 | Optoelectronic Component and Method for Producing an Optoelectronic Component - In an embodiment an optoelectronic component includes a radiation-emitting semiconductor chip configured to emit electromagnetic primary radiation from a radiation exit surface, a conversion element configured to convert the primary radiation into electromagnetic secondary radiation, wherein the conversion element has a frame which covers side surfaces of a conversion segment, and wherein the frame is formed reflective, and a bonding agent fixing the conversion element on the radiation exit surface of the semiconductor chip, wherein a contact point of the semiconductor chip projects beyond the conversion element in an edge region of the semiconductor chip in lateral directions, and wherein the bonding agent covers an outer surface of the frame and the contact point of the semiconductor chip in places. | 2021-10-14 |
20210320233 | LIGHT-EMITTING DEVICE AND ILLUMINATING APPARATUS COMPRISING THE SAME - A light-emitting device includes an LED chip disposed on a supporting component. The LED chip includes a semiconductor stack formed on a substrate, a first electrode, and a second electrode. A light-blocking layer fills the supporting component to cover a lateral side of the LED chip and expose a top chip surface of the LED chip. The light-blocking layer has a top surface not lower than the top chip surface of the LED chip. A height difference among the top chip surface, the top surface of the light-blocking layer and a top end of the supporting component is less than 10 μm. A top light exit port defined by the light-blocking layer to expose the top chip surface has a cross sectional area not larger than that of the top chip surface. | 2021-10-14 |
20210320234 | LIGHT EMITTING DIODE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A LED structure includes a substrate, a bonding layer, a first doping type semiconductor layer, a multiple quantum well (MQW) layer, a second doping type semiconductor layer, a passivation layer and an electrode layer. The bonding layer is formed on the substrate, and the first doping type semiconductor layer is formed on the bonding layer. The MQW layer is formed on the first doping type semiconductor layer, and the second doping type semiconductor layer is formed on the MQW layer. The second doping type semiconductor layer includes an isolation material made through implantation, and the passivation layer is formed on the second doping type semiconductor layer. The electrode layer is formed on the passivation layer in contact with a portion of the second doping type semiconductor layer through a first opening on the passivation layer. | 2021-10-14 |
20210320235 | LED CHIP INITIAL STRUCTURE, SUBSTRATE STRUCTURE, CHIP TRANSFERRING METHOD AND IMAGE DISPLAY DEVICE - An LED chip initial structure, a substrate structure for carrying the LED chip initial structure, a chip transferring method using the LED chip initial structure, and an LED image display device manufactured by the LED chip transferring method are provided. The LED chip initial structure includes an LED chip main body and a conductive electrode. One of a top side and a bottom side of the LED chip main body is a temporary electrodeless side, another one of the top side and the bottom side of the LED chip main body is a connecting electrode side, and the temporary electrodeless side has an unoccupied surface. The conductive electrode is disposed on the connecting electrode side of the LED chip main body so as to electrically connect to the LED chip main body. The LED chip initial structure is adhered to a hot-melt material through the conductive electrode. | 2021-10-14 |
20210320236 | METHOD FOR TRANSFERRING AND BONDING OF DEVICES - Provided is a method for transferring and bonding devices. The method includes applying an adhesive layer to a carrier, arranging a plurality of devices, attaching the arranged devices to the carrier, applying a polymer film to a substrate, aligning the carrier to which the plurality of devices are attached with the substrate, bonding the plurality of devices to the substrate by radiating laser, and releasing the carrier from the substrate to which the plurality of devices are bonded. | 2021-10-14 |
20210320237 | DISPLAY DEVICE - A display device comprises a substrate, a semiconductor layer thereon, a first insulating layer on the semiconductor layer, a first conductive layer on the first insulating layer and including a first electrode pattern, a second insulating layer on the first insulating layer and including first and second conductive patterns, a third insulating layer on the second conductive layer, and a display element layer on the third insulating layer and including a first pixel electrode connected to the first conductive pattern through a first via hole, a second pixel electrode connected to the second conductive pattern through a second via hole, and a micro light-emitting element between the pixel electrodes, the first conductive pattern contacting the semiconductor layer through a first contact hole and the first electrode pattern through a second contact hole, and the second conductive pattern overlapping the first electrode pattern to form a first capacitor therewith. | 2021-10-14 |
20210320238 | Electro-optical assembly having heat dissipation, and method for producing such an assembly - An assembly ( | 2021-10-14 |
20210320239 | THERMOELECTRIC CONVERSION MATERIAL AND THERMOELECTRIC CONVERSION DEVICE USING SAME - A thermoelectric conversion material is a polycrystalline material composed of a plurality of crystal grains and has a composition represented by formula (I): Mg | 2021-10-14 |
20210320240 | VERTICAL AL/EPI SI/AL, AND ALSO AL/AL OXIDE/AL, JOSEPHSON JUNCTION DEVICES FOR QUBITS - A vertical Josephson junction device includes a substrate, and an epitaxial stack formed on the substrate. The vertical Josephson junction device includes a first superconducting electrode embedded in the epitaxial stack, and a second superconducting electrode embedded in the epitaxial stack, the second superconducting electrode being separated from the first superconducting electrode by a dielectric layer. In operation, the first superconducting electrode, the dielectric layer, and the second superconducting electrode form a vertical Josephson junction. | 2021-10-14 |
20210320241 | VIBRATION DEVICE AND IMAGING DEVICE - A vibration device includes a light-transmissive cover, a piezoelectric element to vibrate the light-transmissive cover, at least one vibration body connected to the piezoelectric element, at least one power feed conductor in contact with the piezoelectric element and feeding power to the piezoelectric element, and at least one elastic portion to press the at least one power feed conductor against the piezoelectric element. | 2021-10-14 |
20210320242 | METHOD FOR POLARIZING PIEZOELECTRIC FILM - A method for polarizing a piezoelectric film is described. In this method, a piezoelectric film is formed by using an injection deposition method. The piezoelectric film is flat adhered to a surface of a conductive substrate. A polarization process is performed on the piezoelectric film while the piezoelectric film is flat adhered to the surface of the conductive substrate. | 2021-10-14 |
20210320243 | COMPOSITE SUBSTRATE, PIEZOELECTRIC DEVICE, AND METHOD FOR MANUFACTURING COMPOSITE SUBSTRATE - A composite substrate of the present disclosure is a composite substrate in which a piezoelectric substrate and a sapphire substrate are directly bonded, and a bonding surface of the sapphire substrate has a step bunch structure. A piezoelectric device of the present disclosure includes the composite substrate. A method for manufacturing a composite substrate includes the steps of: preparing a piezoelectric substrate and a sapphire substrate including a surface having a predetermined off-angle to a specific crystal plane, heat treating the sapphire substrate in an oxidizing atmosphere to form a step bunch on the surface of the sapphire substrate, and bonding the piezoelectric substrate and the surface of the sapphire substrate directly. | 2021-10-14 |
20210320244 | TOP ELECTRODE FOR A MEMORY DEVICE AND METHODS OF MAKING SUCH A MEMORY DEVICE - One illustrative device disclosed herein includes a memory cell positioned in a first opening in at least one layer of insulating material. The memory cell comprises a bottom electrode, a memory state material positioned above the bottom electrode and an internal sidewall spacer positioned within the first opening, wherein the internal sidewall spacer defines a spacer opening. The device also comprises a top electrode positioned within the spacer opening. | 2021-10-14 |
20210320245 | MAGNETORESISTIVE MEMORY DEVICE INCLUDING A PLURALITY OF REFERENCE LAYERS - Magnetoelectric or magnetoresistive memory cells may include a plurality of reference layers and optionally a plurality of free layers to enhance the tunneling magnetoresistance (TMR) ratio. | 2021-10-14 |
20210320246 | METHODS FOR TREATING MAGNESIUM OXIDE FILM - A method of forming a tunnel layer of a magnetoresistive random-access memory (MRAM) structure includes forming a first magnesium oxide (MgO) layer by sputtering an MgO target using radio frequency (RF) power, exposing the first MgO layer to oxygen for approximately | 2021-10-14 |
20210320247 | MAGNETIC TUNNEL JUNCTIONS WITH TUNABLE HIGH PERPENDICULAR MAGNETIC ANISOTROPY - Embodiments of the disclosure provide methods for forming MTJ structures from a film stack disposed on a substrate for MRAM applications and associated MTJ devices. The methods described herein include forming the film properties of material layers from the film stack to create a film stack with a sufficiently high perpendicular magnetic anisotropy (PMA). An iron containing oxide capping layer is utilized to generate the desirable PMA. By utilizing an iron containing oxide capping layer, thickness of the capping layer can be more finely controlled and reliance on boron at the interface of the magnetic storage layer and the capping layer is reduced. | 2021-10-14 |
20210320248 | VARIABLE RESISTANCE NON-VOLATILE MEMORY ELEMENT AND VARIABLE RESISTANCE NON-VOLATILE MEMORY DEVICE USING THE ELEMENT - A variable resistance non-volatile memory element includes first and second electrodes and a variable resistance layer between the electrodes. The layer has a resistance value reversibly variable based on an electrical signal. The layer includes a first variable resistance layer that includes an oxygen deficient first metal oxide containing a first metal element and oxygen, and a second variable resistance layer that includes a composite oxide containing the first metal element, a second metal element different from the first metal element, and oxygen, and having a different degree of oxygen deficiency from the first metal oxide. The composite oxide has a lower degree of oxygen deficiency than the first metal oxide. At room temperature, the composite oxide has a smaller oxygen diffusion coefficient than a second metal oxide containing the first metal element and oxygen, and having the degree of oxygen deficiency equal to that of the composite oxide. | 2021-10-14 |