42nd week of 2009 patent applcation highlights part 12 |
Patent application number | Title | Published |
20090256124 | DEVICE FOR LAYING CABLE IN A CONDUIT - The device for installing a wire in a conduit of the type with thin walls and ribbed, comprises in particular a support sleeve suitable for preventing a radial expansion as well as a lengthening of a portion of said conduit above ground. | 2009-10-15 |
20090256125 | Winch - The present invention relates to a winch for elevating plant, in particular cranes, cable-operated excavators and similar construction machinery, comprising a hoisting drum, an electric motor for the drive of the hoisting drum which is received in the interior of the hoisting drum as well as power electronics and/or control electronics for the electric motor comprising at least one frequency inverter and/or frequency converter. In accordance with the invention, the power electronics and/or control electronics for the electric motor are received at least partly in the interior of the hoisting drum. Not only short cabling distances are hereby achieved; interference emissions with negative effects on the electromagnetic compatibility are avoided; and voltage overshoots impairing the service life of the inverter and the motor are reduced, but also a particularly compact construction of the winch is achieved. | 2009-10-15 |
20090256126 | CORNER ASSEMBLY - A corner assembly and manufacturing method comprising two cap rail components each having a channel and at least one receiver within the channel, the components connected or bonded to form a corner fitting having an angle and having a first end and a second end such that the first cap rail component channel and the second cap rail component channel form an angled channel within the corner fitting. At least one pin is disposed in a portion of the receiver within the first cap rail component channel, and at least one pin is disposed in a portion of the receiver within the second cap rail component channel. The assembly also may include a bracket disposed within the channels of the corner fitting. | 2009-10-15 |
20090256127 | Compounds for Depositing Tellurium-Containing Films - Disclosed herein are tellurium metal-organic precursors and methods for depositing tellurium-containing films on a substrate. | 2009-10-15 |
20090256128 | Nonvolatile data storage, semicoductor memory device including nonvolatile data storage and method of forming the same - A data storage and a semiconductor memory device including the same are provided, the data storage including a lower electrode, a first discharge prevention layer stacked on the lower electrode, a phase-transition layer on the first discharge prevention layer, a second discharge prevention layer stacked on the phase-transition layer, and an upper electrode stacked on the second discharge prevention layer. The phase transition layer includes oxygen and exhibits two different resistance characteristics depending on whether an insulating property thereof changed. The first and second discharge prevention layers block discharge of the oxygen from the phase transition layer. | 2009-10-15 |
20090256129 | Sidewall structured switchable resistor cell - A method of making a memory device includes forming a first conductive electrode, forming an insulating structure over the first conductive electrode, forming a resistivity switching element on a sidewall of the insulating structure, forming a second conductive electrode over the resistivity switching element, and forming a steering element in series with the resistivity switching element between the first conductive electrode and the second conductive electrode, wherein a height of the resistivity switching element in a first direction from the first conductive electrode to the second conductive electrode is greater than a thickness of the resistivity switching element in second direction perpendicular to the first direction. | 2009-10-15 |
20090256130 | MEMORY CELL THAT EMPLOYS A SELECTIVELY FABRICATED CARBON NANO-TUBE REVERSIBLE RESISTANCE-SWITCHING ELEMENT, AND METHODS OF FORMING THE SAME - In some aspects, a method of fabricating a memory cell is provided that includes fabricating a steering element above a substrate, and fabricating a reversible-resistance switching element coupled to the steering element by fabricating a carbon nano-tube (“CNT”) seeding layer by depositing a silicon-germanium layer above the substrate, patterning and etching the CNT seeding layer, and selectively fabricating CNT material on the CNT seeding layer. Numerous other aspects are provided. | 2009-10-15 |
20090256131 | MEMORY CELL THAT EMPLOYS A SELECTIVELY FABRICATED CARBON NANO-TUBE REVERSIBLE RESISTANCE-SWITCHING ELEMENT FORMED OVER A BOTTOM CONDUCTOR AND METHODS OF FORMING THE SAME - In some aspects, a method of fabricating a memory cell is provided that includes: (1) fabricating a first conductor above a substrate; (2) selectively fabricating a carbon nano-tube (“CNT”) material above the first conductor by: (a) fabricating a CNT seeding layer on the first conductor, wherein the CNT seeding layer comprises silicon-germanium (“Si/Ge”), (b) planarizing a surface of the deposited CNT seeding layer, and (c) selectively fabricating CNT material on the CNT seeding layer; (3) fabricating a diode above the CNT material; and (4) fabricating a second conductor above the diode. Numerous other aspects are provided. | 2009-10-15 |
20090256132 | MEMORY CELL THAT INCLUDES A CARBON-BASED MEMORY ELEMENT AND METHODS OF FORMING THE SAME - In accordance with aspects of the invention, a method of forming a memory cell is provided, the method including forming a steering element above a substrate, and forming a memory element coupled to the steering element, wherein the memory element comprises a carbon-based material having a thickness of not more than ten atomic layers. The memory element may be formed by repeatedly performing the following steps: forming a layer of a carbon-based material, the layer having a thickness of about one monolayer, and subjecting the layer of carbon-based material to a thermal anneal. Other aspects are also described. | 2009-10-15 |
20090256133 | Multiple layer resistive memory - A resistive memory cell may be composed of four stacked layers. Each layer may be sandwiched by electrodes. Connections may be formed from each of four directions around the stack, for example, aligned with each of four edges where the resistive layers are rectangular. | 2009-10-15 |
20090256134 | Process for Fabricating Nanowire Arrays - A process is provided for etching a silicon-containing substrate to form nanowire arrays. In this process, one deposits nanoparticles and a metal film onto the substrate in such a way that the metal is present and touches silicon where etching is desired and is blocked from touching silicon or not present elsewhere. One submerges the metallized substrate into an etchant aqueous solution comprising HF and an oxidizing agent. In this way arrays of nanowires with controlled diameter and length are produced. | 2009-10-15 |
20090256135 | Thermal electron emitter and thermal electron emission device using the same - A thermal electron emitter includes at least one carbon nanotube twisted wire and a plurality of electron emission particles mixed with the twisted wire. The carbon nanotube twisted wire comprises a plurality of carbon nanotubes. A work function of the electron emission particles is lower than the work function of the carbon nanotubes. A thermal electron emission device using the thermal electron emitter is also related. | 2009-10-15 |
20090256136 | MICRORESONATOR SYSTEMS AND METHODS OF FABRICATING THE SAME - Various embodiments of the present invention are related to microresonator systems that can be used as a laser, a modulator, and a photodetector and to methods for fabricating the microresonator systems. In one embodiment, a microdisk comprises: a top layer; a bottom layer; an intermediate layer having at least one quantum well, the intermediate layer sandwiched between the top layer and the bottom layer; a peripheral annular region including at least a portion of the top, intermediate, and bottom layers; and a current isolation region configured to occupy at least a portion of a central region of the microdisk including at least a portion of the top, intermediate, and bottom layers and having relatively lower index of refraction than the peripheral annular region. | 2009-10-15 |
20090256137 | N-TYPE SEMICONDUCTOR MATERIALS IN THIN FILM TRANSISTORS AND ELECTRONIC DEVICES - A thin film transistor comprises a layer of organic semiconductor that comprises an N,N′-1,4,5,8-naphthalenetetracarboxylic acid diimide having at least one cycloalkyl group having a fluorinated substituent at its 4-position that adopts an equatorial orientation in the trans configuration of the cycloalkyl group and an axial orientation in the cis configuration of the cycloalkyl group. Such transistors can be a field effect transistor having a dielectric layer, a gate electrode, a source electrode and a drain electrode. The gate electrode and the thin film of organic semiconductor material both contact the dielectric layer, and the source electrode and the drain electrode both contact the thin film of organic semiconductor material. | 2009-10-15 |
20090256138 | ORGANIC THIN FILM TRANSISTOR - Organic thin film transistors with improved mobility are disclosed. The semiconducting layer comprises a semiconductor material of Formula (I): | 2009-10-15 |
20090256139 | THIN-FILM TRANSISTORS - A thin film transistor having a semiconducting layer with improved flexibility and/or mobility is disclosed. The semiconducting layer comprises a semiconducting polymer and insulating polymer. Methods for forming and using such thin-film transistors are also disclosed. | 2009-10-15 |
20090256140 | Light-detecting device structure - A light-detecting device structure comprises a substrate, a vertical organic light-emitting transistor and a light-detecting unit, wherein the vertical organic light-emitting transistor is disposed at a first location on the substrate, and the light-detecting unit is disposed at a second location on the substrate, in which the first and the second locations can be spaced out an appropriate distance as needed. The vertical organic light-emitting transistor emits a light to an object, and the light-detecting unit receives a reflected light from the object. The reflected light received is analyzed to determine a distance between the light-detecting device structure and the object, as well as a shape or a composition of the object. | 2009-10-15 |
20090256141 | ORGANIC PHOTOSENSITIVE OPTOELECTRONIC DEVICES CONTAINING TETRA-AZAPORPHYRINS - Embodiments of the present invention provide an organic photosensitive optoelectronic device comprising at least one tetra-azaporphyrin compound of formula (I) are disclosed herein. | 2009-10-15 |
20090256142 | ORGANIC THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING SAME - Disclosed are an organic thin film transistor exhibiting a high switching current value even when a distance (channel length) between source and the drain electrodes is large, and a manufacturing method thereof. The organic thin film transistor of the invention comprises a substrate, a gate electrode, a gate insulating layer, an organic semiconductor layer, a source electrode, a drain electrode and at least one different type electrodes characterized in that the different type electrode is formed in a channel region between the source electrode and the drain electrode on the organic semiconductor layer. | 2009-10-15 |
20090256143 | OLIGOTHIOPHENE-ARYLENE DERIVATIVES AND ORGANIC THIN FILM TRANSISTORS USING THE SAME - An oligothiophene-arylene derivative wherein an arylene having n-type semiconductor characteristics is introduced into an oligothiophene having p-type semiconductor characteristics, thereby simultaneously exhibiting both p-type and n-type semiconductor characteristics. Further, an organic thin film transistor using the oligothiophene-arylene derivative. | 2009-10-15 |
20090256144 | METHOD FOR MANUFACTURING ORGANIC TRANSISTOR AND ORGANIC TRANSISTOR - A method of producing an organic transistor which can form directly an organic semiconductor layer in pattern by simple processes and can produce an organic transistor excellent in transistor characteristics. The method includes: forming a hydrophobic/hydrophilic pattern substrate, in which a hydrophobic/hydrophilic pattern substrate is formed by using a hydrophobic substrate and by forming the hydrophilic region in pattern on the hydrophobic surface; forming a lyophilic functional layer, in which a lyophilic functional layer, made of an insulating functional material having the predetermined characteristics and having higher lyophilic properties to an organic solvent than that of the hydrophobic region, is formed on the hydrophilic region; forming an organic semiconductor layer, in which an organic semiconductor layer is formed on the lyophilic functional layer by selectively coating a coating solution for forming an organic semiconductor layer, which has an organic semiconductor material and an organic solvent, to the lyophilic functional layer. | 2009-10-15 |
20090256145 | ORGANIC THIN FILM TRANSISTOR AND ORGANIC THIN FILM LIGHT-EMITTING TRANSISTOR - An organic thin film transistor including a substrate having thereon at least three terminals of a gate electrode, a source electrode and a drain electrode, an insulator layer and an organic semiconductor layer, with a current between a source and a drain being controlled upon application of a voltage to the gate electrode, wherein the organic semiconductor layer includes a specified organic compound having a divalent aromatic hydrocarbon group having a phenanthrene structure in the center thereof; and an organic thin film light emitting transistor utilizing an organic thin film transistor, wherein the organic thin film transistor is one in which light emission is obtained utilizing a current flowing between the source and the drain, and the light emission is controlled upon application of a voltage to the gate electrode, and is made high with respect to the response speed and has a large ON/OFF ratio, are provided. | 2009-10-15 |
20090256146 | SEMICONDUCTOR SUBSTRATE WITH SOLID PHASE EPITAXIAL REGROWTH WITH REDUCED DEPTH OF DOPING PROFILE AND METHOD OF PRODUCING SAME - Method of producing a semiconductor device, comprising: a) providing a semiconductor substrate, b) providing an insulating layer on a top surface of the semiconductor substrate, c) making an amorphous layer in a top layer of said semiconductor substrate by a suitable implant, d) implanting a dopant into said semiconductor substrate through said insulating layer to provide said amorphous layer with a predetermined doping profile, said implant being performed such that said doping profile has a peak value located within said insulating layer, e) applying a solid phase epitaxial regrowth action to regrow said amorphous layer and activate said dopant. | 2009-10-15 |
20090256147 | Thin film transistor and method of manufacturing the same - A thin film transistor, including a transparent channel pattern, a transparent gate insulating layer in contact with the channel pattern, a passivation film pattern disposed on the channel pattern, a source/drain coupled to the channel pattern through a via hole in the passivation film pattern, and a gate facing the channel pattern, the gate insulating layer interposed between the gate and the channel pattern, wherein the passivation film pattern includes at least one of polyimide, photoacryl, and spin on glass (SOG). | 2009-10-15 |
20090256148 | ZINC OXIDE LIGHT EMITTING DIODE - Provided is a zinc oxide light emitting diode having improved optical characteristics. The zinc oxide light emitting diode includes an n-type semiconductor layer, a zinc oxide active layer formed on the n-type semiconductor layer, a p-type semiconductor layer formed on the active layer, an anode in electrical contact with the p-type semiconductor layer, a cathode in electrical contact with the n-type semiconductor layer, and a surface plasmon layer disposed between the n-type semiconductor layer and the active layer or between the active layer and the p-type semiconductor layer. Since the surface plasmon layer is formed between the n-type semiconductor layer and the active layer or between the active layer and the p-type semiconductor layer, the light emitting diode is not affected by an increase in resistance due to reduction of the thickness of the p-type semiconductor layer, and has improved optical characteristics due to a resonance phenomenon between the surface plasmon layer and the active layer. | 2009-10-15 |
20090256149 | Structure for Measuring Body Pinch Resistance of High Density Trench MOSFET Array - A structure is disclosed for measuring body pinch resistance Rp of trench MOSFET arrays on a wafer. The trench MOSFET array has a common drain layer of first conductivity type and a 2D-trench MOSFET array atop the common drain layer. The 2D-trench MOSFET array has an interdigitated array of source-body columns and gate trench columns. Each source-body column has a bottom body region of second conductivity type with up-extending finger structures. Each source-body column has top source regions of first conductivity type bridging the finger structures. The structure includes:
| 2009-10-15 |
20090256150 | THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME - A thin film transistor array panel according to an exemplary embodiment of the present invention comprises a substrate; a first signal line and a second signal line disposed on the substrate; a switching thin film transistor connected to the first signal line and the second signal line, and comprising a first insulating layer; a driving thin film transistor connected to the switching thin film transistor and comprising a second insulating layer; and a discharge thin film transistor connected to one of the first signal line and the second signal line, and comprising the first insulating layer and the second insulating layer. | 2009-10-15 |
20090256151 | DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A display substrate comprises a substrate; a source electrode arranged on the substrate; a drain electrode arranged on the substrate and spaced from the source electrode; a semiconductor layer arranged on the source electrode and the drain electrode; an insulating layer arranged on the semiconductor layer; and a gate electrode arranged on the insulating layer, wherein the semiconductor layer comprises: a first ohmic contact region that overlays an upper surface and a side surface of the source electrode; a second ohmic contact region that overlays an upper surface and a side surface of the drain electrode; and a channel region that is spaced from the source and drain electrodes and interconnects the first ohmic contact region and the second ohmic contact region. | 2009-10-15 |
20090256152 | PIXEL STRUCTURE FOR TRANSFLECTIVE LCD PANEL - A pixel structure for a transflective LCD having a transparent region and a reflective region is provided. The pixel structure includes a transparent substrate, a TFT, at least one reflective structure, a passivation layer, a pixel electrode and a reflective layer. The TFT is disposed in a reflective region of the transparent substrate. The reflective structure is configured at one side of the TFT, and located in the reflective region of the transparent substrate. The passivation layer is disposed over the transparent substrate and covers the TFT and the reflective structure. The pixel electrode is disposed above the TFT and the reflective structure, and is at least located in a transparent region. The pixel electrode is electrically connected to the TFT. The reflective layer is disposed above the TFT and the reflective structure, and is located in the reflective region. | 2009-10-15 |
20090256153 | THIN FILM TRANSISTOR MATRIX DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a thin film transistor matrix device which includes forming a transparent insulating substrate, arranging a plurality of thin film transistors on the substrate in a matrix, arranging a plurality of picture element electrodes on the substrate in a matrix and connecting the picture element electrodes to sources of the thin film transistors. The method also includes forming a plurality of bus lines for commonly connecting gates or drains of the thin film transistors, forming a plurality of bus line terminals on the ends of the bus lines, respectively, with each bus line terminal being provided for each bus line, and forming one connection line on the substrate in a region outer of plurality of the bus line terminals and commonly connecting the plurality of bus lines. The method further includes the step of electrically disconnecting the bus lines from the connection line by laser melting. | 2009-10-15 |
20090256154 | Flexible substrate, method of fabricating the same, and thin film transistor using the same - A flexible substrate for a TFT includes a metal substrate having a predetermined coefficient of thermal expansion, and a buffer layer on the metal substrate, the buffer layer including a silicon oxide or a silicon nitride, wherein the predetermined coefficient of thermal expansion of the metal substrate satisfies an equation as follows, | 2009-10-15 |
20090256155 | THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME - A thin film transistor panel includes a substrate, a gate line extending in a first direction on the substrate, a data line disposed on the substrate, the data line crossing the gate line with an insulation layer therebetween and extending in a second direction, a thin film transistor including a control terminal connected to the gate line, an input terminal connected to the data line, and an output terminal, a color filter disposed on the thin film transistor, the color filter having an opening corresponding to the output terminal of the thin film transistor, a light blocking member disposed in the opening of the color filter, the light blocking member exposing a first region of a first end portion of the output terminal of the thin film transistor and having an output terminal light blocking portion enclosing the circumference of the first region, and a pixel electrode disposed on the light blocking member and the color filter, the pixel electrode contacting the first region of the output terminal. | 2009-10-15 |
20090256156 | Hybrid imaging sensor with approximately equal potential photodiodes - A hybrid MOS or CMOS image sensor. The sensor includes photon-sensing elements comprised of an array of photo-sensing regions deposited in the form of separate islands on or in a substrate. Pixel circuitry is created on and/or in the substrate at or near the edge of or beneath the photon-sensing elements. The photo-sensing elements may be comprised of multiple photo-sensing semiconductor layers or be created in a single photon-sensing semiconductor layer. Special circuitry is provided to keep the potential across the pixel photon-sensing element at or near zero volts to minimize or eliminate dark current. The potential difference is preferably less than 1.0 volt. The circuitry also keeps the small potential difference across the photodiodes constant or approximately constant throughout the charge collection cycle. In preferred embodiments the substrate is a crystalline substrate and the photon-sensing elements are separated from the substrate by a dielectric material except for a hole at the bottom through which the material of the photon-sensing element can be grown epitaxially from the substrate. | 2009-10-15 |
20090256157 | DISPLAY DEVICE AND MANUFACTURING METHOD OF DISPLAY DEVICE - A display device includes a first substrate on which a semiconductor circuit is formed. A second substrate is disposed over the first substrate to include a first electrode formed on a first surface to perform image displaying, and a second electrode exposed to a second surface and bonded to the first electrode via a contact hole. A third substrate is disposed over the second substrate to include a third electrode formed to perform image displaying in association with the first electrode of the second substrate. An image displaying layer is disposed between the second substrate and the third substrate to perform image displaying. An electrode on a surface of the first substrate on which the semiconductor circuit is formed is electrically connected to the second electrode exposed to the second surface of the second substrate. | 2009-10-15 |
20090256158 | ARRAY SUBSTRATE OF LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - An array substrate comprising a base substrate, a common electrode, a gate line, a data line, a thin film transistor, a passivation layer and a pixel electrode of “ | 2009-10-15 |
20090256159 | GaN semiconductor device - This invention discloses a GaN semiconductor device comprising a substrate; a metal-rich nitride compound thin film on the substrate; a buffer layer formed on the metal-rich nitride compound thin film, and a semiconductor stack layer on the buffer layer wherein the metal-dominated nitride compound thin film covers a partial upper surface of the substrate. Because metal-rich nitride compound is amorphous, the epitaxial growth direction of the buffer layer grows upwards in the beginning and then turns laterally, and the epitaxy defects of the buffer layer also bend with the epitaxial growth direction of the buffer layer. Therefore, the probability of the epitaxial defects extending to the semiconductor stack layer is reduced and the reliability of the GaN semiconductor device is improved. | 2009-10-15 |
20090256160 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device is provided. A gate structure is formed on a substrate. A first dopant implantation and a first strain atom implantation are performed. Thereafter, spacers are formed on sidewalls of the gate structure. A second dopant implantation and a second strain atom implantation are performed. A solid-phase epitaxy annealing process is performed to form source and drain regions made of a semiconductor compound solid-phase epitaxial layer beside the gate structure. | 2009-10-15 |
20090256161 | POWER CONVERSION APPARATUS - In the case where a chip is made of wide band gap semiconductor, a power conversion apparatus is obtained in which a component having a low heat resistant temperature is prevented from receiving thermal damage by heat generated at the chip. In a configuration including: a chip portion ( | 2009-10-15 |
20090256162 | Method for Producing Semi-Insulating Resistivity in High Purity Silicon Carbide Crystals - A method is disclosed for producing high quality semi-insulating silicon carbide crystals in the absence of relevant amounts of deep level trapping elements. The invention includes the steps of heating a silicon carbide crystal having a first concentration of point defects to a temperature that thermodynamically increases the number of point defects and resulting states in the crystal, and then cooling the heated crystal at a sufficiently rapid rate to maintain an increased concentration of point defects in the cooled crystal. | 2009-10-15 |
20090256163 | LEDs using single crystalline phosphor and methods of fabricating same - Methods for fabricating LED chips from a wafer and devices fabricated using the methods with one method comprising depositing LED epitaxial layers on an LED growth wafer to form a plurality of LEDs on the growth wafer. A single crystalline phosphor is bonded over at least some the plurality of LEDs so that at least some light from the covered LEDs passes through the single crystalline phosphor and is converted. The LED chips can then be singulated from the wafer to provide LED chips each having a portion of said single crystalline phosphor to convert LED light. | 2009-10-15 |
20090256164 | Active Device Array Substrate and Method for Fabricating the Same - An active device array substrate and its fabricating method are provided. According to the subject invention, the elements of an array substrate such as the thin film transistors, gate lines, gate pads, data lines, data pads and storage electrodes, are provided by forming a patterned first metal layer, an insulating layer, a patterned semiconductor layer and a patterned metal multilayer. Furthermore, the subject invention uses the means of selectively etching certain layers. Using the aforesaid means, the array substrate of the subject invention has some layers with under-cut structures, and thus, the number of the time-consuming and complicated mask etching process involved in the production of an array substrate can be reduced. The subject invention provides a relatively simple and time-saving method for producing an array substrate. | 2009-10-15 |
20090256165 | METHOD OF GROWING AN ACTIVE REGION IN A SEMICONDUCTOR DEVICE USING MOLECULAR BEAM EPITAXY - A method of making an (Al, Ga, In)N semiconductor device having a substrate and an active region is provided. The method includes growing the active region using a combination of (i) plasma-assisted molecular beam epitaxy; and (ii) molecular beam epitaxy with a gas including nitrogen-containing molecules in which the nitrogen-containing molecules dissociate at a surface of the substrate at a temperature which the active region is grown. | 2009-10-15 |
20090256166 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light-emitting device | 2009-10-15 |
20090256167 | LIGHT-EMITTING DEVICE - A light-emitting device ( | 2009-10-15 |
20090256168 | DISPLAY ELEMENT, MANUFACTURING METHOD OF THE SAME AND DISPLAY DEVICE - A display element including: a first electrode; an auxiliary wiring formed on the periphery of the first electrode in such a manner as to be insulated from the first electrode; an insulating portion having first and second openings, the first opening adapted to expose the first electrode, and the second opening adapted to expose the auxiliary wiring, an organic layer adapted to cover at least the exposed surface of the first electrode in the first opening; and a second electrode adapted to cover at least the organic layer and the exposed surface of the auxiliary wiring in the second opening, wherein the organic layer has a layered structure which includes at least a hole injection layer and light-emitting layer stacked in this order from the side of the first electrode, and the edge of the hole injection layer is provided more inward than the edge of the organic layer. | 2009-10-15 |
20090256169 | Deposition Substrate and Method for Manufacturing Light-Emitting Device - The deposition substrate of the present invention includes a light-transmitting substrate having a first region and a second region. In the first region, a first heat-insulating layer transmitting light is provided over the light-transmitting substrate, a light absorption layer is provided over the first heat-insulating layer, and a first organic compound-containing layer is provided over the light absorption layer. In the second region, a reflective layer is provided over the light-transmitting substrate, a second heat-insulating layer is provided over the reflective layer, and a second organic compound-containing layer is provided over the second heat-insulating layer. The edge of the second heat-insulating layer is placed inside the edge of the reflective layer, and there is a space between the first heat-insulating layer and the second heat-insulating layer. | 2009-10-15 |
20090256170 | SEMICONDUCTOR LIGHT EMITTING ELEMENT AND METHOD FOR MANUFACTURING SAME - A semiconductor light emitter (A) includes an n-type semiconductor layer ( | 2009-10-15 |
20090256171 | RESIN COMPOSITION FOR SEALING LIGHT-EMITTING DEVICE AND LAMP - A resin composition for sealing a light-emitting device of the present invention includes a silsesquioxane resin including two or more oxetanyl groups, a cationic polymerization initiator and a metal oxide fine particle. Furthermore, a lamp of the present invention includes a package equipped with a sealing member, an electrode exposed in the bottom portion of the sealing member, and a light-emitting device arranged on the bottom portion and electrically connected with the electrode, wherein the light-emitting device is sealed with the resin composition for sealing a light-emitting device filled in the sealing member. | 2009-10-15 |
20090256172 | METHOD OF LASER ANNEALING SEMICONDUCTOR LAYER AND SEMICONDUCTOR DEVICES PRODUCED THEREBY - A laser annealing method includes forming a nitrogen-doped layer on a semiconductor layer, the nitrogen-doped layer having a nitrogen concentration of at least 3×10 | 2009-10-15 |
20090256173 | COMPLEMENTARY FIELD EFFECT TRANSISTORS HAVING EMBEDDED SILICON SOURCE AND DRAIN REGIONS - A method is provided of fabricating complementary stressed semiconductor devices, e.g., an NFET having a tensile stressed channel and a PFET having a compressive stressed channel. In such method, a first semiconductor region having a lattice constant larger than silicon can be epitaxially grown on an underlying semiconductor region of a substrate. The first semiconductor region can be grown laterally adjacent to a second semiconductor region which has a lattice constant smaller than that of silicon. Layers consisting essentially of silicon can be grown epitaxially onto exposed major surfaces of the first and second semiconductor regions after which gates can be formed which overlie the epitaxially grown silicon layers. Portions of the first and second semiconductor regions adjacent to the gates can be removed to form recesses. Regions consisting essentially of silicon can be grown within the recesses to form embedded silicon regions. Source and drain regions then can be formed in the embedded silicon regions. The difference between the lattice constant of silicon and that of the underlying first and second regions results in tensile stressed silicon over the first semiconductor region and compressive stressed silicon over the second semiconductor region. | 2009-10-15 |
20090256174 | DEVICE STRUCTURES FOR A HIGH VOLTAGE JUNCTION FIELD EFFECT TRANSISTOR MANUFACTURED USING A HYBRID ORIENTATION TECHNOLOGY WAFER AND DESIGN STRUCTURES FOR A HIGH VOLTAGE INTEGRATED CIRCUIT - Device structures for a high voltage junction field effect transistor and design structures for a high voltage integrated circuit. The device structure is manufactured using a hybrid orientation technology wafer with a first semiconductor layer with a first crystalline orientation, a second semiconductor layer with a second crystalline orientation, and an insulating layer between the first and second semiconductor layers. The device structure includes an epitaxial semiconductor region having the second crystalline orientation and first and second p-n junctions in the epitaxial semiconductor region. The epitaxial semiconductor region extends from the second semiconductor layer through the insulating layer and the first semiconductor layer toward a top surface of the first semiconductor layer. The first and second p-n junctions are arranged in depth within the epitaxial semiconductor region between the second semiconductor layer and the top surface of the first semiconductor layer. | 2009-10-15 |
20090256175 | Method of doping transistor comprising carbon nanotube, method of controlling position of doping ion, and transistors using the same - Provided are a method of doping a carbon nanotube (CNT) of a field effect transistor and a method of controlling the position of doping ions. The method may include providing a source, a drain, the CNT as a channel between the source and the drain, and a gate, applying a first voltage to the gate, and adsorbing ions on a surface of the CNT. | 2009-10-15 |
20090256176 | SOLID-STATE IMAGING APPARATUS - A solid-state imaging apparatus, controlling a potential on a semiconductor substrate for an electronic shutter operation, includes: a first semiconductor region of the first conductivity type for forming a photoelectric conversion region; a second semiconductor region of the first conductivity type, formed separately from the photoelectric conversion region, for accumulating carriers; a third semiconductor region of a second conductivity type arranged under the second semiconductor region, for operating as a potential barrier; a fourth semiconductor region of the second conductivity type extending between the first semiconductor region and the semiconductor substrate, and between the third semiconductor region and the semiconductor substrate; and a first voltage supply portion for supplying a voltage to the third semiconductor region; wherein the first voltage supply portion includes a fifth semiconductor region of the second conductivity type arranged in the pixel region, and a first electrode connected to the fifth semiconductor region. | 2009-10-15 |
20090256177 | Semiconductor device including an ohmic layer - In an ohmic layer and methods of forming the ohmic layer, a gate structure including the ohmic layer and a metal wiring having the ohmic layer, the ohmic layer is formed using tungsten silicide that includes tungsten and silicon with an atomic ratio within a range of about 1:5 to about 1:15. The tungsten silicide may be obtained in a chamber using a reaction gas including a tungsten source gas and a silicon source gas by a partial pressure ratio within a range of about 1.0:25.0 to about 1.0:160.0. The reaction gas may have a partial pressure within a range of about 2.05 percent to about 30.0 percent of a total internal pressure of the chamber. When the ohmic layer is employed for a conductive structure, such as a gate structure or a metal wiring, the conductive structure may have a reduced resistance. | 2009-10-15 |
20090256178 | SEMICONDUCTOR DEVICE HAVING MISFETS AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a dielectric film and gate electrode that are stacked on a substrate, sidewalls formed to cover the side surfaces of the electrode and dielectric film, and SiGe films formed to sandwich the sidewalls, electrode and dielectric film, filled in portions separated from the sidewalls, having upper portions higher than the surface of the substrate and having silicide layers formed on regions of exposed from the substrate. The lower portion of the SiGe film that faces the electrode is formed to extend in a direction perpendicular to the surface of the substrate and the upper portion is inclined and separated farther apart from the gate electrode as the upper portion is separated away from the surface of the substrate. The surface of the silicide layer of the SiGe film that faces the gate electrode is higher than the channel region. | 2009-10-15 |
20090256179 | IMAGE SENSOR - Embodiments relate to and image sensor. In embodiments, the image sensor may include a semiconductor substrate, a photodiode region, a gate electrode, a dummy gate, and an interlayer dielectric layer. The semiconductor substrate includes a field oxide layer. The photodiode region may be formed on the semiconductor substrate. The gate electrode may be formed on the semiconductor substrate. The dummy gate may be formed on the field oxide layer. The interlayer dielectric layer may be formed on one side of the dummy gate and includes an opening exposing the photodiode region. | 2009-10-15 |
20090256180 | Standard cell having compensation capacitance - A standard cell includes a capacity element which is made up of a first well diffusion layer into which a first conductive impurity is diffused in a region from a surface of a substrate to a predetermined depth, an insulation film which is provided on the first well diffusion layer, and a first dummy pattern which is provided on the insulation film. | 2009-10-15 |
20090256181 | MEMORY ARRAY WITH ULTRA-THIN ETCHED PILLAR SURROUND GATE ACCESS TRANSISTORS AND BURIED DATA/BIT LINES - A memory array with data/bit lines extending generally in a first direction formed in an upper surface of a substrate and access transistors extending generally upward and aligned generally atop a corresponding data/bit line. The access transistors have a pillar extending generally upward with a source region formed so as to be in electrical communication with the corresponding data/bit line and a drain region formed generally at an upper portion of the pillar and a surround gate structure substantially completely encompassing the pillar in lateral directions and extending substantially the entire vertical extent of the pillar and word lines extending generally in a second direction and in electrical contact with a corresponding surround gate structure at least a first surface thereof such that bias voltage applied to a given word line is communicated substantially uniformly in a laterally symmetric extent about the corresponding pillar via the surround gate structure. | 2009-10-15 |
20090256182 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device includes a memory cell portion and a peripheral circuit portion. The memory cell portion includes a pillar capacitor with a lower electrode, a dielectric film, and an upper electrode sequentially formed on a side surface of a first insulating portion which is parallel to a predetermined direction, and a transistor electrically connected to the lower electrode. The peripheral circuit portion includes a plate electrode, a cylinder capacitor with an upper electrode, a dielectric film, and a lower electrode sequentially formed on a side surface of the plate electrode which is parallel to the predetermined direction, and a transistor electrically connected to the lower electrode. | 2009-10-15 |
20090256183 | Single Gate Nonvolatile Memory Cell With Transistor and Capacitor - A nonvolatile memory integrated circuit has a semiconductor substrate and a nonvolatile memory device on the semiconductor substrate. The device has a transistor and a capacitor on the semiconductor substrate, and a shared floating gate connecting the gate regions of the transistor and the capacitor. The transistor has at least a doping region defining the source and drain regions, as well as three other doping regions overlapping the source and drain regions. Also disclosed are a nonvolatile memory circuit with multiple such nonvolatile memory device, and methods for making the nonvolatile memory circuit with one or more such nonvolatile memory devices. | 2009-10-15 |
20090256184 | Single Gate Nonvolatile Memory Cell With Transistor and Capacitor - A nonvolatile memory integrated circuit has a semiconductor substrate and a nonvolatile memory device on the semiconductor substrate. The device has a transistor and a capacitor on the semiconductor substrate, and a shared floating gate connecting the gate regions of the transistor and the capacitor. The transistor has at least a doping region defining the source and drain regions, as well as three other doping regions overlapping the source and drain regions. Also disclosed are a nonvolatile memory circuit with multiple such nonvolatile memory device, and methods for making the nonvolatile memory circuit with one or more such nonvolatile memory devices. | 2009-10-15 |
20090256185 | METALLIZED CONDUCTIVE STRAP SPACER FOR SOI DEEP TRENCH CAPACITOR - A conductive strap spacer is formed within a buried strap cavity above an inner electrode recessed below a top surface of a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A portion of the conductive strap spacer is metallized by reacting with a metal to form a strap metal semiconductor alloy region, which is contiguous over the conductive strap spacer and a source region, and may extend to a top surface of the buried insulator layer along a substantially vertical sidewall of the conductive strap spacer. The conductive strap spacer and the strap metal semiconductor alloy region provide a stable electrical connection between the inner electrode of the deep trench capacitor and the source region of the access transistor. | 2009-10-15 |
20090256186 | SPLIT GATE NON-VOLATILE MEMORY CELL - A non-volatile memory (NVM) cell comprising a layer of discrete charge storing elements, a control gate, and a select gate is provided. The control gate has a first sidewall with a lower portion being at least a first angle 10 degrees away from 90 degrees with respect to substrate. Further, the select gate has a second sidewall with a lower portion being at least a second angle at least 10 degrees away from 90 degrees with respect to the substrate. The NVM cell further comprises a layer of dielectric material located between the first sidewall and the second sidewall. | 2009-10-15 |
20090256187 | SEMICONDUCTOR DEVICE HAVING VERTICAL PILLAR TRANSISTORS AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes vertical pillar transistors formed in respective silicon pillars of a silicon substrate. The gates of the vertical pillar transistor are selectively formed on a single surface of lower portions of the silicon pillars, and drain areas of the vertical pillar transistors are connected with one another. | 2009-10-15 |
20090256188 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND THE SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device which includes: alternately supplying a silicon source and an oxidant to deposit a silicon oxide film on a surface of a semiconductor substrate, wherein the silicon source is supplied under a supply condition where an adsorption amount of molecules of the silicon source on the semiconductor substrate is increased without causing an adsorption saturation of the molecules of the silicon source on the semiconductor substrate, and wherein the oxidant is supplied under a supply condition where impurities remain in the molecules of the silicon source adsorbed on the semiconductor substrate. | 2009-10-15 |
20090256189 | TWO BIT U-SHAPED MEMORY STRUCTURE AND METHOD OF MAKING THE SAME - A memory structure includes: a substrate; a control gate positioned on the substrate; floating gates positioned at two sides of the control gate, wherein the floating gates have a U-shaped bottom embedded in the substrate; a first dielectric layer positioned between the control gate and the substrate; a second dielectric layer positioned between the U-shaped bottom of the floating gates and the substrate; a third dielectric layer positioned between the control gate and the floating gates; a local doping region positioned around the floating gates channel; and a source/drain doping region positioned in the substrate at a side of the floating gates. | 2009-10-15 |
20090256190 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - According to an aspect of the present invention, there is provided a semiconductor device including: a semiconductor substrate; active areas with island-like shapes formed on the semiconductor substrate; an element isolation area surrounding the active areas and including an element isolation groove formed on the semiconductor substrate and an element isolation film embedded into the element isolation groove; gate insulating films each formed on corresponding one of the active areas and having a first end portion that overhangs from the corresponding active area onto the element isolation area at one side and a second end portion that overhangs from the corresponding active area onto the element isolation area at the other side, wherein an overhang of the first end portion has a different length from a length of an overhang of the second end portion. | 2009-10-15 |
20090256191 | SPLIT GATE NON-VOLATILE MEMORY CELL WITH IMPROVED ENDURANCE AND METHOD THEREFOR - A non-volatile memory cell including a substrate in which is formed a source region and a drain region defining a channel region between the source region and the drain region is provided. The non-volatile memory cell further includes a select gate structure overlying a first portion of the channel region. The non-volatile memory cell further includes a control gate structure formed overlying a second portion of the channel region, wherein the control gate structure includes a nanocrystal stack having a height, wherein the control gate structure has a convex shape in a corner region formed at an intersection of a first plane substantially parallel to a top surface of the substrate and a second plane substantially parallel to a side surface of the control gate structure, wherein a ratio of radius of the control gate structure in the corner region to the height of the nanocrystal stack is at least 0.5. | 2009-10-15 |
20090256192 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - In a nonvolatile semiconductor memory device where a tunnel insulating film, a charge storage layer, a blocking insulating film, and a control gate are stacked one on top of another on a semiconductor substrate, with an element isolation insulating film buried between adjacent cells, a barrier layer composed of at least one of a silicon nitride film, a silicon oxynitride film, and a silicon oxide film which has a higher density than that of the element isolation insulating film is provided at the interface between the element isolation insulating film and the blocking insulating film or between the element isolation film and the control gate. | 2009-10-15 |
20090256193 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - In a semiconductor device which includes a split-gate type memory cell having a control gate and a memory gate, a low withstand voltage MISFET and a high withstand voltage MISFET, variations of the threshold voltage of the memory cell are suppressed. A gate insulating film of a control gate is thinner than a gate insulating film of a high withstand voltage MISFET, the control gate is thicker than a gate electrode | 2009-10-15 |
20090256194 | SEMICONDUCTOR DEVICE WITH REDUCED RESISTANCE OF BIT LINES AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device comprises buried bit lines which are formed to be brought into contact with drain areas of vertical pillar transistors. The buried bit lines are arranged along a first direction in a silicon substrate. The buried bit lines are formed of epi-silicon to reduce the resistance of the buried bit lines. | 2009-10-15 |
20090256195 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device in which current flows in a vertical direction includes a structure that decreases resistance between a source electrode and a drain electrode along with a current path at a position different from a position having highest electric field intensity between the source electrode and the drain electrode. | 2009-10-15 |
20090256196 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICE STRUCTURES AND METHODS - A three-dimensional semiconductor device structure includes a first semiconductor device and a second semiconductor device bonded together using a patterned conductive layer according to an embodiment of the invention. The first semiconductor device includes a first plurality of terminals on its front side, and the second semiconductor device includes a second plurality of terminals on its front side. The patterned conductive layer includes a plurality of conductive regions. Each of the conductive regions is bonded to a conductor coupled to one of the first plurality of terminals and bonded to another conductor coupled to one of the second plurality of terminals, providing electrical coupling between the first semiconductor device and the second semiconductor device. In a specific embodiment, each terminal of the first semiconductor device is bonded to a corresponding terminal of the second semiconductor device, providing a parallel combination of the first and the second semiconductor devices. | 2009-10-15 |
20090256197 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Provided is a technology, in a semiconductor device having a power MISFET and a Schottky barrier diode on one semiconductor substrate, capable of suppressing a drastic increase in the on-resistance of the power MISFET while making the avalanche breakdown voltage of the Schottky barrier diode greater than that of the power MISFET. In the present invention, two epitaxial layers, one having a high doping concentration and the other having a low doping concentration, are formed over a semiconductor substrate and the boundary between these two epitaxial layers is located in a region equal in depth to or shallower than the bottom portion of a trench. | 2009-10-15 |
20090256198 | SEMICONDUCTOR DEVICES HAVING LINE TYPE ACTIVE REGIONS AND METHODS OF FABRICATING THE SAME - In a semiconductor device having line type active regions and a method of fabricating the semiconductor device, the semiconductor device includes a device isolation layer which defines the line type active regions in a in a semiconductor substrate. Gate electrodes which are parallel to each other and intersect the line type active regions are disposed over the semiconductor substrate. Here, the gate electrodes include both a device gate electrode and a recessed device isolation gate electrode. Alternatively, each of the gate electrodes is constituted of a device gate electrode and a plan type device isolation gate electrode, and a width of the plan type device isolation gate electrode greater than a width of the device gate electrode. | 2009-10-15 |
20090256199 | LATERAL METAL OXIDE SEMICONDUCTOR DRAIN EXTENSION DESIGN - A semiconductor device comprising source and drain regions and insulating region and a plate structure. The source and drain regions are on or in a semiconductor substrate. The insulating region is on or in the semiconductor substrate and located between the source and drain regions. The insulating region has a thin layer and a thick layer. The thick layer includes a plurality of insulating stripes that are separated from each other and that extend across a length between the source and the drain regions. The plate structure is located between the source and the drain regions, wherein the plate structure is located on the thin layer and portions of the thick layer, the plate structure having one or more conductive bands that are directly over individual ones of the plurality of insulating stripes. | 2009-10-15 |
20090256200 | Disconnected DPW Structures for Improving On-State Performance of MOS Devices - A semiconductor structure includes a semiconductor substrate; a first high-voltage well (HVW) region of a first conductivity type overlying the semiconductor substrate; a second HVW region of a second conductivity type opposite the first conductivity type overlying the substrate and laterally adjoining the first HVW region; a gate dielectric extending from over the first HVW region to over the second HVW region; a gate electrode on the gate dielectric; a drain region in the second HVW region; a source region at an opposite side of the gate dielectric than the drain region; and a deep well region of the first conductivity type underlying the second HVW region. Substantially no deep well region is formed directly underlying the drain region. | 2009-10-15 |
20090256201 | METAL OXIDE SEMICONDUCTOR TRANSISTOR WITH REDUCED GATE HEIGHT, AND RELATED FABRICATION METHODS - A metal oxide semiconductor transistor device having a reduced gate height is provided. One embodiment of the device includes a substrate having a layer of semiconductor material, a gate structure overlying the layer of semiconductor material, and source/drain recesses formed in the semiconductor material adjacent to the gate structure, such that remaining semiconductor material is located below the source/drain recesses. The device also includes shallow source/drain implant regions formed in the remaining semiconductor material, and epitaxially grown, in situ doped, semiconductor material in the source/drain recesses. | 2009-10-15 |
20090256202 | SEMICONDUCTOR-ON-INSULATOR DEVICE STRUCTURES WITH A BODY-TO-SUBSTRATE CONNECTION FOR ENHANCED ELECTROSTATIC DISCHARGE PROTECTION, AND DESIGN STRUCTURES FOR SUCH SEMICONDUCTOR-ON-INSULATOR DEVICE STRUCTURES - Semiconductor-on-insulator device structures with enhanced electrostatic discharge protection, and design structures for an integrated circuit with device structures exhibiting enhanced electrostatic discharge protection. A device is formed in a body region of a device layer of a semiconductor-on-insulator substrate, which is bounded by an inner peripheral sidewall of an annular dielectric-filled isolation structure that extends from a top surface of the device layer to the insulating layer of the semiconductor-on-insulator substrate. An annular conductive interconnect extends through the body region and the insulating layer to connect the body region with the bulk wafer of the semiconductor-on-insulator substrate. The annular conductive interconnect is disposed inside the inner peripheral sidewall of the isolation structure, which annularly encircles the body region. | 2009-10-15 |
20090256203 | Top Gate Thin Film Transistor with Independent Field Control for Off-Current Suppression - A bottom-contacted top gate (TG) thin film transistor (TFT) with independent field control for off-current suppression is provided, along with an associated fabrication method. The method provides a substrate, and forms source and drain regions overlying the substrate, each having a channel interface top surface. A channel is interposed between the source and drain, with source and drain contact regions immediately overlying the source/drain (S/D) interface top surfaces, respectively. A first dielectric layer is formed overlying the source, drain, and channel. A first gate is formed overlying the first dielectric, having a drain sidewall located between the contact regions. A second dielectric layer is formed overlying the first gate and first dielectric. A second gate overlies the second dielectric, located over the drain contact region. | 2009-10-15 |
20090256204 | SOI TRANSISTOR WITH MERGED LATERAL BIPOLAR TRANSISTOR - A semiconductor-on-insulator transistor device includes a source region, a drain region, a body region, and a source-side lateral bipolar transistor. The source region has a first conductivity type. The body region has a second conductivity type and is positioned between the source region and the drain region. The source-side lateral bipolar transistor includes a base, a collector, and an emitter. A silicide region connects the base to the collector. The emitter is the body region. The collector has the second conductivity type, and the base is the source region and is positioned between the emitter and the collector. | 2009-10-15 |
20090256205 | 2-T SRAM CELL STRUCTURE AND METHOD - The present invention, in one embodiment, provides a memory device including a substrate including at least one device region; a first field effect transistor having a first threshold voltage and a second field effect transistor having a second threshold voltage, the second field effect transistor including a second active region present in the at least one device region of the substrate, the second active region including a second drain and a second source separated by a second channel region, wherein the second channel region includes a second trap that stores holes produced when the first field effect transistor is in the on state, wherein the holes stored in the second trap increase the second threshold voltage to be greater than the first threshold voltage. | 2009-10-15 |
20090256206 | P-Channel germanium on insulator (GOI) one transistor memory cell - According to one exemplary embodiment, a p-channel germanium on insulator (GOI) one transistor memory cell comprises a buried oxide (BOX) layer formed over a bulk substrate, and a gate formed over a gate dielectric layer situated over a germanium layer formed over the buried oxide (BOX) layer. A source region is formed in the germanium layer adjacent to a channel region underlying the gate and overlaying the BOX layer, and a drain region is formed in the germanium layer adjacent to the channel region. The source region and the drain region are implanted with a p-type dopant. In one embodiment, a p-channel GOI one transistor memory cell is implemented as a capacitorless dynamic random access memory (DRAM) cell. In one embodiment, a plurality of p-channel GOI one transistor memory cells are included in a memory array. | 2009-10-15 |
20090256207 | FINFET DEVICES FROM BULK SEMICONDUCTOR AND METHODS FOR MANUFACTURING THE SAME - Disclosed herein is a transistor comprising a first fin having a first gate electrode disposed across the first fin; the gate electrode contacting opposing surfaces of the fin; and a planar oxide layer having a second gate electrode disposed across the planar oxide layer to form a planar metal oxide semiconductor field effect transistor; the first fin and the planar oxide layer being disposed upon a surface of a wafer. | 2009-10-15 |
20090256208 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device according to one embodiment includes: forming a fin and a film on a semiconductor substrate, the film being located at least either on the fin or under the fin and on the semiconductor substrate; forming a gate electrode so as to sandwich both side faces of the fin via a gate insulating film; and expanding or shrinking the film, thereby generating a strain in a height direction of the fin in a channel region. | 2009-10-15 |
20090256209 | Gate Structure of Semiconductor Device - A gate structure of a semiconductor device comprising a silicon substrate having a field oxide film, a plurality of gates formed by sequentially stacking a first gate dielectric film, a first gate conductive film, and a gate silicide film on the silicon substrate. a thermal oxide film formed on a side of the first gate conductive film, a plurality of trenches formed between the gates, a second gate oxide film formed on an interior wall of each trench; and a second conductive film formed in a spacer shape on a predetermined region of the second gate oxide film, and on a side of the first gate conductive film, the gate silicide film and the thermal oxide film. | 2009-10-15 |
20090256210 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD OF THE SEMICONDUCTOR DEVICE - A semiconductor device, which can prevent an element breakdown by alleviating of electric field concentrations, and can also prevent reduction of gain is provided. | 2009-10-15 |
20090256211 | METAL GATE COMPATIBLE FLASH MEMORY GATE STACK - A first gate stack comprising two stacked gate electrodes in a first device region, a second gate stack comprising a metal gate electrode in a second device region, and a third gate stack comprising a semiconductor gate electrode in a third device region are formed by forming and removing portions of a silicon-oxide based gate dielectric layer, a first doped semiconductor layer, an interfacial dielectric layer, a high-k gate dielectric layer, a metal gate layer, and an optional semiconductor material layer in various device regions. The first gate stack may be employed to form a flash memory, and the second and third gate stacks may be employed to form a pair of p-type and n-type field effect transistors. | 2009-10-15 |
20090256212 | LATERAL DRAIN-EXTENDED MOSFET HAVING CHANNEL ALONG SIDEWALL OF DRAIN EXTENSION DIELECTRIC - An integrated circuit ( | 2009-10-15 |
20090256213 | STRUCTURE AND METHOD FOR MANUFACTURING DEVICE WITH A V-SHAPE CHANNEL NMOSFET - A CMOS structure includes a v-shape surface in an nMOSFET region. The v-shape surface has an orientation in a (100) plane and extends into a Si layer in the nMOSFET region. The nMOSFET gate dielectric layer is a high-k material, such as Hf02. The nMOSFET has a metal gate layer, such as Ta. Poly-Si is deposited on top of the metal gate layer. | 2009-10-15 |
20090256214 | Semiconductor device and associated methods - A semiconductor device and process of fabricating the same, the semiconductor device including a semiconductor substrate, a gate insulating layer on the semiconductor substrate, a gate electrode having sidewalls, on the gate insulating layer, first spacers on the sidewalls of the gate electrode, a source/drain region in the semiconductor substrate, aligned with the sidewalls, a silicide layer on the gate electrode, a silicide layer on the source/drain region, and second spacers covering the first spacers and end parts of a surface of the silicide layer on the source drain region. | 2009-10-15 |
20090256215 | GATED METAL OXIDE SENSOR - An apparatus for sensing an analyte gas is provided. The apparatus may include a signal amplifier that may include a thin film transistor that may include a semiconducting film that may include a metal oxide capable of chemical interaction with the analyte gas, such as carbon monoxide. The apparatus may be tuned for detecting the analyte gas by varying the gate voltage of the transistor. | 2009-10-15 |
20090256216 | Wafer Level CSP Sensor - An electronics package has a wafer level chip scale package (WLCSP) die substrate containing electronic circuits. Through-silicon vias through the die substrate electrically connect the electronic circuits to the bottom surface of the die substrate. A package sensor is coupled to the die substrate for sensing an environmental parameter. A protective encapsulant layer covers the top surface of the die substrate. A sensor aperture over the package sensor provides access for the package sensor to the environmental parameter. | 2009-10-15 |
20090256217 | CARBON NANOTUBE MEMORY CELLS HAVING FLAT BOTTOM ELECTRODE CONTACT SURFACE - The present invention is directed to structures and methods of fabricating nanotube electromechanical memory cells having a bottom electrode with a substantially planar contact surface. The bottom electrode is configured so that during the operation of the memory cell the nanotube crossbar of the cell can make contact with a substantially planar surface of the bottom electrode. | 2009-10-15 |
20090256218 | MEMS DEVICE HAVING A LAYER MOVABLE AT ASYMMETRIC RATES - A microelectromechanical (MEMS) device includes a substrate and a movable layer mechanically coupled to the substrate. The movable layer moves from a first position to a second position at a first rate and from the second position to the first position at a second rate faster than the first rate. The MEMS device further includes an adjustable cavity defined between the substrate and the movable layer and containing a fluid. The MEMS device further includes a fluid conductive element through which the fluid flows at a first flowrate from inside the cavity to outside the cavity upon movement of the movable layer from the second position to the first position and through which the fluid flows at a second flowrate slower than the first flowrate from outside the cavity to inside the cavity upon movement of the movable layer from the first position to the second position. | 2009-10-15 |
20090256219 | METHOD FOR MANUFACTURING A SEMICONDUCTOR COMPONENT, AS WELL AS A SEMICONDUCTOR COMPONENT, IN A PARTICULAR A DIAPHRAGM SENSOR - A method for producing a micromechanical diaphragm sensor includes providing a semiconductor substrate having a first region, a diaphragm, and a cavity that is located at least partially below the diaphragm. Above at least one part of the first region, a second region is generated in or on the surface of the semiconductor substrate, with at least one part of the second region being provided as crosspieces. The diaphragm is formed by a deposited sealing layer, and includes at least a part of the crosspieces. | 2009-10-15 |
20090256220 | Low switching current MTJ element for ultra-high STT-RAM and a method for making the same - A STT-RAM MTJ that minimizes spin-transfer magnetization switching current (Jc) while achieving a high dR/R is disclosed. The MTJ has a MgO tunnel barrier formed by natural oxidation to achieve a low RA, and a CoFeB/FeSiO/CoFeB composite free layer with a middle nanocurrent channel layer to minimize Jc | 2009-10-15 |
20090256221 | METHOD FOR MAKING VERY SMALL ISOLATED DOTS ON SUBSTRATES - A method for forming very small isolated dots of a target material, e.g., a ferromagnetic material or phase change material, on a substrate includes providing a substrate having a layer of the target material disposed on a surface thereof, etching the layer of target material so as to form a plurality of lines of the material on the surface of the substrate, and etching the lines of the target material so as to form a rectangular matrix of substantially similar, very small isolated dots of the target material on the substrate. By the successive formation of orthogonally intersecting linear patterns on the substrate, including the formation and use of “hard” etch masks, spacer approach and selective etching techniques, the method enables very small (<65 nm) isolated dots of the target material to be formed on the substrate reliably and with the use of conventional 193 nm wavelength photolithographic methods and apparatus. | 2009-10-15 |
20090256222 | Packaging method of image sensing device - A packaging method for an image sensing device is disclosed. The packaging method includes the steps of a) providing an annular dam on a substrate; b) mounting an image sensing module, having a light-receiving region exposed, inside the annular dam on the substrate; c) connecting the image sensing module and the substrate via a plurality of bonding wires; d) forming a barrier around the light-receiving region on the image sensing module; e) filling an adhesive between the barrier and the annular dam with the plurality of bonding wires being encapsulated; f) forming a transparent lid above the light-receiving region; and g) cutting off the annular dam. | 2009-10-15 |
20090256223 | PHOTODIODE ARRAY - A photodiode array | 2009-10-15 |