42nd week of 2017 patent applcation highlights part 59 |
Patent application number | Title | Published |
20170301535 | NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device includes a substrate; a nitride semiconductor multilayer structure which is formed on the substrate, includes a first nitride semiconductor layer and a second nitride semiconductor layer having a different composition from that of the first nitride semiconductor layer, and generates two dimensional electron gas on a hetero interface between the first nitride semiconductor layer and the second nitride semiconductor layer; and an insulating film which covers at least a portion of a surface of the nitride semiconductor multilayer structure, has a concentration of Si—H bonds equal to or less than 6.0×10 | 2017-10-19 |
20170301536 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for forming an epitaxial layer on a substrate is disclosed. The method includes the steps of: providing a substrate into a chamber; injecting a precursor and a carrier gas to form the epitaxial layer on the substrate at a starting pressure; and pumping down the starting pressure to a second pressure according to a gradient during a cool down process in the chamber. | 2017-10-19 |
20170301537 | ULTRA-CONFORMAL CARBON FILM DEPOSITION - Embodiments of the disclosure relate to deposition of a conformal carbon-based material. In one embodiment, the method comprises depositing a sacrificial dielectric layer over a substrate, forming patterned features on the substrate by removing portions of the sacrificial dielectric layer to expose an upper surface of the substrate, introducing a hydrocarbon source, a plasma-initiating gas, and a dilution gas into the processing chamber, generating a plasma in the processing chamber at a deposition temperature of about 80° C. to about 550° C. to deposit a conformal amorphous carbon layer on the patterned features and the exposed upper surface of the substrate, selectively removing the amorphous carbon layer from an upper surface of the patterned features and the upper surface of the substrate using an anisotropic etching process to provide the patterned features filled within sidewall spacers, and removing the patterned features formed from the sacrificial dielectric layer. | 2017-10-19 |
20170301538 | DEPOSITION METHOD AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An object is to provide a deposition method in which a gallium oxide film is formed by a DC sputtering method. Another object is to provide a method for manufacturing a semiconductor device using a gallium oxide film as an insulating layer such as a gate insulating layer of a transistor. An insulating film is formed by a DC sputtering method or a pulsed DC sputtering method, using an oxide target including gallium oxide (also referred to as GaO | 2017-10-19 |
20170301539 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM - A method of manufacturing a semiconductor device includes forming a film on a substrate by overlapping the following during at least a certain period: (a) supplying a first source to the substrate, the first source including at least one of an inorganic source containing a specific element and a halogen element and an organic source containing the specific element and the halogen element; (b) supplying a second source to the substrate, the second source including at least one of amine, organic hydrazine, and hydrogen nitride; and (c) supplying a third source to the substrate, the third source including at least one of amine, organic hydrazine, hydrogen nitride, and organic borane. | 2017-10-19 |
20170301540 | SUBSTRATE TREATING APPARATUS AND SUBSTRATE TREATING METHOD - A substrate treating apparatus including an unloading order changing unit. The unloading order changing unit reverses an order, in regard to unloading of substrates in a carrier from the top, between a poor inclined substrate and a substrate at least immediately above the poor inclined substrate when the poor inclined substrate is present whose inclination is determined larger than a pre-set threshold by a poor inclination determining unit. That is, the order is reversed such that the poor inclined substrate whose surface may be possibly be scratched with a hand is unloaded prior to the substrate immediately above the poor inclined substrate. Accordingly, this inhibits damages on the substrate caused by scratching a substrate surface with the hand of a substrate transport mechanism. | 2017-10-19 |
20170301541 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - The present invention provides a semiconductor device manufacturing method for lowering the technical difficulties of a process forming a horizontal single crystal nanowire and a manufacturing cost, the semiconductor device manufacturing method comprising the steps of: preparing a substrate including a first area and a second area; determining a position at which a nanowire is to be formed on the substrate of the first area and arranging an empty space in which the nanowire is to be filled; exposing a substrate surface of a part adjacent to the first area; causing selective single crystal growth from the exposed substrate surface; and forming a nanowire by a self-aligned method through an etching process within the first area, and removing, from outside the first area, a single crystal growth layer of the remaining areas excluding a part necessary for the wiring of the second area. | 2017-10-19 |
20170301542 | COMBINED ANNEAL AND SELECTIVE DEPOSITION PROCESS - A method for forming a film with an annealing step and a deposition step is disclosed. The method comprises an annealing step for inducing self-assembly or alignment within a polymer. The method also comprises a selective deposition step in order to enable selective deposition on a polymer. | 2017-10-19 |
20170301543 | Method of Fabricating Semiconductor Device - A method for fabricating a semiconductor device includes forming a first material layer over a substrate, forming a middle layer over the first material layer, forming a first hard mask (HM) layer over the middle layer, forming a second HM layer over the first HM layer, forming a first trench in the second HM layer that extends into the first HM layer, forming a second trench in the second HM layer, The second trench is parallel to the first trench. The method also includes forming a first hole feature in the middle layer within the first trench by using the second HM layer and the first HM layer as a mask and forming a second hole feature in the middle layer within the second trench by using the second HM layer as a mask. | 2017-10-19 |
20170301544 | METHOD AND APPARATUS FOR REDUCING THRESHOLD VOLTAGE MISMATCH IN AN INTEGRATED CIRCUIT - A method of making a transistor for an integrated circuit includes providing a substrate and forming a dummy gate for the transistor within a gate trench on the substrate. The gate trench includes sidewalls, a trench bottom, and a trench centerline extending normally from a center portion of the trench bottom. The dummy gate is removed from the gate trench. A gate dielectric layer is disposed within the gate trench. A gate work-function metal layer is disposed over the gate dielectric layer, the work-function metal layer including a pair of corner regions proximate the trench bottom. An angled implantation process is utilized to implant a work-function tuning species into the corner regions at a tilt angle relative to the trench centerline, the tilt angle being greater than zero. | 2017-10-19 |
20170301545 | TRANSISTOR AND FABRICATION METHOD THEREOF - A transistor and a method of forming the transistor are provided. The method includes forming a first interlayer dielectric layer on a substrate, forming an opening through the first interlayer dielectric layer, and forming a work function layer over side surfaces and a bottom of the opening. The method further includes forming a gate electrode layer over the work function layer, removing at least a portion of the work function layer over side surfaces of the gate electrode layer to form grooves, and forming a protection layer in the grooves. | 2017-10-19 |
20170301546 | DIELECTRIC STRUCTURES FOR NITRIDE SEMICONDUCTOR DEVICES - A dielectric structure for a nitride semiconductor device and a method of forming the same. A semiconductor device includes at least one semiconductor layer. The at least one semiconductor layer includes a gallium nitride semiconductor material. The semiconductor device also includes an oxidized layer disposed over the at least one semiconductor layer. The oxidized layer includes an oxidized form of the gallium nitride semiconductor of the at least one semiconductor layer. A silicon oxide layer is disposed over the oxidized layer. A gate is disposed over the silicon oxide layer. | 2017-10-19 |
20170301547 | METHOD FOR MANUFACTURING NONVOLATILE MEMORY THIN FILM DEVICE BY USING NEUTRAL PARTICLE BEAM GENERATION APPARATUS - The present invention relates to a method for manufacturing a nonvolatile memory thin film device by using a neutral particle beam generation apparatus. The present invention solves the problem that substrates such as glass and a plastic film may not be used for manufacturing the memory thin film device due to the high temperature heat treatment process for a long time, in the existing method for manufacturing the thin film device having the nonvolatile memory function by forming the mobile proton layer. | 2017-10-19 |
20170301548 | INTEGRATED CIRCUITS WITH BACKSIDE METALIZATION AND PRODUCTION METHOD THEREOF - An embodiment of an integrated device, including a chip of semiconductor material wherein an integrated circuit is integrated, is proposed; the integrated device includes a set of contact terminals for contacting the integrated circuit. At least one contact terminal of said set of contact terminals includes a contact layer of metal material being suitable to be directly coupled mechanically to an element external to the chip, and a coupling element for improving an electrical and/or mechanical coupling between the contact layer and the chip. The coupling element includes a coupling layer being formed by a combination between the metal material of the contact layer and the semiconductor material of the chip, with the coupling layer that is directly coupled to the chip and to the contact layer. | 2017-10-19 |
20170301549 | METHOD OF PROCESSING SiC WAFER - A SiC wafer is processed by a laser beam having a wavelength that transmits SiC to form a peeling plane in a region of the wafer which corresponds to a device area of a first surface of the wafer. A plurality of devices demarcated by a plurality of intersecting projected dicing lines in the device area are formed on the first surface. An annular groove is formed on a second surface of the wafer which is opposite the first surface, in a boundary region of the wafer between the device area and an outer peripheral excessive area surrounding the device area. A portion of the wafer which is positioned radially inwardly of the annular groove is peeled from the peeling plane, thereby thinning the device area and forming an annular stiffener area on a region of the second surface which corresponds to the outer peripheral excessive area. | 2017-10-19 |
20170301550 | METHOD FOR PREFERENTIAL OXIDATION OF SILICON IN SUBSTRATES CONTAINING SILICON AND GERMANIUM - A method for preferential oxidation of silicon in substrates containing silicon (Si) and germanium (Ge) is described. According to one embodiment, the method includes providing a substrate containing Si and Ge, forming a plasma containing H | 2017-10-19 |
20170301551 | FABRICATION OF MULTI THRESHOLD-VOLTAGE DEVICES - A method of fabricating multi V | 2017-10-19 |
20170301552 | Method for Patterning a Substrate Using a Layer with Multiple Materials - Techniques disclosed herein provide a method of patterning for creating high-resolution features and also for cutting on pitch of sub-resolution features. Techniques include forming bi-layer or multi-layer mandrels and then forming one or more lines of material running along sidewalls of the mandrels. The different materials can have different etch resistivities to be able to selectively etch one or more of the materials to create features and create cuts and blocks where specified. Etching using an etch mask positioned above or below this multi-line layer further defines a pattern that is transferred into an underlying layer. Having a mandrel of two or more layers of material enables one of those materials to be sacrificial such as when etching a spin-on reversal overcoat material that has filled-in open spaces, but leaves an overburden. | 2017-10-19 |
20170301553 | CLEANING APPARATUS, CHEMICAL MECHANICAL POLISHING SYSTEM INCLUDING THE SAME, CLEANING METHOD AFTER CHEMICAL MECHANICAL POLISHING, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE INCLUDING THE SAME - A cleaning apparatus for removing particles from a substrate is provided. The cleaning apparatus includes a first cleaning unit including a first dual nozzle supplying, to a substrate, a first chemical liquid and a first spray including a first liquid dissolving the first chemical liquid, and a second cleaning unit including a second dual nozzle supplying, to the substrate, a second chemical liquid different from the first chemical liquid and a second spray including a second liquid dissolving the second chemical liquid and being the same as the first liquid. | 2017-10-19 |
20170301554 | Stacked Nanowires - Techniques for producing stacked SiGe nanowires using a condensation process without parasitic Ge nanowires as an undesired by-product. In one aspect, a method of forming SiGe nanowires includes the steps of: forming a stack of alternating Si and SiGe layers on a wafer; patterning fins in the stack; selectively thinning the SiGe layers in the fins such that the Si and SiGe layers give the fins an hourglass shape; burying the fins in an oxide material; and annealing the fins under conditions sufficient to diffuse Ge from the SiGe layers in the fins to the Si layers in the fins to form the SiGe nanowires. A FET device and method for formation thereof are also provided. | 2017-10-19 |
20170301555 | Stacked Nanowires - Techniques for producing stacked SiGe nanowires using a condensation process without parasitic Ge nanowires as an undesired by-product. In one aspect, a method of forming SiGe nanowires includes the steps of: forming a stack of alternating Si and SiGe layers on a wafer; patterning fins in the stack; selectively thinning the SiGe layers in the fins such that the Si and SiGe layers give the fins an hourglass shape; burying the fins in an oxide material; and annealing the fins under conditions sufficient to diffuse Ge from the SiGe layers in the fins to the Si layers in the fins to form the SiGe nanowires. A FET device and method for formation thereof are also provided. | 2017-10-19 |
20170301556 | DEVICE CONFORMITY CONTROL BY LOW TEMPERATURE, LOW PRESSURE, INDUCTIVELY COUPLED AMMONIA-NITROGEN TRIFLUORIDE PLASMA - The present disclosure generally relates to methods of removing oxides and oxide-containing layers from the surfaces of substrates. In one aspect, a method of processing a substrate comprises positioning a substrate in a process chamber, the substrate having an oxide layer thereon; introducing one or more process gases to an interior of the process chamber; ionizing the one or more process gases; exposing the oxide layer to the one or more ionized process gases, wherein the process chamber is maintained at a pressure less than about 50 mTorr during the exposing, and the substrate is maintained at a temperature within a range of about zero degrees Celsius to about 30 degrees Celsius during the exposing; and removing the oxide layer from the surface of the substrate. | 2017-10-19 |
20170301557 | Method of Integration Process for Metal CMP - A method of fabricating a semiconductor device is disclosed. The method includes forming a dielectric layer over a substrate. The substrate has an edge region and a center region. The method also includes forming a dielectric ring in the edge region, forming a metal layer over the center region of the substrate and over the dielectric ring in the edge region of the substrate and polishing the metal layer in the center region and the edge region to expose the dielectric ring in the edge region of the substrate. | 2017-10-19 |
20170301558 | WIRING SUBSTRATE, METHOD OF MANUFACTURING WIRING SUBSTRATE, COMPONENT-EMBEDDED GLASS SUBSTRATE, AND METHOD OF MANUFACTURING COMPONENT-EMBEDDED GLASS SUBSTRATE - A method of manufacturing a wiring substrate that has a wiring including a through glass via and is formed of a glass substrate includes forming an alteration layer that penetrates the wiring substrate and is patterned, forming the wiring on a front surface of the wiring substrate in which the alteration layer has been formed, and filling an electrode material in a hole formed by removing the alteration layer, thereby forming the through glass via that connects the wiring on the front surface of the wiring substrate and the wiring on a back surface side thereof. | 2017-10-19 |
20170301559 | METHOD OF ATTACHING COMPONENTS TO PRINTED CIRUCUIT BOARD WITH REDUCED ACCUMULATED TOLERANCES - A method is provided for attaching components to pads on a PCB, where total accumulated tolerances are reduced by separating accumulated tolerances into multiple processes. The method includes performing first and second processes having first and second accumulated tolerances, respectively. The first process includes placing a first stencil over the PCB, the first stencil defining first apertures corresponding to the pads; printing solder paste onto the pads using the first stencil; and reflowing the printed solder paste to form corresponding solder bumps on the pads. The second process includes placing a second stencil over the PCB, the second stencil defining second apertures corresponding to the pads; printing flux onto the solder bumps using the second stencil; placing at least one component on the printed flux; and reflowing the printed flux and the solder bumps to form corresponding solder joints between the at least one component and the first pads, respectively. | 2017-10-19 |
20170301560 | SYSTEM AND METHOD FOR LASER ASSISTED BONDING OF SEMICONDUCTOR DIE - A system and method for laser assisted bonding of semiconductor die. As non-limiting examples, various aspects of this disclosure provide systems and methods that enhance or control laser irradiation of a semiconductor die, for example spatially and/or temporally, to improve bonding of the semiconductor die to a substrate. | 2017-10-19 |
20170301561 | HIGH-FREQUENCY MODULE - On a substrate ( | 2017-10-19 |
20170301562 | Semiconductor Structure and Method of Forming - A structure and method of forming are provided. The structure includes a dielectric layer disposed on a substrate. The structure includes a cavity in the dielectric layer, and a plurality of contacts positioned in the cavity and bonded to the substrate. A component is bonded to the plurality of contacts. Underfill is disposed in the cavity between the dielectric layer and the component. A plurality of connectors is on the dielectric layer, the connectors being connected through the dielectric layer to a conductor that is at a same level of metallization as the plurality of contacts. | 2017-10-19 |
20170301563 | WAFER CARRIER ASSEMBLY - A wafer carrier assembly includes a wafer carrier and a fluid passage. The wafer carrier comprises a retainer ring confining a wafer accommodation space. The fluid passage is inside the wafer carrier. The fluid passage includes an inlet and at least an outlet to dispense fluid into the wafer accommodation space. | 2017-10-19 |
20170301564 | Plasma assisted method of accurate alignment and pre-bonding for microstructure including glass or quartz chip - The plasma-assisted method of precise alignment and pre-bonding for microstructure of glass and quartz microchip belongs to micromachining and bonding technologies of the microchip. The steps of which are as follows: photoresist and chromium layers on glass or quartz microchip are completely removed followed by sufficient cleaning of the surface with nonionic surfactant and quantities of ultra-pure water. Then the surface treatment is proceeded for an equipping surface with high hydrophily with the usage of plasma cleaning device. Under the drying condition, the precise alignment is accomplished through moving substrate and cover plate after being washed with the help of microscope observation. Further on, to achieve precise alignment and pre-bonding of the microstructure of glass and quartz microchip, a minute quantity of ultrapure water is instilled into a limbic crevice for adhesion, and entire water is completely wiped out by vacuum drying following sufficient squeezing. Based on the steps above, it is available to achieve permanent bonding by further adopting thermal bonding method. In summary, it takes within 30 min to finish the whole operation of precise alignment and pre-bonding by this method. Besides, this method is of great promise because of its speediness, efficiency, easy maneuverability, operational safety and wide applications. | 2017-10-19 |
20170301565 | UPPER PLASMA-EXCLUSION-ZONE RINGS FOR A BEVEL ETCHER - An upper plasma-exclusion-zone ring for a bevel etcher is provided that is configured to etch a bevel edge of a substrate. The upper plasma-exclusion-zone ring includes a ring-shaped body and a radially-inner stepped surface. The ring-shaped body of the upper plasma-exclusion-zone ring defines an upper surface, a lower surface, a radially inner surface, and a radially outer surface. The radially-inner stepped surface of the upper plasma-exclusion-zone ring extends inwardly into the ring-shaped body between the radially inner surface of the ring-shaped body and the lower surface of the ring-shaped body. The ring-shaped body is made of a material selected from a group consisting of aluminum oxide, aluminum nitride, silicon, silicon carbide, silicon nitride, and yttria. | 2017-10-19 |
20170301566 | LOWER PLASMA-EXCLUSION-ZONE RINGS FOR A BEVEL ETCHER - A lower plasma-exclusion-zone ring for a bevel etcher is provided that is configured to etch a bevel edge of a substrate. The lower plasma-exclusion-zone ring includes a ring-shaped body and a radially-outer stepped surface. The ring-shaped body of the lower plasma-exclusion-zone ring defines an upper surface, a lower surface, a radially inner surface, and a radially outer surface. The radially-outer stepped surface of the lower plasma-exclusion-zone ring extending inwardly into the ring-shaped body between the radially outer surface of the ring-shaped body and the upper surface of the ring-shaped body. The ring-shaped body is made of a material selected from a group consisting of aluminum oxide, aluminum nitride, silicon, silicon carbide, silicon nitride, and yttria. | 2017-10-19 |
20170301567 | SYSTEM OF CONTROLLING TREATMENT LIQUID DISPENSE FOR SPINNING SUBSTRATES - Provided is a method for cleaning an ion implanted resist layer or a substrate after an ashing process. A duty cycle for turning on and turning off flows of a treatment liquid in two or more nozzles is generated. The substrate is exposed to the treatment liquid comprising a first treatment chemical, the first treatment chemical with a first film thickness, temperature, total flow rate, and first composition. A portion of a surface of the substrate is concurrently irradiated with UV light while controlling the selected plurality of cleaning operating variables in order to achieve the two or more cleaning objectives. The cleaning operating variables comprise two or more of the first temperature, first composition, first film thickness, UV wavelength, UV power, first process time, first rotation speed, duty cycle, and percentage of residue removal. | 2017-10-19 |
20170301568 | GAS SUPPLY MECHANISM AND SEMICONDUCTOR MANUFACTURING SYSTEM - The mechanism includes a pipe and a valve provided in the pipe. The pipe is configured to connect a gas source and a semiconductor manufacturing apparatus. The valve is configured to control a flow rate of the gas. The valve includes a housing and a columnar shaft. The housing includes an inlet and an outlet. A gas flows from the gas source into the internal space through the inlet. A gas flows from the internal space to the semiconductor manufacturing apparatus through the outlet. A gap is provided between an outer peripheral surface of the shaft and an inner wall surface of the housing. The shaft is accommodated in the internal space of the housing and is rotatable. A through hole which penetrates the shaft is formed on the outer peripheral surface of the shaft. Both ends of the through hole correspond to the inlet and the outlet. | 2017-10-19 |
20170301569 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING DRY ETCHING - A method of fabricating a semiconductor device includes forming a material layer and a mask pattern on a substrate, mounting the substrate onto an electrostatic chuck, loading the substrate, including the material layer and the mask pattern, mounted on the electrostatic chuck, into an etching chamber, and forming a material pattern by dry etching the material layer using the mask pattern as an etching mask. The dry etching of the material layer includes adjusting a pressure of the etching chamber to adjust a lateral over-etch of the material pattern in a first direction, wherein the first direction is parallel to a surface of the substrate facing the material pattern, and adjusting a temperature of the electrostatic chuck to adjust an etching of the material pattern in a second direction, wherein the second direction crosses the first direction. | 2017-10-19 |
20170301570 | WAFER CASSETTE AND PLACEMENT METHOD THEREOF - A wafer cassette and a method for placing a wafer are provided. The wafer cassette includes a box body including a plurality of groups of card slots formed on sidewalls of the box body. Each group of the card slots is configured to hold a wafer and includes a wafer input terminal. The wafer cassette also includes a guide device including a plurality of groups of guide slots configured to be docked to the wafer input terminals. Each group of the guide slots and a docking group of the card slots are formed at a same floor. | 2017-10-19 |
20170301571 | WAFER PROCESSING METHOD - Disclosed herein is a wafer processing method for removing an annular reinforcing portion from a wafer having a device area, the annular reinforcing portion being formed around the device area. The wafer processing method includes the steps of supporting the wafer through an adhesive tape to an annular frame, forming a mark corresponding to a notch at a position radially inside a boundary portion between the annular reinforcing portion and the device area, cutting the boundary portion together with the adhesive tape to thereby separate the annular reinforcing portion from the device area, and moving the annular reinforcing portion supported through the adhesive tape to the annular frame away from a holding table to thereby remove the annular reinforcing portion from the wafer. | 2017-10-19 |
20170301572 | Systems and Methods for Annealing Semiconductor Structures - Systems and methods are provided for annealing a semiconductor structure. In one embodiment, the method includes providing an energy-converting structure proximate a semiconductor structure, the energy-converting structure comprising a material having a loss tangent larger than that of the semiconductor structure; providing a heat reflecting structure between the semiconductor structure and the energy-converting structure; and providing microwave radiation to the energy-converting structure and the semiconductor structure. The semiconductor structure may include at least one material selected from the group consisting of boron-doped silicon germanium, silicon phosphide, titanium, nickel, silicon nitride, silicon dioxide, silicon carbide, n-type doped silicon, and aluminum capped silicon carbide. The heat reflecting structure may include a material substantially transparent to microwave radiation and having substantial reflectivity with respect to infrared radiation. | 2017-10-19 |
20170301573 | NOZZLE AND WORK POLISHING APPARATUS - A nozzle according to the invention includes a liquid flow passage through which a liquid flows, a gas flow passage through which a gas flows, the gas flow passage communicating with the liquid flow passage and feeding the gas to the liquid flow passage, and a plasma generating mechanism for generating plasma in the gas fed from the gas flow passage to the liquid flow passage, in which the plasma generating mechanism includes a first electrode provided so as to be exposed to an inside of the liquid flow passage, a second electrode provided so as not to be exposed to the inside of the liquid flow passage and so as to be exposed to an inside of the gas flow passage, and a power source for applying a predetermined voltage across the first electrode and the second electrode, and in which the liquid with which the gas including the generated plasma is mixed as bubbles having a predetermined diameter is spouted. | 2017-10-19 |
20170301574 | RECIPE ID MANAGEMENT SERVER, RECIPE ID MANAGEMENT SYSTEM, AND TERMINAL DEVICE - When receiving a partial ID request from a terminal device, a partial ID transmission unit reads out one or more partial IDs, of which each is a part of a recipe ID, from a partial ID storage unit and transmits the one or more partial IDs to the terminal device. A duplication determination unit determines whether the same recipe ID as a recipe ID created by the terminal device is stored in a recipe ID storage unit. When the same recipe ID as the recipe ID created by the terminal device is not stored in the recipe ID storage unit, an availability notification unit notifies the terminal device of usage permission of the recipe ID and causes the recipe ID storage unit to store the recipe ID created by the terminal device. | 2017-10-19 |
20170301575 | CHIP TRAY - A chip tray, comprising: a first plate configured to allow a plurality of semiconductor elements to be placed thereon, a positioning and clamping mechanism for pressing and holding the semiconductor elements in predetermined locations on the first plate, and actuator means for actuating the positioning and clamping mechanism comprising movable parts of the positioning and clamping mechanism which can be actuated simultaneously to perform a pressing and holding operation and a releasing operation by the positioning and clamping mechanism simultaneously for all the semiconductor elements, wherein the positioning and clamping mechanism comprises a second plate which is laterally shiftable and lockable with respect to the first plate and comprises a plurality of openings and of elastic members each corresponding to an opening and each provided with a pressure piece adapted for abutting against at least one edge of one of the semiconductor elements, characterized in that wherein the elastic members are self-guiding elements mounted on a surface of the second plate, and elastically deformable in a plane parallel to the plane of the second plate in a self-guiding manner. | 2017-10-19 |
20170301576 | SUBSTRATE HANDLING SYSTEM FOR ALIGNING AND ORIENTING SUBSTRATES DURING A TRANSFER OPERATION - A system for sensing, orienting, and transporting wafers in an automated wafer handling process that reduces the generation of particles and contamination so that the wafer yield is increased. The system includes a robotic arm for moving a wafer from one station to a destination station, and an end-effector connected to an end of the robotic arm for receiving the wafer. The end-effector includes a mechanism for gripping the wafer, a direct drive motor for rotating the wafer gripping mechanism, and at least one sensor for sensing the location and orientation of the wafer. A control processor calculates the location of the center and the notch of the wafer based on measurements by the sensor(s) and generates an alignment signal for rotating the wafer gripping mechanism so that the wafer is oriented at a predetermined position on the end-effector while the robotic arm is moving to another station. | 2017-10-19 |
20170301577 | METHODS OF FORMING 3-D CIRCUITS WITH INTEGRATED PASSIVE DEVICES - Methods of forming 3-D ICs with integrated passive devices (IPDs) include stacking separately prefabricated substrates. An active device (AD) substrate has contacts on its upper portion. A ground plane is located between the AD substrate and an IPD substrate. The ground plane provides superior IPD to AD cross-talk attenuation. | 2017-10-19 |
20170301578 | FOCUS RING ASSEMBLY AND A METHOD OF PROCESSING A SUBSTRATE USING THE SAME - A method of processing a substrate including loading the substrate into a plasma-processing apparatus. The plasma-processing apparatus includes a focus ring. The substrate is processed in the plasma-processing apparatus using plasma. The substrate is unloaded from the plasma-processing apparatus. A layer is formed on the focus ring. The layer is formed by an in-situ process in the plasma-processing apparatus. | 2017-10-19 |
20170301579 | TEMPERATURE CONTROL DEVICE FOR PROCESSING TARGET OBJECT AND METHOD OF SELECTIVELY ETCHING NITRIDE FILM FROM MULTILAYER FILM - A temperature control device includes a moving stage allowed to be heated and configured to mount a processing target object on a top surface thereof; a cooling body allowed to be cooled and fixed at a position under the moving stage; a shaft, having one end connected to the moving stage; the other end positioned under the cooling body; a first flange provided at the other end; and a second flange provided between the first flange and the cooling body, extended between the one end and the other end; a driving plate, provided between the first flange and the second flange, having a top surface facing the second flange and a bottom surface opposite to the top surface; an elastic body provided between the bottom surface of the driving plate and the first flange; and a driving unit configured to move the driving plate up and down. | 2017-10-19 |
20170301580 | SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD - A substrate processing apparatus includes a substrate heating unit arranged to heat the underside of a substrate while supporting the substrate thereon and an attitude changing unit arranged to cause the substrate heating unit to undergo an attitude change between a horizontal attitude and a tilted attitude. In an organic solvent removing step to be performed following a substrate heating step of heating the substrate, the substrate heating unit undergoes an attitude change to the tilted attitude so that the upper surface of the substrate becomes tilted with respect to the horizontal surface. | 2017-10-19 |
20170301581 | METHODS OF FABRICATING SEMICONDUCTOR DEVICES INCLUDING FIN-SHAPED ACTIVE REGIONS - A method of manufacturing a semiconductor device includes forming a plurality of fins by forming a plurality of first device isolating trenches repeated at a first pitch in a substrate, forming a plurality of fin-type active areas protruding from a top surface of a first device isolating layer by forming the first device isolating layer in the plurality of first device isolating trenches, forming a plurality of second device isolating trenches at a pitch different from the first pitch by etching a portion of the substrate and the first device isolating layer, and forming a second device isolating layer in the plurality of second device isolating trenches, so as to form a plurality of fin-type active area groups separated from each other with the second device isolating layer therebetween. | 2017-10-19 |
20170301582 | METHOD FOR MANUFACTURING BONDED WAFER - A method for manufacturing a bonded wafer using a base wafer which is an epitaxial wafer produced by a method including at least one of: (1) setting a chamfer width of a wafer for epitaxial growth to be 0.20 mm or less on an epitaxial growth side; (2) preparing a wafer for epitaxial growth having a rise shape on an epitaxial growth side periphery, thereby adjusting the wafer to have an amount of sag within a range of −30 nm/mm | 2017-10-19 |
20170301583 | METHOD FOR PRODUCING AN INTEGRATED CIRCUIT INCLUDING A METALLIZATION LAYER COMPRISING LOW K DIELECTRIC MATERIAL - A method of forming a metallization layer of an IC having a lower via level and an upper trench level is disclosed. In one aspect, the method includes applying a dual damascene process to a stack of two layers. The bottom layer includes a porous low-k dielectric in which the pores have been filled by a template material. The top layer is a template layer. This stack is obtained by depositing a template layer on top of a porous low-k dielectric and annealing in order to let the template material diffuse into the pores of the low-k layer. At the end of the anneal process, a stack of a pore-filled layer and a template layer is obtained. Vias are etched in the low-k layer and trenches are etched in the template layer. The template pore-filling protects the low-k dielectric during plasma etching, metal barrier deposition and metal deposition. | 2017-10-19 |
20170301584 | METHOD AND APPARATUS FOR SINGLE CHAMBER TREATMENT - The disclosure relates to using a single chamber for multiple treatments resulting in a semiconductor chip having an interconnect. An exemplary process many include forming a via to expose several layers of a microchip. The layers may include, pattered dielectric layer, a capping layer, a first metal layer and an insulator. A surface modification step is then implemented to modify and/or densify the treated surfaces of the dielectric surface. A metal compound removal step is then implemented to remove metal compounds from the bottom of the via. Finally, the via is filled with a conductive material. The surface modification and the metal compound removal steps are implemented in one chamber. | 2017-10-19 |
20170301585 | METHOD FOR CREATING THROUGH-CONNECTED VIAS AND CONDUCTORS ON A SUBSTRATE - A method to reduce the number and type of processing steps to achieve conductive lines in the planes of a substrate concurrently interconnecting conductor through the substrate, by forming structures in the planes of a substrate. These structures may include interconnect lines, bond pads, and other structures, and improve the performance of subsequent unique processing while simultaneously reducing the manufacturing complexity to reduce time and cost. These structures are formed by selective etching using chemical mechanical polishing, and then completed using a single fill step with a conductive material. | 2017-10-19 |
20170301586 | FINFET SWITCH - An embodiment of a semiconductor switch structure includes source contacts, drain contacts, gates and fins. The contacts and gates are elongated in a first direction and are spaced apart from each other in a second direction perpendicular to the first direction. The gates are interspersed between the contacts. The fins underlie both the contacts and the gates. The fins are elongated in the second direction and are spaced apart from each other in the first direction. A contact via extends through one of the contacts without contacting a gate or a fin. A gate via extends through one of the gates without contacting a contact or a fin. A contact-gate via is in contact with both a contact and a gate but not a fin. | 2017-10-19 |
20170301587 | RECONFIGURABLE SEMICONDUCTOR DEVICE - A reconfigurable device and an analog circuit are formed on a single chip so that the analog circuit can be controlled by the reconfigurable device. A reconfigurable semiconductor device ( | 2017-10-19 |
20170301588 | Structure and Method for FinFET Device - The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a substrate having a first gate region, a first fin structure over the substrate in the first gate region. The first fin structure includes an upper semiconductor material member, a lower semiconductor material member, surrounded by an oxide feature and a liner wrapping around the oxide feature of the lower semiconductor material member, and extending upwards to wrap around a lower portion of the upper semiconductor material member. The device also includes a dielectric layer laterally proximate to an upper portion of the upper semiconductor material member. Therefore the upper semiconductor material member includes a middle portion that is neither laterally proximate to the dielectric layer nor wrapped by the liner. | 2017-10-19 |
20170301589 | METHODS OF FORMING NMOS AND PMOS FINFET DEVICES AND THE RESULTING PRODUCT - A method includes forming an initial strain relaxed buffer layer on a semiconductor substrate. A trench is formed within the initial strain relaxed buffer layer. An epitaxial deposition process is performed to form an in situ carbon-doped strain relaxed buffer layer in the trench. A channel semiconductor material is formed on the initial strain relaxed buffer layer and on the in situ carbon-doped strain relaxed buffer layer in the trench. A plurality of fin-formation trenches that extend into the initial strain relaxed buffer layer is formed so as to thereby form an NMOS fin including the channel semiconductor material and the in situ carbon-doped strain relaxed buffer layer and a PMOS fin including the channel semiconductor material and the initial strain relaxed buffer layer. A recessed layer of insulating material and gate structures are formed around the NMOS fin and the PMOS fin. | 2017-10-19 |
20170301590 | LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE INTEGRATED WITH VERTICAL FIELD EFFECT TRANSISTOR - An electrical device that in some embodiments includes a substrate including a lateral device region and a vertical device region. A lateral diffusion metal oxide semiconductor (LDMOS) device may be present in the lateral device region, wherein a drift region of the LDMOS device has a length that is parrallel to an upper surface of the substrate in which the LDMOS device is formed. A vertical field effect transistor (VFET) device may be present in the vertical device region, wherein a vertical channel of the VFET has a length that is perpendicular to said upper surface of the substrate, the VFET including a gate structure that is positioned around the vertical channel. | 2017-10-19 |
20170301591 | X-RAY SYSTEM, SEMICONDUCTOR PACKAGE, AND TRAY HAVING X-RAY ABSORPTION FILTER - An X-ray source is disposed and a detector is disposed adjacent to the X-ray source. A test specimen holder is disposed between the X-ray source and the detector. A filter is disposed between the X-ray source and the test specimen holder. The filter has a plate-shaped semiconductor, a granular semiconductor, or a combination thereof. | 2017-10-19 |
20170301592 | WAFER PROCESSING METHOD - There is provided a wafer processing method for dividing a wafer having a plurality of devices formed in regions partitioned by a plurality of crossing division lines on a front surface of a substrate having a birefringent crystal structure, into individual device chips. The wafer processing method includes a detection step of detecting the division line formed on the front surface of the wafer by an imaging unit from the back side of the wafer. In the detection step, a polarizer disposed on an optical axis connecting an imaging element and an image forming lens provided in the imaging unit intercepts extraordinary light appearing due to birefringence in the substrate and guides ordinary light to the imaging element. | 2017-10-19 |
20170301593 | METHOD FOR PRODUCING A PLURALITY OF MEASUREMENT REGIONS ON A CHIP, AND CHIP WITH MEASUREMENT REGIONS - A chip and a method for producing the chip with a plurality of measurement regions which are provided with electrodes for electrically detecting reactions in which, in order to reliably separate the individual measurement regions from one another, a monolayer of a fluorosilane is formed on the chip surface which has strongly hydrophobic properties. Therefore, during spotting with a liquid, the drops of liquid applied by spotting can be reliably prevented from coalescing, and thus, causing mixing of the substances in the drops of liquid which are supposed to be immobilized in the measurement regions. | 2017-10-19 |
20170301594 | SEMICONDUCTOR MODULE - A semiconductor module includes a rectangular base plate; a substrate which is placed on the base plate and on which a circuit including a semiconductor chip and so forth is formed; a rectangular parallelepiped case made of resin that is attached to the base plate and houses the substrate within; and a plurality of external terminals lower ends of which are fixed to the substrate with upper ends thereof being exposed on a top face of the case. The case is provided with a first case opening portion and a second case opening portion that are respectively formed by cutting off a front face and a rear face of the case from an upper edge thereof along a longitudinal direction thereof; and the top face of the case between the first case opening portion and the second case opening portion includes an external terminal holding portion to hold the plurality of external terminals along the longitudinal direction with the upper ends thereof being exposed. A sealing material is injected from the first case opening portion and the second case opening portion onto a top face of the substrate, and thereby the semiconductor module is sealed. | 2017-10-19 |
20170301595 | SILICON PACKAGE FOR EMBEDDED SEMICONDUCTOR CHIP AND POWER CONVERTER - A packaged transistor device ( | 2017-10-19 |
20170301596 | SILICON PACKAGE FOR EMBEDDED SEMICONDUCTOR CHIP AND POWER CONVERTER - A packaged transistor device ( | 2017-10-19 |
20170301597 | THERMOSETTING RESIN COMPOSITION AND METHOD OF PRODUCING SAME - Provided is a thermosetting resin composition, which can be used as underfill for obtaining favorable solder connectivity while suppressing the formation of voids in the case of treating under heating conditions required by the underfill in a semiconductor chip thermocompression bonding step using the thermal compression bonding technique. The thermosetting resin composition contains a thermosetting resin, a curing agent and a fluxing agent, and the temperature at which the rate of temperature change of viscosity when temperature is increased according to a prescribed heating profile reaches 30 Pa·s/° C. is 200° C. to 250° C. | 2017-10-19 |
20170301598 | MICROELECTRONIC DEVICES, STACKED MICROELECTRONIC DEVICES, AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES - Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices are described herein. In one embodiment, a set of stacked microelectronic devices includes (a) a first microelectronic die having a first side and a second side opposite the first side, (b) a first substrate attached to the first side of the first microelectronic die and electrically coupled to the first microelectronic die, (c) a second substrate attached to the second side of the first microelectronic die, (d) a plurality of electrical couplers attached to the second substrate, (e) a third substrate coupled to the electrical couplers, and (f) a second microelectronic die attached to the third substrate. The electrical couplers are positioned such that at least some of the electrical couplers are inboard the first microelectronic die. | 2017-10-19 |
20170301599 | SEMICONDUCTOR DEVICE - A semiconductor device includes a lead frame; a circuit board located on the lead frame; a power device that includes a switching element and is mounted on the circuit board via a bump located between the power device and the circuit board; and a heat releasing member connected to the power device. The circuit board may be a multi-layer wiring board. The circuit board may include a capacitor element, a resistor element, an inductor element, a diode element and a switching element. | 2017-10-19 |
20170301600 | POWER ELECTRONICS ARRANGEMENT AND VEHICLE WITH SAID ARRANGEMENT - A power electronics arrangement has a power semiconductor module, with a contact spring, with a load connecting element and with a mounting device which is embodied as part of an electrically operated vehicle. The power semiconductor module has a load connection element which preferably projects outwards from the interior of the power semiconductor module, and preferably has there a first external contact face for external connection, and the load-connecting element has a second contact face. An electrically conductive pressure contact connection is embodied between the first contact face and the second contact face by a contact spring, wherein the pressure on the contact spring which is necessary for this is implemented by connecting the power semiconductor module in a frictionally locking fashion to the mounting device. | 2017-10-19 |
20170301601 | Trench-type heat sink structure applicable to semiconductor device - The present invention discloses a trench-type heat sink structure applicable to semiconductor devices. An embodiment of the present invention comprises: a first semiconductor substrate; a heat source including at least one heat spot, in which the heat source is on/in the semiconductor substrate or being a part of the semiconductor substrate; at least one first heat conduction layer; at least one first heat conduction structure configured to connect the at least one heat spot with the at least one first heat conduction layer; at least one heat sink trench; and at least one second heat conduction structure configured to connect the at least one first heat conduction layer with the at least one heat sink trench, so as to transmit heat from the heat source to the at least one heat sink trench. | 2017-10-19 |
20170301602 | HEAT DISSIPATION STRUCTURE OF SEMICONDUCTOR DEVICE - A heat dissipation structure of a semiconductor device with excellent heat dissipation applicable to surface-mount thin semiconductor devices is provided, and preferably a heat dissipation structure of a semiconductor device also with excellent insulating reliability is provided. In a heat dissipation structure | 2017-10-19 |
20170301603 | SEMICONDUCTOR DEVICE - A semiconductor device includes a base plate, a case, a power semiconductor element, and a control semiconductor element. Case is provided on base plate. Power semiconductor element is disposed over base plate in case. Control semiconductor element is disposed in case. Case has an opening formed therein opposite to base plate. The semiconductor device further includes a cover to close opening in case. Cover has a hole formed in at least a portion of a region overlapping control semiconductor element in plan view. | 2017-10-19 |
20170301604 | SEMICONDUCTOR DEVICE - A semiconductor device according to the present disclosure includes an electrically conductive first electrode block, an electrically conductive submount, an insulating layer, a semiconductor element, an electrically conductive bump, and an electrically conductive second electrode block. The submount is provided in a first region of the upper surface of the first electrode block, and electrically connected to the first electrode block. The semiconductor element is provided on the submount, and has a first electrode electrically connected to the submount. The bump is provided on the upper surface of a second electrode, opposite the first electrode, of the semiconductor element, and electrically connected to the second electrode. A third region of the lower surface of the second electrode block is electrically connected to the bump via an electrically conductive metal layer. An electrically conductive metal sheet is provided between the metal layer and the bump. | 2017-10-19 |
20170301605 | EMBEDDING DIAMOND AND OTHER CERAMIC MEDIA INTO METAL SUBSTRATES TO FORM THERMAL INTERFACE MATERIALS - A multi-layer structure includes a substrate with a surface and with particles partially covering and partially embedded in the surface. The particles have high thermal conductivity and low electrical conductivity. A dielectric layer on the surface partially covers the partially embedded particles. A metal layer on the dielectric layer covering the partially covered particles forms a thermal interface material (TIM) for electronic packaging applications. | 2017-10-19 |
20170301606 | BIDIRECTIONAL SEMICONDUCTOR PACKAGE - Provided is a bidirectional semiconductor package in which the number of processes for manufacturing the bidirectional semiconductor package is reduced. According to present application, a portion between one end and the other end of the buffer wire is in contact with the lower surface of the upper DBC substrate and heat generated by the semiconductor chip is transferred to the upper DBC substrate. | 2017-10-19 |
20170301607 | COOLING OF WIDE BANDGAP SEMICONDUCTOR DEVICES - A power device comprises at least one power semiconductor module comprising a wide bandgap semiconductor element; and a cooling system for actively cooling the wide bandgap semiconductor element with a cooling medium, wherein the cooling system comprises a refrigeration device for lowering a temperature of the cooling medium below an ambient temperature of the power device; wherein the cooling system is adapted for lowering the temperature of the cooling medium in such a way that a temperature of the wide bandgap semiconductor element is below 100° C. | 2017-10-19 |
20170301608 | Wafer Level Embedded Heat Spreader - Disclosed herein are a device having an embedded heat spreader and method for forming the same. A carrier substrate may comprise a carrier, an adhesive layer, a base film layer, and a seed layer. A patterned mask is formed with a heat spreader opening and via openings. Vias and a heat spreader may be formed in the pattern mask openings at the same time using a plating process and a die attached to the head spreader by a die attachment layer. A molding compound is applied over the die and heat spreader so that the heat spreader is disposed at the second side of the molded substrate. A first RDL may have a plurality of mounting pads and a plurality of conductive lines is formed on the molded substrate, the mounting pads may have a bond pitch greater than the bond pitch of the die contact pads. | 2017-10-19 |
20170301609 | POWER ELECTRONICS MODULE - A power electronics module is provided having one or more power converter semiconductor components. The power electronics module further has a substrate having a first surface to which the one or more components are mounted, and having an opposing second surface from which project a plurality of heat transfer formations for enhancing heat transfer from the substrate. The power electronics module further has a coolant housing which sealingly connects to the substrate to form a void over the heat transfer formations of the second surface. The coolant housing has an inlet for directing a flow of an electrically insulating coolant into the void and an outlet for removing the coolant flow from the void, whereby heat generated during operation of the one or more components is transferred into the coolant flow via the substrate. | 2017-10-19 |
20170301610 | COOLER MODULE, AND METHOD FOR MANUFACTURING COOLER MODULE - A cooler module has a cooling tube and a support member. The cooling tube has a first protruding tube portion and a second protruding tube portion. The first protruding tube portion is provided with a first flexible portion formed in an annular shape. The second protruding tube portion is provided with a second flexible portion formed in an annular shape. The support member has a first fitting portion fitted to the first protruding tube portion and a second fitting portion fitted to the second protruding tube portion. The support member supports a longitudinal center portion of the cooling tube on a condition that the first protruding tube portion and the first fitting portion are fitted together, the second protruding tube portion and the second fitting portion are fitted together, and the first flexible portion and the second flexible portion are recessed toward an inside of the cooling tube. | 2017-10-19 |
20170301611 | METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE COMPRISING A SEMICONDUCTOR DEVICE LAYER FORMED ON A TEMPORARY SUBSTRATE HAVING A GRADED SiGe ETCH STOP LAYER THERE BETWEEN - The present disclosure provides a semiconductor structure, including: a semiconductor device layer including a first surface and a second surface, wherein the first surface is at a front side of the semiconductor device layer, and the second surface is at a backside of the semiconductor device layer; an insulating layer above the second surface of the semiconductor device; and a through-silicon via (TSV) traversing the insulating layer. Associated manufacturing methods of the same are also provided. | 2017-10-19 |
20170301612 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a plurality of islands, each having an outer surface including an upper surface and end surfaces, semiconductor chips, above the respective islands, a bonding material, between the islands and the semiconductor chips, and plating layers, formed on the outer surfaces of the islands, and with at least one of the plurality of islands, the island is exposed as a bare surface region at a first end surface, which, among the end surfaces of the one island, faces the island adjacent thereto. | 2017-10-19 |
20170301613 | Adaptable Molded Leadframe Package and Related Method - A semiconductor package includes at least one semiconductor device situated on a leadframe island, a first at least one lead protruding from a first side of the semiconductor package and configured to provide a first electrical connection to at least one terminal of the at least one semiconductor device, a second at least one lead protruding from a second side of the semiconductor package and configured to provide a second electrical connection to the at least one terminal of the at least one semiconductor device, and a continuous conductive structure configured to provide a conductive path between the first at least one lead, the second at least one lead, and the at least one terminal of the at least one semiconductor device through the leadframe island such that the at least one semiconductor device continues to function after trimming the first at least one lead. | 2017-10-19 |
20170301614 | SEMICONDUCTOR MODULE - A semiconductor module of an electric power converter includes an IGBT and a MOSFET which are connected in parallel to each other and provided on the same lead frame, either one of the IGBT and the MOSFET is a first switching element and the remaining one is a second switching element, and the conduction path of the second switching element is disposed at a position that is separated from a conduction path of the first switching element in the same lead frame. | 2017-10-19 |
20170301615 | SEMICONDUCTOR DEVICE THAT INCLUDES A MOLECULAR BONDING LAYER FOR BONDING OF ELEMENTS - A semiconductor device includes a semiconductor chip having a terminal thereon, a lead frame for connection to an external device, a bonding wire connecting the terminal of the semiconductor chip and the lead frame. A mold resin layer encloses the semiconductor chip and the bonding wire, such that a portion of the lead frame extends out of the mold resin layer. A molecular bonding layer has a portion on a surface of the bonding wire and includes a first molecular portion covalently bonded to a material of the bonding wire and a material of the mold resin layer. | 2017-10-19 |
20170301616 | Body-Mountable Device with a Common Substrate for Electronics and Battery - An example device includes a silicon substrate having a first substrate surface and a second substrate surface; a plurality of layers associated with one or more electronic components of an integrated circuit (IC), where the plurality of layers are deposited on the second substrate surface; a lithium-based battery having a plurality of battery layers deposited on the first substrate surface of the silicon substrate, where the lithium-based battery includes an anode current collector and a cathode current collector; a first through-silicon via (TSV) passing through the silicon substrate and providing an electrical connection between the anode current collector and the plurality of layers associated with the one or more electronic components of the IC; and a second TSV passing through the silicon substrate and providing an electrical connection between the cathode current collector and the plurality of layers associated with the one or more electronic components of the IC. | 2017-10-19 |
20170301617 | LEADFRAME SUBSTRATE WITH ISOLATOR INCORPORATED THEREIN AND SEMICONDUCTOR ASSEMBLY AND MANUFACTURING METHOD THEREOF - The leadframe substrate includes an isolator incorporated with metal leads by a compound layer. The metal leads are disposed about sidewalls of the isolator and provide horizontal and vertical routing for a semiconductor device to be assembled on the isolator. The compound layer covers the sidewalls of the isolator and fills in spaces between the metal leads, and provides robust mechanical bonds between the metal leads and the isolator. | 2017-10-19 |
20170301618 | Advanced Metal Connection With Metal Cut - Examples of an integrated circuit a having an advanced two-dimensional (2D) metal connection with metal cut and methods of fabricating the same are provided. An example method for fabricating a conductive interconnection layer of an integrated circuit may include: patterning a conductive connector portion on the conductive interconnection layer of the integrated circuit using extreme ultraviolet (EUV) lithography, wherein the conductive connector portion is patterned to extend across multiple semiconductor structures in a different layer of the integrated circuit; and cutting the conductive connector portion into a plurality of conductive connector sections, wherein the conductive connector portion is cut by removing conductive material from the metal connector portion at one or more locations between the semiconductor structures. | 2017-10-19 |
20170301619 | INTEGRATED CIRCUIT SURFACE LAYER WITH ADHESION-FUNCTIONAL GROUP - Embodiments of the present disclosure describe an integrated circuit and associated fabrication techniques and configurations, which may include forming on at least one of a metal layer or a polymer layer of an integrated circuit die a surface layer that includes an adhesion-functional group, and applying to the surface layer a next layer to adhere to the surface layer with the adhesion-functional group. In embodiments wherein the at least one of the metal layer or the polymer layer is a polymer layer, forming the surface layer may include copolymerizing on the polymer layer a polar monomer that includes the adhesion-functional group. In embodiments wherein the at least one of the metal layer or the polymer layer is a metal layer, forming the surface layer may include forming on the metal layer a self-assembled monolayer that includes amine group terminations. Other embodiments may be described and/or claimed. | 2017-10-19 |
20170301620 | STRUCTURE AND PROCESS FOR METAL CAP INTEGRATION - The disclosure relates to semiconductor interconnect structure having enhanced electromigration (EM) reliability in which an oxygen scavenger layer deposited (directly or indirectly) over a surface of conductive material. In one embodiment, the disclosure relates to semiconductor structure having a substrate having a cavity formed therein; a barrier material lining a portion of the cavity; a conductive material formed over the barrier material, the conductive material defining an interconnect layer; a metal cap formed over at least a portion of the conductive material; an oxygen scavenger layer formed over the metal cap layer, the oxygen scavenger layer comprising one or more of Al, TiAl or Al alloys, Mg, TiMg, Mg alloys, and deposited over the metal cap layer using one or more of a Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Electroless Plating Deposition (ELD) electrodeless deposition techniques; wherein the oxygen scavenger layer removes oxygen from the interface between the conductive material surface and the metal cap layer. | 2017-10-19 |
20170301621 | AIRGAP PROTECTION LAYER FOR VIA ALIGNMENT - A method for via alignment includes forming first airgaps between interconnect structures and depositing a pinch off layer to close off openings to the first airgaps. A protection layer is formed in divots in the pinch off layer. The protection layer and the pinch off layer are planarized to form a surface where the protection layer remains in the divots. An interlevel dielectric layer (ILD) is deposited on the surface. The ILD and the pinch off layer are etched using the protection layer as an etch stop to align a via and expose the interconnect structure through the via. | 2017-10-19 |
20170301622 | III-V COMPATIBLE ANTI-FUSES - An anti-fuse is provided above a semiconductor material. The anti-fuse includes a first end region including a first metal structure; a second end region including a second metal structure; and a middle region located between the first end region and the second end region. In accordance with the present application, the middle region of the anti-fuse includes at least a portion of the second metal structure that is located in a gap positioned between a bottom III-V compound semiconductor material and a top III-V compound semiconductor material. A high-k dielectric material liner separates the second metal structure from a portion of the first metal structure. | 2017-10-19 |
20170301623 | STACK OF LAYERS FOR PROTECTING AGAINST A PREMATURE BREAKDOWN OF INTERLINE POROUS DIELECTRICS WITHIN AN INTEGRATED CIRCUIT - A stack including a dual-passivation is etched locally so as to reveal contact pads of an integrated circuit which are situated above a last metallization level of an interconnection part of the integrated circuit. This stack serves to protect the integrated circuit against a breakdown of at least one dielectric region, at least in part porous, separating two electrically conducting elements of the interconnection part of the integrated circuit. Such a breakdown may occur due to electrical conduction assisted by the presence of defects within the at least one dielectric region. | 2017-10-19 |
20170301624 | SELECTIVE AND NON-SELECTIVE BARRIER LAYER WET REMOVAL - A method for manufacturing a semiconductor device includes forming a dielectric layer on a substrate, forming a plurality of openings in the dielectric layer, conformally depositing a barrier layer on the dielectric layer and on sides and a bottom of each one of the plurality of openings, depositing a contact layer on the barrier layer in each one of the plurality of openings, removing a portion of each contact layer from each one of the plurality of openings, and removing a portion of the barrier layer from each one of the plurality of openings, wherein at least the removal of the portion of the barrier layer is performed using an etchant including: (a) a compound selected from group consisting of -azole, -triazole, and combinations thereof; (b) a compound containing one or more peroxy groups; (c) one or more alkaline metal hydroxides; and (d) water. | 2017-10-19 |
20170301625 | INTEGRATED CIRCUIT PACKAGE WITH EMBEDDED BRIDGE - Embodiments of the present disclosure are directed towards an integrated circuit (IC) package having first and second dies with first and second input/output (I/O) interconnect structures, respectively. The IC package may include a bridge having first and second electrical routing features coupled to a portion of the first and second I/O interconnect structures, respectively. In embodiments, the first and second electrical routing features may be disposed on one side of the bridge; and third electrical routing features may be disposed on an opposite side. The first and second electrical routing features may be configured to route electrical signals between the first die and the second die and the third electrical routing features may be configured to route electrical signals between the one side and the opposite side. The first die, the second die, and the bridge may be embedded in electrically insulating material. Other embodiments may be described and/or claimed. | 2017-10-19 |
20170301626 | EMBEDDED COMPONENT PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME - An embedded component package structure includes a substrate. A first conductive component extends from a first surface of the substrate to a second surface of the substrate, a first conductive layer is disposed on the first surface of the substrate, and a second conductive layer is disposed on the second surface of the substrate and is electrically connected to the first conductive layer by the first conductive component. A die is disposed in a through hole in the substrate. A back surface of the die is exposed from the second surface of the substrate. A first dielectric layer covers an active surface of the die and the first surface of the substrate. A third conductive layer is disposed on the first dielectric layer and is electrically connected to the die by a second conductive component. A first metal layer is disposed directly on the back surface of the die. | 2017-10-19 |
20170301627 | LINE STRUCTURE AND A METHOD FOR PRODUCING THE SAME - A multi-layer line structure including a substrate, a lower layer Cu line located on the substrate, an upper layer Cu line located on an insulating layer including an inorganic film located on the lower layer Cu line and an organic resin film located on the inorganic film, and a via connection part located in a via connection hole running in an up-down direction through the insulating layer in an area where the lower layer Cu line and the upper layer Cu line overlap each other is provided. The via connection part includes a barrier conductive layer located on a part of the lower layer Cu line exposed to a bottom part of the via connection hole and on an inner wall of the via connection hole. | 2017-10-19 |
20170301628 | ELECTRONIC CIRCUIT PACKAGE - Disclosed herein is an electronic circuit package includes: a substrate having a power supply pattern; an electronic component mounted on a surface of the substrate; a mold resin covering the surface of the substrate so as to embed therein the electronic component; a laminated structure of a magnetic film and a metal film, the laminated structure covering at least an upper surface of the molding resin. The metal film is connected to the power supply pattern, and a resistance value at an interface between the magnetic film and the metal film is equal to or larger than 10 | 2017-10-19 |
20170301629 | SEMICONDUCTOR PACKAGE HAVING A METAL PAINT LAYER - Disclosed are devices and methods related to a conductive paint layer configured to provide radio-frequency (RF) shielding for a packaged semiconductor module. Such a module can include a packaging substrate, one or more RF components mounted on the packaging substrate, a ground plane disposed within the packaging substrate, and a plurality of RF-shielding wirebonds disposed on the packaging substrate and electrically connected to the ground plane. The module can further include an overmold structure formed over the packaging substrate and dimensioned to substantially encapsulate the RF component(s) and the RF-shielding wirebonds. The overmold structure can define an upper surface that exposes upper portions of the RF-shielding wirebonds. The module can further include a conductive paint layer having silver flakes disposed on the upper surface of the overmold structure so that the conductive paint layer, the RF-shielding wirebonds, and the ground plane form an RF-shield for the RF component(s). | 2017-10-19 |
20170301630 | METHODS FOR SELECTIVELY SHIELDING RADIO FREQUENCY MODULES - Aspects of this disclosure relate to methods of selectively shielded radio frequency modules. A radio frequency module can be provided with a radio frequency component and an antenna. A shielding layer can be formed over a portion of the radio frequency module such that the radio frequency component is shielded by the shielding layer and the antenna is unshielded by the shielding layer. | 2017-10-19 |
20170301631 | VERTICAL INTERCONNECTS FOR SELF SHIELDED SYSTEM IN PACKAGE (SiP) MODULES - A system in package (SiP) is disclosed that uses an EMI shield to inhibit EMI or other electrical interference on the components within the SiP. A metal shield may be formed on an upper surface of an encapsulant encapsulating the SiP. The metal shield may be electrically coupled to a ground layer in a printed circuit board (PCB) to form the EMI shield around the SiP. The metal shield may be electrically coupled to the ground layer using one or more conductive structures located in the encapsulant. The conductive structures may be located on a perimeter of the components in the SiP. The conductive structures may provide a substantially vertical connection between the substrate and the shield on the upper surface of the encapsulant. | 2017-10-19 |
20170301632 | PACKAGE AND METHOD OF MANUFACTURING THE SAME - The method of manufacturing a package comprising: preparing a strip substrate having a plurality of separate package regions which are partitioned by a dicing region and via pads which are connected to one ends of plated tails which are divided to be disconnected in the dicing region; mounting at least one electronic component on at least one surface of each package region of the substrate; forming a connection pattern having conductivity in disconnected portions of the plated tails to form electrical connections therebetween; forming a molded part on the surface of the substrate to enclose the electronic component; forming at least one via penetrating through the molded part by applying current through the plated tails; and dicing the substrate in the dicing region to divide the substrate into separate packages, each having the connection pattern exposed to the exterior of the substrate. | 2017-10-19 |
20170301633 | Power Module and Power Conversion Apparatus - An object of the present invention is to provide a power module that secures a heat dissipation route and has increased reliability. A power module of the present invention includes a first circuit body having a first semiconductor element and a first conductor portion, a second circuit body having a second semiconductor element and a second conductor portion, a resin sealing material for sealing the first circuit body and the second circuit body, and a warpage suppression portion that is formed along an array direction of the first circuit body and the second circuit body and is formed to have greater rigidity than a sealing portion of the resin sealing material, wherein the warpage suppression portion is formed of the same material as a resin member of the resin sealing material and is formed to be thicker than the sealing portion of the resin sealing material. | 2017-10-19 |
20170301634 | SEMICONDUCTOR APPARATUS WITH FAKE FUNCTIONALITY - A semiconductor apparatus with fake functionality includes a logic device and at least one fake device. The logic device is formed on a substrate and turned on by a bias voltage. The fake device is also formed on the substrate. The fake device cannot be turned on by the same bias voltage applied on the logic device. | 2017-10-19 |