42nd week of 2017 patent applcation highlights part 61 |
Patent application number | Title | Published |
20170301735 | CHARGE INTEGRATING DEVICES AND RELATED SYSTEMS - An organic charge integrating device is presented. The organic charge integrating device includes a thin film transistor (TFT) array, a first electrode layer disposed on the TFT array, an organic photoactive layer disposed on the first electrode layer, and a second electrode layer disposed on the organic photoactive layer. The organic photoactive layer has a thickness in a range from about 700 nanometers to about 3 microns. An organic x-ray detector is presented. An imaging system including the organic x-ray detector is also presented. | 2017-10-19 |
20170301736 | DISPLAY DEVICE AND FABRICATION METHOD THEREOF - A display device and fabrication method thereof are provided. The display device includes an encapsulation film encapsulating a thin film transistor array and a pixel array on a base substrate; a protection film on the encapsulation film and including a first retardation film; a touch film on the protection film and including a second retardation film; and a polarizer film on the touch | 2017-10-19 |
20170301737 | SUBPIXEL ARRANGEMENTS OF DISPLAYS AND METHOD FOR RENDERING THE SAME - An apparatus including a display and control logic is provided. In one example, the display includes an array of subpixels having a plurality of zigzag subpixel groups. Each zigzag subpixel group includes at least three zigzag subpixel units arranged adjacently along a horizontal or vertical direction. Each zigzag subpixel unit includes a plurality of subpixels of the same color arranged in a zigzag pattern. In each zigzag subpixel unit, a first plurality of subpixels are arranged along one diagonal direction from a turning subpixel disposed at a turning corner of the zigzag pattern, and a second plurality of subpixels are arranged along another diagonal direction from the turning subpixel. In another example, the display includes an array of subpixels having a novel subpixel repeating group. The control logic is operatively coupled to the display and configured to receive display data and render the display data into control signals for driving the display. | 2017-10-19 |
20170301738 | P-TYPE OXIDE SEMICONDUCTOR, COMPOSITION FOR PRODUCING P-TYPE OXIDE SEMICONDUCTOR, METHOD FOR PRODUCING P-TYPE OXIDE SEMICONDUCTOR, SEMICONDUCTOR ELEMENT, DISPLAY ELEMENT, IMAGE DISPLAY DEVICE, AND SYSTEM - A p-type oxide semiconductor, which contains: a metal oxide containing thallium (Tl), where the metal oxide has been hole doped. | 2017-10-19 |
20170301739 | ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE - An organic light emitting device includes a first substrate including a display area and a non-display area, and a dummy metal layer disposed o the first substrate in the non-display area. The dummy metal layer includes a first dummy metal layer and a second dummy metal layer that overlap each other. The organic light emitting device further includes an insulating layer disposed between the first dummy metal layer and the second dummy metal layer in a cross-sectional view, a second substrate covering the first substrate, and a sealant disposed between the first substrate and the second substrate and overlapping the dummy metal layer. The first dummy metal layer is electrically connected to the second dummy metal layer, and the sealant contacts the second dummy metal layer. | 2017-10-19 |
20170301740 | METHOD FOR MANUFACTURING ORGANIC EL DISPLAY PANEL - Forming functional layers including functional material in application regions by applying ink to the application regions then drying the ink, which contains the functional material, by causing nozzles to be scanned relative to the substrate along the row direction while, among the nozzles, only use-nozzles that are not selected as a defective nozzle eject the ink, the nozzles being arranged in the column direction over the substrate and including a nozzle selected in advance as a defective nozzle. Among the nozzles, when applying the ink, at least one reserve nozzle is present, a reserve nozzle being a nozzle that is not one of the use-nozzles, is not selected as the defective nozzle, passes over the application region, and does not eject the ink. | 2017-10-19 |
20170301741 | TEST ELEMENT GROUP, METHOD OF TESTING ELECTRICAL CHARACTERISTICS OF SEMICONDUCTOR ELEMENTS, AND FABRICATING METHOD THEREOF - The present application discloses an array substrate having a plurality of semiconductor elements and a plurality of test electrodes. Each of the plurality of semiconductor elements comprises a plurality of terminals, each of which is electrically connected to a different test electrode. At least one of the plurality of test electrodes is electrically connected to at least two different semiconductor elements. | 2017-10-19 |
20170301742 | ORGANIC LIGHT-EMITTING DIODE DISPLAY - An organic light-emitting diode (OLED) display is disclosed. In one aspect, the display includes a stretchable substrate, a unit pixel over the stretchable substrate and including a plurality of emission layers emitting red light, green light, and blue light separately, and a plurality of interconnection lines connected to a corner portion of the unit pixel. The unit pixel has at least four corners, and the interconnection lines are respectively connected to the four corners. | 2017-10-19 |
20170301743 | ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING ORGANIC LIGHT EMITTING DISPLAY DEVICE - An organic light emitting display device includes a substrate, a buffer layer, an active layer, a gate insulation layer, a protective insulating layer, a gate electrode, an insulating interlayer, source and drain electrodes, and a sub-pixel structure. The buffer layer is disposed on the substrate. The active layer is disposed on the buffer layer, and has a source region, a drain region, and a channel region. The gate insulation layer is disposed in the channel region on the active layer. The protective insulating layer is disposed on the buffer layer, the source and drain regions of the active layer, and the gate insulation layer. The gate electrode is disposed in the channel region on the protective insulating layer. The insulating interlayer is disposed on the gate electrode. The source and drain electrodes are disposed on the insulating interlayer. | 2017-10-19 |
20170301744 | DISPLAY PANEL - A display panel includes a substrate, a plurality of first electrode series, a plurality of first electrode series and a plurality of conducting wires. The substrate is divided into a first display area and a second display area. The first display area and the second display area are respectively divided into light emitting zones and interval zones. The first electrode series are disposed in the first display area and the second display area. The second electrode series are disposed in the first display area and the second display area. Each first electrode series extends along a first direction. Each second electrode series extends along a second direction. The connection portion of each first electrode series extends into the interval zone of the first display area. The conducting wires are respectively coupled to the second electrode series in the first display area. | 2017-10-19 |
20170301745 | METAL RESISTORS HAVING VARYING RESISTIVITY - A semiconductor structure is provided that includes a first metal resistor structure located on a portion of a dielectric-containing substrate. The first metal resistor structure includes, from bottom to top, a first nitridized dielectric surface layer portion having a first nitrogen content, a first metal portion, and a first dielectric capping layer portion. The semiconductor structure of the present application further includes a second metal resistor structure located on a second portion of the dielectric-containing substrate and spaced apart from the first metal resistor structure. The second metal resistor structure includes, from bottom to top, a second nitridized dielectric surface layer portion having a second nitrogen content that differs from the first nitrogen content, a second metal portion, and a second dielectric capping layer portion. | 2017-10-19 |
20170301746 | METAL RESISTORS HAVING NITRIDIZED DIELECTRIC SURFACE LAYERS AND NITRIDIZED METAL SURFACE LAYERS - A semiconductor structure containing at least two metal resistor structures having different resistivities is provided and includes a first metal resistor structure located on a portion of a dielectric-containing substrate. The first metal resistor structure includes, from bottom to top, a first nitridized dielectric surface layer portion having a first nitrogen content, a first metal layer portion and a first nitridized metal surface layer. A second metal resistor structure is located on a second portion of the dielectric-containing substrate and spaced apart from the first metal resistor structure. The second metal resistor structure includes, from bottom to top, a second nitridized dielectric surface layer portion having a second nitrogen content, a second metal layer portion and a second nitridized metal surface layer. The second nitrogen content of the second nitridized dielectric surface layer portion differs from the first nitrogen content of the first nitridized dielectric surface layer portion. | 2017-10-19 |
20170301747 | METAL RESISTORS HAVING NITRIDIZED METAL SURFACE LAYERS WITH DIFFERENT NITROGEN CONTENT - A semiconductor structure containing at least two metal resistor structures having different amounts of nitrogen on the resistor surface is provided. The resulted resistances (and hence resisitivty) of the two metal resistors can be either the same or different. The semiconductor structure may include a first metal resistor structure located on a portion of a dielectric-containing substrate. The first metal resistor structure includes, from bottom to top, a first metal layer portion and a first nitridized metal surface layer having a first nitrogen content. The semiconductor structure further includes a second metal resistor structure located on a second portion of the dielectric-containing substrate and spaced apart from the first metal resistor structure. The second metal resistor structure includes, from bottom to top, a second metal layer portion and a second nitridized metal surface layer having a second nitrogen content that differs from the first nitrogen content. | 2017-10-19 |
20170301748 | DEVICES, SYSTEMS, AND METHODS FOR ION TRAPPING - Devices, methods, and systems for ion trapping are described herein. One device includes a through-silicon via (TSV) and a trench capacitor formed around the TSV. | 2017-10-19 |
20170301749 | HIGH-DENSITY MIM CAPACITORS - Capacitors and methods of forming the same include forming a gap in a dielectric layer underneath one or more conducting lines, such that the one or more conducting lines are suspended over the gap. A capacitor stack is deposited in the gap and on the conducting lines. Respective contacts are deposited on the conducting lines and on the capacitor stack. | 2017-10-19 |
20170301750 | MEMORY DEVICES INCLUDING CAPACITOR STRUCTURES HAVING IMPROVED AREA EFFICIENCY - Semiconductor structures including a plurality of conductive structures having a dielectric material therebetween are disclosed. The thickness of the dielectric material spacing apart the conductive structures may be adjusted to provide optimization of capacitance and voltage threshold. The semiconductor structures may be used as capacitors, for example, in memory devices. Various methods may be used to form such semiconductor structures and capacitors including such semiconductor structures. Memory devices including such capacitors are also disclosed. | 2017-10-19 |
20170301751 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: a first conductivity type drift region having crystal defects generated by electron-beam irradiation; a first main electrode region of a first conductivity type arranged in the drift region and having an impurity concentration higher than that of the drift region; and a second main electrode region of a second conductivity type arranged in the drift region to be separated from the first main electrode region, wherein the crystal defects contain a first composite defect implemented by a vacancy and oxygen and a second composite defect implemented by carbon and oxygen, and a density of the crystal defects is set so that a peak signal intensity of a level of the first composite defect identified by a deep-level transient spectroscopy measurement is five times or more than a peak signal intensity of a level of the second composite defect. | 2017-10-19 |
20170301752 | Vertical Semiconductor Structure - A diode includes upper and lower electrodes and first and second N-type doped semiconductor substrate portions connected to the lower electrode. A first vertical transistor and a second transistor are formed in the first portion and series-connected between the electrodes. The gate of the first transistor is N-type doped and coupled to the upper electrode. The second transistor has a P channel and has a P-type doped gate. First and second doped areas of the second conductivity type are located in the second portion and are separated by a substrate portion topped with another N-type doped gate. The first doped area is coupled to the gate of the second transistor. The second doped area and the other gate are coupled to the upper electrode. | 2017-10-19 |
20170301753 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate in which an active region and an edge termination region are defined, a semiconductor element formed in the active region, and first to fourth P layers formed in a region spanning from an edge portion of the active region to the edge termination region in the surface of the semiconductor substrate. The first to fourth P layers respectively have surface concentrations P( | 2017-10-19 |
20170301754 | ISOLATED WELL CONTACT IN SEMICONDUCTOR DEVICES - An integrated circuit and method has an isolated well with an improved isolated well contact. The well contact diffusion is isolated from a device diffusion of opposite conductivity type within the isolated well by an isolation transistor gate. | 2017-10-19 |
20170301755 | LATERAL BIPOLAR JUNCTION TRANSISTOR WITH ABRUPT JUNCTION AND COMPOUND BURIED OXIDE - A lateral bipolar junction transistor (LBJT) device that may include a dielectric stack including a pedestal of a base region passivating dielectric and a nucleation dielectric layer; and a base region composed of a germanium containing material or a type III-V semiconductor material in contact with the pedestal of the base region passivating dielectric. An emitter region and collector region may be present on opposing sides of the base region contacting a sidewall of the pedestal of the base region passivating dielectric and an upper surface of the nucleation dielectric layer. | 2017-10-19 |
20170301756 | LATERAL BIPOLAR JUNCTION TRANSISTOR WITH ABRUPT JUNCTION AND COMPOUND BURIED OXIDE - A lateral bipolar junction transistor (LBJT) device that may include a dielectric stack including a pedestal of a base region passivating dielectric and a nucleation dielectric layer; and a base region composed of a germanium containing material or a type III-V semiconductor material in contact with the pedestal of the base region passivating dielectric. An emitter region and collector region may be present on opposing sides of the base region contacting a sidewall of the pedestal of the base region passivating dielectric and an upper surface of the nucleation dielectric layer. | 2017-10-19 |
20170301757 | SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE AND REPLACEMENT METAL GATE STRUCTURE AND RELATED METHODS - A semiconductor device may include a substrate having a channel recess therein, a plurality of spaced apart shallow trench isolation (STI) regions in the substrate, and source and drain regions spaced apart in the substrate and between a pair of the STI regions. A superlattice channel may be in the channel recess of the substrate and extend between the source and drain regions, with the superlattice channel including a plurality of stacked group of layers, and each group of layers of the superlattice channel including stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A replacement gate may be over the superlattice channel. | 2017-10-19 |
20170301758 | STACKED BODY AND ELECTRONIC DEVICE - A stacked body includes: a substrate made of silicon carbide and having a first main surface forming an angle of 20° or less with a silicon plane; and a graphene film disposed on the first main surface and having an atomic arrangement oriented in relation to an atomic arrangement of silicon carbide forming the substrate. In an exposed surface of the graphene film which is a main surface opposite to the substrate, an area ratio of a region having a full width at half maximum of G′ of 40 cm | 2017-10-19 |
20170301759 | STACKED BODY AND ELECTRONIC DEVICE - A stacked body includes: a substrate made of silicon carbide and having a first main surface forming an angle of 20° or less with a carbon plane; and a graphene film disposed on the first main surface and having an atomic arrangement oriented in relation to an atomic arrangement of silicon carbide forming the substrate. In an exposed surface of the graphene film as seen in plan view, 10 or less regions are present per 1 mm | 2017-10-19 |
20170301760 | SEMICONDUCTOR DEVICE, INVERTER CIRCUIT, AND VEHICLE - A semiconductor device according to embodiments described herein includes a p-type SiC layer, a gate electrode, and a gate insulating layer between the SiC layer and the gate electrode. The gate insulating layer includes a first layer, a second layer, a first region, and a second region. The second layer is between the first layer and the gate electrode and has a higher oxygen density than the first layer. The first region is provided across the first layer and the second layer, includes a first element from F, D, and H, and has a first concentration peak of the first element. The second region is provided in the first layer, includes a second element from Ge, B, Al, Ga, In, Be, Mg, Ca, Sr, Ba, Sc, Y, La, and lanthanoid, and has a second concentration peak of the second element and a third concentration peak of C. | 2017-10-19 |
20170301761 | GaN SEMICONDUCTOR DEVICE COMPRISING CARBON AND IRON - A semiconductor device includes: a substrate; a first GaN layer on the substrate and containing carbon; a second GaN layer on the first GaN layer and containing transition metal and carbon; a third GaN layer on the second GaN layer and containing transition metal and carbon; and an electron supply layer on the third GaN layer and having a larger band gap than GaN. A transition metal concentration of the third GaN layer gradually decreases from that of the second GaN layer from the second GaN layer toward the electron supply layer and is higher than 1×10 | 2017-10-19 |
20170301762 | FinFET with Trench Field Plate - An integrated circuit device includes a pad layer having a body portion with a first doping type laterally adjacent to a drift region portion with a second doping type, a trench formed in the pad layer, the trench extending through an interface of the body portion and the drift region portion, a gate formed in the trench and over a top surface of the pad layer along the interface of the body portion and the drift region portion, an oxide formed in the trench on opposing sides of the gate, and a field plate embedded in the oxide on each of the opposing sides of the gate. | 2017-10-19 |
20170301763 | Power Semiconductor Device Trench Having Field Plate and Gate Electrode - A method of processing a power semiconductor device includes: providing a semiconductor body with a trench extending into the semiconductor body along an extension direction and including an insulator; providing a monolithic electrode zone within the trench; and removing a section of the monolithic electrode zone within the trench to divide the monolithic electrode zone into at least a first electrode structure and a second electrode structure arranged separately and electrically insulated from each other. | 2017-10-19 |
20170301764 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device with a high radiation tolerance is provided. A semiconductor device comprising a semiconductor substrate, a first body region and a second body region provided on a front surface side of the semiconductor substrate, a neck portion provided between the first body region and the second body region, a first source region formed within the first body region and a second source region formed within the second body region, a first gate electrode provided to face the first body region between the first source region and the neck portion, a second gate electrode provided to face the second body region between the second source region and the neck portion, and an insulating film continuously provided between the first gate electrode and the semiconductor substrate, between the second gate electrode and the semiconductor substrate, and on the front surface side of the neck portion, is provided. | 2017-10-19 |
20170301765 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a semiconductor device, a gate insulating film is provided with a multi-layer structure including a first insulating film and a second insulating film. The first insulating film is formed of an insulating film containing an element having an oxygen binding force larger than that of an element contained in the second insulating film, and the total charge amount is increased. Specifically, by performing oxygen anneal, it is possible to perform the step of supplying oxygen into an aluminum oxide film and increase the total charge amount. This allows a negative fixed charge density in the gate insulating film in the vicinity of an interface with a GaN layer to be set to a value of not less than 2.5×10 | 2017-10-19 |
20170301766 | COMPOUND SEMICONDUCTOR FIELD EFFECT TRANSISTOR - A connection portion ( | 2017-10-19 |
20170301767 | HYBRID SOURCE AND DRAIN CONTACT FORMATION USING METAL LINER AND METAL INSULATOR SEMICONDUCTOR CONTACTS - An electrical device including a first semiconductor device having a silicon and germanium containing source and drain region, and a second semiconductor device having a silicon containing source and drain region. A first device contact to at least one of said silicon and germanium containing source and drain region of the first semiconductor device including a metal liner of an aluminum titanium and silicon alloy and a first tungsten fill. A second device contact is in contact with at least one of the silicon containing source and drain region of the second semiconductor device including a material stack of a titanium oxide layer and a titanium layer. The second device contact may further include a second tungsten fill. | 2017-10-19 |
20170301768 | N-Work Function Metal with Crystal Structure - A method includes forming a dummy gate stack over a semiconductor substrate, wherein the semiconductor substrate is comprised in a wafer. The method further includes removing the dummy gate stack to form a recess, forming a gate dielectric layer in the recess, and forming a metal layer in the recess and over the gate dielectric layer. The metal layer has an n-work function. A portion of the metal layer has a crystalline structure. The method further includes filling a remaining portion of the recess with metallic materials, wherein the metallic materials are overlying the metal layer. | 2017-10-19 |
20170301769 | Semiconductor Device and Method of Manufacturing the Semiconductor Device - In a semiconductor device, a first interlayer insulating layer made of an inorganic material and formed on inverse stagger type TFTs, a second interlayer insulating layer made of an organic material and formed on the first interlayer insulating layer, and a pixel electrode formed in contact with the second interlayer insulating layer are disposed on a substrate, and an input terminal portion that is electrically connected to a wiring of another substrate is provided on an end portion of the substrate. The input terminal portion includes a first layer made of the same material as that of the gate electrode and a second layer made of the same material as that of the pixel electrode. With this structure, the number of photomasks used in the photolithography method can be reduced to 5. | 2017-10-19 |
20170301770 | STRESS RETENTION IN FINS OF FIN FIELD-EFFECT TRANSISTORS - Embodiments of the present invention provide a structure and method of minimizing stress relaxation during fin formation. Embodiments may involve forming a looped spacer on an upper surface of a substrate and adjacent to at least a sidewall of a mandrel. The mandrel may be removed, leaving the looped spacer on the substrate. An exposed portion of the substrate may be removed to form a looped fin below the looped spacer. The spacer may be removed, leaving a looped fin. A looped fin formation may reduce stress relaxation compared to conventional fin formation methods. Embodiments may include forming a gate over a looped portion of a looped fin. Securing a looped portion in position with a gate may decrease stress relaxation in the fin. Thus, a looped fin with a looped portion of the looped fin under a gate may have substantially reduced stress relaxation compared to a conventional fin. | 2017-10-19 |
20170301771 | TRENCH SCHOTTKY RECTIFIER DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for fabricating a trench Schottky rectifier device is provided. At first, a plurality of trenched are formed in a substrate of a first conductivity type. An insulating layer is formed on sidewalls of the trenches. Then, an ion implantation procedure is performed through the trenches to form a plurality of doped regions of a second conductivity type under the trenches. Subsequently, the trenches are filled with conductive structure such as metal structure or tungsten structure. At last, an electrode overlying the conductive structure and the substrate is formed. Thus, a Schottky contact appears between the electrode and the substrate. Each doped region and the substrate will form a PN junction to pinch off current flowing toward the Schottky contact to suppress the current leakage in a reverse bias mode. | 2017-10-19 |
20170301772 | GaN DEVICES FABRICATED VIA WAFER BONDING - A wafer bonding technique to fabricate GaN devices is disclosed. In this technique, a GaN layer (or a GaN stack including at least one GaN layer) is fabricated on a first substrate (e.g., a silicon substrate) and has a high quality surface with a dislocation density less than 10 | 2017-10-19 |
20170301773 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided is a semiconductor device including a substrate with an active pattern, a gate electrode crossing the active pattern, and a gate capping pattern on the gate electrode. The gate capping pattern may have a width larger than that of the gate electrode, and the gate capping pattern may include extended portions extending toward the substrate and at least partially covering both sidewalls of the gate electrode. | 2017-10-19 |
20170301774 | METHODS TO ENHANCE EFFECTIVE WORK FUNCTION OF MID-GAP METAL BY INCORPORATING OXYGEN AND HYDROGEN AT A LOW THERMAL BUDGET - A process is disclosed of forming metal replacement gates for PMOS transistors with oxygen in the metal gates such that the PMOS gates have effective work functions above 4.85. Metal work function layers in the PMOS gates are oxidized at low temperature to increase their effective work functions to the desired PMOS range. Hydrogen may also be incorporated at an interface between the metal gates and underlying gate dielectrics. Materials for the metal work function layers and processes for the low temperature oxidation are disclosed. | 2017-10-19 |
20170301775 | SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF - A semiconductor arrangement and method of formation are provided. The semiconductor arrangement comprises a conductive contact in contact with a substantially planar first top surface of a first active area, the contact between and in contact with a first alignment spacer and a second alignment spacer both having substantially vertical outer surfaces. The contact formed between the first alignment spacer and the second alignment spacer has a more desired contact shape then a contact formed between alignment spacers that do not have substantially vertical outer surfaces. The substantially planar surface of the first active area is indicative of a substantially undamaged structure of the first active area as compared to an active area that is not substantially planar. The substantially undamaged first active area has a greater contact area for the contact and a lower contact resistance as compared to a damaged first active area. | 2017-10-19 |
20170301776 | METHODS OF FORMING A GATE STRUCTURE ON A VERTICAL TRANSISTOR DEVICE - One illustrative method disclosed herein includes forming a multi-layered sidewall spacer (MLSS) around a vertically oriented channel semiconductor structure, wherein the MLSS comprises a non-sacrificial innermost first spacer (a high-k insulating material), a sacrificial outermost spacer and at least one non-sacrificial second spacer (a metal-containing material) positioned between the innermost spacer and the outermost spacer, removing at least a portion of the sacrificial outermost spacer from the MLSS while leaving the at least one non-sacrificial second spacer and the non-sacrificial innermost first spacer in position and forming a final conductive gate electrode in place of the removed sacrificial outermost spacer. | 2017-10-19 |
20170301777 | FABRICATION METHOD OF THIN FILM TRANSISTOR, FABRICATION METHOD OF ARRAY SUBSTRATE, DISPLAY PANEL, AND DISPLAY DEVICE - A fabrication method of a thin film transistor, a fabrication method of an array substrate, a display panel, and a display device are provided. The fabrication method of the thin film transistor comprises: forming a gate electrode, a gate insulating layer and an oxide active layer; forming an inverted trapezoidal dissolution layer whose cross section is inverted trapezoidal on the oxide active layer, the inverted trapezoidal dissolution layer being soluble in an organic solvent; forming a source/drain layer on the oxide active layer, the gate insulating layer and the inverted trapezoidal dissolution layer, a thickness of the inverted trapezoidal dissolution layer being greater than a thickness of the source/drain layer; and dissolving and removing the inverted trapezoidal dissolution layer with the organic solvent and removing the source/drain layer on the inverted trapezoidal dissolution layer, to form a source electrode and a drain electrode. | 2017-10-19 |
20170301778 | SPIN CONTROL ELECTRONIC DEVICE OPERABLE AT ROOM TEMPERATURE - A spin control electronic device operable at room temperature according to an embodiment of the present invention includes a transfer channel that includes a low-dimensional nanostructure, the nanostructure being located on a substrate, having an elongate shape in a first direction and having a cross section, cut along a second direction that is perpendicular to the first direction, in the shape of a triangle; a source electrode located on the substrate and intersecting the transfer channel, the source electrode covering part of the transfer channel; and a drain electrode spaced apart from the source electrode on the substrate, the drain electrode intersecting the transfer channel and covering part of the transfer channel. | 2017-10-19 |
20170301779 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus comprises a semiconductor substrate, a dummy trench section which is formed in a front surface of the semiconductor substrate, and a first front-surface-side electrode which is formed above the front surface of the semiconductor substrate and contains metals, and the dummy trench section has a dummy trench formed in the front surface of the semiconductor substrate, an insulation film formed on an inner wall of the dummy trench, a dummy conductive section formed inside the dummy trench on an inner side than the insulation film, and a protection section having an opening to expose at least a part of the dummy conductive section and covering the insulation film on the front surface of the semiconductor substrate, and the first front-surface-side electrode has a portion formed within the opening of the protection section and contacts with the dummy conductive section. | 2017-10-19 |
20170301780 | HIGH-VOLTAGE GAN HIGH ELECTRON MOBILITY TRANSISTORS WITH REDUCED LEAKAGE CURRENT - High-voltage, gallium-nitride HEMTs are described that are capable of withstanding reverse-bias voltages of at least 900 V and, in some cases, in excess of 2000 V with low reverse-bias leakage current. A HEMT may comprise a lateral geometry having a gate, a thin insulating layer formed beneath the gate, a gate-connected field plate, and a source-connected field plate. | 2017-10-19 |
20170301781 | HIGH-VOLTAGE GAN HIGH ELECTRON MOBILITY TRANSISTORS - High-voltage, gallium-nitride HEMTs are described that are capable of withstanding reverse-bias voltages of at least 900 V and, in some cases, in excess of 2000 V with low reverse-bias leakage current. A HEMT may comprise a lateral geometry having a gate, gate-connected field plate, and source-connected field plate. | 2017-10-19 |
20170301782 | SEMICONDUCTOR DEVICE - To enhance electromigration resistance of an electrode. | 2017-10-19 |
20170301783 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A silicon carbide semiconductor device includes an ohmic electrode and a Schottky electrode that are in contact with the drain electrode respectively on the drain electrode and are next to each other; a first conductivity type first withstand voltage holding region in contact with the ohmic electrode on the ohmic electrode; a second conductivity type second withstand voltage holding region in contact with the Schottky electrode on the Schottky electrode and is next to the first withstand voltage holding region; a second conductivity type well region in contact onto the first and second withstand voltage holding regions; a first conductivity type source region selectively provided on a surface layer of the well region; and a gate electrode opposite to a channel region defined by the well region sandwiched between the source region and the first withstand voltage holding region, with a gate oxide film interposed therebetween. | 2017-10-19 |
20170301784 | Semiconductor Device Having Field-Effect Structures with Different Gate Materials - A semiconductor device includes a plurality of first field-effect structures each including a polysilicon gate arranged on and in contact with a first gate dielectric, and a plurality of second field-effect structures each including a metal gate arranged on and in contact with a second gate dielectric. The plurality of first field-effect structures and the plurality of second field-effect structures form part of a power semiconductor device. | 2017-10-19 |
20170301785 | EPI BLOCK STRUCTURE IN SEMICONDUCTOR PRODUCT PROVIDING HIGH BREAKDOWN VOLTAGE - The present disclosure is generally directed to semiconductor structures and methods that improve breakdown characteristics in finFET device designs, while retaining cost effectiveness for integration into the process flow. The semiconductor structure includes an extended lightly-doped-drain (LDD) region formed on a source/drain structure. The extended LDD regions provide extra separation between source and drain regions, which in turn provides for an increased source to drain resistance. The increased source to drain resistance improves the breakdown voltage of the semiconductor device, and significantly reduces its susceptibility to latch-up. The source to drain resistance may be tuned by adjusting the length of epi block regions, and may also be tuned by selecting desired doping profiles for the LDD and source/drain regions. The length of epi block regions may also be adjusted to maintain high uniformity of epitaxial growth in the S/D regions. | 2017-10-19 |
20170301786 | SELF ALIGNED EPITAXIAL BASED PUNCH THROUGH CONTROL - A method of forming a semiconductor device that may include etching source and drain portions of a fin structure of a first semiconductor material selectively to an underlying semiconductor layer of a second semiconductor material, and laterally etching undercut region in the semiconductor layer underlying the fin structure. The method may further include filling the undercut region with a first conductivity type semiconductor material, and forming a second conductivity type semiconductor material for a source region and a drain region on opposing sides of the channel region portion of the fin structure. | 2017-10-19 |
20170301787 | SEMICONDUCTOR DEVICE INCLUDING A STACKED WIRE STRUCTURE - A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a stacked wire structure formed over the substrate. The semiconductor device structure also includes a gate structure formed over a middle portion of the stacked wire structure and a source/drain (S/D) structure formed at two opposite sides of the stacked wire structure. The S/D structure includes a top surface, a sidewall surface, and a rounded corner between the top surface and the sidewall surface. | 2017-10-19 |
20170301788 | SEMICONDUCTOR DEVICE - A trench-gate semiconductor device including an outside trench, increases reliability of an insulating film at a corner of an open end of the outside trench. The semiconductor device includes: a gate trench reaching an inner part of an n-type drift layer in a cell region; an outside trench outside the cell region; a gate electrode formed inside the gate trench through a gate insulating film; a gate line formed inside the outside trench through an insulating film; and a gate line leading portion formed through the insulating film to cover a corner of an open end of the outside trench closer to the cell region, and electrically connecting the gate electrode to the gate line, and the surface layer of the drift layer in contact with the corner has a second impurity region of p-type that is a part of the well region. | 2017-10-19 |
20170301789 | SILICON CARBIDE SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE, AND METHOD OF CONTROLLING SILICON CARBIDE SEMICONDUCTOR DEVICE - In a trench-gate vertical MOSFET, an n-type drift layer and p-type base layer are epitaxially grown on an n | 2017-10-19 |
20170301790 | METHOD OF PRODUCING A SYMMETRIC LDMOS TRANSISTOR - A well of a first type of conductivity is formed in a semiconductor substrate, and wells of a second type of conductivity are formed in the well of the first type of conductivity at a distance from one another. By an implantation of dopants, a doped region of the second type of conductivity is formed in the well of the first type of conductivity between the wells of the second type of conductivity and at a distance from the wells of the second type of conductivity. Source/drain contacts are applied to the wells of the second type of conductivity, and a gate dielectric and a gate electrode are arranged above regions of the well of the first type of conductivity that are located between the wells of the second type of conductivity and the doped region of the second type of conductivity. | 2017-10-19 |
20170301791 | Method for Manufacturing an Integrated Circuit Including a Lateral Trench Transistor and a Logic Circuit Element - A method of forming an integrated circuit includes forming gate trenches in the first main surface of a semiconductor substrate, the gate trenches being formed so that a longitudinal axis of the gate trenches runs in a first direction parallel to the first main surface. The method further includes forming a source contact groove running in a second direction parallel to the first main surface, the second direction being perpendicular to the first direction, the source contact groove extending along the plurality of gate trenches, forming a source region including performing a doping process to introduce dopants through a sidewall of the source contact groove, and filling a sacrificial material in the source contact groove. The method also includes, thereafter, forming components of the logic circuit element, thereafter, removing the sacrificial material from the source contact groove, and filling a source conductive material in the source contact groove. | 2017-10-19 |
20170301792 | Semiconductor Devices and a Method for Forming a Semiconductor Device - A semiconductor device includes a gate trench of at least one transistor structure extending into a semiconductor substrate. The gate trench includes at least one sidewall having a bevel portion located adjacent to a bottom of the gate trench. The at least one sidewall of the gate trench is formed by the semiconductor substrate. An angle between the bevel portion and a lateral surface of the semiconductor substrate is between 110′ and 160°. A lateral dimension of the bevel portion is larger than 50 nm. Methods for forming the semiconductor device are also provided. | 2017-10-19 |
20170301793 | FIN FIELD EFFECT TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A method of fabricating a FinFET includes at last the following steps. A <551> direction is determined by tilting 8.05±2 degrees from a normal vector of a (110) lattice plane of a semiconductor substrate. The semiconductor substrate is patterned along a lattice plane perpendicular to the <551> direction, so as to form a plurality of trenches in the semiconductor substrate and at least one semiconductor fin having sidewalls disposed on a (551) lattice plane. Insulators are in the trenches. A gate stack is formed over portions of the semiconductor fin and over portions of the insulators. Strained material portions are formed over the semiconductor fins revealed by the gate stack. | 2017-10-19 |
20170301794 | STRAINED STRUCTURE OF A SEMICONDUCTOR DEVICE - A p-type field effect transistor includes a pair of spacers over a substrate top surface. The p-type field effect transistor includes a channel recess cavity in the substrate top surface between the pair of spacers. The p-type field effect transistor includes a gate stack with a bottom portion in the channel recess cavity. The p-type field effect transistor includes a source/drain (S/D) recess cavity including a bottom surface and sidewalls below the substrate top surface, wherein the S/D recess cavity includes a portion extending below the gate stack. The p-type field effect transistor includes a strained material filling the S/D recess cavity. The p-type field effect transistor further includes a source/drain (S/D) extension substantially conformably surrounding the bottom surface and sidewalls of the S/D recess cavity. The S/D extension includes a portion between the gate stack and the S/D recess cavity. | 2017-10-19 |
20170301795 | FIN FIELD EFFECT TRANSISTOR - A FinFET including a substrate, a plurality of insulators and a gate stack is provided. The substrate comprises a plurality of trenches and at least one semiconductor fin between the trenches, wherein the semiconductor fin comprises at least one groove, and the at least one groove is located on a top surface of the semiconductor fin. The insulators are disposed in the trenches. The gate stack partially covers the semiconductor fin, the at least one groove and the insulators. | 2017-10-19 |
20170301796 | SEMICONDUCTOR DEVICE - Defects in an oxide semiconductor film are reduced in a semiconductor device including the oxide semiconductor film. The electrical characteristics of a semiconductor device including an oxide semiconductor film are improved. The reliability of a semiconductor device including an oxide semiconductor film is improved. A semiconductor device including an oxide semiconductor layer; a metal oxide layer in contact with the oxide semiconductor layer, the metal oxide layer including an In-M oxide (M is Ti, Ga, Y, Zr, La, Ce, Nd, or Hf); and a conductive layer in contact with the metal oxide layer, the conductive layer including copper, aluminum, gold, or silver is provided. In the semiconductor device, y/(x+y) is greater than or equal to 0.75 and less than 1 where the atomic ratio of In to M included in the metal oxide layer is In:M=x:y. | 2017-10-19 |
20170301797 | SEMICONDUCTOR DEVICE - The semiconductor device includes an oxide semiconductor layer including a plurality of channel formation regions arranged in the channel width direction and parallel to each other and a gate electrode layer covering a side surface and a top surface of each channel formation region with a gate insulating layer placed between the gate electrode layer and the channel formation regions. With this structure, an electric field is applied to each channel formation region from the side surface direction and the top surface direction. This makes it possible to favorably control the threshold voltage of the transistor and improve the S value thereof. Moreover, with the plurality of channel formation regions, the transistor can have increased effective channel width; thus, a decrease in on-state current can be prevented. | 2017-10-19 |
20170301798 | HIGH-VOLTAGE LATERAL GAN-ON-SILICON SCHOTTKY DIODE - High-voltage, gallium-nitride Schottky diodes are described that are capable of withstanding reverse-bias voltages of up to and in excess of 2000 V with reverse current leakage as low as 0.4 microamp/millimeter. A Schottky diode may comprise a lateral geometry having an anode located between two cathodes, where the anode-to-cathode spacing can be less than about 20 microns. A diode may include at least one field plate connected to the anode that extends above and beyond the anode towards the cathodes. | 2017-10-19 |
20170301799 | HIGH-VOLTAGE LATERAL GAN-ON-SILICON SCHOTTKY DIODE WITH REDUCED JUNCTION LEAKAGE CURRENT - High-voltage, gallium-nitride Schottky diodes are described that are capable of withstanding reverse-bias voltages of up to and in excess of 2000 V with reverse current leakage as low as 0.4 microamp/millimeter. A Schottky diode may comprise a lateral geometry having an anode located between two cathodes, where the anode-to-cathode spacing can be less than about 20 microns. A diode may include at least one field plate connected to the anode that extends above and beyond the anode towards the cathodes. | 2017-10-19 |
20170301800 | TERMINATION STRUCTURE FOR GALLIUM NITRIDE SCHOTTKY DIODE - A termination structure for a nitride-based Schottky diode includes a guard ring formed by an epitaxially grown P-type nitride-based compound semiconductor layer and dielectric field plates formed on the guard ring. The termination structure is formed at the edge of the anode electrode of the Schottky diode and has the effect of reducing electric field crowding at the anode electrode edge, especially when the Schottky diode is reverse biased. In one embodiment, the P-type epitaxial layer includes a step recess to further enhance the field spreading effect of the termination structure. | 2017-10-19 |
20170301801 | PHOTOVOLTAIC STRUCTURES WITH INTERLOCKING BUSBARS - One embodiment can provide a current-collecting mechanism of a photovoltaic structure. The current-collecting mechanism can include a top metallic grid positioned on a top surface of the photovoltaic structure and a bottom metallic grid positioned on the bottom surface of the photovoltaic structure. The top metallic grid can include a top busbar positioned near an edge of the photovoltaic structure, and the bottom metallic grid can include a bottom busbar positioned near an opposite edge. The top busbar and the bottom busbar can have complementary topology profiles such that, when the edge of the photovoltaic structure overlaps with an opposite edge of an adjacent photovoltaic structure, the top busbar of the photovoltaic structure and the bottom busbar of the adjacent photovoltaic structure interlock with each other. | 2017-10-19 |
20170301802 | SOLAR MODULE HAVING A PLURALITY OF STRINGS CONFIGURED FROM A FIVE STRIP CELL - In an example, the present invention provides a method of manufacturing a solar module. The method includes providing a substrate member having a surface region, the surface region comprising a spatial region, a first end strip comprising a first edge region and a first interior region, the first interior region comprising a first bus bar, a plurality of strips, a second end strip comprising a second edge region and a second interior region, the second edge region comprising a second bus bar, the first end strip, the plurality of strips, and the second end strip arranged in parallel to each other and occupying the spatial region such that the first end strip, the second end strip, and the plurality of strips consists of a total number of five (5) strips. The method includes separating each of the plurality of strips, arranging the plurality of strips in a string configuration, and using the string in the solar module. | 2017-10-19 |
20170301803 | CONDUCTIVE THICK FILM PASTE FOR SOLAR CELL CONTACTS - The present invention relates to an inorganic reaction system used in the manufacture of electroconductive pastes. The inorganic reaction system comprises a lead containing matrix forming composition and a tellurium oxide additive. Preferably the lead containing matrix forming composition is between 5-95 wt. % of the inorganic reaction system, and the tellurium oxide additive is between 5-95 wt. % of the inorganic reaction system. The lead containing matrix forming composition may be a glass frit, and may comprise lead oxide. Another aspect of the present invention relates to an electroconductive paste composition that comprises metallic particles, an inorganic reaction system as previously disclosed, and an organic vehicle. Another aspect of the present invention relates to an organic vehicle that comprises one or more of a binder, a surfactant, a solvent, and a thixatropic agent. Another aspect of the present invention relates to a solar cell printed with an electroconductive paste composition as disclosed, as well as an assembled solar cell module. Another aspect of the present invention relates to a method of producing a solar cell. | 2017-10-19 |
20170301804 | CONDUCTIVE PASTE COMPOSITION AND SEMICONDUCTOR DEVICES MADE THEREWITH - The present invention provides a thick-film paste composition for printing the front side of a solar cell device having one or more insulating layers. The thick-film paste comprises an electrically conductive metal and a dual-frit oxide composition dispersed in an organic medium. | 2017-10-19 |
20170301805 | SOLAR CELL MANUFACTURING METHOD AND SOLAR CELL - A solar cell manufacturing method including: forming, on one surface of a first conductivity-type semiconductor substrate, a first doped layer in which second conductivity-type impurities are diffused in a first concentration, and a second doped layer in which the second conductivity-type impurities are diffused in a second concentration lower than the first concentration, the second doped layer has surface roughness different from the first doped layer; and forming a metal electrode on the first doped layer to be electrically connected to the first doped layer, wherein a position of the first doped layer is detected based on a difference in light reflectance between the first and second doped layers, which results from a difference in surface roughness between the first and second doped layers, and then the metal electrode is formed in alignment with a detected position of the first doped layer. | 2017-10-19 |
20170301806 | METAL CHALCOGENIDE NANOPARTICLES FOR PREPARING LIGHT ABSORPTION LAYER OF SOLAR CELLS AND METHOD OF PREPARING THE SAME - Disclosed are metal chalcogenide nanoparticles forming a light absorption layer of solar cells including a first phase including copper (Cu)-tin (Sn) chalcogenide and a second phase including zinc (Zn) chalcogenide, and a method of preparing the same. | 2017-10-19 |
20170301807 | PRECURSOR FOR PREPARING LIGHT ABSORPTION LAYER OF SOLAR CELLS AND METHOD OF PREPARING THE SAME - Disclosed are a precursor for preparing a light absorption layer of a solar cell including (a) an aggregate-phase composite including a first phase including a copper (Cu)-tin (Sn) bimetallic metal and a second phase including zinc (Zn)-containing chalcogenide, or including the first phase including a copper (Cu)-tin (Sn) bimetallic metal, the second phase including zinc (Zn)-containing chalcogenide and a third phase including copper (Cu)-containing chalcogenide; or (b) core-shell structured nanoparticles including a core including copper (Cu)-tin (Sn) bimetallic metal nanoparticles and a shell including zinc (Zn)-containing chalcogenide, or the zinc (Zn)-containing chalcogenide and copper (Cu)-containing chalcogenide; or (c) a mixture thereof, and a method of preparing the same. | 2017-10-19 |
20170301808 | MATERIALS, FABRICATION EQUIPMENT, AND METHODS FOR STABLE, SENSITIVE PHOTODETECTORS AND IMAGE SENSORS MADE THEREFROM - Optically sensitive devices include a device comprising a first contact and a second contact, each having a work function, and an optically sensitive material between the first contact and the second contact. The optically sensitive material comprises a p-type semiconductor, and the optically sensitive material has a work function. Circuitry applies a bias voltage between the first contact and the second contact. The optically sensitive material has an electron lifetime that is greater than the electron transit time from the first contact to the second contact when the bias is applied between the first contact and the second contact. The first contact provides injection of electrons and blocking the extraction of holes. The interface between the first contact and the optically sensitive material provides a surface recombination velocity less than 1 cm/s. | 2017-10-19 |
20170301809 | DUAL WAVELENGTH IMAGING CELL ARRAY INTEGRATED CIRCUIT - A semiconductor device is provided that includes an array of imaging cells realized from a plurality of layers formed on a substrate, wherein the plurality of layers includes at least one modulation doped quantum well structure spaced from at least one quantum dot structure. Each respective imaging cell includes an imaging region spaced from a corresponding charge storage region. The at least one quantum dot structure of the imaging region generates photocurrent arising from absorption of incident electromagnetic radiation. The at least one modulation doped quantum well structure defines a buried channel for lateral transfer of the photocurrent for charge accumulation in the charge storage region and output therefrom. The at least one modulation doped quantum well structure and the at least one quantum dot structure of each imaging cell can be disposed within a resonant cavity that receives the incident electromagnetic radiation or below a structured metal film having a periodic array of holes. | 2017-10-19 |
20170301810 | HIGH EFFICIENCY PHOTOVOLTAIC CELLS AND MANUFACTURING THEREOF - This invention relates to a novel structure of photovoltaic devices (e.g. photovoltaic cells also called as solar cells) are provided. The cells are based on the micro or nano scaled structures which could not only increase the surface area but also have the capability of reducing the reflection and increasing the absorption of incident light. More specifically, the structures are based on 3D structure which are made of electric materials covering semiconductors, insulators, dielectric, polymer, and metallic type materials. By using such structures reflection loss of the light from the cell is significantly reduced, increasing the absorption, which results in increasing the conversion efficiency of the solar cell, and reducing the usage of material while increasing the flexibility of the solar cell. The structures can be also used in other optical devices wherein the reflection loss and absorption are required to enhance significantly improve the device performances. | 2017-10-19 |
20170301811 | SOLAR CELL BONDED TO A FLEXIBLE SUPPORT - A solar cell assembly in which a solar cell component is bonded to a flexible support is disclosed. The solar cell assembly comprises a flexible support with a predetermined size, a solar cell component, bonding adhesive between the support and the solar cell component, wherein the support with the predetermined size has a uniform borders of 0.003 inch to 0.2 inch in width extending beyond the edges of the solar cell component. | 2017-10-19 |
20170301812 | SOLAR POWER MODULE - A solar power module includes a solar panel, a metallic frame, a soft insulation glue material, and a hard insulation spacer. The solar panel is embedded in the metallic frame. The metallic frame includes an upper portion, an intermediate portion, and a lower portion. The soft insulation glue material is adapted to wrap at least one portion of an edge of the solar panel. The soft insulation glue material is fixedly disposed in the metallic frame. The soft insulation glue material to wrap the solar panel is divided into an upper part, an intermediate part, and a lower part. The hard insulation spacer is disposed between the solar panel and the lower portion of the metallic frame. | 2017-10-19 |
20170301813 | SEALING MATERIAL FOR SOLAR CELL MODULES, AND MANUFACTURING METHOD THEREOF - Disclosed are a sealing material for solar cell modules and a manufacturing method thereof capable of endowing good transparency and heat resistance to the sealing material for solar cell modules while using a polyethylene-based resin. The disclosed sealing material for solar cell modules uses a polyethylene-based resin with a density of 0.900 g/cm3 or less, and an MFR between 0.1 g/10 min and 1.0 g/10 min. The sealing material is obtained by melt molding a resin composition containing a polyethylene-based resin with density 0.890 g/cm3 or less, and a polymerization initiator contained at 0.02 mass % or more but less than 0.5 mass % of the composition, wherein the density difference of the resin composition before and after the melt molding is within 0.05 g/cm3, and the MFR difference of the resin composition before and after the melt molding is 1.0 g/10 min or greater. | 2017-10-19 |
20170301814 | HORIZONTAL BALANCED SOLAR TRACKER - In an example, the present invention provides a solar tracker apparatus. In an example, the apparatus comprises a center of mass with an adjustable hanger assembly configured with a clam shell clamp assembly on the adjustable hanger assembly and a cylindrical torque tube comprising a plurality of torque tubes configured together in a continuous length from a first end to a second end such that the center of mass is aligned with a center of rotation of the cylindrical torque tubes to reduce a load of a drive motor operably coupled to the cylindrical torque tube. Further details of the present example, among others, can be found throughout the present specification and more particularly below. | 2017-10-19 |
20170301815 | SOLAR-CELL MODULE - This solar-cell module and method is provided with a plurality of solar cells and a connecting member that connects the light-receiving-surface side of one solar cell to the back-surface side of an adjacent solar cell. Said connecting member comprises a conductor that includes the following: a flat section laid out on the light-receiving-surface side of the aforementioned one solar cell, a flat section laid out on the back-surface side of the other solar cell, and a middle section that joins said flat sections to each other. The hardness of a boundary region between one of the flat sections and the middle section is no more than 1.25 times the hardness of that flat section. | 2017-10-19 |
20170301816 | SINGLE PHOTON AVALANCHE DIODE HAVING PULSE SHAPING FILTER - An electronic device disclosed herein includes a single photon avalanche diode (SPAD) configured to detect an incoming photon and to generate a first pulse signal in response thereto. Pulse shaping circuitry is configured to generate a second pulse signal from the first pulse signal by high pass filtering the first pulse signal. The pulse shaping circuitry includes a transistor drain-source coupled between a first node and a reference node, and a capacitor coupling the first node to an anode of the SPAD. | 2017-10-19 |
20170301817 | GERMANIUM DEVICES ON AMORPHOUS SUBSTRATES - A germanium metal-semiconductor-metal (MSM) photodetector is fabricated by growing crystalline germanium from an amorphous silicon seed, supported by an amorphous substrate, at a temperature of about 450° C. In this fabrication, crystalline Ge is grown via selective deposition in geometrically confined channels, where amorphous silicon is disposed as the growth seed. Ge growth extends from the growth seed along the channels to a lithographically defined trench. The Ge emerging out of the channels includes crystalline grains that coalesce to fill the trench, forming a Ge strip that can be used as the active area of a photodetector. One or more Schottky contacts can be formed by a thin tunneling layer (e.g., Al | 2017-10-19 |
20170301818 | ACTIVE PHOTONIC DEVICE HAVING A DARLINGTON CONFIGURATION WITH FEEDBACK - Disclosed is an active photonic device having a Darlington configuration with a substrate and a collector layer that is over the substrate. The collector layer includes an inner collector region. An outer collector region substantially surrounds the inner collector region and is spaced apart from the inner collector region. A base layer is over the collector layer. A first outer base region and a second outer base region substantially surround the inner base region and are spaced apart from the inner base region and each other. An emitter layer is over the base layer. The emitter layer includes an inner emitter region that is ring-shaped and resides over and extends substantially around an outer periphery of the inner base region. A first outer emitter region and a second outer emitter region substantially surround the inner emitter region and are spaced apart from the inner emitter region and each other. | 2017-10-19 |
20170301819 | ANTENNA-ASSISTED PHOTOVOLTAIC GRAPHENE DETECTORS - A photovoltaic photodetector includes a substrate, a graphene layer, and a dielectric layer positioned between the substrate and the graphene layer. One or more first antenna electrodes includes a first metal in direct contact with the graphene layer. One or more second antenna electrodes includes a second metal in direct contact with the graphene layer. The first and second metals have different work functions. A drain electrode is electrically coupled to the one or more first antenna electrodes, and a source electrode is electrically coupled to the one or more second antenna electrodes. The photovoltaic photodetector can be configured to be operable over a wavelength region of 2 μm to 24 μm and has a response time of 10 ns or less. | 2017-10-19 |
20170301820 | SOLAR CELL PRODUCTION APPARATUS FOR PROCESSING A SUBSTRATE, AND METHOD FOR PROCESSING A SUBSTRATE FOR THE PRODUCTION OF A SOLAR CELL - The present disclosure provides a solar cell production apparatus for processing a substrate. The solar cell production apparatus includes at least one substrate support configured to support the substrate; one or more printing stations configured for forming a printing structure on the substrate positioned on the substrate support; and an inspection system including at least one first camera, wherein the at least one first camera is configured for detecting a position of the printing structure on the substrate positioned on the substrate support while the substrate is passing through a field of view of the at least one first camera. | 2017-10-19 |
20170301821 | TILED SOLAR MODULE REPAIR PROCESS - In an example, a method includes providing a photovoltaic string comprising a plurality of from 2 to 45 strips, each of the plurality of strips being configured in a series arrangement with each other, each of the plurality of strips being coupled to another one of the plurality of strips using an electrically conductive adhesive (ECA) material, detecting at least one defective strip in the photovoltaic string, applying thermal energy to the ECA material to release the ECA material from a pair of photovoltaic strips to remove the defective photovoltaic strip, removing any residual ECA material from one or more good photovoltaic strip, aligning the photovoltaic string without the damaged photovoltaic strip, and a replacement photovoltaic strip that replaces the defective photovoltaic strip, and curing a reapplied ECA material on the replacement photovoltaic strip to provide the photovoltaic string with the replacement photovoltaic strip. | 2017-10-19 |
20170301822 | TILED SOLAR CELL LASER PROCESS - In an example, the present invention provides a method of separating a photovoltaic strip from a solar cell. The method includes providing a solar cell, placing the front side of the solar cell on a platen such that the backside is facing a laser source, initiating a laser source to output a laser beam having a wavelength from 200 to 600 nanometers and a spot size of 18 to 30 microns, subjecting a portion of the backside to the laser beam at a power level ranging from about 20 Watts to about 35 Watts to cause an ablation to form a scribe region having a depth, width, and a length, the depth being from 40% to 60% of a thickness of the solar cell, the width being between 16 and 35 microns to create a plurality of scribe regions spatially disposed on the backside of the solar cell. | 2017-10-19 |
20170301823 | NANOWIRE SIZED OPTO-ELECTRONIC STRUCTURE AND METHOD FOR MODIFYING SELECTED PORTIONS OF SAME - A LED structure includes a support and a plurality of nanowires located on the support, where each nanowire includes a tip and a sidewall. A method of making the LED structure includes reducing or eliminating the conductivity of the tips of the nanowires compared to the conductivity of the sidewalls during or after creation of the nanowires. | 2017-10-19 |
20170301824 | OPTICAL DEVICE AND METHOD FOR ITS FABRICATION - An optical device comprising:
| 2017-10-19 |
20170301825 | MULTICOLOR LED AND METHOD OF FABRICATING THEREOF - A device includes a support including at least a first area and a second area, and a plurality of first light emitting devices located over the first area of the support, each first light emitting device containing a first growth template including a first nanostructure, and each first light emitting device has a first peak emission wavelength. The device also includes a plurality of second light emitting devices located over the second area of the support, each second light emitting device containing a second growth template including a second nanostructure, and each second light emitting device has a second peak emission wavelength different from the first peak emission wavelength. Each first growth template differs from each second growth template. | 2017-10-19 |
20170301826 | LIGHT EMITTING DIODE WITH HIGH EFFICIENCY - A light emitting diode includes: a substrate; a semiconductor stack disposed on the substrate and including a lower semiconductor layer, an upper semiconductor layer and an active layer interposed between the lower semiconductor layer and the upper semiconductor layer, the semiconductor stack having an isolation groove exposing the substrate through the upper semiconductor layer, the active layer and the lower semiconductor layer; a first electrode pad and an upper extension portion electrically connected to the upper semiconductor layer; a second electrode pad and a lower extension portion electrically connected to the lower semiconductor layer; a connecting portion connecting the upper extension portion and the lower extension portion to each other across the isolation groove; a first current blocking layer interposed between the lower extension portion and the lower semiconductor layer; and a second current blocking layer interposed between the second electrode pad and the lower semiconductor layer. | 2017-10-19 |
20170301827 | LIGHT EMITTING DIODE HAVING CARBON NANOTUBES - A light emitting diode includes a substrate, a first semiconductor layer, an active layer, a second semiconductor layer, a first electrode, a second electrode, a static electrode and a carbon nanotube structure. The first semiconductor layer, the active layer, and the second semiconductor layer are stacked on the substrate. The first electrode is located on and electrically connected to the first semiconductor layer. The carbon nanotube structure is located on and electrically connected to the second semiconductor layer. The second electrode is located on and electrically connected to the carbon nanotube structure. The static electrode is located between the second semiconductor layer and the carbon nanotube structure. The carbon nanotube structure includes a first portion in direct contact with the second semiconductor layer and a second portion sandwiched between the static electrode and the second electrode. | 2017-10-19 |
20170301828 | LED PACKAGE - A method for manufacturing a light emitting diode (LED) die includes providing an LED die including a substrate, an N type semiconductor layer, an active layer, and a P type semiconductor layer grown on the substrate in sequence. The N type semiconductor layer, the active layer, and the P type semiconductor layer are etched to define a plurality of recesses and a groove. An insulating layer to cover side surfaces of the recesses and the P type semiconductor layer is formed and a portion of the insulating layer is etched to define an opening to expose a top portion of the P type semiconductor layer. A pair of electrodes is formed and the LED die is cut along the groove to obtain an individual LED die. | 2017-10-19 |
20170301829 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - According to one embodiment, the p-side electrode is provided on the second semiconductor layer. The insulating film is provided on the p-side electrode. The n-side electrode includes a first portion, a second portion, and a third portion. The first portion is provided on a side face of the first semiconductor layer. The second portion is provided in the first n-side region. The third portion overlaps the p-side electrode via the insulating film and connects the first portion and the second portion to each other. | 2017-10-19 |
20170301830 | LIGHT-EMITTING DIODE INCLUDING A PLURALITY OF LUMINESCENT REGIONS - Various embodiments may relate to A light-emitting diode, including an LED chip having at least one emitter surface for emitting primary light, and a plurality of luminescent regions, which are connected optically downstream from the at least one emitter surface. At least one harder one of the luminescent regions is embedded in another, softer one of the luminescent regions. | 2017-10-19 |
20170301831 | THIN FILM LIGHT EMITTING DIODE - A light emitting device can include a light emitting structure including a p-GaN based layer, an active layer having multiple quantum wells, and an n-GaN based layer; a p-electrode and an n-electrode electrically connecting with the light emitting structure, respectively, in which the n-electrode has a plurality of layers; a phosphor layer disposed on a top surface of the light emitting structure; and a passivation layer disposed between the phosphor layer and the top surface of the light emitting structure, and disposed on outermost side surfaces of the light emitting structure, in which the p-electrode and the n-electrode are disposed on opposite sides of the light emitting structure. Also, the phosphor layer has a two-digit micrometer thickness, and includes a pattern to bond an n-electrode pad on a portion of the n-electrode by a wire, and comprises different phosphor materials configured to emit light of different colors. | 2017-10-19 |
20170301832 | GLUELESS LIGHT EMITTING DEVICE WITH PHOSPHOR CONVERTER - A multi-stage lamination process is used to laminate a wavelength conversion film ( | 2017-10-19 |
20170301833 | QUANTUM DOTS (QD) GLASS CELLS, AND THE MANUFACTURING METHODS AND APPLICATIONS THEREOF - A QD glass cell includes a glass cell and QD fluorescent powder material. The glass cell includes a receiving chamber, and the QD fluorescent powder being encapsulated within the receiving chamber. A manufacturing method of the QD glass cell includes: S | 2017-10-19 |
20170301834 | CHIP SCALE LIGHT EMITTING DEVICE PACKAGE WITH DOME - Light Emitting Devices (LEDs) are fabricated on a wafer substrate with one or more thick metal layers that provide structural support to each LED. The streets, or lanes, between individual LEDs do not include this metal, and the wafer can be easily sliced/diced into singulated self-supporting LEDs. Because these devices are self-supporting, a separate support submount is not required. Before singulation, further processes may be applied at the wafer-level; after singulation, these self-supporting LEDs may be picked and placed upon an intermediate substrate for further processing as required. In an embodiment of this invention, protective optical domes are formed over the light emitting devices at the wafer-level or while the light emitting devices are situated on the intermediate substrate. | 2017-10-19 |