42nd week of 2010 patent applcation highlights part 59 |
Patent application number | Title | Published |
20100268910 | FLEXRAY SYSTEM USING EFFICIENT STORAGE OF INSTRUCTIONS - A data processing system comprises multiple data processing nodes that communicate with one another using the FlexRay protocol. Each respective node works according to a respective schedule based on a repetitive sequence of cycles, each cycle having a sequence of time slots. Each node executes instructions, one per time slot, if any. The instructions are stored in a memory. Each instruction is identified by the relevant cycle number and time slot number in the relevant cycle. Accordingly, the combination of cycle number and slot number identify a memory address. Typical instructions appear more than once in the repetitive sequence of cycles for a node. This temporal pattern of occurrences of the same instruction at a node is used to modify the generation of the memory addresses, so that the same memory address is generated each time the instruction is needed. This makes efficient use of storage space. | 2010-10-21 |
20100268911 | Method and Apparatus for Dynamic Partial Reconfiguration on an Array of Processors - A method and apparatus for dynamic partial reconfiguration on an array of processors. The method includes the steps of verifying if a processor is ready for dynamic partial reconfiguration to begin, deciding the degree of dynamic partial reconfiguration, including the number and identity of all processors to be modified, executing native machine code in the port of a processing device, and modifying a segment of the internal memory of said single processing device. Additional embodiments allow modification of multiple processors in the array, including the modification of all processors on a die or system. The apparatus includes a processor array having a first group of processors connected together for performing a first task, and a second group of processors connected together for performing a second task with at least one processor connected to said first group of processors and said second group of processors for facilitating communications between said first group of processors and said second group of processors without participating in said first task and said second task. In an embodiment of the apparatus, this one processor dynamically reconfigures the array. Additional embodiments allow additional processors to aid in the reconfiguration. | 2010-10-21 |
20100268912 | THREAD MAPPING IN MULTI-CORE PROCESSORS - Techniques for thread mapping in multi-core processors are disclosed. An example computing system is disclosed having a multi-core processor with a plurality of processor cores. A performance counter may be configured to collect data relating to the performance of the multi-core processor. A core controller may be configured to map threads of execution to the processor cores based at least in part on the data collected by the performance counter. | 2010-10-21 |
20100268913 | LITHOGRAPHIC APPARATUS, CONTROL SYSTEM, MULTI-CORE PROCESSOR, AND A METHOD TO START TASKS ON A MULTI-CORE PROCESSOR - A multi-core processor includes two or more cores; an external communication facility that is shared by the cores and is capable of communicating with one of the cores at a time; and an internal communication facility capable of communicating simultaneously with each one of the cores; wherein the multi-core processor is configured to: receive a first signal via the external communication facility; relay the first signal to one of the cores; handle the first signal by the one of the cores, thereby generating a second signal; transmit substantially at the same time the second signal to each one of the cores by the internal communication facility; start a task on each one of the cores in response to the receiving of the second signal. | 2010-10-21 |
20100268914 | PROCESSING SYSTEM WITH INTERSPERSED PROCESSORS AND DYNAMIC PATHWAY CREATION - A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports. The dynamically configurable communication elements each comprise a plurality of communication ports, a first memory, and a routing engine. For each of the processors, the plurality of processor ports is configured for coupling to a first subset of the plurality of dynamically configurable communication elements. For each of the dynamically configurable communication elements, the plurality of communication ports comprises a first subset of communication ports configured for coupling to a subset of the plurality of processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements. | 2010-10-21 |
20100268915 | Remote Update Programming Idiom Accelerator with Allocated Processor Resources - A data processing system comprises at least one processing unit, a virtualization layer, and a remote update programming idiom accelerator. The remote update programming idiom accelerator is configured to receive a complex remote update programming idiom from a remote node. Responsive to a determination that the sequence of instructions in the complex remote update programming idiom is longer than a dedicated processor threshold, the remote update programming idiom accelerator is configured to request a processing unit from the virtualization layer in the data processing system, and receive an allocation of a processing unit from the virtualization layer. The allocated processing unit is configured to read the data from the storage location local to the data processing system, execute the sequence of instructions to perform the update operation on the data to form result data, and write the result data to the storage location local to the data processing system. | 2010-10-21 |
20100268916 | RISC PROCESSOR AND ITS REGISTER FLAG BIT PROCESSING METHOD - The present invention discloses a RISC processor and a method of processing flag bits of a register in the RISC processor. Said RISC processor comprises a physical register stack, an operating component connected to the physical register stack and an decoder connected to the operating component; the physical register stack comprises an emulation flag register for emulating to realize flag bits of a flag register in a CISC processor; the operating component comprises a flag read-write module for reading and writing the values of the flag bits of the emulation flag register. The operating component further comprises an operating controller for performing an operation control according to the values of the flag bits of the emulation flag register when the RISC processor is in the working mode of X86 virtual machine during an operation process. | 2010-10-21 |
20100268917 | Systems and Methods for Ramped Power State Control in a Semiconductor Device - Various embodiments of the present invention provide systems and methods for ramping current usage in a semiconductor device. For example, various embodiments of the present invention provide semiconductor devices that include at least a first function circuit and a second function circuit, and a power state change control circuit. The power state change control circuit is operable to transition the power state of the first function circuit from a reduced power state to an operative power state, and to transition the second function circuit from a reduced power state to an operative power state. Transition of the power state of at least one of the first function circuit and the second function circuit is done in at least a first stage at a first time and a second stage at a second time, with the second time being after the first time. | 2010-10-21 |
20100268918 | ASIP ARCHITECTURE FOR EXECUTING AT LEAST TWO DECODING METHODS - A system for execution of a decoding method is disclosed. The system is capable of executing at least two data decoding methods which are different in underlying coding principle, wherein at least one of the data decoding methods requires data shuffling operations on the data. In one aspect, the system includes at least one application specific processor having an instruction set having arithmetic operators excluding multiplication, division and power. The processor is selected for execution of approximations of each of the at least two data decoding methods. The system also includes at least a first memory unit, e.g. background memory, for storing data. The system also includes a transfer unit for transferring data from the first memory unit towards the at least one programmable processor. The transfer unit includes a data shuffler. The system may also include a controller for controlling the data shuffler independent from the processor. | 2010-10-21 |
20100268919 | METHOD AND STRUCTURE FOR SOLVING THE EVIL-TWIN PROBLEM - A register file, in a processor, includes a first plurality of registers of a first size, n-bits. A decoder uses a mapping that divides the register file into a second plurality M of registers having a second size. Each of the registers having the second size is assigned a different name in a continuous name space. Each register of the second size includes a plurality N of registers of the first size, n-bits. Each register in the plurality N of registers is assigned the same name as the register of the second size that includes that plurality. State information is maintained in the register file for each n-bit register. The dependence of an instruction on other instructions is detected through the continuous name space. The state information allows the processor to determine when the information in any portion, or all, of a register is valid. | 2010-10-21 |
20100268920 | MECHANISM FOR HANDLING UNFUSED MULTIPLY-ACCUMULATE ACCRUED EXCEPTION BITS IN A PROCESSOR - A mechanism for handling unfused multiply-add accrued exception bits includes a processor including a floating point unit, a storage, and exception logic. The floating-point unit may be configured to execute an unfused multiply-accumulate instruction defined with the instruction set architecture (ISA). The unfused multiply-accumulate instruction may include a multiply sub-operation and an accumulate sub-operation. The storage may be configured to maintain floating-point exception state information. The exception logic may be configured to capture the floating-point exception state after completion of the multiply sub-operation and prior to completion of the accumulate sub-operation, for example, and to update the storage to reflect the floating-point exception state. | 2010-10-21 |
20100268921 | DATA COLLECTION PREFETCH DEVICE AND METHODS THEREOF - A method of retrieving information from a memory includes receiving an instruction associated with a data collection. In response to determining the instruction is a request to retrieve a first element of the data collection, an application program interface (API) generates an instruction to prefetch a second element of the data collection. In one embodiment, the second element to be prefetched is indicated by a pointer or other information associated with the first element. In response to the prefetch instruction, an execution core of the data processing device retrieves the second element from a memory module and stores the second element at a cache. By prefetching the second element before it has been explicitly requested by the application, the efficiency of the application can be increased. | 2010-10-21 |
20100268922 | Processor that utilizes re-configurable logic to construct persistent finite state machines from machine instruction sequences - A processor, integrated with re-configurable logic and memory elements, is disclosed which is to be used as part of a shared memory, multiprocessor computer system. The invention utilizes the re-configurable elements to construct persistent finite state machines based on information decoded by the invention from sequences of CISC or RISC type processor machine instructions residing in memory. The invention implements the same algorithm represented by the sequence of encoded instructions, but executes the algorithm consuming significantly fewer clock cycles than would be consumed by the processor originally targeted to execute the sequence of encoded instructions. | 2010-10-21 |
20100268923 | METHOD AND DEVICE FOR CONTROLLING A COMPUTER SYSTEM HAVING AT LEAST TWO GROUPS OF INTERNAL STATES - A method and device for controlling a computer system having at least two execution units and having at least two groups of internal states, in particular processor states, in at least one of the execution units, and having a switchover device, through which it is possible to switch between at least two different operating modes, in particular a performance mode and a compare mode, of the computer system, wherein a switchover is triggered by the fact that at least one execution unit changes its internal state. | 2010-10-21 |
20100268924 | INFORMATION PROCESSING APPARATUS AND SETUP PROGRAM EXECUTION METHOD - According to one embodiment, an information processing apparatus includes a display unit, a touch panel, a BIOS storage unit, and a setup program execution unit. The display unit displays various kinds of information. The touch panel is installed on a display screen of the display unit and used for input corresponding to a contact operation. The BIOS storage unit stores a BIOS (basic input/output system) to execute startup of an operating system. The setup program execution unit executes a setup program for the BIOS in response to that an input from the touch panel is detected during the execution of the startup based on the BIOS. | 2010-10-21 |
20100268925 | SYSTEM AND METHOD FOR POPULATING A DEDICATED SYSTEM SERVICE REPOSITORY FOR AN INFORMATION HANDLING SYSTEM - An information handling system includes a processor, a memory device coupled to the processor, and a dedicated system service repository (DSSR) coupled to the processor. The DSSR is configured to store a base image that includes a plurality of partitions and a first system configuration image, wherein the first system configuration image is stored in a first partition of the plurality of partitions, wherein the first system configuration image is configured to provide in-band and/or out-of-band managed access to the DSSR when executed; and by accessing the first system configuration image, the DSSR is populated with a second system configuration image, wherein the second system configuration image is stored in a second partition of the plurality of partitions. | 2010-10-21 |
20100268926 | Method and Apparatus for Preventing BIOS from Failing to Enter Boot Program - A method and an apparatus for preventing a basic input/output system (BIOS) from failing to enter a boot program are adapted to solve the problem that when a central processing unit (CPU) executes a first instruction after a computer is powered on, a start address to be executed is erroneously set as another corresponding start address, resulting in that a BIOS cannot enter a boot program. In the method of the present invention, a jump instruction is written to the corresponding start address, so as to enable an execution instruction to jump to a boot block of the BIOS when the start address is erroneously set in the computer, thus performing a normal boot operation. Moreover, in the present invention, a step for checking a register that may cause the start address to be inverted to the corresponding start address is further added to the BIOS program, such that in each boot process, the value of the register can be pre-checked and overwritten when an error occurs, so as to avoid the problem of false pointing next time the computer is booted. | 2010-10-21 |
20100268927 | Booting An Operating System Of A System Using A Read Ahead Technique - In one embodiment, the present invention includes a method for generating a list of files accessed during an operating system (OS) boot process to profile the OS boot process, and optimizing the list of files to generate an optimized file list for use in future OS boot processes, where the optimizing is according to a first optimization technique if the files were accessed from a solid state medium and according to a second optimization technique if the files were accessed from a rotating medium. Other embodiments are described and claimed. | 2010-10-21 |
20100268928 | DISABLING A FEATURE THAT PREVENTS ACCESS TO PERSISTENT SECONDARY STORAGE - During a boot block part of a boot procedure in an electronic device having a persistent secondary storage, a feature that prevents access to the persistent secondary storage is disabled. The persistent secondary storage is accessed during the boot block part of the boot procedure to retrieve information to perform a predetermined task. | 2010-10-21 |
20100268929 | ELECTRONIC DEVICE AND SETTING METHOD THEREOF - According to one embodiment, an electronic device that is configured to be removably connected to a host device includes a first storage module, a first determination module, and a setting change module. The first storage module stores a data file received from the host device. Each time a data file is newly stored in the first storage module, the first determination module determines whether the data file contains setting instruction information instructing to change a setting of the electronic device. When the first determination module determines that the data file contains the setting instruction information, the setting change module changes the setting of the electronic device as instructed by the setting instruction information. | 2010-10-21 |
20100268930 | ON-CHIP POWER PROXY BASED ARCHITECTURE - The embodiments provide an assigned counter of a first set of counters and stores a value for an activity of a set of activities forming a set of stored values. The value comprises the count multiplied by a weight factor specific to the activity. A power manager manages the first set of counters, receives a set of activities to be monitored for a unit, groups the portion into subsets based on at least one of a frequency of occurrence of each activity and power consumption for each activity, sums the stored values corresponding to each activity in each subset to reach a total value for each subset, multiplies the total value of each subset by factor corresponding to the subset to form a scaled value for each subset, and sums the scaled value of each subset to form a power usage value. | 2010-10-21 |
20100268931 | Resiliently Retaining State Information Of A Many-Core Processor - In one embodiment, the present invention includes a method for performing dynamic testing of a many-core processor including a plurality of cores, manipulating data obtained from the dynamic testing into profile information of the many-core processor, and storing the profile information in a non-volatile memory. The non-volatile memory may be within the many-core processor, in some embodiments. Other embodiments are described and claimed. | 2010-10-21 |
20100268932 | SYSTEM AND METHOD OF VERIFYING THE ORIGIN OF A CLIENT REQUEST - A system and method for verifying the origin of a client request. The system includes two devices, a “Security Device” which resides within the web-server in the client end, and an “Authenticator Device” which resides within the web-server in the server end. The “Security Device” adds an Extended Validation SSL (EV SSL) certificate to the client-side web-request. The “Authenticator Device” then parses the http request from the client, gets the EV SSL certificate and gets the “Organization Name” of the client from this EV SSL certificate. If the “Organization Name” matches a list of “Organization” that the “Authenticator Device” is allowed to do a transaction, then the client request is authenticated and the transaction goes through, else the client-request is denied. | 2010-10-21 |
20100268933 | METHOD FOR NETWORK TRAFFIC MIRRORING WITH DATA PRIVACY - Systems and methods are provided for preserving the privacy of data contained in mirrored network traffic. The mirrored network traffic may comprise data that may be considered confidential, privileged, private, or otherwise sensitive data. For example, the data payload of a frame of mirrored network traffic may include private Voice over IP (VoIP) communications between users on one or more networks. The present invention provides various techniques for securing the privacy of data contained in the mirrored network traffic. Using the techniques of the present invention, network traffic comprising confidential, privileged, private, or otherwise sensitive data may be mirrored in such a manner as to provide for the privacy of such data over at least a portion if not all of the mirrored communications between the mirror source point and the minor destination point. | 2010-10-21 |
20100268934 | METHOD AND SYSTEM FOR SECURE DOCUMENT EXCHANGE - A document management (DM), data leak prevention (DLP) or similar application in a data processing system is instrumented with a document protection service provider interface (SPI). The service provider interface is used to call an external function, such as an encryption utility, that is used to facilitate secure document exchange between a sending entity and a receiving entity. The encryption utility may be configured for local download to and installation in the machine on which the SPI is invoked, but a preferred approach is to use the SPI to invoke an external encryption utility as a “service.” In such case, the external encryption utility is implemented by a service provider. When the calling program invokes the SPI, preferably the user is provided with a display panel. Using that panel, the end user provides a password that is used for encryption key generation, together with an indication of the desired encryption strength. The service provider uses the password to generate the encryption key. In one embodiment, the service provider provides the key to the service provider interface, which then uses the key to encrypt the document and to complete the file transfer operation. In the alternative, the service provider itself performs the document or file encryption. The service provider interface also preferably generates and sends an email or other message to the receiving entity that includes the key or a link to enable the receiving entity to retrieve the key. This approach obviates the sending and receiving entity having to install and manage matched or other special-purpose encryption utilities. | 2010-10-21 |
20100268935 | METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR MAINTAINING FLOW AFFINITY TO INTERNET PROTOCOL SECURITY (IPSEC) SESSIONS IN A LOAD-SHARING SECURITY GATEWAY - Methods, systems, and computer readable media for maintaining flow affinity to IPSec sessions in a load-sharing security gateway are disclosed. According to one embodiment, the method includes receiving packets at a security gateway that provides communications of packet flows between source and destination entities using IPSec sessions. For each packet, it is determined whether the packet is assigned to an existing packet flow between a source and a destination entity that is being processed by the SG. In response to determining that the packet belongs to an existing flow, the packet is forwarded to a processing element associated with that flow and IPSec processing is performed at the processing element. In response to determining that the packet does not belong to an existing flow, a new flow is defined and assigned to a next available processing element. IPSec processing is performed for the flow at the next available processing element. | 2010-10-21 |
20100268936 | INFORMATION SECURITY DEVICE AND INFORMATION SECURITY SYSTEM - Provided is a migration system considering security authentication levels and data protection strength levels of the both security devices between which data is migrated. | 2010-10-21 |
20100268937 | KEY MANAGEMENT FOR SECURE COMMUNICATION - A method and arrangement is disclosed for managing session keys for secure communication between a first and at least a second user device in a communications network. The method is characterized being independent of what type of credential each user device implements for security operations. A first user receives from a first key management server keying information and a voucher and generates a first session key. The voucher is forwarded to at least a responding user device that, with support from a second key management server communicating with the first key management server, resolves the voucher and determines a second session keys. First and second session keys are, thereafter, used for secure communication. In one embodiment the communication traverses an intermediary whereby first and second session keys protect communication with respective leg to intermediary. | 2010-10-21 |
20100268938 | SECURING DATA IN A DISPERSED STORAGE NETWORK USING SECURITY SENTINAL VALUE - A sentinel value is combined with a data segment, and encrypted. A digest of the encrypted combined data segment is calculated, and used in conjunction with an encryption key to generate a masked key. This masked key is then appended to the encrypted combined data segment and transmitted to an encoder. When the data segment is retrieved, the original encryption key can be recovered and used to decrypt the data segment. The sentinel value can then be extracted from the data segment and checked for integrity. The data segment can then be delivered, discarded, flagged, or otherwise handled based on the integrity of the sentinel value. | 2010-10-21 |
20100268939 | METHOD AND APPARATUS FOR AUTHENTICATION OF A REMOTE SESSION - Examples of systems and methods are provided for facilitating establishing a remote session between a host device and a remote server. The system may facilitate establishing a trusted relationship between a client device and the host device. The system may provide remote session login information to the host device to enable the host device to establish a first remote session with the remote server. The system may launch a second remote session with the remote server using the login information. | 2010-10-21 |
20100268940 | METHOD AND APPARATUS FOR PORTABILITY OF A REMOTE SESSION - Examples of systems and methods are provided for facilitating establishing a remote session between a host device and a remote server. The system may facilitate establishing a first remote session between a client device and the remote server. The system may facilitate establishing a trusted relationship between the client device and the host device. The system may provide remote session login information from the client device to the host device to enable the host device to establish a second remote session with the remote server. The system may facilitate termination of the first remote session at the client device after the login information is provided to the host device. | 2010-10-21 |
20100268941 | REMOTE-SESSION-TO-GO METHOD AND APPARATUS - Examples of systems and methods are provided for communication and for facilitating establishing a remote session between a client device and a remote server. The system may facilitate establishing a trusted relationship between the client device and a host device. The system may be configured to receive login information from the host device for a first remote session established between the host device and the remote server. The system may facilitate continuing the first remote session previously established between the host device and the remote server as a continued remote session between the client device and the remote server. | 2010-10-21 |
20100268942 | Systems and Methods for Using Cryptographic Keys - Systems and methods for using cryptographic keys read an existing digital certificate from a hardware cryptographic device and extract a public key from the existing digital certificate. A certificate request message is generated that identifies a new usage and/or certificate field associated with the public key. The certificate request message is signed and communicated to a certification authority. A new digital certificate is received from the certification authority that includes the new usage/field. The new digital certificate is then applied to cryptographic operations, such as signing procedures, encryption procedures and so forth using the existing key pair. | 2010-10-21 |
20100268943 | Method and System for Source Authentication in Group Communications - A method and system for authentication is provided. A central node for issuing certificates to a plurality of nodes associated with the central node in a network is also provided. The central node receives a first key from at least one node from among the plurality of nodes and generates a second key based on the received first key and generates a certificate for the at least one node. The generated certificate is transmitted to the at least one node. | 2010-10-21 |
20100268944 | INFORMATION PROCESSING DEVICE, DISC, INFORMATION PROCESSING METHOD, AND PROGRAM - A configuration is provided wherein usage restrictions of an application are determined in accordance with timestamps. A certificate revocation list (CRL) in which the revocation information of a content owner who is a providing entity of an application program recorded in a disc is recorded is referred to verify whether or not a content owner identifier recorded in an application certificate is included in the CRL, and in the case that the content owner identifier is included in the CRL, comparison between a timestamp stored in a content certificate and a CRL timestamp is executed, and in the case that the content certificate timestamp has date data equal to or later than the CRL timestamp, utilization processing of the application program is prohibited or restricted. According to the present configuration, a configuration is realized wherein an unrevoked application is not subjected to utilization restriction, and only a revoked application is subjected to utilization restriction. | 2010-10-21 |
20100268945 | SYSTEM AND METHOD FOR SECURE COMMUNICATION - A secure communication module is provided for securing communication between a client application and a network service. The secure communication module comprises an authentication identifier provider for providing the client application a pool of authentication identifiers for use in subsequent communication with the network service, and an authentication identifier validator for checking the validity of an authentication identifiers from the pool of authentication identifiers sent with the subsequent communication. | 2010-10-21 |
20100268946 | SYSTEM AND METHOD FOR GENERATING SECURED AUTHENTICATION IMAGE FILES FOR USE IN DEVICE AUTHENTICATION - A secure authentication image file is generated for use in authenticating a device. The device performs a secure authentication algorithm on the secure authentication image file and a received plaintext challenge, and outputs a cyphertext response. If the cyphertext response matches a pre-stored cyphertext string associated with the plaintext challenge, then the device is authenticated. The secure authentication image file is pre-generated in a secure environment. A plurality of key address locations are reserved in a raw memory image file. A key merger application merges the secure key data into the raw memory image file to generate a secure authentication image file. A test set of plaintext/cyphertext pairs are generated using the newly created secure authentication image file. To maintain security of the secure authentication image file, the secure key data and the raw memory image file are erased from a working memory. The test set of plaintext/cyphertext pairs are used to verify a production device containing the secure authentication image file. | 2010-10-21 |
20100268947 | SYSTEMS AND METHODS FOR REGISTERING A CLIENT DEVICE IN A DATA COMMUNICATION SYSTEM - A two-way wireless communication system comprises a central authority in communication with a plurality of client devices via both a circuit switched data communication system and a packet switched data communication system. The packet switched communication system can assign packet switched network addresses to the client devices dynamically. Therefore, the central authority can be configured to send a circuit switched message, through the circuit switched data network, to a client device requesting the client device to register with the central authority through the packet switched data network | 2010-10-21 |
20100268948 | RECORDING DEVICE AND CONTENT-DATA DISTRIBUTION SYSTEM - A recording device comprises a memory unit configured to be communicationable with an external device and to record key data for encryption of content data through an authentication process, and a controller which controls the memory unit. The memory unit comprises a normal recording unit which is accessible from the exterior through the controller without an authentication process, a protected recording unit which is accessible from the external device when authentication of a first authentication process completes, and a writing restricted/protected recording unit which is accessible from the external device when authentication of a second authentication completes and is unwritable and unaccessible from the external device when authentication of only the first authentication process completes. | 2010-10-21 |
20100268949 | METHOD FOR PROTECTING A SENSOR AND DATA OF THE SENSOR FROM MANIPULATION AND A SENSOR TO THAT END - A method for protecting a sensor and data of the sensor from manipulation, as well as a sensor to that end; in the course of the authentication, a random number being sent by a control unit to the sensor; in order to recognize manipulation of the sensor data, the sensor data from the sensor to the control unit being provided with a cryptographic integrity protection; and to prevent replay attacks, additional time-variant parameters being added to the sensor data, the sensor data, together with the integrity protection and the added time-variant parameters, being sent by the sensor to the control unit. In this context, after the authentication of the sensor, the random number or a part of the random number or a number obtained from the random number by a function is utilized for the time-variant parameters. | 2010-10-21 |
20100268950 | DEVICE AND METHOD FOR DIGITAL RIGHT MANAGEMENT - The present invention provides a method for authenticating the copy right of a device by an offline way, a digital right protection system, and a method for providing digital contents, which mainly includes embedding an authentication agent into the digital content, said authentication agent, instead of the copyright issuer at the server side, authenticates the rendering qualification of the device before rendering the digital content. If the device is a non-compliant device, the authentication agent will not permit the device to render the digital content. The technique of the invention realizes offline digital right management, so it is not restricted by the network condition and can be applied widely in various environments. | 2010-10-21 |
20100268951 | METHOD OF HANDOVER - A method for quickly performing a handover in a wireless access system is disclosed. The method for quickly performing a handover includes transmitting a handover request message to a serving base station (SBS), receiving a handover response message from the serving base station (SBS), and transmitting an uplink sequence generated by authentication-associated information of the serving base station (SBS) to a target base station (TBS). Therefore, a mobile station (MS) can complete the handover without exchanging a ranging message with the target base station (TBS), such that a communication interruption time can be minimized. | 2010-10-21 |
20100268952 | Optimization of Signing SOAP Body Element - An XML digital signature mechanism for providing message integrity. A sending party serializes a source XML document into a serialized byte array, calculates the source offset and length of the array of the signed part in the serialized byte array, and calculates a source hash value using the serialized array and the source offset and length. The serialized byte array is a non-canonicalized array. The array and source hash value used to sign a part or the whole of the serialized byte array is sent to a receiving party. The receiving party calculates the target offset and length of the signed part in the serialized byte array and calculates a target hash value of the signed part by using the array and the target offset and length. The receiving party compares the target hash value and the source hash value to verify the integrity of the target XML document. | 2010-10-21 |
20100268953 | RECORDING DEVICE, AND CONTENT-DATA PLAYBACK SYSTEM - A recording device configured to store content data in an encrypted manner, the recording device comprises a memory unit which stores various data, and a controller which controls the memory unit. The controller possesses a controller key and unique identification information, and is configured to generate a controller-unique key unique for each controller in accordance with the controller key and the identification information. The memory unit stores an MKB generated by encrypting a medium key with a device key set that is a collection of a plurality of device keys, an encrypted device key set generated by encrypting the device key set with the controller-unique key, and a device-key-set index which uniquely identifies the device key set. The controller comprises a decryption unit which obtains a device key set by decrypting the encrypted device key set with the controller-unique key, an ID generating unit which generates a medium ID from the identification information and the device-key-set index, and an authentication unit which executes an authentication process with an exterior in accordance with the device key set, the medium ID and the MKB. | 2010-10-21 |
20100268954 | METHOD OF ONE-WAY ACCESS AUTHENTICATION - A method of one-way access authentication is disclosed. The method includes the following steps. According to system parameters set up by a third entity, a second entity sends an authentication request and key distribution grouping message to a first entity. The first entity verifies the validity of the message sent from the second entity, and if it is valid, the first entity generates authentication and key response grouping message and sends it to the second entity, which verifies the validity of the message sent from the first entity, and if it is valid, the second entity generates the authentication and key confirmation grouping message and sends the message to the first entity. The first entity verifies the validity of the authentication and key conformation grouping message, and if it is valid, the authentication succeeds and the key is regarded as the master key of agreement. | 2010-10-21 |
20100268955 | CONTENT TRANSMISSION DEVICE AND CONTENT RECEPTION DEVICE - A content reception equipment for accessing an in-home content transmission equipment from a remote place executes a first authentication process with the content transmission equipment in advance, executes the remote access information sharing process required for access from a remote place, and causes the information on the content reception equipment and the remote access information to be registered in an equipment information table of the content transmission equipment. | 2010-10-21 |
20100268956 | Efficient and secure data currentness systems - Indicating data currentness includes, on any date of a sequence of dates, issuing a proof indicating the currentness status of the data during a particular time interval. The proof may be a digital signature. The time interval may be in the form of a current date and an amount of time. The proof may include a digital signature of the time interval. The proof may include a digital signature of the time interval and the data. The proof may include a digital signature of the time interval and a compact form of the data, such as a hash. Indicating data currentness may also include distributing the proofs to a plurality of unsecure units that respond to requests by users for the proofs. Indicating data currentness may also include gathering a plurality of separate pieces of data and providing a single proof for the separate pieces of data. The data may be electronic documents. | 2010-10-21 |
20100268957 | SIGNATURE GENERATING APPARATUS, SIGNATURE VERIFYING APPARATUS, AND METHODS AND PROGRAMS THEREFOR - A signature is generated by a scheme in which x denotes a secret key of a signature generating apparatus, m | 2010-10-21 |
20100268958 | Systems and Methods for Watermarking Software and Other Media - Systems and methods are disclosed for embedding information in software and/or other electronic content such that the information is difficult for an unauthorized party to detect, remove, insert, forge, and/or corrupt. The embedded information can be used to protect electronic content by identifying the content's source, thus enabling unauthorized copies or derivatives to be reliably traced, and thus facilitating effective legal recourse by the content owner. Systems and methods are also disclosed for protecting, detecting, removing, and decoding information embedded in electronic content, and for using the embedded information to protect software or other media from unauthorized analysis, attack, and/or modification. | 2010-10-21 |
20100268959 | Verifying Captured Objects Before Presentation - Objects can be extracted from data flows captured by a capture device. Each captured object can then be classified according to content. Meta-data about captured objects can be stored in a tag. In one embodiment, the present invention includes receiving a request to present a previously captured object to a user, accessing a tag associated with the requested object, the tag containing metadata related to the object, the metadata including an object signature, and verifying that the object has not been altered since capture using the object signature before presenting the object to the user. | 2010-10-21 |
20100268960 | SYSTEM AND METHOD FOR ENCRYPTING DATA - A method for encrypting data includes receiving a block of plaintext for a data set at one or more computers, acquiring a cryptographic key for the data set, generating an initialization vector for the block of plaintext based on the block of plaintext, and encrypting the block of plaintext using the cryptographic key and the initialization vector. | 2010-10-21 |
20100268961 | Method and Arrangement for User Validation - A controlled access storage device includes a resource store storing two or more resources, the resource store having two or more levels of administration, wherein at least a first administration level is adapted to provide exclusive access to at least a first resource. The system includes an access control server ( | 2010-10-21 |
20100268962 | WIRELESS RECEIVER AND METHODS FOR STORING CONTENT FROM RF SIGNALS RECEIVED BY WIRELESS RECEIVER - A wireless receiver and methods for storing content from RF signals received by the wireless receiver are provided. The wireless receiver includes a microprocessor and an RF receiver configured to operably communicate with the microprocessor. The RF receiver is configured to receive an RF signal having digital content therein. The wireless receiver further includes a detachable memory device configured to operably communicate with the microprocessor. The detachable memory device has a unique serial number stored therein. The microprocessor is configured to retrieve the unique serial number from the detachable memory device. The microprocessor is further configured to receive the digital content from the RF receiver and to encrypt the digital content utilizing the unique serial number to obtain encrypted digital content. The microprocessor is further configured to store the encrypted digital content on the detachable memory device. | 2010-10-21 |
20100268963 | INTER-BUS COMMUNICATION INTERFACE DEVICE AND DATA SECURITY DEVICE - There is provided an inter-bus communication interface device capable of efficiently performing transfer of data between a plurality of devices connected to different buses, respectively. When communication data is transmitted, a first device writes the communication data into a buffer, whereas when communication control information is transmitted, the first device writes the communication control information into a register. A control circuit passes the communication data stored in the buffer to a second device, and passes the communication control information stored in the register to a second device. | 2010-10-21 |
20100268964 | METHOD FOR EVALUATING USER'S RIGHTS STORED IN A SECURITY MODULE - The aim of the present invention consists of reducing the switching time from one reception channel to another. In fact, this reduction will be particularly discernable since the number of different rights stored in a security module of a multimedia unit or decoder is high. When a user selects a service among those proposed by an electronic programs guide, an access control module explores a stored service information table in order to extract an access condition associated to the service. This access condition allows determining an index in a rights table stored in the access control module of a right that fulfils the access condition. The access control module transmits to the security module the index thus determined alone or accompanied by a control message. This index allows the security module to find quickly the right that it compares afterwards with the access condition included in the control message after decryption of the latter. | 2010-10-21 |
20100268965 | AUTO-NEGOTIATION OF CONTENT FORMATS USING A SECURE COMPONENT MODEL - In accordance with one embodiment of the present invention, secure content objects are transcoded from an input format to an output format based upon identified capabilities of a receiving device. In one embodiment, a plurality of trusted processing components are identified to collectively transcode the secure content object from the identified input format to the determined output format. In one embodiment, each of the trusted processing components are authenticated prior to operating on the secure content object. | 2010-10-21 |
20100268966 | Efficient and secure data storage utilizing a dispersed data storage system - A method of securely storing data to a dispersed data storage system is disclosed. A data segment is arranged along the columns or rows of an appropriately sized matrix. Data slices are then created based on either the columns or the rows so that no consecutive data is stored in a data slice. Each data slice is then stored in a separate storage node. | 2010-10-21 |
20100268967 | INFORMATION PROCESSING APPARATUS, AND METHOD AND COMPUTER PROGRAM PRODUCT FOR VERIFICATION - An information processing apparatus includes a main memory unit storing while on-power; an auxiliary storage unit functionable even off-power; a control unit performing hibernation of generating operating-state data indicating a state when the power is lost, storing the data in the auxiliary storage unit, and, when restored, reading the data from the auxiliary storage unit; and a security chip that including a configuration register, encrypts data, and storing the data in the auxiliary storage unit. The control unit includes: a first registration unit performing, when the data is generated, calculation based thereon to obtain a calculated value; a second registration unit performing, when the data is read from the auxiliary storage unit at the hibernation, calculation based on the data to obtain a calculated value to write it into the configuration register; and a verification unit performing verification at boot-up from the hibernation based on the value written. | 2010-10-21 |
20100268968 | MANAGING PROCESSOR POWER-PERFORMANCE STATES - Disclosed are systems, methods, and computer program products for managing power states in processors of a data processing system. In one embodiment, the invention is directed to a data processing system having dynamically configurable power-performance states (“pstates”). The data processing system includes a processor configured to operate at multiple states of frequency and voltage. The data processing system also has a power manager module configured to monitor operation of the data processing system. The data processing system further includes a pstates table having a plurality of pstate definitions, wherein each pstate definition includes a voltage value, a frequency value, and at least one unique pointer that indicates a transition from a given pstate to a different pstate. The voltage value, frequency value, and unique pointer of a given pstate definition are configurable, during operation of the data processing system, by the power manager module in response to changes in the operating parameters of the data processing system. | 2010-10-21 |
20100268969 | POWER SUPPLY CONVERTING CIRCUIT - A power supply converting circuit includes a multi-phase pulse-width modulation (PWM) controller, a single-phase PWM controller, some first voltage converting circuits, a second voltage converting circuit, first and second electrical switch units. The multi-phase PWM controller provides some first PWM signals and a second PWM signal. The single-phase PWM controller provides a third PWM signal. The first voltage converting circuits receive the first PWM signals to output a first power supply to a central processing unit (CPU) chipset. The first electrical switch unit receives the second and third PWM signals to selectively output the second or third PWM signal to the second voltage converting circuit to output one of the first and second power supplies. The second electrical switch unit receives one of the first and second power supplies from the second voltage converting circuit to selectively output one of the first and second power supplies to the CPU chipset. | 2010-10-21 |
20100268970 | PORTABLE COMPUTER AND CHARGING METHOD THEREOF - A portable computer and a charging method thereof are provided. The portable computer includes a charge integrated circuit (IC), a basic input/output system (BIOS) and embedded controller (EC), a south bridge chip, a north bridge chip and a central processing unit (CPU). After the portable computer is connected to a battery, the BIOS and EC controls the south bridge chip to read a sealed security bit of the battery and checks whether the sealed security bit equals a default value. The BIOS and EC controls the south bridge chip to read a battery data of the battery if the sealed security bit equals default value. The BIOS and EC controls the charge IC via the south bridge chip to charge the battery according to the battery data. The CPU controls the south bridge chip and the north bridge chip. | 2010-10-21 |
20100268971 | METHOD AND APPARATUS FOR REDUCING POWER CONSUMPTION DURING WIRELESS DATA TRANSFER - Apparatus for reducing power consumption during wireless data transfer between a host device and another device is disclosed. The apparatus comprises a plurality of wireless modules, each of the plurality of wireless modules comprising a different wireless protocol, each wireless protocol having a different transmission range and data transfer rate. The apparatus also comprises a processor having a determination module. The determination module is configured to determine which of the plurality of wireless protocols is able to be used for the wireless data transfer, and which of the different wireless protocols able to be used for the wireless data transfer has a power consumption that is the lowest of the wireless protocols able to be used for the wireless data transfer, the wireless protocol so determined being used for the wireless data transfer. A corresponding method is also disclosed. | 2010-10-21 |
20100268972 | METHOD AND APPARATUS FOR CONTROLLING CLOCK FREQUENCY - A clock frequency adjusting method capable of reducing power consumption without reducing a response speed for a command output from a host in an idle mode is provided. In the clock frequency adjusting method, a central processing unit (CPU) generates a detection signal according to whether an interrupt signal is activated, and a frequency adjusting circuit provides a clock signal having a first frequency or a second frequency higher than the first frequency to the CPU in response to the detection signal. | 2010-10-21 |
20100268973 | INTERFACE CARD, NETWORK DEVICE HAVING THE SAME AND CONTROL METHOD THEREOF - An interface card is capable of communicating with an external device and includes a power supplier; a non-volatile memory which stores executable instructions to operate in an active-mode and a sleep-mode; a small-capacity volatile memory which is supplied with power in the sleep mode; a transmitter-receiver which transmits and receives packet data to/from the external device; and a controller which retrieves sleep-mode instructions stored in the non-volatile memory and loads the sleep mode instructions in the small-capacity volatile memory to transition the interface card into the sleep mode if the transmitter-receiver does not receive the packet data for predetermined time period in an active mode. The interface card processes certain packet data in the sleep mode and transitions back into the active mode when sleep mode operations determine that the packet data cannot be processed in the sleep mode. The non-volatile memory, and other components of an external circuit, is powered down when the interface card is in the sleep mode. | 2010-10-21 |
20100268974 | Using Power Proxies Combined with On-Chip Actuators to Meet a Defined Power Target - A mechanism is provided for using a power proxy unit combined with on-chip actuators to meet a defined power target value identifying a target power consumption of a component of a data processing system. A power manager in the data processing system identifies a proxy power threshold value, for the defined power target value, identifying a maximum power usage for the component, and a power usage estimate value identifying a current power usage estimate for the component. The power manager sends a set of signals to one or more on-chip actuators in the power proxy unit associated with the component in response to the power usage estimate value being greater than the power proxy threshold value. The one or more on-chip actuators adjusts a set of operational parameters associated with the component in order to meet the defined power target value. | 2010-10-21 |
20100268975 | On-Chip Power Proxy Based Architecture - A method for estimating power consumption within a multi-core microprocessor chip is provided. An authorized user selects a set of activities to be monitored. A value for each activity of the set of activities is stored in a separate counter of a set of counters, forming a set of stored values. The value comprises the count multiplied by a weight factor specific to the activity. The set of activities are grouped into subsets. The stored values corresponding to each activity in each subset are summed, forming a total value for each subset. The total value of each subset is multiplied by a factor corresponding to the subset, forming a scaled value for each subset. The scaled value of each subset is summed, forming a power usage value. A power manager adjusts the operational parameters of the unit based on a comparison of the power usage value to a threshold value. | 2010-10-21 |
20100268976 | Clock Distribution With Forward Frequency Error Information - This disclosure relates to providing an information signal to one or more sub-systems within a wireless communications device, where the information signal enables the sub-systems to operate based on virtually corrected reference frequency clock signal(s). | 2010-10-21 |
20100268977 | METHOD AND APPARATUS FOR ACCESSING MEMORY UNITS - An apparatus for accessing a memory is provided, and comprises a first device, a second device, an adjusting unit, a buffer and a memory. The first device operates at a first clock. The second device operates at a second clock. The buffer reads data from the second device to be written to the memory unit and reads from the memory unit to be read by the first device. The adjusting unit masks a portion of pulses of the first clock to generate an adjusted clock, wherein the first device reads the buffer according to the adjusted clock. The apparatus for accessing a memory is a video processor, and the first device and the second device are an input unit and an output unit of the video processor. | 2010-10-21 |
20100268978 | APPARATUS AND METHOD TO INTERFACE TWO DIFFERENT CLOCK DOMAINS - A gearbox is placed between two clock domains to allow data to be transferred from one domain to the other. Although the two domains may operate at the same clock frequency, typically one domain has a faster clock speed than the other. The gearbox is disposed between the two clock domains to control timing of data transfer from one to the other, by selecting a pattern which identifies when data is made transparent for the transfer. The gearbox allows a number of clock ratios to be selected, so that a particular clock ratio between the two domains may be readily selected in the gearbox for the data transfer. | 2010-10-21 |
20100268979 | METHOD AND SYSTEM FOR SYNTAX ERROR REPAIR IN PROGRAMMING LANGUAGES - The described embodiments present techniques for recovering from syntax errors. These techniques correct potential errors while preserving the shape of the parse tree, and the specific implementation of the techniques can be automatically generated from the grammar. These techniques may operate by looking back at states associated with previously-received tokens to determine pair matching status, when a synchronizing symbol is received. The techniques can respond to the pair matching status determination by potentially adding a synthesized token or by deleting a token that has already been received. The techniques may use a structure referred to herein as a tuple to assist with the evaluation of the pair matching status. Some of the techniques utilize indentation information to evaluate the pair matching status, while other techniques ignore such information. The described embodiments also include a technique for automatically generating the tuples from a set of grammar rules associated with the parser. | 2010-10-21 |
20100268980 | NODE APPARATUS MOUNTED IN VEHICLE AND IN-VEHICLE NETWORK SYSTEM - An in-vehicle network system includes plural electronic control units data-communicably connected via a network. The electronic control units include a master unit and a node apparatus composed of electronic control units other than master unit. In the node apparatus, a node time locally used as a reference time by the node apparatus is produced, and a system reference time is received from the master unit via the network. A node time rate, which is a rate of change of the node time per predetermined time period, is calculated based on changes in the node time. A reference time rate, which is a rate of change of the system reference time per the predetermined time period, is also calculated based on changes in the received system reference. The node time production is controlled such that the node time reduces a difference between the node and reference time rates. | 2010-10-21 |
20100268981 | System and Method for Tunneling System Error Handling Between Communications Systems - A system and method for tunneling system error handling between communications systems are provided. A method for error handling by a controller in an interworking system includes receiving a notification of an occurrence of an error in a first communications system, determining if the error is a long-term error, causing a device in a second communications system with a session in the first communications system to halt communications with the first communications system if the error is a long-term error, and not causing the device in the second communications system with the session in the first communications system to halt communications with the first communications system if the error is not a long-term error. | 2010-10-21 |
20100268982 | ENFORCEMENT PROCESS FOR CORRECTION OF HARDWARE AND SOFTWARE DEFECTS - A method and apparatus for improvement of computer-related products to solve problems caused by artificially embedded locks, barriers, defects, and the like, that force a consumer to needlessly upgrade hardware or software on a computer. An independent developer may procure access to a product, develop a testing regimen for functionality of the product, and perform evaluations to identify sources of any operational defects found. Accordingly, the developer may then provide a generalized testing regimen to test instances of product provided by a supplier, identify those containing the flaw, and may optionally provide a solution to the flaw, where practicable. The independent developer may obtain intellectual property rights in the testing, solution or both for the product. Thus, by notifying a supplier, an independent developer may become a supplier of testing or solution systems, motivating a supplier by one of several mechanisms. The developer may obtain a legal status with respect to the supplier by becoming a customer or user, in order to provide motivation to a recalcitrant supplier not designed to take responsibility for defects known and continued in marketed products. | 2010-10-21 |
20100268983 | Computer System and Method of Control thereof - A computer system is described having a plurality of hardware resources, a plurality of virtual partitions having allocated thereto some of those of hardware resources or parts thereof, said virtual partitions having an operating system loaded thereon, a partition monitoring application layer, which is capable of determining whether one or more of the partitions has failed, wherein said partition monitoring application layer also includes at least one hardware resource diagnostic function which is capable of interrogating at least one of the hardware resources allocated to a partition after failure of said partition, and a hardware resource reallocation function which is triggered when the hardware diagnostic function determines that one or more particular hardware resources associated with a failed partition is healthy, and which reallocates that healthy resource to an alternate healthy partition. A method of reallocating such hardware resources is also disclosed. | 2010-10-21 |
20100268984 | Delete Of Cache Line With Correctable Error - A processing unit includes a processor core and a cache memory coupled to the processor core. The cache memory includes a data array, a directory of the data array, error detection logic that sequentially detects a first, second and third correctable errors in the data array of the cache memory and provides indications of detection of the first, second and third correctable errors, and control circuitry that, responsive to the indication of the third correctable error and an indication that the first and second correctable errors occurred at too high a frequency, marks an entry of the data array containing a cache line having the third correctable error as deleted in the directory of the cache memory regardless of which entry of the data array contains a cache line having the second correctable error. | 2010-10-21 |
20100268985 | DATA RECOVERY IN A SOLID STATE STORAGE SYSTEM - Methods for data recovery and memory systems are provided. According to at least one such method, when defective data is read from a memory location, the data is recovered by an XOR operation on the remaining good data and associated RAID data to reconstruct the defective data. The defective data is excluded from the XOR operation. | 2010-10-21 |
20100268986 | MULTI-NODE CONFIGURATION OF PROCESSOR CARDS CONNECTED VIA PROCESSOR FABRICS - Provided is a system comprising a first node comprising a plurality of processor cards each including a processor fabric, wherein the processor cards in the first node connect via their processor fabrics; a second node comprising a plurality of processor cards each including a processor fabric, wherein the processor cards in the second node connect via their processor fabrics; and a plurality of communication interfaces, wherein each interface connects one processor card in the second node to one processor card in the first node to enable communication between the connected processor cards to coordinate processor operations between the connected processor cards in the first and second nodes. | 2010-10-21 |
20100268987 | Circuits And Methods For Processors With Multiple Redundancy Techniques For Mitigating Radiation Errors - Embodiments of circuits for processors with multiple redundancy techniques for mitigating radiation errors are described herein. Other embodiments and related methods and examples are also described herein. | 2010-10-21 |
20100268988 | SECURE FLASH MEMORY USING ERROR CORRECTING CODE CIRCUITRY - A processor and memory system includes memory, a table of exceptions, and a processor. The memory includes a plurality of memory blocks. The table of exceptions identifies at least one of the plurality of memory blocks that includes an expected error. The processor diagnoses a security fault based on data stored in at least one of the plurality of memory blocks and the table of exceptions. | 2010-10-21 |
20100268989 | IMAGE FORMING APPARATUS - There is provided an image forming apparatus which adopts a distributed control system and increases the error detection accuracy of each control unit. To accomplish this, the image forming apparatus includes a master control unit that controls the overall image forming apparatus, a plurality of sub-master control units that control a plurality of functions for performing image formation, and a plurality of salve control units that control loads for implementing a plurality of functions. The master control unit determines a diagnosis path for performing a diagnosis process for an error using the signal lines and connection bridge connected to the respective control units. The master control unit performs the diagnosis process for an error in accordance with the determined diagnosis path. | 2010-10-21 |
20100268990 | TRACING SUPPORT FOR INTERCONNECT FABRIC - Complex on-chip interconnect fabrics, particularly those that include point-to-point interconnects and coherent routing networks, can present significant challenges for conventional trace techniques that may be applied in an effort to efficiently provide an external debugger with visibility into on-chip interconnect transactions. Embodiments described herein generate and supply separate in-circuit-trace messages including address messages and data messages, which are sent out (i.e., off-chip) to external debug tools generally without delay and coincident with the distinct, but related, trace events within address and data paths of the interconnect fabric. These separate message instances embed appropriate tag and mark values to allow the message instances to be post-processed and correlated by the external debug tools so as to reconstruct the transaction information for operations performed in the on-chip interconnect. | 2010-10-21 |
20100268991 | APPARATUS, SYSTEM, AND METHOD FOR VALIDATING APPLICATION SERVER REPLICATION ERRORS - An apparatus, system, and method are disclosed for validating application server replication errors. The method includes receiving a first information message with a test sequence from a caller. The caller is engaged in a communication session with a callee according to a communication protocol and the communication session is managed by a first application server. The method also includes storing the test sequence in a replicable data structure on the first application server. The replicable data structure is replicated to a second application server to form a replicated data structure and both servers operate within an active-active configuration. The method also includes receiving a second information message from the caller. The second information message includes a confirmation sequence. In addition, the method includes determining a replication error in response to comparing the stored test sequence in the replicated data structure with the confirmation sequence. | 2010-10-21 |
20100268992 | METHOD AND SYSTEM FOR PROTOCOL EMBEDDED AUTOMATED TEST CONTROL - A method and system of an embodiment may include executing a first test case using a user record provisioned on a network, the first test case comprising transmitting at least a first portion of the data to a network element being tested and receiving a response from the network element being tested in the first test case based at least in part on the configuration data for the first test case contained in the transmitted first portion of the data, executing a second test case using the user record provisioned on the network, the second test case comprising transmitting at least a second portion of the data to a network element being tested and receiving a response from the network element being tested in the second test case based at least in part on configuration data for the second test case contained in the transmitted second portion of the data. | 2010-10-21 |
20100268993 | DISABLEMENT OF AN EXCEPTION GENERATING OPERATION OF A CLIENT SYSTEM - A method and system of disablement of an exception generating operation of a client system are disclosed. In an embodiment, a method is disclosed in which a snapshot of a client system is acquired. An execution of the client system is recorded, and a system wide exception is intercepted before it causes a client system crash. The execution of the client system is replayed from the snapshot of the client system, and an operation that generates the system wide exception is disabled. | 2010-10-21 |
20100268994 | AUTOMATIC KEYBOARD TESTING SYSTEM - An automatic keyboard testing system includes a computer, an automatic testing program and a testing frame. A keyboard circuit board to be tested in placed on the testing frame. The automatic testing program is installed in the computer for generating a testing signal and has a predetermined time period. The testing frame generates a simulating signal according to the testing signal and conducts a key intersection point corresponding to the simulating signal, so that the keyboard circuit board output a key scanning code corresponding to the conducted key intersection point to the computer. The automatic testing program discriminates whether the key scanning code is transmitted to the computer within the predetermined time period. | 2010-10-21 |
20100268995 | HARDWARE PROCESS TRACE FACILITY - A method for tracing thread bus transactions in a multiprocessor system comprises decoding, by a processor, a first thread instruction of a thread, the thread comprising an ordered series of thread instructions. In the event the first thread instruction is a set bus trace enable bit (BTEB) instruction, the processor sets a bus trace enable bit corresponding to the thread. In the event the BTEB is set, the processor determines whether the first thread instruction is a trace-eligible instruction and, in the event the first thread instruction is a trace-eligible instruction, and the BTEB is set, the processor sets a snoop tag trace enable bit (STTEB). A hardware trace monitor (HTM) monitors bus transactions, each bus transaction comprising a STTE. In the event a monitored bus transaction comprises a set STTEB, the HTM stores the bus transaction as trace data. In the event a monitored bus transaction comprises a reset STTEB, the HTM does not store the bus transaction as trace data. | 2010-10-21 |
20100268996 | Systems and Methods for Predicting Failure of a Storage Medium - Various embodiments of the present invention provide systems and methods for determining storage medium health. For example, a storage device is disclosed that includes a storage medium and a data processing circuit. The data processing circuit receives a data set derived from the storage medium. The data processing circuit includes a data detector circuit, a data decoder circuit, and a health detection circuit. The data detector circuit receives the data set and provides a detected output. The data decoder circuit receives a derivative of the detected output and provides a decoded output. The health detection circuit receives an indication of a number of times that the data set is processed through the combination of the data detector circuit and the data decoder circuit. Further, the health detection circuit generates an indirect health status of the storage medium based at least in part on the number of times that the data set is processed through the combination of the data detector circuit and the data decoder circuit. | 2010-10-21 |
20100268997 | METHOD AND DEVICE FOR MONITORING AND CONTROLLING THE OPERATIONAL PERFORMANCE OF A COMPUTER PROCESSOR SYSTEM - In order to monitor and control the operational performance of a computer system or processor system ( | 2010-10-21 |
20100268998 | MASTER/SLAVE COMMUNICATION SYSTEM - A master includes a unit configured to register, for each slave, an expected communication time needed to exchange control data; a unit configured to register a slave in which a communication error is detected during exchange of the control data in a communication period; and a unit configured to re-execute exchange of the control data with the registered slave in the same communication period as that in which the communication error is detected. The unit configured to re-execute exchange of control data calculates a remaining resending time that can be used to re-execute exchange of the control data and, when the remaining resending time is longer than the expected communication time of the registered slave, resends the control data. | 2010-10-21 |
20100268999 | MEMORY TESTING WITH SNOOP CAPABILITIES IN A DATA PROCESSING SYSTEM - A method of testing a memory includes generating a plurality of addresses, such as a test address, accessing contents of each of the plurality of addresses and storing them in storage circuitry, performing a test on the plurality of addresses, accessing the memory test circuitry by sending an access address to snooping circuitry, determining if the access address matches at least one of the plurality of addresses and generating at least one hit indicator in response thereto, generating a snoop miss indicator, determining if it indicates a miss, if it indicates a miss, accessing the memory in response to the access address, and if it does not indicate a miss, either storing snooped data from a interconnect master to a selected portion of the storage circuitry or reading the snooped data from the selected portion of the storage circuitry to the interconnect master. | 2010-10-21 |
20100269000 | METHODS AND APPARATUSES FOR MANAGING BAD MEMORY CELL - A method for managing a bad cell is provided. The method includes reading status data from a page buffer and detecting a location of a bad cell from the status data. The method may further include remapping a bad address for the bad cell to a spare address for a spare cell in the same page. | 2010-10-21 |
20100269001 | TESTING SYSTEM AND METHOD THEREOF - Testing system capable of detecting different kinds of memory faults of a memory under I/O compression includes a data pattern selection circuit, writing pattern selection units, reading pattern selection units, and a data comparison circuit. The data pattern selection circuit converts a testing data into different data patterns by the writing pattern selection units and accordingly writes to the corresponding memory data ends in order to allow the corresponding memory cells to store the data with the corresponding data pattern. The data comparison circuit executes reverse-converting through the reading pattern selection units for comparing if the data stored in the memory cells corresponding to each memory data end are matched and accordingly determines if a failure memory cell exists in the memory. | 2010-10-21 |
20100269002 | Pseudo-Random Balanced Scan Burnin - According to various illustrative embodiments, a method and system for toggling a scan enable signal are described. In one aspect, the method comprises setting a scanin seed and resetting a monitor, generating random shift patterns, and resetting the monitor a second time. The method also comprises generating the random shift patterns a second time and strobing an activity flag. The method also comprises resetting the monitor a third time and enabling the scan enable signal toggling mechanism, and generating random shift/capture patterns repeatedly at least a predetermined number of times. | 2010-10-21 |
20100269003 | DELAY FAULT DIAGNOSIS PROGRAM - An extraction unit of fault assumption and a finish-point FF is provided, the fault assumption is selected from fault assumption information, and a logic trace is executed from the fault assumption toward an output side. A test result of a finish-point FF obtained as a result of the trace from the fault assumption is determined. The maximum value and the minimum value of the propagation route up to the finish-point FF are determined, and a delay margin is determined from the values. A delay range is determined by using the delay margin and the test result, and a fault candidate and a delay range of the delay fault are specified by the process of the determination of the fault candidate and the delay range. | 2010-10-21 |
20100269004 | State Retention using a variable retention voltage - A data processing apparatus is provided with state retention circuits 14 into which state values are saved from nodes within the data processing circuitry when entering a sleep mode from an active mode. Error management circuitry | 2010-10-21 |
20100269005 | APPARATUS AND METHOD FOR IMPROVED RELIABILITY OF WIRELESS COMMUNICATIONS USING PACKET COMBINATION-BASED ERROR CORRECTION - Various techniques are disclosed for improved reliability of wireless communications using packet combination-based error correction. For example, a method includes receiving a first message transmitted wirelessly, where the first message contains a first copy of a data packet and has at least one error. The method also includes receiving a second message transmitted wirelessly, where the second message contains a second copy of the data packet and has at least one error. The method further includes identifying a set of bit positions based on where the first and second copies of the data packet differ and modifying the set of bit positions to produce a modified set of bit positions. In addition, the method includes modifying one or more bit values in the modified set of bit positions to produce at least one modified copy of the data packet and determining if the at least one modified copy of the data packet is error-free. | 2010-10-21 |
20100269006 | APPARATUS AND METHOD FOR TRANSMITTING AND RECEIVING AUTOMATIC REPEAT REQUEST FEEDBACK MESSAGE IN WIRELESS COMMUNICATION SYSTEM - An apparatus and a method for transmitting and receiving an Automatic Repeat reQuest (ARQ) feedback message in a wireless communication system are provided. A method for receiving an ARQ feedback message at a transmitting unit in a wireless communication system includes allocating a fixed-size resource for transmitting an ARQ feedback message, to a receiving unit, the resource being an unsolicited bandwidth, and receiving an ARQ feedback message or a resource request message from the receiving unit over the fixed-size resource allocated. | 2010-10-21 |
20100269007 | DIGITIZED RADAR INFORMATION REDUNDANCY METHOD AND SYSTEM - The present invention relates to a real time radar data transmission system and process for transmitting forward error correctable data to a plurality of parallel communication channels. | 2010-10-21 |
20100269008 | DISPERSED DATA STORAGE SYSTEM DATA DECODING AND DECRYPTION - A computing system retrieves securely stored encrypted and encoded data from a dispersed data storage system. The computing system includes a processing module and a plurality of storage units. The processing module includes an error decoder and a decryptor and to decode and decrypt the encrypted and encoded data retrieved from the dispersed data storage system utilizing a read command to the storage units. The storage units retrieve the encrypted and encoded data and send the encrypted and encoded data to the processing module when receiving the read command. | 2010-10-21 |
20100269009 | ENCODER, DECODER, ENCODING METHOD, AND DECODING METHOD - There is provided an encoder that provides a termination sequence with a simple structure for LDPC-CC encoding and reduces an amount of the termination sequence transmitted to a transmission line. The LDPC-CC encoder ( | 2010-10-21 |