42nd week of 2021 patent applcation highlights part 62 |
Patent application number | Title | Published |
20210327661 | KEYBOARD HAVING TOUCH-SENSITIVE KEYCAPS WHICH ARE ALSO PRESSABLE AND METHOD FOR MAKING SAME - A keyboard able to recognize fingertip touches and touches in gestures such as fingertip sliding, in addition to simple presses on keycaps, includes a plurality of keycaps, a touch layer, a function trigger layer, a touch controller, and a function controller. Each keycap has an operation surface for receiving the pressings and touches. The touch layer generates touch sensing signals according to the touches, the function component generates key signals according to the pressings. The touch controller obtains touch information from the touch sensing signals. The function controller triggers desired key functions according to the key signals received. A method for making such keyboard is also disclosed. | 2021-10-21 |
20210327662 | CONTROL DEVICE BASE THAT ATTACHES TO THE PADDLE ACTUATOR OF A MECHANICAL SWITCH - A remote control device may control electrical loads and/or load control devices of a load control system without accessing electrical wiring. The remote control device may be configured to be mounted over an installed mechanical switch having a paddle actuator and may include a base and a control unit that is configured to be removably attached to the base. The base may include a frame, a clamp arm, a screw, and/or a sleeve. The clamp arm may be configured to secure the base to a protruding portion of the paddle actuator. The clamp arm may be attached to the frame at a pivot joint. The clamp arm may be configured to pivot about the pivot joint. The pivot joint may be located proximate to an endpoint or a midpoint of the frame. | 2021-10-21 |
20210327663 | SWITCHING DEVICE - A switching device for low-voltage or medium-voltage applications including: one or more electric poles; for each electric pole, at least a fixed contact and at least a movable contact, each movable contact being reversibly movable between a coupled position, at which the movable contact is coupled with a corresponding fixed contact, and an uncoupled position, at which the movable contact is separated from the fixed contact, wherein a separation gap is present between the movable contact and the fixed contact, when the movable contact is in the uncoupled position. The switching device includes, for each electric pole, at least an arc-diverting element made of electrically insulating material. | 2021-10-21 |
20210327664 | CONTACTOR WITH ARC SUPPRESSOR - A contactor includes a housing holding fixed contacts and a movable contact and an arc suppressor in the housing having magnet assemblies. The first magnet assembly includes first and second magnets aligned with the first and second contacts and the second magnet assembly includes third and fourth magnets aligned with the first and second contacts. The first and second magnets are arranged in the cavity such that north B-fields of the first and second magnets face in opposite directions. The third and fourth magnets are arranged in the cavity such that north B-fields of the third and fourth magnets face in opposite directions. | 2021-10-21 |
20210327665 | DEVICE FOR INTERRUPTING NON-SHORT CIRCUIT CURRENTS ONLY, IN PARTICULAR DISCONNECTOR OR EARTHING SWITCH - The present invention relates to a device for interrupting non-short circuit currents only, and in particular relates to a disconnector, more particularly high voltage disconnector, or to an earthing switch, more particularly make-proof earthing switch, and further relates to a low voltage circuit breaker. The device comprises at least two contacts movable in relation to each other between a closed state and an open state and defining an arcing region, in which an arc is generated during a current interrupting operation and in which an arc-quenching medium comprising an organofluorine compound is present. According to the application, a counter-arcing component is allocated to the arcing region, the counter-arcing component being designed for counteracting the generation of an arc and/or being designed for supporting the extinction of an arc. | 2021-10-21 |
20210327666 | VACUUM INTERRUPTER AND HIGH-VOLTAGE SWITCHING ASSEMBLY - A vacuum interrupter includes a housing having at least one annular ceramic insulating element which forms a vacuum chamber. A contact system has two contacts which are movable relative to one another. A capacitive element has two electrodes and a dielectric material disposed between the electrodes. The capacitive element is form-lockingly mounted on the insulating element and has a capacitance between 400 pF and 4000 pF. A high-voltage switching assembly including the vacuum interrupter is also provided. | 2021-10-21 |
20210327667 | SENSOR SWITCH - A sensor switch includes a ceramic body including an intermediate layer assembly having an inner peripheral surface with a through hole, a first side layer assembly having a first groove, and a second side layer assembly having a second groove. A first conductive layer is disposed in the first groove, and has a first contact surface. A second conductive layer is disposed in the second groove, and has a second contact surface. The inner peripheral surface and the first and second contact surfaces cooperatively define a sensing cavity. A conductive member is rollably disposed in the sensing cavity and is movable between closed and open circuit positions to achieve a sensing effect. | 2021-10-21 |
20210327668 | SENSOR SWITCH - A sensor switch includes abase unit having bottom, top and intermediate layer assemblies cooperatively defining a receiving space. One of the bottom, top and intermediate layer assemblies has a mounting surface. A sensor unit is disposed in the receiving space and includes a light emitter, a light receiver, and a rolling member for changing the amount of light received by the light receiver. A conducting unit includes a power supply section, a power supply conducting element disposed on the mounting surface, and a signal conducting element disposed on the mounting surface and spaced apart from the power supply conducting element. | 2021-10-21 |
20210327669 | Controlling a Controllably Conductive Device Based on Zero-Crossing Detection - A load control device may control power delivered to an electrical load from an AC power source. The load control device may include a controllably conductive device adapted to be coupled in series electrical connection between the AC power source and the electrical load, a zero-cross detect circuit configured to generate a zero-cross signal representative of the zero-crossings of an AC voltage. The zero-cross signal may be characterized by pulses occurring in time with the zero-crossings of the AC voltage. The load control device may include a control circuit operatively coupled to the controllably conductive device and the zero cross detect circuit. The control circuit may be configured to identify a rising-edge time and a falling-edge time of one of the pulses of the zero-cross signal, and may control a conductive state of the controllably conductive device based on the rising-edge time and the falling-edge time of the pulse. | 2021-10-21 |
20210327670 | ELECTRONIC COMPONENT MODULE - An electronic component module according to the present disclosure includes a fuse, a relay, a first conductor, a first connecting conductor, a second conductor, a second connecting conductor, and a third conductor. The first conductor, the second conductor, and the third conductor are arranged in the order of the third conductor, the second conductor, and the first conductor in a first direction. A first fuse terminal is connected to a plate-shaped portion of the first connecting conductor. A second fuse terminal is connected to a plate-shaped portion of the second connecting conductor. A first relay terminal is connected to an end of the second conductor that is located in a direction opposite to the first direction. A second relay terminal is connected to an end of the third conductor that is located in the first direction. | 2021-10-21 |
20210327671 | ELECTROMAGNETIC RELAY - An electromagnetic relay includes a fixed contact, a movable contact piece having a movable contact, a drive shaft, an electromagnetic drive device, and a positioning portion. The movable contact piece is movable in a first direction contacting the fixed contact and in a second direction separating from the fixed contact. The electromagnetic drive device includes a movable iron core integrally movably connected to the drive shaft. The electromagnetic drive device switches between a contact state in which the movable contact comes into contact with the fixed contact and a separate state in which the movable contact is separated from the fixed contact by moving the drive shaft with the movable iron core. The positioning portion positions the drive shaft or the movable iron core in the separate state. The drive shaft or the movable iron core includes a first inclined portion that contacts the positioning portion in the separate state. | 2021-10-21 |
20210327672 | HIGH-RESOLUTION DISPLAY PLASMA MODULE AND MANUFACTURING METHOD THEREOF - The present invention belongs to the field of electronic display technology, and relates to a high-resolution display plasma module and a manufacturing method thereof. The high-resolution display plasma module includes a pixel electrode and a transparent electrode. A display plasma is provided between the pixel electrode and the transparent electrode, and a spacer frame is provided around the display plasma. A plasma barrier enclosure array is provided on the pixel electrode. The plasma barrier enclosure array includes a plurality of plasma barrier enclosures arranged in an array. The pixel electrode includes a plurality of pixel electrode units arranged in an array. The plasma barrier enclosure is located on the gap between the pixel electrode units. Each plasma barrier enclosure contains only one pixel electrode unit. | 2021-10-21 |
20210327673 | A SHIELDED X-RAY RADIATION APPARATUS - A shielded X-ray radiation apparatus is provided comprising an X-ray source, an X-ray attenuation shield including an elongate cavity to house the X-ray source and incorporating a region to accommodate a sample, a neutron attenuation shield, and a gamma attenuation shield. The neutron attenuation shield is situated adjacent to and substantially surrounds the X-ray attenuation shield and the gamma attenuation shield is adjacent to and substantially surrounds the neutron attenuation shield. In some embodiments a removable sample insertion means is provided to insert samples into the elongate cavity and which is composed of adjacent blocks of material, each respective block having a thickness and a composition which substantially matches the thickness and a composition of one of the X-ray attenuation, neutron attenuation and gamma-ray attenuation shields. | 2021-10-21 |
20210327674 | ELECTRON SOURCE, METHOD FOR MANUFACTURING THE SAME, AND ELECTRON BEAM DEVICE USING THE SAME - The invention provides an electron source including a columnar chip of a hexaboride single crystal, a metal pipe that holds the columnar chip of the hexaboride single crystal, and a filament connected to the metal pipe at a central portion. The columnar chip of the hexaboride single crystal is formed into a cone shape at a portion closer to a tip than a portion held in the metal pipe, and a tip end portion having the cone shape has a (310) crystal face. Schottky electrons are emitted from the (310) crystal face. According to the invention, it is possible to provide a novel electron source having monochromaticity, long-term stability of an emitter current, and high current density. | 2021-10-21 |
20210327675 | SYSTEM AND METHOD FOR GENERATING AND ANALYZING ROUGHNESS MEASUREMENTS - In one embodiment, a method includes receiving measured linescan information describing a pattern structure of a feature, applying the received measured linescan information to an inverse linescan model that relates measured linescan information to feature geometry information, and identifying, based at least in part on the applying the received measured linescan model to the inverse linescan model, feature geometry information that describes a feature that would produce a linescan corresponding to the received measured linescan information. The method also includes determining, at least in part using the inverse linescan model, feature edge positions of the identified feature, analyzing the feature edge positions to determine errors in the manufacture of the pattern structure, and controlling a lithography tool based on the analysis of the feature edge positions. | 2021-10-21 |
20210327676 | Thin Pellicle Material for Protection of Solid-State Electron Detectors - An electron beam system and method are provided. The system includes a detector having a detector face configured to detect back-scattered electrons reflected off of a sample. The system further includes an annular cap disposed on the detector face, and a protective pellicle disposed on the annular cap, covering the detector face. The protective pellicle is transparent to back-scattered electrons and provides a physical barrier to particles directed at the detector face. | 2021-10-21 |
20210327677 | METHOD IMPLEMENTED BY A DATA PROCESSING APPARATUS, AND CHARGED PARTICLE BEAM DEVICE FOR INSPECTING A SPECIMEN USING SUCH A METHOD - The invention relates to a method implemented by a data processing apparatus, comprising the steps of receiving an image; providing a set-point for a desired image quality parameter of said image; and processing said image using an image analysis technique for determining a current image quality parameter of said image. In the method, the current image quality parameter is compared with said desired set-point. Based on said comparison, a modified image is generated by using an image modification technique. The generating comprises the steps of improving said image in terms of said image quality parameter in case said current image quality parameter is lower than said set-point; and deteriorating said image in terms of said image quality parameter in case said current image quality parameter exceeds said set-point. The modified image is then output. | 2021-10-21 |
20210327678 | PARTICLE BEAM APPARATUS, DEFECT REPAIR METHOD, LITHOGRAPHIC EXPOSURE PROCESS AND LITHOGRAPHIC SYSTEM - A particle beam apparatus includes an object table configured to hold a semiconductor substrate; a particle beam source configured to generate a particle beam; a detector configured to detect a response of the substrate caused by interaction of the particle beam with the substrate and to output a detector signal representative of the response; and a processing unit configured to: receive or determine a location of one or more defect target areas on the substrate; control the particle beam source to inspect the one or more defect target areas; identify one or more defects within the one or more defect target areas, based on the detector signal obtained during the inspection of the one or more defect target areas; control the particle beam source to repair the one or more defects. | 2021-10-21 |
20210327679 | SYSTEM, METHOD, AND APPARATUS FOR ION CURRENT COMPENSATION - Systems, methods and apparatus for regulating ion energies in a plasma chamber and chucking a substrate to a substrate support are disclosed. An exemplary method includes placing a substrate in a plasma chamber, forming a plasma in the plasma chamber, controllably switching power to the substrate so as to apply a periodic voltage function (or a modified periodic voltage function) to the substrate, and modulating, over multiple cycles of the periodic voltage function, the periodic voltage function responsive to a defined distribution of energies of ions at the surface of the substrate so as to effectuate the defined distribution of ion energies on a time-averaged basis. | 2021-10-21 |
20210327680 | HIGH FREQUENCY GENERATOR HAVING DUAL OUTPUTS AND ITS DRIVING METHOD - A high frequency generator having dual outputs comprises: a high frequency amplifying unit configured to amplify a DC voltage of a predetermined level, and output a first and a second high frequency amplification signal; a combiner configured to combine the first high frequency amplification signal and the second high frequency amplification signal, and output a high frequency power signal; a high frequency sensor disposed on output side of the combiner, configured to detect an electrical signal flowing the output side of the combiner, and output an electrical detection signal; a controller configured to output multiple control signals by using an externally applied control signal and the electrical detection signal; and a switching unit disposed between the combiner and the plasma chamber, and controlled by a switching control signal outputted from the controller to output the high frequency power signal to a first high frequency power output signal through a first output terminal and to output the high frequency power signal to a second high frequency power signal through a second output terminal. | 2021-10-21 |
20210327681 | CONTROL METHOD AND PLASMA PROCESSING APPARATUS - A control method of a plasma processing apparatus including a first electrode that places a workpiece thereon includes supplying a bias power to the first electrode, and supplying a source power having a frequency higher than that of the bias power into a plasma processing space. The source power has a first state and a second state. The control method further includes a first control process of alternately applying the first state and the second state of the source power in synchronization with a signal synchronized with a cycle of a radio frequency of the bias power, or a phase within one cycle of a reference electrical state that represents any one of a voltage, current, and electromagnetic field measured in a power feeding system of the bias power. | 2021-10-21 |
20210327682 | SPATIALLY VARIABLE WAFER BIAS POWER SYSTEM - A plasma deposition system comprising a wafer platform, a second electrode, a first electrode, a first high voltage pulser, and a second high voltage pulser. In some embodiments, the second electrode may be disposed proximate with the wafer platform. In some embodiments, the second electrode can include a disc shape with a central aperture; a central axis, an aperture diameter, and an outer diameter. In some embodiments, the first electrode may be disposed proximate with the wafer platform and within the central aperture of the second electrode. In some embodiments, the first electrode can include a disc shape, a central axis, and an outer diameter. In some embodiments, the first high voltage pulser can be electrically coupled with the first electrode. In some embodiments, the second high voltage pulser can be electrically coupled with the second electrode. | 2021-10-21 |
20210327683 | RADIO-FREQUENCY ANTENNA AND PLASMA PROCESSING DEVICE - A radio-frequency antenna through which a high amount of current can be efficiently passed even at a radio-frequency level for plasma generation, as well as a plasma processing device utilizing the radio-frequency antenna. A radio-frequency antenna includes a metal fiber sheet. A plasma processing device includes: a vacuum container including a wall having an opening; a radio-frequency antenna including a metal fiber sheet and located at the opening; and a dielectric protection plate located closer to the interior of the vacuum container than the radio-frequency antenna and configured to close the opening in a gas-tight manner. The radio-frequency antenna including a metal fiber sheet has a larger surface area and a lower impedance to a radio-frequency current than a radio-frequency antenna including a metal plate having the same outer shape. Therefore, it allows a radio-frequency current commonly used for plasma generation to be more efficiently passed through in large amounts. | 2021-10-21 |
20210327684 | COMBINED RF GENERATOR AND RF SOLID-STATE MATCHING NETWORK - In one embodiment, a method of matching an impedance is disclosed. An impedance matching network is coupled between a radio frequency (RF) source and a plasma chamber. The matching network includes a variable reactance element (VRE) having different positions for providing different reactances. The RF source has an RF source control circuit carrying out a power control scheme to control a power delivered to the matching network. Based on a determined parameter, a new position for the VRE is determined to reduce a reflected power at the RF input of the matching network. The matching network provides a notice signal to the RF source indicating the VRE will be altered. In response to the notice signal, the RF source control circuit alters the power control scheme. While the power control scheme is altered, the VRE is altered to the new position. | 2021-10-21 |
20210327685 | MODULAR HIGH-FREQUENCY SOURCE - Embodiments include a modular high-frequency emission source. In an embodiment, the modular high-frequency emission source includes a plurality of high-frequency emission modules, where each high-frequency emission module comprises and oscillator module, an amplification module, and an applicator. In an embodiment the oscillator module comprises a voltage control circuit and a voltage controlled oscillator. In an embodiment, the amplification module is coupled to the oscillator module. In an embodiment, the applicator is coupled to the amplification module. In an embodiment, each high-frequency emission module includes a different oscillator module. | 2021-10-21 |
20210327686 | Microwave Plasma Source For Spatial Plasma Enhanced Atomic Layer Deposition (PE-ALD) Processing Tool - Plasma source assemblies, gas distribution assemblies including the plasma source assembly and methods of generating a plasma are described. The plasma source assemblies include a powered electrode with a ground electrode adjacent a first side and a dielectric adjacent a second side. A first microwave generator is electrically coupled to the first end of the powered electrode through a first feed and a second microwave generator is electrically coupled to the second end of the powered electrode through a second feed. | 2021-10-21 |
20210327687 | PLASMA GENERATING APPARATUS AND GAS TREATING APPARATUS - A plasma generating apparatus may include a cathode assembly including a cathode, an anode assembly including an anode having therein a plasma generation space, and one or more magnetic force generators configured to generate a magnetic force. The anode assembly has one end portion in which a gas supply path is provided and the other end portion having an opening, the gas supply path configured to supply a plasma generating gas to the plasma generation space. The gas supply path is configured to generate a vortex of the plasma generating gas in the plasma generation space and said one or more magnetic force generators are arranged such that the magnetic force is generated in a direction opposite to a rotational direction of the vortex of the plasma generating gas. | 2021-10-21 |
20210327688 | MOUNTING BASE, SUBSTRATE PROCESSING DEVICE, EDGE RING, AND EDGE RING TRANSFER METHOD - A mounting base for placing a substrate to be subjected to a predetermined processing is provided. The mounting base includes an electrostatic chuck for electrostatically attracting and holding the substrate, a first edge ring that is disposed around the substrate and is transferrable, a second edge ring fixed around the first edge ring, a lifter pin for raising and lowering the first edge ring, a first electrode disposed in a position facing the first edge ring in the electrostatic chuck to electrostatically attract and hold the first edge ring; and a second electrode disposed in a position facing the second edge ring in the electrostatic chuck to electrostatically attract and hold the second edge ring. | 2021-10-21 |
20210327689 | METAL CONTAMINATION REDUCTION IN SUBSTRATE PROCESSING SYSTEMS WITH TRANSFORMER COUPLED PLASMA - A substrate processing system includes a processing chamber including a substrate support to support a substrate. A coil includes at least one terminal. An RF source configured to supply RF power to the coil. A dielectric window is arranged on one surface of the processing chamber adjacent to the coil. A contamination reducer includes a first plate that is arranged between the at least one terminal of the coil and the dielectric window. | 2021-10-21 |
20210327690 | METHOD FOR GENERATING AND PROCESSING A UNIFORM HIGH DENSITY PLASMA SHEET - A method of generating and processing a uniform high density plasma sheet. The method comprising generating a plasma within a chamber using plasma source; and within the same chamber containing and shaping the plasma using magnetic and/or electrostatic fields. The plasma is propagated as a uniform high density sheet within the chamber. | 2021-10-21 |
20210327691 | HIGH DENSITY PLASMA PROCESSING APPARATUS - A high density plasma processing apparatus. The apparatus comprising: a process chamber containing a gaseous medium; a length of antenna extending through the process chamber; a housing enclosing the antenna from the process chamber; and one or more magnets. In use, the antenna excites the gaseous medium within the process chamber to generate a plasma; and wherein the one or more magnets are configured such that the plasma is propagated as a sheet across the process chamber in an orthogonal direction relative to the length of the antenna. | 2021-10-21 |
20210327692 | MULTI-CATHODE PROCESSING CHAMBER WITH DUAL ROTATABLE SHIELDS - Embodiments of a process kits for use in a process chamber are provided herein. In some embodiments, a process kit for use in a multi-cathode processing chamber includes: a first rotatable shield coupled to a first shaft, wherein the first rotatable shield includes a base, a conical portion extending downward and radially outward from the base, and one or more holes formed through the conical portion, wherein no two holes of the one or more holes are diametrically opposed; and a second rotatable shield coupled to a second shaft concentric with the first shaft, wherein the second rotatable shield is disposed in the first rotatable shield, and wherein the first rotatable shield is configured to rotate independent of the first rotatable shield. | 2021-10-21 |
20210327693 | SYSTEM AND METHOD FOR PARTICLE CONTROL IN MRAM PROCESSING - A system and method for reducing particle contamination on substrates during a deposition process using a particle control system is disclosed here. In one embodiment, a film deposition system includes: a processing chamber sealable to create a pressurized environment and configured to contain a plasma, a target and a substrate in the pressurized environment; and a particle control unit, wherein the particle control unit is configured to provide an external force to each of at least one charged atom and at least one contamination particle in the plasma, wherein the at least one charged atom and the at last one contamination particle are generated by the target when it is in direct contact with the plasma, wherein the external force is configured to direct the at least one charged atom to a top surface of the substrate and to direct the at least one contamination particle away from the top surface of the substrate. | 2021-10-21 |
20210327694 | SYSTEM FOR COUPLING RF POWER INTO LINACS AND BELLOWS COATING BY MAGNETRON SPUTTERING WITH KICK PULSE - A system and associated method are described for depositing high-quality films for providing a coating on a three-dimensional surface such as an internal surface of a bellows structure. The system includes a magnetic array comprising multiple sets of magnets arranged to have Hall-Effect regions that run lengthwise along a sputter target. The system further includes an elongated sputtering electrode material tube surrounding the magnetic array comprising multiple sets of magnets arranged to have Hall-Effect regions that run lengthwise along the sputter target. During operation, the system generates and controls ion flux for direct current high-power impulse magnetron sputtering. During operation logic circuitry issues a control signal to control a kick pulse property of a sustained positive voltage kick pulse taken from the group consisting of: onset delay, amplitude and duration. | 2021-10-21 |
20210327695 | SYSTEM AND METHOD FOR ENHANCED ION PUMP LIFESPAN - Within an ion pump, accelerated ions leave the center portion of an anode tube due to the anode tube symmetry and the generally symmetrical electric fields present. The apparent symmetry within the anode tube may be altered by making the anode tube longitudinally segmented and applying independent voltages to each segment. The voltages on two adjacent segments may be time varying at different rates to achieve a rasterizing process. | 2021-10-21 |
20210327696 | SYSTEMS AND METHODS FOR ICPMS MATRIX OFFSET CALIBRATION - Systems and methods are described for calibrating an analytical instrument analyzing a plurality of sample matrices in series. A system embodiment can include, but is not limited to, a sample analysis device configured to receive a plurality of samples from a plurality of remote sampling systems and to determine an intensity of one or more species of interest contained in each of the plurality of samples; and a controller configured to generate a primary calibration curve based on analysis of a first standard solution having a first sample matrix by the sample analysis device and generate at least one secondary calibration curve based on analysis of a second standard solution having a second sample matrix by the sample analysis device, the controller configured to associate the at least one secondary calibration curve with the primary calibration curve according to a matrix correction factor. | 2021-10-21 |
20210327697 | ION DETECTION SYSTEM - An ion detection system is disclosed that comprises one or more first devices | 2021-10-21 |
20210327698 | SYSTEMS FOR INTEGRATED DECOMPOSITION AND SCANNING OF A SEMICONDUCTING WAFER - Systems and methods are described for integrated decomposition and scanning of a material, such as a semiconducting wafer, a scanning nozzle includes, but is not limited to, a nozzle body defining one or more nozzle ports to receive fluid for introduction to the surface of the material and to recover fluid from the surface of the material, and a nozzle hood extending from the nozzle body, the nozzle hood defining an inner channel longitudinally disposed along the nozzle body, the nozzle hood further defining one or more outer channels longitudinally disposed along the nozzle body, the inner channel fluidically coupled with the one or more outer channels via one or more gaps defined by the nozzle hood. | 2021-10-21 |
20210327699 | APPARATUS AND METHOD FOR THERMAL ASSISTED DESORPTION IONIZATION SYSTEMS - The present invention is directed to a method and device to desorb an analyte using heat to allow desorption of the analyte molecules, where the desorbed analyte molecules are ionized with ambient temperature ionizing species. In various embodiments of the invention a current is passed through a mesh upon which the analyte molecules are present. The current heats the mesh and results in desorption of the analyte molecules which then interact with gas phase metastable neutral molecules or atoms to form analyte ions characteristic of the analyte molecules. | 2021-10-21 |
20210327700 | RF/DC Cutoff to Reduce Contamination and Enhance Robustness of Mass Spectrometry Systems - Systems and methods described herein utilize a multipole ion guide that can receive ions from an ion source for transmission to downstream mass analyzers, while preventing unwanted/interfering/contaminating ions from being transmitted into the high-vacuum chambers of mass spectrometry systems. In various aspects, RF and/or DC signals can be provided to auxiliary electrodes interposed within a quadrupole rod set so as to control or manipulate the transmission of ions from the multipole ion guide. | 2021-10-21 |
20210327701 | EXTREME ULTRAVIOLET LIGHT SOURCE APPARATUS AND PLASMA POSITION ADJUSTING METHOD - An extreme ultraviolet light source apparatus includes a disc-shaped cathode rotating about an axis, a disc-shaped anode rotating about an axis, an energy beam irradiation device irradiating a plasma raw material on the cathode with an energy beam to vaporize the plasma raw material, a power supply for causing a discharge between the cathode and the anode for generating a plasma in the gap between the cathode and the anode to emit extreme ultraviolet light, and an irradiation position adjusting mechanism for adjusting a position at which the cathode is irradiated with the energy beam. The cathode, the anode, and the irradiation position adjusting mechanism are accommodated in a housing. A photography device is disposed outside the housing and is configured to photograph a visible-light image of a vicinity of the cathode and the anode, the vicinity including visible light emitted from the plasma. | 2021-10-21 |
20210327702 | METHOD FOR MANUFACTURING GALLIUM NITRIDE SEMICONDUCTOR DEVICE - A method for manufacturing a gallium nitride semiconductor device includes: preparing a gallium nitride wafer; forming an epitaxial growth film on the gallium nitride wafer to provide a processed wafer having chip formation regions; perform a surface side process on a one surface side of the processed wafer; removing the gallium nitride wafer and dividing the processed wafer into a chip formation wafer and a recycle wafer; and forming an other surface side element component on an other surface side of the chip formation wafer. | 2021-10-21 |
20210327703 | GALLIUM OXIDE FILM BASED ON SAPPHIRE SUBSTRATE AS WELL AS GROWTH METHOD AND APPLICATION THEREOF - The disclosure provides a gallium oxide film based on sapphire substrate as well as a growth method and an application thereof. The gallium oxide film based on sapphire substrate is prepared by a method below, including: forming more than one α-(Al | 2021-10-21 |
20210327704 | METHODS OF FORMING STRUCTURES INCLUDING SILICON GERMANIUM AND SILICON LAYERS, DEVICES FORMED USING THE METHODS, AND SYSTEMS FOR PERFORMING THE METHODS - Methods and systems for forming structures including one or more layers comprising silicon germanium and one or more layers comprising silicon are disclosed. Exemplary methods can include using a surfactant, using particular precursors, and/or using a transition step to improve an interface between adjacent layers comprising silicon germanium and comprising silicon. | 2021-10-21 |
20210327705 | STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH OXIDE SEMICONDUCTOR CHANNEL - A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes an oxide semiconductor nanostructure suspended over a substrate. The semiconductor device structure also includes a source/drain structure adjacent to the oxide semiconductor nanostructure. The source/drain structure contains oxygen, and the oxide semiconductor nanostructure has a greater atomic concentration of oxygen than that of the source/drain structure. The semiconductor device structure further includes a gate stack wrapping around the oxide semiconductor nanostructure. | 2021-10-21 |
20210327706 | SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes the following steps. A first patterned photoresist layer is formed on a substrate. A second patterned photoresist layer is formed on the substrate after the first patterned photoresist layer is formed, wherein the first patterned photoresist layer and the second patterned photoresist layer are arranged alternatively. A liner is formed to cover sidewalls of the first patterned photoresist layer and the second patterned photoresist layer. The present invention also provides a semiconductor device, including a plurality of pillars being disposed on a layer, wherein the layer includes first recesses and second recesses, wherein the depths of the first recesses are less than the depths of the second recesses. | 2021-10-21 |
20210327707 | METHOD OF MAKING GRAPHENE AND GRAPHENE DEVICES - The present invention generally relates to a method of making graphene and graphene devices. | 2021-10-21 |
20210327708 | PRECURSOR COMPOSITION FOR FORMING METAL FILM, METAL FILM FORMING METHOD USING SAME, AND SEMICONDUCTOR DEVICE COMPRISING SAME METAL FILM - Proposed is a precursor composition for forming a metal film including a zirconium compound represented by any one of Chemical Formulas 1 to 3 and a hafnium compound represented by any one of Chemical Formulas 4 to 6. | 2021-10-21 |
20210327709 | METHOD FOR FORMING GATE INSULATOR FILM AND HEAT TREATMENT METHOD - A gate insulator film made of silicon dioxide or gallium oxide is formed on a gallium nitride (GaN) substrate. The GaN substrate is preheated by irradiation with light from halogen lamps, and the surface of the substrate including the gate insulator film is heated to a high temperature for an extremely short time by irradiation with a flash of light from flash lamps. Heating the substrate surface including the gate insulator film in an extremely short heat treatment time prevents the desorption of nitrogen from GaN and makes it possible to reduce the traps existing at the interface between the gate insulator film and GaN without diffusing gallium into the gate insulator film. | 2021-10-21 |
20210327710 | GALLIUM NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A gallium nitride semiconductor device includes: a chip formation substrate made of gallium nitride and having one surface and an other surface opposite to the one surface; a one surface side element component disposed on the one surface and providing a component of an one surface side of a semiconductor element; and a metal film constituting a back surface electrode in contact with the other surface. The other surface has an irregularity provided by a plurality of convex portions with a trapezoidal cross section and a plurality of concave portions located between the convex portions; and an upper base surface of the trapezoidal cross section in each of the plurality of convex portions is opposed to the one surface. | 2021-10-21 |
20210327711 | SEMICONDUCTOR DEVICE, INSPECTION APPARATUS OF SEMICONDUCTOR DEVICE, AND METHOD FOR INSPECTING SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first transistor, and a first mounting member. The first transistor includes a nitride semiconductor layer and includes a first element electrode, a second element electrode, and a third element electrode. The first mounting member includes a first frame electrode, a plurality of first frame connection members electrically connecting the first element electrode and the first frame electrode, a first pad electrode, and a first pad connection member electrically connecting the first element electrode and the first pad electrode. | 2021-10-21 |
20210327712 | REINFORCED THIN-FILM DEVICE - A reinforced thin-film device ( | 2021-10-21 |
20210327713 | NITROGEN-DOPED CARBON HARDMASK FILMS - Disclosed herein is a method and apparatus for forming carbon hard masks to improve deposition uniformity and etch selectivity. The carbon hard mask may be formed in a PECVD process chamber and is a nitrogen-doped carbon hardmask. The nitrogen-doped carbon hardmask is formed using a nitrogen containing gas, an argon containing gas, and a hydrocarbon gas. | 2021-10-21 |
20210327714 | METHOD FOR PROCESSING A SUBSTRATE - Provided is a method to adjust a film stress. In one embodiment, a first film is formed on the substrate by supplying a first reactant and a second reactant sequentially and alternately in a first step, and the first film is converted into a second film by supplying a third reactant to the first film in a second step. The film stress of the second film is adjusted by controlling the ratio of the first step and the second step. | 2021-10-21 |
20210327715 | METHOD OF FORMING CHROMIUM NITRIDE LAYER AND STRUCTURE INCLUDING THE CHROMIUM NITRIDE LAYER - Methods and systems for depositing chromium nitride layers onto a surface of the substrate and structures and devices formed using the methods are disclosed. An exemplary method includes using a deposition process, depositing a chromium nitride layer onto a surface of the substrate. The deposition process can include providing a chromium precursor to the reaction chamber and separately providing a nitrogen reactant to the reaction chamber. The deposition process may be a thermal cyclical deposition process. | 2021-10-21 |
20210327716 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME INCLUDING RE-GROWTH PROCESS TO FORM NON-UNIFORM GATE DIELECTRIC LAYER - A method for fabricating a semiconductor device includes: forming a gate structure including a source side and a drain side over a substrate, wherein a dielectric material and a columnar crystal grain material are stacked over the substrate; doping a chemical species on the drain side of the gate structure; and exposing the gate structure doped with the chemical species to a re-growth process in order to thicken the dielectric material on the drain side of the gate structure. | 2021-10-21 |
20210327717 | Methods and Apparatus for Integrated Cobalt Disilicide Formation - Methods and apparatus for the formation of cobalt disilicide are described. Some embodiments of the disclosure provide in-situ methods of forming cobalt disilicide. The resulting films are smoother and have lower resistance and resistivity than films formed by similar ex-situ methods. Some embodiments of the disclosure provide apparatus for performing the described methods without an air break between processes. | 2021-10-21 |
20210327718 | METHOD OF HELICAL CHAMFER MACHINING SILICON WAFER - Provided is a method of chamfer machining a silicon wafer which makes it possible to increase the number of machining operations that can be performed using a chamfering wheel used for helical chamfer machining in the case of obtaining a small finished wafer taper angle. The method in which helical chamfer machining is performed so that the finished wafer taper angle θ of an edge portion in the one silicon wafer is within an allowable angle range of a target wafer taper angle θ | 2021-10-21 |
20210327719 | METHOD FOR PROCESSING WORKPIECE - In an embodiment, in the method for processing a workpiece including an etching target layer containing silicon oxide, a mask provided on the etching target layer, and an opening provided in the mask and exposing the etching target layer, according to the embodiment, the etching target layer is etched by removing the etching target layer for each atomic layer through repetitive execution of a sequence of generating plasma of a first processing gas containing nitrogen, forming a mixed layer containing ions included in the plasma on an atomic layer on an exposed surface of the etching target layer, generating plasma of a second processing gas containing fluorine, and removing the mixed layer by radicals included in the plasma. The plasma of the second processing gas contains the radicals that remove the mixed layer containing silicon nitride. | 2021-10-21 |
20210327720 | Magnetic Slurry for Highly Efficiency CMP - A chemical-mechanical polishing (CMP) system includes a head, a polishing pad, and a magnetic system. The slurry used in the CMP process contains magnetizable abrasives. Application and control of a magnetic field, by the magnetic system, allows precise control over how the magnetizable abrasives in the slurry may be drawn toward the wafer or toward the polishing pad. | 2021-10-21 |
20210327721 | ETCHING METHOD OF COPPER-MOLYBDENUM FILM AND ARRAY SUBSTRATE - A etching method of a copper-molybdenum film and an array substrate are provided. The etching method of a copper-molybdenum film includes forming a copper-molybdenum film on a substrate; forming a photoresist in a predetermined pattern on the copper-molybdenum film; etching a copper film of the copper-molybdenum film with an acidic first etching solution; etching a molybdenum film of the copper-molybdenum film with a neutral or basic second etching solution, to form the copper-molybdenum film in the predetermined pattern. | 2021-10-21 |
20210327722 | METHOD FOR PRODUCING SEMICONDUCTOR ELEMENT - The present disclosure provides a method for producing a semiconductor element that can lower the potential risk of malfunction. The production method of the disclosure is a method for producing a semiconductor element which includes providing a semiconductor element precursor, the precursor having a metal electrode layer formed on the surface of a gallium oxide-based single crystal semiconductor layer and a dopant doped in at least part of an exposed portion on the surface of the gallium oxide-based single crystal semiconductor layer where the metal electrode layer is not layered, and annealing treatment of the semiconductor element precursor whereby the dopant is diffused to a portion of the gallium oxide-based single crystal semiconductor layer that are overlapping with the metal electrode layer in the layering direction, to form a Schottky junction between the gallium oxide-based single crystal semiconductor layer and the metal electrode layer. | 2021-10-21 |
20210327723 | SEMICONDUTOR PACKAGES AND METHODS OF FORMING SAME - One embodiment includes partially forming a first through via in a substrate of an interposer, the first through via extending into a first side of the substrate of the interposer. The method also includes bonding a first die to the first side of the substrate of the interposer. The method also includes recessing a second side of the substrate of the interposer to expose the first through via, the first through via protruding from the second side of the substrate of the interposer, where after the recessing, the substrate of the interposer is less than 50 μm thick. The method also includes and forming a first set of conductive bumps on the second side of the substrate of the interposer, at least one of the first set of conductive bumps being electrically coupled to the exposed first through via. | 2021-10-21 |
20210327724 | METHOD OF MANUFACTURING A POWER SEMICONDUCTOR COMPONENT ARRANGEMENT OR A POWER SEMICONDUCTOR COMPONENT HOUSING - Disclosed is a method of manufacturing a power semiconductor component arrangement or a power semiconductor component housing. The method involves a sintering process in which the plurality of layer-shaped unsintered ceramic substrates are converted into a sintered ceramic single layer or multilayer substrate or into a sintered ceramic single layer or multilayer interconnect device. Also disclosed is a power semiconductor component arrangement or a power semiconductor component housing that can be manufactured using the above method. Further disclosed are the uses of the power semiconductor component arrangement or the power semiconductor component housing. | 2021-10-21 |
20210327725 | METHOD OF FASTENING A SEMICONDUCTOR CHIP ON A LEAD FRAME, AND ELECTRONIC COMPONENT - An electronic component includes a lead frame; a semiconductor chip arranged above the lead frame; and a connection layer sequence arranged between the lead frame and the semiconductor chip, wherein the connection layer sequence includes a first intermetallic layer including gold and indium or gold, indium and tin, a second intermetallic layer including indium and a titanium compound, indium and nickel, indium and platinum or indium and titanium, and a third intermetallic layer including indium and gold. | 2021-10-21 |
20210327726 | Redistribution Structures for Semiconductor Packages and Methods of Forming the Same - A method for forming a redistribution structure in a semiconductor package and a semiconductor package including the redistribution structure are disclosed. In an embodiment, the method may include encapsulating an integrated circuit die and a through via in a molding compound, the integrated circuit die having a die connector; depositing a first dielectric layer over the molding compound; patterning a first opening through the first dielectric layer exposing the die connector of the integrated circuit die; planarizing the first dielectric layer; depositing a first seed layer over the first dielectric layer and in the first opening; and plating a first conductive via extending through the first dielectric layer on the first seed layer. | 2021-10-21 |
20210327727 | Valve Apparatuses and Related Methods for Reactive Process Gas Isolation and Facilitating Purge During Isolation - An isolation valve assembly including a valve body having an inlet and an outlet. The isolation valve includes a seal plate disposed within an interior cavity of the valve body. The seal plate is movable between a first position allowing gas flow from the inlet to the outlet, and a second position preventing gas flow from the inlet to the outlet. The isolation valve includes a closure element disposed within the valve body. The closure element is configured to retain the seal plate stationary in the first position or the second position. The closure element includes a first sealing element positioned adjacent to a first surface of the seal plate. A working surface of the first sealing element is substantially obscured from the gas flow when the seal plate is stationary. | 2021-10-21 |
20210327728 | SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD - A substrate processing apparatus includes at least one nozzle unit configured to eject a processing liquid to a substrate. The at least one nozzle unit includes a conductive part for voltage application configured to be brought into contact with the processing liquid, and a voltage detection part or a current detection part configured to be brought into contact with the processing liquid. A non-conductive part is interposed between the conductive part for voltage application and the voltage detection part or between the conductive part for voltage application and the current detection part. A voltage application part is connected to the conductive part for voltage application, and a voltage detector is installed in the voltage detection part or a current detector is installed in the current detection part. | 2021-10-21 |
20210327729 | SUBSTRATE PROCESSING METHOD - A substrate processing device includes a processing tank, a substrate holding unit, a fluid supply unit, and a control unit. The processing tank stores a processing liquid for processing a substrate. The substrate holding unit holds the substrate in the processing liquid in the processing tank. The fluid supply unit supplies a fluid to the processing tank. The control unit controls the fluid supply unit. The control unit controls the fluid supply unit such that the fluid supply unit changes supply of the fluid during a period from a start of supply of the fluid to the processing tank storing the processing liquid in which the substrate is immersed to an end of supply of the fluid to the processing tank storing the processing liquid in which the substrate is immersed. | 2021-10-21 |
20210327730 | HEATING PLATFORM, THERMAL TREATMENT AND MANUFACTURING METHOD - A heating platform for heating a wafer is provided. The heating platform includes a support carrier, a detection module and a first heating module. The wafer is supported by the support carrier. The detection module is configured to monitor a surface condition of the wafer supported by the support carrier. The first heating module is disposed at a side of the support carrier. The first heating module includes a plurality of heating units electrically connected to the detection module, and the heating units is arranged in an array. A thermal treatment and a manufacturing method are further provided. | 2021-10-21 |
20210327731 | MASS TRANSFER METHOD, MASS TRANSFER DEVICE AND BUFFER CARRIER - A mass transfer method, a mass transfer device and a buffer carrier are provided. The mass transfer method includes: (a) providing a plurality of electronic components disposed on a source carrier; (b) providing a buffer carrier including a plurality of adjusting cavities; and (c) transferring the electronic components from the source carrier to the buffer carrier, wherein the electronic components are placed in the adjusting cavities of the buffer carrier to adjust positions of the electronic components from shifted positions to correct positions. | 2021-10-21 |
20210327732 | APPARATUS, SYSTEMS, AND METHODS OF MEASURING EDGE RING DISTANCE FOR THERMAL PROCESSING CHAMBERS - Aspects of the present disclosure relate to apparatus, systems, and methods of measuring edge ring distance for thermal processing chambers. In one example, the distance measured is used to determine a center position shift of the edge ring. | 2021-10-21 |
20210327733 | WAFER FORMING APPARATUS - A wafer forming apparatus includes a conveying tray having an ingot accommodating section that accommodates a semiconductor ingot and a wafer accommodating section that accommodates a wafer formed from the semiconductor ingot, a belt conveyor unit that conveys the conveying tray to each processing apparatus, a cassette rack on which cassettes accommodating the wafers are placed correspondingly to the conveying trays, and a transferring unit that transfers the wafer from the wafer accommodating section of the conveying tray to the cassette placed on the cassette rack. The conveying tray is provided with an identification mark. The cassette rack or the cassette corresponding to the conveying tray is provided with the same identification mark as the identification mark provided on the conveying tray. | 2021-10-21 |
20210327734 | RETICLE POD HAVING COATED SENSOR ZONES - Sensor zones are created on an inner pod of a reticle container using a dry coating method. The sensor zones are discrete zones having a specific spectral reflectivity. The sensor zones are positioned such that they can be read by a tool to determine distance of portions of the pod. The use of discrete zones and a dry coating method for applying those discrete zones overcomes issues with inconsistency and difficulty in cleaning or maintaining reflectance of an inner pod of the reticle container in comparison with inner pods plated entirely with material or other wet coating applied materials. | 2021-10-21 |
20210327735 | APPARATUS FOR FABRICATING A SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - The present disclosure provides a method for fabricating a semiconductor structure, including disposing a mask at a first position in a first chamber, generating; a first plurality of ions toward the mask by an ionizer, forming a photoresist layer on a substrate, receiving the substrate in the first chamber, and exposing the photoresist layer with actinic radiation through the mask in the first chamber. | 2021-10-21 |
20210327736 | MINI-ENVIRONMENT SYSTEM FOR CONTROLLING OXYGEN AND HUMIDITY LEVELS WITHIN A SAMPLE TRANSPORT DEVICE - A mini-environment apparatus is disclosed. The apparatus may include an enclosure including a frame with two or more openings. The frame may define an internal cavity within the enclosure. The apparatus may include a flapper blade coupled to a portion of the frame. The flapper blade may be configured to close at least one opening of the two or more openings of the frame to form a sealed enclosure when the flapper blade is in a closed position. The apparatus may include a floating plate coupled to a portion of the frame. The floating plate may include one or more slots. The apparatus may include one or more shutters coupled a portion of the floating plate to cover the one or more slots. | 2021-10-21 |
20210327737 | TRANSPORT DEVICE HAVING LOCAL PURGE FUNCTION - The purpose of the present invention is to provide, at low cost, a transport apparatus | 2021-10-21 |
20210327738 | SUBSTRATE PROCESSING SYSTEM AND SUBSTRATE PROCESSING METHOD - A substrate processing system includes a first main surface grinding device configured to grind, while holding a substrate from below with a first main surface of the substrate facing upwards, the first main surface of the substrate; a first inverting device configured to invert the substrate ground by the first main surface grinding device; and a second main surface grinding device configured to grin, while holding the ground first main surface of the substrate from below with a second main surface of the substrate facing upwards, the second main surface of the substrate. | 2021-10-21 |
20210327739 | SELECTIVE MICRO DEVICE TRANSFER TO RECEIVER SUBSTRATE - A method of selectively transferring micro devices from a donor substrate to contact pads on a receiver substrate. Micro devices being attached to a donor substrate with a donor force. The donor substrate and receiver substrate are aligned and brought together so that selected micro devices meet corresponding contact pads. A receiver force is generated to hold selected micro devices to the contact pads on the receiver substrate. The donor force is weakened and the substrates are moved apart leaving selected micro devices on the receiver substrate. Several methods of generating the receiver force are disclosed, including adhesive, mechanical and electrostatic techniques. | 2021-10-21 |
20210327740 | SELECTIVE MICRO DEVICE TRANSFER TO RECEIVER SUBSTRATE - A method of selectively transferring micro devices from a donor substrate to contact pads on a receiver substrate. Micro devices being attached to a donor substrate with a donor force. The donor substrate and receiver substrate are aligned and brought together so that selected micro devices meet corresponding contact pads. A receiver force is generated to hold selected micro devices to the contact pads on the receiver substrate. The donor force is weakened and the substrates are moved apart leaving selected micro devices on the receiver substrate. Several methods of generating the receiver force are disclosed, including adhesive, mechanical and electrostatic techniques. | 2021-10-21 |
20210327741 | SUBSTRATE SUPPORT AND SUBSTRATE PROCESSING APPARATUS - A substrate support is provided that includes: a base; an electrostatic chuck on which a substrate is placed; an electrode provided in the electrostatic chuck; a contact portion of the electrode; an adhesive layer that bonds the electrostatic chuck with the base and that does not cover the contact portion; and a power supply terminal contacting the contact portion of the electrode without being fixed to the contact portion. | 2021-10-21 |
20210327742 | Thermal Pad for Etch Rate Uniformity - Etch uniformity is improved by providing a thermal pad between an insert ring and electrostatic chuck in an etching chamber. The thermal pad provides a continuous passive heat path to dissipate heat from the insert ring and wafer edge to the electrostatic chuck. The thermal pad helps to keep the temperature of the various components in contact with or near the wafer at a more consistent temperature. Because temperature may affect etch rate, such as with etching hard masks over dummy gate formations, a more consistent etch rate is attained. The thermal pad also provides for etch rate uniformity across the whole wafer and not just at the edge. The thermal pad may be used in an etch process to perform gate replacement by removing hard mask layer(s) over a dummy gate electrode. | 2021-10-21 |
20210327743 | CLEANING TOOL - A method includes transmitting a radiation toward an electrostatic chuck, receiving a reflection of the radiation, analyzing the reflection of the radiation, determining whether a particle is present on the electrostatic chuck based on the analyzing the reflection of the radiation, and moving a cleaning tool to a location of the particle on the electrostatic chuck when the determination determines that the particle is present. | 2021-10-21 |
20210327744 | WAFER PROCESSING METHOD - A wafer processing method includes a modified layer forming step, a protective member disposing step, a reinforcing portion forming step, and an undersurface processing step. The modified layer forming step forms, in a ring shape, a modified layer not reaching a finished thickness of a wafer by irradiating the wafer with a laser beam such that a condensing point of the laser beam is positioned in an inner part of the wafer, the inner part corresponding to a peripheral surplus region. The reinforcing portion forming step makes a cleavage plane reach the top surface from the modified layer formed in a ring shape, removes the modified layer, thins a region corresponding to a device region of the wafer to the finished thickness, and forms a ring-shaped reinforcing portion in a region corresponding to the peripheral surplus region of the wafer by grinding the undersurface of the wafer. | 2021-10-21 |
20210327745 | PICKUP AND CONTACT DEVICE - A pickup and contact device is adapted to be connected to a moving device to move a picked-up electronic element to an electrical testing zone. The moving device pressurizes the electronic element through the pickup and contact device, so that a contact point of the electronic element stably contacts a contact pad of the electrical testing zone. The pickup and contact device includes a main body including a base and a contact portion and a plurality of heat dissipation fins disposed at two opposite sides of the base. The contact portion is adapted to pick up the electronic element and to move the electronic element to the electrical testing zone along with the moving device. When the electronic element is tested in the electrical testing zone, heat emitted from the electronic element is adapted to be transmitted out through the heat dissipation fins of the main body. | 2021-10-21 |
20210327746 | TRAY STRUCTURE - A tray structure adapted to a deposition apparatus is provided. The tray structure includes a first tray and a second tray, wherein the first tray is disposed on the deposition apparatus for control of temperature and includes a first carrying portion and at least one heat-conducting structure. The first carrying portion is disposed on a top surface of the first tray. The at least one heat-conducting structure is disposed in a recess of the first carrying portion. The second tray is disposed on the first carrying portion and the at least one heat-conducting structure. | 2021-10-21 |
20210327747 | TEMPERATURE ADJUSTMENT SYSTEM - A heat exchange unit performs heat exchange using a coolant and is disposed inside a placing table and equipped with heat exchange chambers. The heat exchange chambers are disposed in regions, respectively, set on the placing table. The regions are set along a placing surface of the placing table. A chiller device circulates the coolant with respect to the heat exchange chambers. A temperature detection device includes temperature detectors. The temperature detectors are disposed in the regions, respectively, between the respective heat exchange chambers and the placing surface. A control device controls the chiller device to adjust a pressure of the coolant such that a temperature of the placing table reaches a first temperature range, and controls the chiller device to individually adjust flow rates of the coolant supplied to the heat exchange chambers, respectively, such that all of temperatures measured by the temperature detectors reach the first temperature range. | 2021-10-21 |
20210327748 | SEMICONDUCTOR DEVICE AND METHODS OF MANUFACTURING THEREOF - In a method of manufacturing a semiconductor device, a first interlayer dielectric (ILD) layer is formed over a substrate, a chemical mechanical polishing (CMP) stop layer is formed over the first ILD layer, a trench is formed by patterning the CMP stop layer and the first ILD layer, a metal layer is formed over the CMP stop layer and in the trench, a sacrificial layer is formed over the metal layer, a CMP operation is performed on the sacrificial layer and the metal layer to remove a portion of the metal layer over the CMP stop layer, and a remaining portion of the sacrificial layer over the trench is removed. | 2021-10-21 |
20210327749 | Trench Filling Through Reflowing Filling Material - A method includes forming a first protruding fin and a second protruding fin over a base structure, with a trench located between the first protruding fin and the second protruding fin, depositing a trench-filling material extending into the trench, and performing a laser reflow process on the trench-filling material. In the reflow process, the trench-filling material has a temperature higher than a first melting point of the trench-filling material, and lower than a second melting point of the first protruding fin and the second protruding fin. After the laser reflow process, the trench-filling material is solidified. The method further includes patterning the trench-filling material, with a remaining portion of the trench-filling material forming a part of a gate stack, and forming a source/drain region on a side of the gate stack. | 2021-10-21 |
20210327750 | HIGH RESISTIVITY SOI WAFERS AND A METHOD OF MANUFACTURING THEREOF - A high resistivity single crystal semiconductor handle structure for use in the manufacture of SOI structure is provided. The handle structure comprises an intermediate semiconductor layer between the handle substrate and the buried oxide layer. The intermediate semiconductor layer comprises a polycrystalline, amorphous, nanocrystalline, or monocrystalline structure and comprises a material selected from the group consisting of Si | 2021-10-21 |
20210327751 | ETCH STOP LAYER REMOVAL FOR CAPACITANCE REDUCTION IN DAMASCENE TOP VIA INTEGRATION - A method of forming an interconnect structure includes forming at least one second-level interconnect in a sacrificial dielectric layer that is formed on an upper surface of a sacrificial etch stop layer, and removing the sacrificial dielectric layer and the sacrificial etch stop layer while maintaining the at least one second-level interconnect so as to expose an underlying dielectric layer. The method further includes depositing a replacement dielectric layer on an upper surface of the underlying dielectric layer to embed the at least one second-level interconnect in the replacement dielectric layer. Accordingly, an interconnect structure can be formed that includes one or more first-level interconnect in a dielectric layer and one or more second-level interconnects in a replacement dielectric layer stacked on the dielectric layer. The replacement dielectric layer directly contacts the dielectric layer. | 2021-10-21 |
20210327752 | High Bias Deposition of High Quality Gapfill - Embodiments of the present disclosure generally relate to the fabrication of integrated circuits. More particularly, the implementations described herein provide techniques for deposition of high quality gapfill. Some embodiments utilize chemical vapor deposition, plasma vapor deposition, physical vapor deposition and combinations thereof to deposit the gapfill. The gapfill is of high quality and similar in properties to similarly composed bulk materials. | 2021-10-21 |
20210327753 | MULTI-PASS PLATING PROCESS WITH INTERMEDIATE RINSE AND DRY - Methods of forming metal interconnections of an integrated circuit include electroplating two or more metal layers over a metal seed layer, rinsing each of the metal layers with deionized water after the electroplating, and drying each of the metal layers after the rinsing. After forming a last metal layer, the two or more metal layers are annealed thereby forming a final metal layer, resulting in a low defect density of the final metal layer. | 2021-10-21 |
20210327754 | TUNGSTEN FEATURE FILL - Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features. Inside-out fill techniques can include selective deposition on etched tungsten layers in features. Conformal and non-conformal etch techniques can be used according to various implementations. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) word lines. Examples of applications include logic and memory contact fill, DRAM buried word line fill, vertically integrated memory gate/word line fill, and 3-D integration with through-silicon vias (TSVs). | 2021-10-21 |
20210327755 | METHOD FOR INCREASING THE ELECTRICAL FUNCTIONALITY, AND/OR SERVICE LIFE, OF POWER ELECTRONIC MODULES - In a method for increasing the electrical functionality, and/or service life, of power electronic modules, the power electronic circuit carrier, and/or the metallisation applied onto the power electronic circuit carrier, and/or a base plate connected, or to be connected, to a rear face of the power electronic circuit carrier, is finely structured by means of local material removal with at least one laser beam, so as to reduce thermomechanical stresses occurring during the production or operation of the module. In an alternative form of embodiment, the metallisation applied onto the front face of the power electronic circuit carrier is structured, or an already created structure is refined or supplemented, by means of local material removal with laser radiation, so as to achieve a prescribed electrical functionality of the metallisation. | 2021-10-21 |
20210327756 | METHOD AND STRUCTURE FOR FORMING FULLY-ALIGNED VIA - A method for manufacturing a semiconductor device includes forming a first dielectric layer, and forming a second dielectric layer stacked on the first dielectric layer. In the method, a plurality of conductive lines are formed in the first and second dielectric layers, and the plurality of conductive lines are recessed to form a plurality of openings in the second dielectric layer. The method also includes forming a plurality of dielectric fill layers on the plurality of conductive lines in the plurality of openings. At least one of the plurality of dielectric fill layers is selectively removed with respect to the second dielectric layer to expose a conductive line of the plurality of conductive lines, and a via is formed in place of the selectively removed dielectric fill layer. | 2021-10-21 |
20210327757 | SEMICONDUCTOR CHIP AND METHOD FOR MANUFACTURING THE SAME - A semiconductor chip includes: an epitaxial film made of gallium nitride; a semiconductor element disposed in the epitaxial film; a chip formation substrate including the epitaxial film and having a first surface, a second surface opposite to the first surface, and a side surface connecting the first surface and the second surface; and a convex and a concavity on the side surface. | 2021-10-21 |
20210327758 | ATOMIC PRECISION CONTROL OF WAFER-SCALE TWO-DIMENSIONAL MATERIALS - Embodiments of this disclosure include apparatus, systems, and methods for fabricating monolayers. In one example, a method includes forming a multilayer film having a plurality of monolayers of a two-dimensional (2D) material on a growth substrate. The multilayer film has a first side proximate the growth substrate and a second side opposite the first side. | 2021-10-21 |
20210327759 | CONFINED GATE RECESSING FOR VERTICAL TRANSPORT FIELD EFFECT TRANSISTORS - A method for manufacturing a vertical transistor device includes forming a plurality of fins on a substrate, and forming a gate dielectric layer on the fins and on the substrate adjacent the fins. In the method, one or more sacrificial layers are formed on the gate dielectric layer, and portions of the gate dielectric layer and the one or more sacrificial layers are removed to define a plurality of gate regions. The method also includes depositing a dielectric fill layer in gaps left by the removed gate dielectric and sacrificial layers, and selectively removing the remaining portions of the one or more sacrificial layers to form a plurality of vacant areas in the gate regions. First and second gate structures are respectively formed in first and second vacant areas of the plurality of vacant areas. The first and second gate structures are recessed to a uniform height. | 2021-10-21 |
20210327760 | METHOD FOR FORMING SEMICONDUCTOR DEVICE THAT INCLUDES COVERING METAL GATE WITH MULTILAYER DIELECTRIC - A method includes forming a dummy gate structure over a substrate; forming a plurality of gate spacers on opposite sidewalls of the dummy gate structure; forming an interlayer dielectric (ILD) layer surrounding the gate spacers; replacing the dummy gate structure with a metal gate structure; etching back the metal gate structure to form a gate trench between the gate spacers; depositing a first dielectric layer in the gate trench, in which the first dielectric layer has horizontal portions over the metal gate structure and the ILD layer, and vertical portions on sidewalls of the gate spacers; etching the vertical portions of the first dielectric layer until the sidewalls of the gate spacers exposed; and performing depositing the first dielectric layer and etching the vertical portions of the first dielectric layer in an alternate manner. | 2021-10-21 |