43rd week of 2015 patent applcation highlights part 66 |
Patent application number | Title | Published |
20150303209 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICES INCLUDING A CONNECTION REGION - Semiconductor devices and methods of forming the semiconductor devices are provided. The semiconductor devices may include a peripheral circuit part that is disposed under a cell array circuit part. The peripheral circuit part may drive the cell array circuit part. The semiconductor devices may also include first conductive lines, which are connected to the peripheral circuit part, and second conductive lines, which are connected to the cell array circuit part. The first conductive lines and the second conductive lines may have substantially the same shape, and the first conductive lines may overlap with the second conductive lines in a connection region, respectively. | 2015-10-22 |
20150303210 | Lithography-friendly Local Read Circuit for NAND Flash Memory Devices and Manufacturing Method Thereof - A flash memory device comprising a local sensing circuitry is provided in a hierarchical structure with local and global bit lines. The local sensing circuitry comprise read and pass circuits configured to sense and amplify read currents during read operations, wherein the amplified read signals may be passed to a global circuit via the local and global bit lines. | 2015-10-22 |
20150303211 | SEMICONDUCTOR DEVICE HAVING THREE-DIMENSIONAL STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor pattern; conductive layers each including a first portion through which the semiconductor pattern passes and a second portion having a thickness greater than the first portion, wherein the first portion of each conductive layer includes a first barrier pattern surrounding the semiconductor pattern and a material pattern, which is formed in the first barrier pattern and has an etch selectivity with respect to the first barrier pattern, and the second portion of each conductive layer includes a conductive pattern; and contact plugs connected to the second portion of each of the conductive layers. | 2015-10-22 |
20150303212 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a semiconductor substrate, a plurality of NAND strings each of which includes a plurality of memory cells provided on the semiconductor substrate and disposed in a first direction, and a select gate provided adjacent to the memory cell at an end portion of the plurality of memory cells, such that two select gates face each other at the ends of their respective memory cells, and a first spacer layer formed on a side wall between the select gates of the NAND strings disposed adjacent to each other. The first spacer layer includes a recess therein at the portion thereof located adjacent to the semiconductor substrate. | 2015-10-22 |
20150303213 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES INCLUDING A VERTICAL CHANNEL - Semiconductor memory devices and methods of forming the semiconductor devices may be provided. The semiconductor memory devices may include a channel portion of an active pillar that may be formed of a semiconductor material having a charge mobility greater than a charge mobility of silicon. The semiconductor devices may also include a non-channel portion of the active pillar including a semiconductor material having a high silicon content. | 2015-10-22 |
20150303214 | VERTICAL MEMORY DEVICES - A vertical memory device includes a substrate including a cell region and a peripheral circuit region, the peripheral circuit region including a gate structure comprising a transistor, a plurality of channels on the cell region, each of the channels extending in a first direction that is vertical with respect to a top surface of the substrate, a plurality of gate lines stacked in the first direction and spaced apart from each other, the gate lines surrounding outer sidewalls of the channels, and a blocking structure between the cell region and the peripheral circuit region, wherein a height of the blocking structure is greater than a height of the gate structure in the peripheral region. | 2015-10-22 |
20150303215 | THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - A 3D semiconductor device includes an electrode structure has electrodes stacked on a substrate, semiconductor patterns penetrating the electrode structure, charge storing patterns interposed between the semiconductor patterns and the electrode structure, and blocking insulating patterns interposed between the charge storing patterns and the electrode structure. Each of the blocking insulating patterns surrounds the semiconductor patterns, and the charge storing patterns are horizontally spaced from each other and configured in such a way as to each be disposed around a respective one of the semiconductor patterns. Also, each of the charge storing patterns includes a plurality of horizontal segments, each interposed between vertically adjacent ones of the electrodes. | 2015-10-22 |
20150303216 | SEMICONDUCTOR DEVICE - A local interconnect is formed in contact with an upper surface of an impurity diffusion region and extends to below a potential supply interconnect. A contact hole electrically couples the local interconnect to the potential supply interconnect. The local interconnect, which is formed in contact with the upper surface of the impurity diffusion region, is used for electrically coupling the impurity diffusion region to the potential supply interconnect. | 2015-10-22 |
20150303217 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE - The electric characteristics of a semiconductor device using an oxide semiconductor are improved. The reliability of a semiconductor device using an oxide semiconductor is improved. The semiconductor device includes an element layer. The element layer includes a first film, a transistor, and a second film. The first film and the second film are partly in contact with each other. The region in which the first film and the second film are in contact with each other has a closed-loop shape when seen from above. The transistor is located between the first film and the second film. The region in which the first film and the second film are in contact with each other is located between a side surface of the element layer and the transistor. | 2015-10-22 |
20150303218 | METHOD TO CO-INTEGRATE OPPOSITELY STRAINED SEMICONDUCTOR DEVICES ON A SAME SUBSTRATE - Methods and structures for forming localized, differently-strained regions in a semiconductor layer on a substrate are described. An initial, unstrained, semiconductor-on-insulator substrate may be processed to form the differently-strained regions in the original semiconductor layer. The differently-strained regions may have opposite types of strain. The strains in the different regions may be formed independently. | 2015-10-22 |
20150303219 | DISPLAY APPARATUS - A liquid crystal display device includes: a TFT substrate that includes gate lines; and a driver circuit section that includes a gate driver that is connected to the gate lines. A frame region includes a wiring substrate that sandwiches the gate lines. The wiring substrate includes: a first wiring substrate that has first wiring lines that are connected to the gate lines; a second wiring substrate that has second wiring lines that are connected to the first wiring lines; and a third wiring substrate that is attached to the second wiring substrate and has third wiring lines that are connected to the second wiring lines and a gate driver. | 2015-10-22 |
20150303220 | SUBSTRATE FOR DISPLAY DEVICE AND METHOD FOR MANUFACTURING DISPLAY DEVICE - According to one embodiment, a substrate for display device includes an insulating substrate and a conductive film formed on at least one main surface of the insulating substrate. As to the substrate in an etching process in which a fluoric acid solution containing 10% or more hydrogen fluoride is used, a first etching rate of the conductive film is substantially the same as a second etching rate of the insulating substrate, or the first etching rate is greater than the second etching rate. | 2015-10-22 |
20150303221 | ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE COMPRISING ARRAY SUBSTRATE - An embodiment of the disclosure provides an array substrate comprising: a base substrate, an active layer and a transparent electrode disposed on the base substrate, an etch stop layer disposed on the active layer and configured for protecting a portion of the active layer, wherein the active layer, the transparent electrode and the etch stop layer are formed through one patterning process and one doping process, the doped region and the first transparent electrode are made of same material and are disposed on the same layer. | 2015-10-22 |
20150303222 | THIN FILM TRANSISTOR, ARRAY SUBSTRATE AND METHOD FOR FABRICATING THE SAME, AND DISPLAY DEVICE - A thin film transistor, an array substrate and a method for fabricating the array substrate, and a display device are disclosed. The thin film transistor comprises a gate electrode, a gate insulation layer, a semiconductor active layer, a source electrode, a drain electrode and a protection layer provided on a base substrate, and comprises: a first transparent electrode provided between the source electrode and the semiconductor active layer, corresponding to the source electrode and in direct contact with the source electrode; a second transparent electrode provided between the drain electrode and the semiconductor active layer, corresponding to the drain electrode and in direct contact with the drain electrode, the first transparent electrode is in contact with the semiconductor active layer through a first via provided in the protection layer, the second transparent electrode is in contact with the semiconductor active layer through a second via provided in the protection layer. | 2015-10-22 |
20150303223 | METHOD FOR MANUFACTURING ESD DEVICE, ESD DEVICE AND DISPLAY PANEL - There is disclosed a method for manufacturing an Electro Static Discharge (ESD) device, an ESD device and a display panel, which are capable of addressing an issue that static-electric charges accumulated on the array substrate damage the unformed ESD device and improving a yield ratio of the array substrate. The method includes forming a TFT, a first lead wire, wherein the first lead wire or the second lead wire comprises at least two separate lead-wire segments; depositing a layer of passivation thin film, and forming via-holes for connecting the at least two separate lead-wire segments on the layer of passivation thin film; depositing a layer of transparent conductive film on the substrate on which the via-holes are formed, wherein the layer of transparent conductive film connects the lead-wire segments by the via-holes. | 2015-10-22 |
20150303224 | PIXEL STRUCTURE OF DISPLAY PANEL - The present invention provides a pixel structure of a display panel and a method for manufacturing the same. The pixel structure comprises a first pixel area and a second pixel area that are adjacent to each other. The first pixel area has a first transparent conductive layer disposed therein and the second pixel area has a second transparent conductive layer disposed therein. The first transparent conductive layer in the first pixel area and the second transparent conductive layer in the second pixel area are located at different heights. The pixel structure of the present invention can efficiently increase an aperture ratio for the pixels on the display panel. | 2015-10-22 |
20150303225 | ARRAY SUBSTRATE, FABRICATION METHOD THEREOF AND DISPLAY DEVICE - An array substrate and a fabrication method thereof and a display device are provided. The fabrication method comprises: preparing a base substrate, the base substrate including a pixel region and a gate on array region; forming a pattern including a gate electrode and a pattern of an active layer on the base substrate, and forming a gate lead on the gate on array region, by a first patterning process; forming a pattern of a gate insulating layer by a second patterning process; forming a pattern including a source/drain electrode by a third patterning process; forming a pattern of a planarization layer by a fourth patterning layer; and forming a pattern including a pixel electrode by a fifth patterning layer. | 2015-10-22 |
20150303226 | PHOTOELECTRIC CONVERSION ELEMENT AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a photoelectric conversion element including a step of forming a layer containing an organic material and particles dispersed in the organic material on a member including a photoelectric conversion portion and a step of roughening a surface of the layer by dry etching. | 2015-10-22 |
20150303227 | SEMICONDUCTOR DEVICE, SOLID-STATE IMAGE SENSOR, METHODS OF MANUFACTURING THE SAME, AND CAMERA - A method of manufacturing a semiconductor device includes forming a silicon compound layer containing nitrogen on a substrate where a silicide layer and an element isolating portion have been formed, forming an opening in the silicon compound layer, and forming an interlayer insulating film which covers the silicon compound layer and the opening. The opening is formed to lie within an area of the silicon compound layer that overlaps the element isolating portion. | 2015-10-22 |
20150303228 | CMOS IMAGING DEVICE HAVING OPTIMIZED SHAPE, AND METHOD FOR PRODUCING SUCH A DEVICE BY MEANS OF PHOTOCOMPOSITION - An imaging device comprises a sensor of surface area of at least 10 cm | 2015-10-22 |
20150303229 | CMOS PROTECTION DURING GERMANIUM PHOTODETECTOR PROCESSING - A method of protecting a CMOS device within an integrated photonic semiconductor structure is provided. The method may include depositing a conformal layer of germanium over the CMOS device and an adjacent area to the CMOS device, depositing a conformal layer of dielectric hardmask over the germanium, and forming, using a mask level, a patterned layer of photoresist for covering the CMOS device and a photonic device formation region within the adjacent area. Openings are etched into areas of the deposited layer of silicon nitride not covered by the patterned photoresist, such that the areas are adjacent to the photonic device formation region. The germanium material is then etched from the conformal layer of germanium at a location underlying the etched openings for forming the photonic device at the photonic device formation region. The conformal layer of germanium deposited over the CMOS device protects the CMOS device. | 2015-10-22 |
20150303230 | METHOD FOR MANUFACTURING IMAGE CAPTURING DEVICE AND IMAGE CAPTURING DEVICE - An offset spacer film (OSS) is formed on a side wall surface of a gate electrode (NLGE, PLGE) to cover a region in which a photo diode (PD) is disposed. Next, an extension region (LNLD, LPLD) is formed using the offset spacer film and the like as an implantation mask. Next, process is provided to remove the offset spacer film covering the region in which the photo diode is disposed. Next, a sidewall insulating film (SWI) is formed on the side wall surface of the gate electrode. Next, a source-drain region (HPDF, LPDF, HNDF, LNDF) is formed using the sidewall insulating film and the like as an implantation mask. | 2015-10-22 |
20150303231 | Color Filter And Photodiode Patterning Configuration - An imaging device that includes an array of photo detectors each configured to generate an electrical signal in response to received light, and an array of color filters disposed over the array of photo detectors such that the photo detectors receive light passing through the color filters. Each of the color filters has a color transmission characteristic, which vary. To even out color balance, some of the color filters are disposed over a plurality of the photo detectors while others are disposed over only one of the photo detectors. Additional color balance can be achieved by varying the relative area sizes of the color filters and underlying photo detectors based on color transmission characteristics, to compensate for the varying absorption coefficient of the photo detectors at different colors. | 2015-10-22 |
20150303232 | PHOTOELECTRIC CONVERSION DEVICE, IMAGE PICKUP SYSTEM, AND DRIVING METHOD OF THE PHOTOELECTRIC CONVERSION DEVICE - A photoelectric conversion device has a pixel area including an effective pixel row and a reference pixel row, the reference pixel row containing a plurality of reference pixel pairs, each pair composed of a first reference pixel and a second reference pixel arranged adjacent to each other. The first and second reference pixels output reference signals having different signal levels and independent of the quantity of incident light. | 2015-10-22 |
20150303233 | IMAGE SENSORS WITH THROUGH-OXIDE VIA STRUCTURES - An imaging system may include an image sensor die stacked on top of a digital signal processor (DSP) die. The image sensor die may be a backside illuminated image sensor die. Through-oxide vias (TOVs) may be formed in the image sensor die and may extend at least partially into in the DSP die to facilitate communications between the image sensor die and the DSP die. Color filter housing structures may be formed over active image sensor pixels on the image sensor die. In-pixel grid structures may be integrated with the color filter housing structures to help reduce crosstalk. Light shielding structures may be formed over reference image sensor pixels on the image sensor die. The TOVs, the in-pixel grid structures, and the light shielding structures may be formed simultaneously. The formation of the color filter housing structures may also be integrated the formation of the TOVs. | 2015-10-22 |
20150303234 | SOLID-STATE IMAGING DEVICE, DRIVING METHOD THEREOF, AND ELECTRONIC DEVICE - A solid-state imaging device including a pixel region in which a plurality of pixels are arranged. The pixels each includes a photoelectric conversion section, a transfer transistor, a plurality of floating diffusion sections that receive a charge from the photoelectric conversion section through the transfer transistor, a reset transistor that resets the floating diffusion sections, a separating transistor that performs on-off control of a connection between the plurality of floating diffusion sections, and an amplifying transistor that outputs a signal corresponding to a potential of the floating diffusion sections. | 2015-10-22 |
20150303235 | IMAGE SENSOR PIXEL HAVING STORAGE GATE IMPLANT WITH GRADIENT PROFILE - A pixel cell includes a storage transistor disposed in a semiconductor substrate. The storage transistor includes a storage gate disposed over the semiconductor substrate, and a storage gate implant that is annealed and has a gradient profile in the semiconductor substrate under the storage transistor gate to store image charge accumulated by a photodiode disposed in the semiconductor substrate. A transfer transistor is disposed in the semiconductor substrate and is coupled between the photodiode and an input of the storage transistor to selectively transfer the image charge from the photodiode to the storage transistor. The transfer transistor includes a transfer gate disposed over the semiconductor substrate. An output transistor is coupled to an output of the storage transistor to selectively transfer the image charge from the storage transistor to a read out node. The output transistor includes an output gate disposed over the semiconductor substrate. | 2015-10-22 |
20150303236 | FLIP-CHIP BONDING METHOD AND SOLID-STATE IMAGE PICKUP DEVICE MANUFACTURING METHOD CHARACTERIZED IN INCLUDING FLIP-CHIP BONDING METHOD - An electrode of an electronic component element ( | 2015-10-22 |
20150303237 | LIGHT EMITTING MODULE AND LIGHTING APPARATUS HAVING THE SAME - A light emitting module includes a printed circuit board (PCB) and first through m-th lighting blocks of optical semiconductor devices (‘m’ is an integer greater than one). The PCB has wiring patterns electrically connecting optical semiconductor devices. The first through the m-th lighting blocks are disposed on the PCB and configured to generate light. Each of the first through the m-th lighting blocks includes first through n-th lighting groups (each block includes at least one group), each of which includes optical semiconductor devices disposed on the PCB. Electric currents configured to flow through each of the first through n-th lighting group is substantially the same. The PCB includes a pair of bodies spaced apart from each other and ‘m’ number of elbows connecting the pair of bodies, and each elbow respectively corresponds to the first through the m-th lighting blocks. | 2015-10-22 |
20150303238 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a first fin-shaped semiconductor layer on a semiconductor substrate, a first insulating film around the first fin-shaped semiconductor layer, a first pillar-shaped semiconductor layer on the first fin-shaped semiconductor layer, a first gate insulating film around the first pillar-shaped semiconductor layer, a first gate line formed around the first gate insulating film and extending in a direction perpendicular to the first fin-shaped semiconductor layer, a second diffusion layer disposed in a lower portion of the first pillar-shaped semiconductor layer, a third gate insulating film surrounding an upper portion of the first pillar-shaped semiconductor layer, a first contact electrode surrounding the third gate insulating film, a second contact electrode that connects an upper portion of the first contact electrode to an upper portion of the first pillar-shaped semiconductor layer, and a first magnetic tunnel junction memory element on the second contact electrode. | 2015-10-22 |
20150303239 | MEMORY DEVICE HAVING SELF-ALIGNED CELL STRUCTURE - Some embodiments include apparatus and methods having a memory device with diodes coupled to memory elements. Each diode may be formed in a recess of the memory device. The recess may have a polygonal sidewall. The diode may include a first material of a first conductivity type (e.g., n-type) and a second material of a second conductive type (e.g., p-type) formed within the recess. | 2015-10-22 |
20150303240 | Organic P-N Junction Based Ultraviolet Detection Device And Ultraviolet Image Detector Using Same - The present invention provides an organic p-n junction based ultraviolet detection device and an ultraviolet image detector using the device. The organic p-n junction based ultraviolet detection device ( | 2015-10-22 |
20150303241 | DISPLAY PANEL, FABRICATING METHOD THEREOF AND DISPLAY DEVICE - A display panel, a fabricating method thereof and a display device. The display panel, including: a transparent substrate; a plurality of display pixels, provided on the transparent substrate, wherein each of the plurality of display pixels includes: a plurality of first transparent self-luminous sub-pixels, provided on a light exiting surface of the transparent substrate; and a plurality of second self-luminous sub-pixels, provided on a surface of the transparent substrate opposite to the light exiting surface, and a light exiting direction of each of the second sub-pixels a direction towards the light exiting surface of the transparent substrate. | 2015-10-22 |
20150303242 | ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE - The present invention provides an array substrate, a manufacturing method thereof, and a display device, belonging to the field of organic electroluminescence display technology, which may solve the problem of low light extraction efficiency of existing array substrates. The array substrate of the present invention comprises an organic light emitting device and a planarization layer disposed therebelow, the OLED comprises: a first electrode layer, a second electrode layer, and a light-emitting layer disposed between the first electrode layer and the second electrode layer, the first electrode layer is a transparent electrode layer and disposed on the planarization layer, and the planarization layer is doped with metal micro/nanoparticles. | 2015-10-22 |
20150303243 | ORGANIC LIGHT EMITTING DISPLAY DEVICES AND METHODS OF MANUFACTURING ORGANIC LIGHT EMITTING DISPLAY DEVICES - An organic light emitting display device is disclosed. The organic light emitting display device includes a substrate, a first electrode, a pixel defining layer, a first hydrophobic pattern, at least one charge transport layer, a second hydrophobic pattern, an organic light emitting layer and a second electrode. The substrate has a pixel region and a non pixel region surrounding the pixel region. The first electrode, the at least one charge transport layer and the organic light emitting layer are disposed on the substrate in the pixel region, while the pixel defining layer, the first hydrophobic pattern and the second hydrophobic pattern are disposed on the substrate in the non pixel region. The charge transport layer of one pixel is separated from a charge transport layer of another pixel by the first and second hydrophobic patterns to prevent crosstalk phenomenon. | 2015-10-22 |
20150303244 | Electronic Devices With Display-Integrated Light Sensors - An electronic device is provided, with a display and a display-integrated light sensor. The display includes a transparent cover layer, light-generating layers, and a touch-sensitive layer. The display-integrated light sensor is interposed between the transparent cover layer and a display layer such as the touch-sensitive layer or a thin-film transistor layer of the light-generating layers. The light-generating layers include a layer of organic light-emitting material. The display-integrated light sensor can be implemented as an ambient light sensor or a proximity sensor. The display-integrated, light sensor may be a packaged light sensor that is integrated into the display layers of the display or may be formed from light-sensor components formed directly on a display circuitry layer such as the touch-sensitive layer or the thin-film transistor layer. | 2015-10-22 |
20150303245 | DISPLAY APPARATUS AND METHOD FOR MANUFACTURING THE SAME - Display apparatus, including a substrate; a pixel electrode on the substrate and corresponding to a pixel; an auxiliary line on the substrate and insulated from the pixel electrode; an insulation layer on the pixel electrode and the auxiliary line, the insulation layer covering at least a portion of the pixel electrode and at least a portion of the auxiliary line; an organic light emitting layer on the pixel electrode, the auxiliary line, and the insulation layer; a first electrode on the organic light emitting layer and overlapping at least a portion of the auxiliary line; an opening in each of the organic light emitting layer and the first electrode to correspond to the auxiliary line; and a second electrode on the first electrode and an exposed portion of the auxiliary line, the second electrode electrically connecting the auxiliary line to the first electrode, the exposed portion of the auxiliary line being exposed by the opening. | 2015-10-22 |
20150303246 | SYSTEMS AND METHODS FOR FABRICATING A POLYCRYSTALINE SEMICONDUCTOR RESISTOR ON A SEMICONDUCTOR SUBSTRATE - In accordance with embodiments of the present disclosure, an integrated circuit may include at least one region of shallow-trench isolation field oxide, at least one region of dummy diffusion, and a polycrystalline semiconductor resistor. The at least one region of shallow-trench isolation field oxide may be formed on a semiconductor substrate. The at least one region of dummy diffusion may be formed adjacent to the at least one region of shallow-trench isolation field oxide on the semiconductor substrate. The polycrystalline semiconductor resistor may comprise at least one resistor arm formed with a polycrystalline semiconductor material, wherein the at least one resistor arm is formed over each of the at least one region of shallow-trench isolation field oxide and the at least one region of dummy diffusion. | 2015-10-22 |
20150303247 | METHOD FOR FABRICATING A STRUCTURE - This method for fabricating a structure comprising, in succession, a support substrate, a dielectric layer, an active layer, a separator layer of polycrystalline silicon, comprising the steps of: a) providing a donor substrate, b) forming an embrittlement area in the donor substrate, c) providing the support structure, d) forming the separator layer on the support substrate, e) forming the dielectric layer, f) assembling the donor substrate and the support substrate, g) fracturing the donor substrate along the embrittlement area, h) subjecting the structure to a strengthening annealing of at least 10 minutes, the fabrication method being noteworthy in that step d) is executed in such a way that the polycrystalline silicon of the separator layer exhibits an entirely random grain orientation, and in that the strengthening annealing is executed at a temperature strictly greater than 950° C. and less than 1200° C. | 2015-10-22 |
20150303248 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A p anode layer is formed on one main surface of an n | 2015-10-22 |
20150303249 | METHODS FOR THE PRODUCTION OF INTEGRATED CIRCUITS COMPRISING EPITAXIALLY GROWN REPLACEMENT STRUCTURES - Integrated circuits and methods for producing such integrated circuits are provided. A method for producing the integrated circuit includes forming dummy structures in a substrate, and forming shallow trench isolation regions between the dummy structures where the shallow trench isolation regions includes a liner overlying a core. The dummy structures are etched to expose structure bases, and the structure bases are precleaned. Replacement structures are epitaxially grown over the structure bases. | 2015-10-22 |
20150303250 | Semiconductor Device Having Shallow Trench Isolation and Method of Forming the Same - A device includes a first dielectric film formed in a first trench along a first bottom surface portion and a first side surface portion with leaving a first gap in the first trench and a second dielectric film formed in a second trench along a second bottom surface portion and a second side surface portion with leaving a second gap in the second trench. The first bottom surface portion is covered approximately conformably with a first part of the first dielectric film, the first side surface portion is covered approximately conformably with a second part of the first dielectric film, and the first part is larger in thickness than the second part. The second bottom surface portion is covered approximately conformably with a third part of the second dielectric film, the second side surface portion is covered approximately conformably with a fourth part of the second dielectric film, and the third part is larger in thickness than the fourth part. | 2015-10-22 |
20150303251 | BONDED EPITAXIAL OXIDE STRUCTURES FOR COMPOUND SEMICONDUCTOR ON SILICON SUBSTRATES - A structure includes a handle substrate and an epitaxial oxide layer. The epitaxial oxide layer is bonded directly or indirectly to the handle substrate. Also included is a compound semiconductor layer adjoining and lattice matched to the epitaxial oxide layer. | 2015-10-22 |
20150303252 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate in which a multi-depth trench is formed, the multi-depth trench including a shallow trench and a deep trench arranged below the shallow trench, a first dielectric material formed in partial area of the multi-depth trench, the first dielectric material including a slope in the shallow trench that extends upward from a corner where a bottom plane of the shallow trench and a sidewall of the deep trench meets, the slope being inclined with respect to the bottom plane of the shallow trench, and a second dielectric material formed in areas of the multi-depth trench in which the first dielectric material is absent. | 2015-10-22 |
20150303253 | ISOLATION STRUCTURE, SEMICONDUCTOR DEVICE HAVING THE SAME, AND METHOD FOR FABRICATING THE ISOLATION STRUCTURE - An isolation structure of a semiconductor, a semiconductor device having the same, and a method for fabricating the isolation structure are provided. An isolation structure of a semiconductor device may include a trench formed in a substrate, an oxide layer formed on a bottom surface and an inner sidewall of the trench, a filler formed on the oxide layer to fill a part of inside of the trench, and a fourth oxide layer filling an upper portion of the filler of the trench to a height above an upper surface of the trench, an undercut structure being formed on a boundary area between the inner sidewall and the oxide layer. | 2015-10-22 |
20150303254 | SEMICONDUCTOR STRUCTURE AND A METHOD FOR PROCESSING A CARRIER - According to various embodiments, a semiconductor structure may include: a first source/drain region and a second source/drain region; a body region disposed between the first source/drain region and the second source/drain region, the body region including a core region and at least one edge region at least partially surrounding the core region; a dielectric region next to the body region and configured to limit a current flow through the body region in a width direction of the body region, wherein the at least one edge region is arranged between the core region and the dielectric region; and a gate structure configured to control the body region; wherein the gate structure is configured to provide a first threshold voltage for the core region of the body region and a second threshold voltage for the at least one edge region of the body region, wherein the first threshold voltage is less than or equal to the second threshold voltage. | 2015-10-22 |
20150303255 | SEMICONDUCTOR DEVICE STRUCTURES INCLUDING A RECTILINEAR ARRAY OF OPENINGS - A method of forming an array of openings in a substrate. The method comprises forming a template structure comprising a plurality of parallel features and a plurality of additional parallel features perpendicularly intersecting the plurality of additional parallel features of the plurality over a substrate to define wells, each of the plurality of parallel features having substantially the same dimensions and relative spacing as each of the plurality of additional parallel features. A block copolymer material is formed in each of the wells. The block copolymer material is processed to form a patterned polymer material defining a pattern of openings. The pattern of openings is transferred to the substrate to form an array of openings in the substrate. A method of forming a semiconductor device structure, and a semiconductor device structure are also described. | 2015-10-22 |
20150303256 | ELECTRONIC DEVICE COMPRISING NANOGAP ELECTRODES AND NANOPARTICLE - An electronic device includes a substrate and at least two electrodes spaced by a nanogap, wherein the at least two electrodes are bridged by at least one nanoparticle and wherein the at least one nanoparticle has an overlap area with the at least two electrodes higher than 2% of the area of the at least one nanoparticle. A method of manufacturing of the electronic device and the use of the electronic device in photodetector, transistor, phototransistor, optical modulator, electrical diode, photovoltaic cell or electroluminescent component are also described. | 2015-10-22 |
20150303257 | Gate-All-Around Nanowire MOSFET and Method of Formation - A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a portion of the nanowire and a portion of the insulator layer; forming recesses in the insulator layer on opposing sides of the dummy gate; forming spacers on opposing sides of the dummy gate; forming source regions and drain regions in the recesses in the insulator layer on opposing sides of the dummy gate; depositing an interlayer dielectric on the source regions and the drain regions; removing the dummy gate to form a trench; removing the insulator layer under the nanowire such that a width of the trench underneath the nanowire is equal to or less than a distance between the spacers; and forming a replacement gate in the trench. | 2015-10-22 |
20150303258 | SILICON AND SILICON GERMANIUM NANOWIRE STRUCTURES - Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other. | 2015-10-22 |
20150303259 | CIRCUITS USING GATE-ALL-AROUND TECHNOLOGY - A semiconductor structure includes a first gate-all-around (GAA) structure configured to form a first circuit and a second GAA structure configured to form a second circuit similar to the first circuit. The first GAA structure and the second GAA structure have a same of at least one of the following exemplary features: a number of GAA devices in which current flows from a first oxide definition (OD) region to a second OD region; a number of GAA devices in which current flows from the second OD region to the first OD region; a number of first OD region contact elements; a number of second OD region contact elements. | 2015-10-22 |
20150303260 | Vertical Semiconductor Device - A semiconductor body includes first and second opposing surfaces, an edge extending in a vertical direction substantially perpendicular to the first surface, an active area, a peripheral area arranged in a horizontal direction substantially parallel to the first surface between the active area and edge, and a pn-junction extending from the active area into the peripheral area. In the peripheral area the semiconductor device further includes a first conductive region arranged next to the first surface, a second conductive region arranged next to the first surface, and arranged in the horizontal direction between the first conductive region and edge, and a passivation structure including a first portion at least partly covering the first conductive region, a second portion at least partly covering the second conductive region. The first portion has a different layer composition than the second portion and/or a thickness which differs from the thickness of the second portion. | 2015-10-22 |
20150303261 | TENSILE NITRIDE PROFILE SHAPER ETCH TO PROVIDE VOID FREE GAPFILL - A method of reducing the impact of FEoL topography on dual stress liner depositions and the resulting device are disclosed. Embodiments include forming a first nitride layer between and over a pFET and an nFET; thinning the first nitride layer; forming a second nitride layer over the first nitride layer; and removing the first and the second nitride layers from over the pFET. | 2015-10-22 |
20150303262 | NANOWIRE FET WITH TENSILE CHANNEL STRESSOR - Fin stacks including a silicon germanium alloy portion and a silicon portion are formed on a surface of a substrate. Sacrificial gate structures are then formed straddling each fin stack. Silicon germanium alloy portions that are exposed are oxidized, while silicon germanium alloy portions that are covered by the sacrificial gate structures are not oxidized. A dielectric material having a topmost surface that is coplanar with a topmost surface of each sacrificial gate structure is formed, and thereafter each sacrificial gate structure is removed. Non-oxidized silicon germanium alloy portions are removed suspending silicon portions that were present on each non-oxidized silicon germanium alloy portion. A functional gate structure is then formed around each suspended silicon portion. The oxidized silicon germanium alloy portions remain and provide stress to a channel portion of the suspended silicon portions. | 2015-10-22 |
20150303263 | METHOD FOR LOW TEMPERATURE BONDING AND BONDED STRUCTURE - A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO | 2015-10-22 |
20150303264 | METHOD FOR COUPLING A GRAPHENE LAYER AND A SUBSTRATE AND DEVICE COMPRISING THE GRAPHENE/SUBSTRATE STRUCTURE OBTAINED - The present disclosure regards a method for coupling a graphene layer to a substrate having at least one hydrophilic surface, the method comprising the steps of providing the substrate having at least one hydrophilic surface, depositing on the hydrophilic surface a layer of a solvent selected in the group constituted by acetone, ethyl lactate, isopropyl alcohol, methylethyl ketone and mixtures thereof and depositing on the solvent layer a graphene layer. It moreover regards an electronic device comprising the graphene/substrate structure obtained. | 2015-10-22 |
20150303265 | SEMICONDUCTOR DEVICE WITH TRENCH ISOLATION - A semiconductor device includes a semiconductor substrate and a trench isolation. The trench isolation is located in the semiconductor substrate, and includes an epitaxial layer and a dielectric material. The epitaxial layer is in a trench of the semiconductor and is peripherally enclosed thereby, in which the epitaxial layer is formed by performing etch and epitaxy processes. The etch and epitaxy process includes etching out a portion of a sidewall of the trench and a portion of a bottom surface of the trench and forming the epitaxial layer conformal to the remaining portion of the sidewall and the remaining portion of the bottom surface. The dielectric material is peripherally enclosed by the epitaxial layer. | 2015-10-22 |
20150303266 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide semiconductor device has a silicon carbide substrate, a gate insulating film, and a gate electrode. Silicon carbide substrate includes a first impurity region having a first conductivity type, a well region being in contact with the first impurity region and having a second conductivity type which is different from the first conductivity type, and a second impurity region separated from the first impurity region by the well region and having the first conductivity type. The gate insulating film is in contact with the first impurity region and the well region. The gate electrode is in contact with the gate insulating film and is arranged opposite to the well region with respect to the gate insulating film. A specific on-resistance at a voltage which is half a gate driving voltage applied to the gate electrode is smaller than twice the specific on-resistance at the gate driving voltage. | 2015-10-22 |
20150303267 | SILICON CARBIDE SEMICONDUCTOR DEVICE - First and second ranges of a silicon carbide film have an interface. The first range includes: a first breakdown voltage holding layer having a first conductivity type; and an outer edge embedded region provided at an interface in the outer edge portion and having a second conductivity type. The second range includes a second breakdown voltage holding layer having the first conductivity type. A semiconductor element is formed in the second range. The first range includes: a central section facing the semiconductor element in the central portion in a thickness direction; and an outer edge section facing the semiconductor element in the outer edge portion in the thickness direction. At the interface, the outer edge section includes a portion having an impurity concentration different from the impurity concentration of the central section. | 2015-10-22 |
20150303268 | DIODE AND POWER CONVERSION DEVICE - It is an object of the present invention to provide a diode that can be produced with a simple method and performs a favorable recovery operation. The diode in accordance with the present invention includes a layer with a high concentration of dopants and a layer with a low concentration of dopants, and the layer with a low concentration of dopants further includes a layer with a different activation rate from other potions (see FIG. | 2015-10-22 |
20150303269 | TRANSISTOR AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - Provided is a semiconductor device including a pillar, a gate electrode having a first conductive pattern surrounding the pillar and a plurality of second conductive patterns which protrude from the first conductive pattern and are arranged to be spaced apart from each other, and an insulating pattern interposed between the pillar and the first conductive pattern. | 2015-10-22 |
20150303270 | CONNECTION STRUCTURE FOR VERTICAL GATE ALL AROUND (VGAA) DEVICES ON SEMICONDUCTOR ON INSULATOR (SOI) SUBSTRATE - A vertical gate all around (VGAA) nanowire device circuit routing structure is disclosed. The circuit routing structure comprises a plurality of VGAA nanowire devices including a NMOS and a PMOS device. The devices are formed on a semiconductor-on-insulator substrate. Each device comprises a bottom plate and a top plate wherein one of the bottom and top plates serves as a drain node and the other serves as a source node. Each device further comprises a gate layer. The gate layer fully surrounds a vertical channel in the device. In one example, a CMOS circuit is formed with an oxide (OD) block layer that serves as a common bottom plate for the NMOS and PMOS devices. In another example, a CMOS circuit is formed with a top plate that serves as a common top plate for the NMOS device and the PMOS devices. In another example, a SRAM circuit is formed. | 2015-10-22 |
20150303271 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - This silicon carbide semiconductor device includes: a silicon carbide semiconductor layer; a gate insulating layer which is arranged over the silicon carbide semiconductor layer and which includes a silicon oxide film; a gate electrode which is arranged on the gate insulating layer; and a carbon transition layer which is interposed between the silicon carbide semiconductor layer and the silicon oxide film and which has a carbon atom concentration is 10% to 90% of a carbon atom concentration of the silicon carbide semiconductor layer. In a region of the carbon transition layer which is located closer to the silicon oxide film than a position where a nitrogen atom concentration becomes the highest is, a ratio of an integral of nitrogen atom concentrations to an integral of carbon atom concentrations is equal to or greater than 0.11. | 2015-10-22 |
20150303272 | STRUCTURE AND METHOD TO FORM A FINFET DEVICE - A method for fabricating a FinFET device includes forming a silicon-on-insulator (SOI) substrate having a semiconductor layer overlaying a buried oxide (BOX) layer; etching the semiconductor layer to form a plurality of fin structures and a semiconductor layer gap in between the plurality of fin structures and the BOX layer; depositing a sacrificial gate over at least one gate region, wherein the gate region separates a source and a drain region; disposing offset spacers on vertical sidewalls of the sacrificial gate; removing the sacrificial gate; removing the semiconductor layer gap in the gate region to prevent merging of the plurality of fin structures in the gate regions; and fabricating a high-k dielectric metal gate structure overlaying the fin structures in the gate region. | 2015-10-22 |
20150303273 | PATTERNING MULTIPLE, DENSE FEATURES IN A SEMICONDUCTOR DEVICE USING A MEMORIZATION LAYER - Provided are approaches for patterning multiple, dense features in a semiconductor device using a memorization layer. Specifically, an approach includes: patterning a plurality of openings in a memorization layer; forming a gap-fill material within each of the plurality of openings; removing the memorization layer; removing an etch stop layer adjacent the gap-fill material, wherein a portion of the etch stop layer remains beneath the gap-fill material; etching a hardmask to form a set of openings above the set of gate structures, wherein the etch to the hardmask also removes the gap-fill material from atop the remaining portion of the etch stop layer; and etching the semiconductor device to remove the hardmask within each of the set of openings. In one embodiment, a set of dummy S/D contact pillars is then formed over a set of fins of the semiconductor device by etching a dielectric layer selective to the gate structures. | 2015-10-22 |
20150303274 | METHOD FOR MANUFACTURING FIN STRUCTURE - A method for manufacturing a fin structure is provided. A method according to an embodiment may include: forming a patterned pattern transfer layer on a substrate; forming a first spacer on sidewalls of the pattern transfer layer; forming a second spacer on sidewalls of the first spacer; selectively removing the pattern transfer layer and the first spacer; and patterning the substrate with the second spacer as a mask, so as to form an initial fin. | 2015-10-22 |
20150303275 | BASE PROFILE OF SELF-ALIGNED BIPOLAR TRANSISTORS FOR POWER AMPLIFIER APPLICATIONS - According to a bipolar transistor structure having a transistor top and a transistor bottom herein, a silicon substrate located at the transistor bottom has a collector region of a first conductivity type. An epitaxial base layer of a second conductivity type overlies, relative to the transistor top and bottom, a portion of the collector region. The epitaxial base layer has a bottom surface on the silicon substrate and a top surface opposite the bottom surface. A top region, relative to the transistor top and bottom, of the epitaxial base layer comprises a concentration of germanium having atomic compositions sufficient to avoid impacting transistor parameters, and sufficient to be resistant to selective chemical etching. A silicon emitter layer of the first conductivity type overlies, relative to the transistor top and bottom, a portion of the epitaxial base layer adjacent to the top surface of the epitaxial base layer. | 2015-10-22 |
20150303276 | METHOD OF FABRICATING A LATERAL INSULATED GATE BIPOLAR TRANSISTOR - A method of fabricating a transistor includes doping non-overlapping first, second, and third wells in a silicon layer of a substrate. The substrate, second and third wells have a first type of conductivity and the first well and silicon layer have a second type of conductivity. First and second insulating layers are thermally grown over the second well between the first well and the third well, and over the third well, respectively. A gate stack is formed over the first insulating layer and the third well. A first source region having the second type of conductivity is formed in the third well. A gate spacer is formed, a fourth well having the first type of conductivity is doped in the third well between the second insulating layer and the gate spacer, a second source region is formed over the fourth well, and a drain is formed in the first well. | 2015-10-22 |
20150303277 | Gate to Diffusion Local Interconnect Scheme Using Selective Replacement Gate Flow - A method of fabricating a device is provided which includes selectively implanting one or more dopants into a semiconductor wafer so as to form doped and undoped regions of the wafer; forming fins in the wafer with at least a given one of the fins being formed both from a portion of the doped region of the wafer and from a portion of the undoped region of the wafer; forming dummy gates on the wafer; depositing a filler layer around the dummy gates; removing the dummy gates forming trenches in the filler layer, at least one of which extends down to the undoped portion of the fin and at least another of which extends down to the doped portion of the fin; selectively forming a gate dielectric lining the trenches which extend down to the undoped portion of the fin; and forming replacement gates in the trenches. | 2015-10-22 |
20150303278 | METHOD OF FABRICATING A MOSFET WITH AN UNDOPED CHANNEL - A method of fabricating a MOSFET with an undoped channel is disclosed. The method comprises fabricating on a substrate a semiconductor structure having a dummy poly gate, dummy interlayer (IL) oxide, and a doped channel. The method further comprises removing the dummy poly gate and the dummy IL oxide to expose the doped channel, removing the doped channel from an area on the substrate, forming an undoped channel for the semiconductor structure at the area on the substrate, and forming a metal gate for the semiconductor structure. Removing the dummy poly gate may comprise dry and wet etch operations. Removing the dummy IL oxide may comprise dry etch operations. Removing the doped channel may comprise anisotropic etch operations on the substrate. Forming an undoped channel may comprise applying an epitaxial process to grow the undoped channel. The method may further comprise growing IL oxide above the undoped channel. | 2015-10-22 |
20150303279 | Method of Forming Tungsten Nitride Layer of Tungsten Gate - A method for manufacturing a semiconductor device includes providing a front-end device containing a dummy gate, removing the dummy gate, and forming a gate structure including a tungsten gate in a location previously occupied by the dummy gate that has been removed. The method also includes etching back a portion of the tungsten gate, forming a laminate structure having at least one layer of tungsten and one layer of tungsten nitride on the etched back tungsten gate, and forming a silicon nitride cap layer on the laminate structure. | 2015-10-22 |
20150303280 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A thin film transistor structure in which a source electrode and a drain electrode formed from a metal material are in direct contact with an oxide semiconductor film may lead to high contact resistance. One cause of high contact resistance is that a Schottky junction is formed at a contact plane between the source and drain electrodes and the oxide semiconductor film. An oxygen-deficient oxide semiconductor layer which includes crystal grains with a size of 1 nm to 10 nm and has a higher carrier concentration than the oxide semiconductor film serving as a channel formation region is provided between the oxide semiconductor film and the source and drain electrodes. | 2015-10-22 |
20150303281 | FINFET DEVICE WITH VERTICAL SILICIDE ON RECESSED SOURCE/DRAIN EPITAXY REGIONS - A method of forming a semiconductor device that includes forming a fin structure from a semiconductor substrate, and forming a gate structure on a channel region portion of the fin structure. A source region and a drain region are formed on a source region portion and a drain region portion of the fin structure on opposing sides of the channel portion of the fin structure. At least one sidewall of the source region portion and the drain region portion of the fin structure is exposed. A metal semiconductor alloy is formed on the at least one sidewall of the source region portion and the drain region portion of the fin structure that is exposed. | 2015-10-22 |
20150303282 | METHOD TO INDUCE STRAIN IN FINFET CHANNELS FROM AN ADJACENT REGION - Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures. | 2015-10-22 |
20150303283 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes the following steps. A substrate including at least a fin layer and a plurality of gate electrodes is provided. A tilt and twist ion implantation is performed to form a plurality of doped regions in the fin layer. An etching process is performed to remove the doped regions to form a plurality of recesses in the fin layer. | 2015-10-22 |
20150303284 | PUNCH THROUGH STOPPER IN BULK FINFET DEVICE - A method of forming a semiconductor device that includes forming a fin structure from a bulk semiconductor substrate and forming an isolation region contacting a lower portion of a sidewall of the fin structure, wherein an upper portion of the sidewall of the fin structure is exposed. A sacrificial spacer is formed on the upper portion of the sidewall of the fin structure. The isolation regions are recessed to provide an exposed section of the sidewall of the fin structure. A doped semiconductor material is formed on the exposed section of the lower portion of the sidewall of the fin structure. Dopant is diffused from the doped semiconductor material to a base portion of the fin structure. | 2015-10-22 |
20150303285 | MULTI-FIN FINFET DEVICE INCLUDING EPITAXIAL GROWTH BARRIER ON OUTSIDE SURFACES OF OUTERMOST FINS AND RELATED METHODS - A multi-fin FINFET device may include a substrate and a plurality of semiconductor fins extending upwardly from the substrate and being spaced apart along the substrate. Each semiconductor fin may have opposing first and second ends and a medial portion therebetween, and outermost fins of the plurality of semiconductor fins may comprise an epitaxial growth barrier on outside surfaces thereof. The FINFET may further include at least one gate overlying the medial portions of the semiconductor fins, a plurality of raised epitaxial semiconductor source regions between the semiconductor fins adjacent the first ends thereof, and a plurality of raised epitaxial semiconductor drain regions between the semiconductor fins adjacent the second ends thereof. | 2015-10-22 |
20150303286 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - In a transistor including an oxide semiconductor film, a metal oxide film which has a function of preventing electrification and covers a source electrode and a drain electrode is formed in contact with the oxide semiconductor film, and then, heat treatment is performed. Through the heat treatment, impurities such as hydrogen, moisture, a hydroxyl group, or hydride are intentionally removed from the oxide semiconductor film, whereby the oxide semiconductor film is highly purified. By providing the metal oxide film, generation of a parasitic channel on the back channel side of the oxide semiconductor film in the transistor is prevented. | 2015-10-22 |
20150303287 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor element with a plurality of gates, an emitter pattern insulated from the plurality of gates and an emitter electrode formed on the emitter pattern, the semiconductor element being formed such that a main current flows into the emitter electrode via the emitter pattern, a first solder formed on a part of the emitter electrode, a second solder formed on a part of the emitter electrode apart from the first solder, and a terminal connected to the emitter electrode by means of the first solder and the second solder, wherein the semiconductor element includes a first solder region, a second solder region and an intermediate region, a density of the gates in each of the solder regions are equal, and a current density of the main current in the intermediate region is lower than current densities of the main currents in the other solder regions. | 2015-10-22 |
20150303288 | Switching Device for Power Conversion and Power Conversion Device - The present invention provides a switching device ( | 2015-10-22 |
20150303289 | NANOWIRE ELECTRIC FIELD EFFECT SENSOR HAVING THREE-DIMENSIONAL STACKING STRUCTURE NANOWIRE AND MANUFACTURING METHOD THEREFOR - The present invention provides a nanowire sensor comprising nanowires, in which the nanowires are stacked to form a three-dimensional structure so that they have a large exposed surface area compared to that of a conventional straight nanowire sensor in the same limited area, thereby increasing the probability of attachment of a target material to the nanowires to thereby increase the measurement sensitivity of the sensor. Thus, a change in the electrical conductivity (conductance or resistance) of the nanowires can be sensed with higher sensitivity, suggesting that the sensor has increased sensitivity. | 2015-10-22 |
20150303290 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device comprises a substrate, a semiconductor multilayer structure supported by the substrate, and a first nitride transistor provided in a first area of the semiconductor multilayer structure. The semiconductor multilayer structure comprises first to fourth nitride semiconductor layers. The first nitride transistor comprises part of the first nitride semiconductor layer, part of the second nitride semiconductor layer, part of the third nitride semiconductor layer, part of the fourth nitride semiconductor layer, a first gate electrode electrically connected to the part of the first nitride semiconductor layer, a first source electrode electrically connected to one of two portions in the third nitride semiconductor layer, a first drain electrode electrically connected to the other one of the two portions, and a first substrate electrode electrically connected to the part of the fourth nitride semiconductor layer. | 2015-10-22 |
20150303291 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor layer made of a nitride semiconductor and formed on a substrate, a second semiconductor layer made of a material including InAlN and formed on the first semiconductor layer, an insulator layer formed by an oxidized surface part of the second semiconductor layer, a gate electrode formed on the insulator layer, and a source electrode and a drain electrode respectively formed on the first or second semiconductor layer. | 2015-10-22 |
20150303292 | NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device includes: a substrate; a buffer layer formed on the substrate; a laminated body formed by two or more cycles of semiconductor layers each including a first nitride semiconductor layer, and a second nitride semiconductor layer having a larger band gap than a band gap of the first nitride semiconductor layer, the first and second nitride semiconductor layers being laminated in this order on the buffer layer; a first electrode; and a second electrode. A channel layer is formed in each of the semiconductor layers at an interface between the first nitride semiconductor layer and the second nitride semiconductor layer. A carrier concentration of the channel layer in the uppermost semiconductor layer is lower than a carrier concentration of each of the channel layers of the other semiconductor layers. | 2015-10-22 |
20150303293 | FIELD-EFFECT TRANSISTOR - A field-effect transistor includes a codoped layer made of Al | 2015-10-22 |
20150303294 | VERTICAL SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE VERTICAL SEMICONDUCTOR DEVICE - Aspects of the invention are directed to a vertical semiconductor device including an element active portion and a voltage withstanding structure portion has a first main electrode and a gate pad electrode on a first main surface of the element active portion, includes first parallel pn layers in a drift layer below the first main electrode, and includes second parallel pn layers below the gate pad electrode. The vertical semiconductor device includes a first conductivity type isolation region between the second parallel pn layers below the gate pad electrode and a p-type well region disposed in a surface layer of the drift layer, and by the repetition pitch of the second parallel pn layers being shorter than the repetition pitch of the first parallel pn layers, it is possible to obtain low on-state resistance, high avalanche withstand, high turn-off withstand, and high reverse recovery withstand. | 2015-10-22 |
20150303295 | SELF-ALIGNED CONTACT OPENINGS OVER FINS OF A SEMICONDUCTOR DEVICE - Approaches for forming a set of contact openings in a semiconductor device (e.g., a FinFET device) are provided. Specifically, the semiconductor device includes a set of fins formed in a substrate, a gate structure (e.g., replacement metal gate (RMG)) formed over the substrate, and a set of contact openings adjacent the gate structure, each of the set of contact openings having a top section and a bottom section, wherein a width of the bottom section, along a length of the gate structure, is greater than a width of the top section. The semiconductor device further includes a set of metal contacts formed within the set of contact openings. | 2015-10-22 |
20150303296 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for producing a semiconductor device includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film around the fin-shaped semiconductor layer; and a second step following the first step and including forming a second insulating film around the fin-shaped semiconductor layer, depositing a first polysilicon on the second insulating film to conduct planarization, forming a second resist for forming a gate line and a pillar-shaped semiconductor layer so that the second resist extends in a direction perpendicular to a direction in which the fin-shaped semiconductor layer extends, and etching the first polysilicon, the second insulating film, and the fin-shaped semiconductor layer to form a pillar-shaped semiconductor layer and a first dummy gate formed of the first polysilicon. | 2015-10-22 |
20150303297 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a cell region of a first major surface of a semiconductor substrate of a first conductivity type, a first well of a second conductivity type is in an upper surface. A diffusion region of a first conductivity type is in the upper surface in the first well. A first gate insulating film is on the first well, and a first gate electrode on the first gate insulating film. A second well of a second conductivity type is in the upper surface of the first major surface on a peripheral portion of the cell region. A second gate insulating film is on the second well, and a thick field oxide film is on the peripheral side than the second gate insulating film. A second gate electrode is sequentially on the second gate insulating film and the field oxide film and electrically connected to the first gate electrode. A first electrode is connected to the first, second well and the diffusion region. A second electrode is connected on a second major surface of the semiconductor substrate. A gate wiring is on the field oxide film, going around a periphery of the cell region, and electrically connected to the second gate electrode. The gate wiring is a silicide of a constituting substance of the second gate electrode. | 2015-10-22 |
20150303298 | Semiconductor Device and Super Junction Semiconductor Device Having Semiconductor Mesas - A semiconductor device includes semiconductor mesas of a first conductivity type extending between a first surface and a bottom plane of a semiconductor portion, and a semiconductor structure of a second, complementary conductivity type extending along sidewalls of the semiconductor mesas and outwardly from the semiconductor mesas. A thickness of the semiconductor structure has a local maximum value at a first distance to both the first surface and the bottom plane. | 2015-10-22 |
20150303299 | 3D UTB TRANSISTOR USING 2D MATERIAL CHANNELS - A semiconductor device and a method of manufacture are provided. A substrate has a dielectric layer formed thereon. A three-dimensional feature, such as a trench or a fin, is formed in the dielectric layer. A two-dimensional layer, such as a layer (or multilayer) of graphene, transition metal dichalcogenides (TMDs), or boron nitride (BN), is formed over sidewalls of the feature. The two-dimensional layer may also extend along horizontal surfaces, such as along a bottom of the trench or along horizontal surfaces of the dielectric layer extending away from the three-dimensional feature. A gate dielectric layer is formed over the two-dimensional layer and a gate electrode is formed over the gate dielectric layer. Source/drain contacts are electrically coupled to the two-dimensional layer on opposing sides of the gate electrode. | 2015-10-22 |
20150303300 | VERTICAL MOS SEMICONDUCTOR DEVICE FOR HIGH-FREQUENCY APPLICATIONS, AND RELATED MANUFACTURING PROCESS - A MOS semiconductor device of a vertical type has: a functional layer, having a first type of conductivity; gate structures, which are formed above the functional layer and have a region of dielectric material and an electrode region; body wells, which have a second type of conductivity, are formed within the functional layer, and are separated by a surface separation region; source regions, which have the first type of conductivity and are formed within the body wells. Each gate structure extends laterally above just one respective body well and does not overlap the surface separation region of the functional layer. The device may further have: at least one shield structure, arranged between adjacent gate structures above the surface separation region; and/or at least one doped control region, having the second type of conductivity, arranged within the surface separation region, which are both set at the source potential. | 2015-10-22 |
20150303301 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A semiconductor device includes a fin-shaped semiconductor layer, a first insulating film formed around the fin-shaped semiconductor layer, a first metal film formed around the first insulating film, a pillar-shaped semiconductor layer formed on the fin-shaped semiconductor layer, a gate insulating film formed around the pillar-shaped semiconductor layer, a gate electrode formed around the gate insulating film and made of a third metal, a gate line connected to the gate electrode, a second insulating film formed around a sidewall of an upper portion of the pillar-shaped semiconductor layer, and a second metal film formed around the second insulating film. The upper portion of the pillar-shaped semiconductor layer and the second metal film are connected to each other, and an upper portion of the fin-shaped semiconductor layer and the first metal film are connected to each other. | 2015-10-22 |
20150303302 | SEMICONDUCTOR DEVICE AND FORMATION THEREOF - A semiconductor device and method of forming the same are described. A semiconductor device includes an active area adjacent a channel in a semiconductor composite. The active area includes a first active area layer having a first dopant concentration, a second active area layer having a second dopant concentration over the first active area layer, and a third active area layer having a third dopant concentration, over the second active area. The third dopant concentration is greater than the second dopant concentration, and the second dopant concentration is greater than the first dopant concentration. The channel includes a second channel layer comprising carbon over a first channel layer and a third channel layer over the second channel layer. The active area configuration improves drive current and reduces contact resistance, and the channel configuration increases short channel control, as compared to a semiconductor device without the active area and channel configuration. | 2015-10-22 |
20150303303 | NANOWIRE FET WITH TENSILE CHANNEL STRESSOR - Fin stacks including a silicon germanium alloy portion and a silicon portion are formed on a surface of a substrate. Sacrificial gate structures are then formed straddling each fin stack. Silicon germanium alloy portions that are exposed are oxidized, while silicon germanium alloy portions that are covered by the sacrificial gate structures are not oxidized. A dielectric material having a topmost surface that is coplanar with a topmost surface of each sacrificial gate structure is formed, and thereafter each sacrificial gate structure is removed. Non-oxidized silicon germanium alloy portions are removed suspending silicon portions that were present on each non-oxidized silicon germanium alloy portion. A functional gate structure is then formed around each suspended silicon portion. The oxidized silicon germanium alloy portions remain and provide stress to a channel portion of the suspended silicon portions. | 2015-10-22 |
20150303304 | METHOD FOR FORMING FIN FET STRUCTURE WITH DUAL-STRESS SPACERS - This application discloses a Fin FET structure and a method for forming the same. In the Fin FET structure, there are lower stress spacers disposed over the lower portion of the fin's opposite sidewalls, asserting one stress type to suppress the carrier mobility; there are also upper stress spacers disposed over the upper portion of the fin's opposite sidewalls, asserting an opposite stress type to increase the carrier mobility. Therefore, the leakage current in the fin FET is reduced and the device performance is improved. In the method, the stress spacers are formed by depositing stress layers and etching back the stress layers, where stress types and magnitudes are controllable, resulting in a simple process. | 2015-10-22 |
20150303305 | FinFET Device with High-K Metal Gate Stack - The present disclosure provides a semiconductor device that includes a substrate, a first fin structure over the substrate. The first fin structure includes a first semiconductor material layer, having a semiconductor oxide layer as its outer layer, as a lower portion of the first fin structure. The first semiconductor has a first width. The first fin structure also includes a second semiconductor material layer as an upper portion of the first fin structure. The second semiconductor material layer has a third width, which is substantially smaller than the first width. The semiconductor structure also includes a gate region formed over a portion of the first fin and a high-k (HK)/metal gate (MG) stack on the substrate including wrapping over a portion of the first fin structure in the gate region. | 2015-10-22 |
20150303306 | THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME, ARRAY SUBSTRATE, DISPLAY DEVICE - There are provided a thin film transistor and a manufacturing method thereof, an array substrate and a display device. The thin film transistor is formed on a base substrate, and includes a gate electrode, an active layer, a source electrode and a drain electrode, the gate electrode includes a first section, a second section and a third section, the first section and the third section correspond to locations of the source electrode and the drain electrode, respectively; the base substrate has two recesses formed therein, and the first section and the third section are situated in the two recesses, respectively; the first section and the third section are covered with a filling layer; the filling layer and the second section are covered with a gate insulating layer, the active layer, the source electrode and the drain electrode in sequence. | 2015-10-22 |
20150303307 | SEMICONDUCTOR DEVICE AND DISPLAY DEVICE - This semiconductor device is provided with: a semiconductor film that comprises an oxide semiconductor, and includes a channel region; a first inorganic insulating film formed on the semiconductor film; a first organic insulating film formed on the first inorganic insulating film; and an inorganic film group. The inorganic film group has: a first electrode comprising an inorganic conductive film formed on the first organic insulating film; a second inorganic insulating film formed on the first electrode; and a second electrode that comprises an inorganic conductive film formed on the second inorganic insulating film, and is electrically connected to the semiconductor film via openings formed in such a manner as to penetrate the first inorganic insulating film, the first organic insulating film, the first electrode and the second inorganic insulating film. The first organic insulating film is disposed between the first inorganic insulating film and the inorganic film group. | 2015-10-22 |
20150303308 | SELF-ALIGNED METAL OXIDE THIN-FILM TRANSISTOR COMPONENT AND MANUFACTURING METHOD THEREOF - The present invention is applicable to the field of electronic component technologies and provides a manufacturing method of a self-aligned metal oxide TFT component, including: selecting a substrate and preparing a gate on the substrate; successively disposing an insulation layer, a transparent electrode layer, and a photoresist on the gate; using the gate as a mask to perform exposure from a back side of the substrate, so as to form a source and a drain that are aligned with the gate; depositing a metal oxide semiconductor layer on the transparent electrode layer; performing etching on the semiconductor layer, the source, and the drain, so that outer ends of the source and the drain are exposed out of the metal oxide semiconductor layer; and depositing a passivation layer and leading out the source and the drain. In the present invention, a transparent conductor is used as the electrode layer, and a bottom gate is used as a mask to perform back exposure, so as to perform etching on the source and the drain, thereby implementing a self-alignment between the source or the drain and the gate, effectively reducing parasitic capacitance, and improving component performance. The component is of a bottom-gate bottom-contact structure, and there is no need to manufacture an etch-stop layer, thereby simplifying a process, reducing use of a photolithographic mask, improving production efficiency, and improving an electrical property of the component. | 2015-10-22 |