43rd week of 2008 patent applcation highlights part 21 |
Patent application number | Title | Published |
20080258682 | Electric Public Transit System - The present invention relates to an electric public transit system, comprising electric driven buses with a cassette battery set and bus-mounted control system, a charge station and a loading and unloading apparatus. When said bus needs change the cassette battery set, said loading and unloading apparatus takes said cassette battery set from said bus and then replace with a charged cassette battery set. Both said charge station and said loading and unloading apparatus are equipped with their control systems, respectively, which can intercommunicate with said bus-mounted control system. In the present invention, the cassette battery sets are charged during power consumption valleys of the power grid, and therefore, the transit system can save energy and benefit the environment. Additionally it is also fast and accurate for loading and unloading the cassette battery set in the system of the present invention, which can also guarantee the bus operating online continuously and greatly enhance the usage ratio of the bus. | 2008-10-23 |
20080258683 | Rechargeable battery assembly and power system using same - A rechargeable battery, battery set or battery pack having a circuit or a plurality of circuits for providing self-discharging thereof electrically connected in parallel are used to form rechargeable battery assemblies and electric power supply systems for use in electric and hybrid vehicles and the like. | 2008-10-23 |
20080258684 | BATTERY SYSTEM - A battery system capable of inhibiting a reverse voltage applied to a unit cell that has lost the electromotive force without active control is provided. The battery system include two or more unit cells electrically connected in series, and a rectification section that is composed of at least one of an electronic device having a rectification function and an interface having a rectification action, and is electrically connected to the respective two or more unit cells in parallel. | 2008-10-23 |
20080258685 | BATTERY DISCHARGE CURRENT SHARING IN A TIGHTLY REGULATED POWER SYSTEM - In a high power system, plural batteries provide back-up power when primary power is unavailable. Each battery has an associated discharge controller which is controlled by a local bus control amplifier which regulates the power bus voltage set-point lower than the main bus voltage set-point. A single main bus control amplifier tightly regulates the power bus to a main bus voltage set-point and controls charging and discharging of all batteries to prevent charging of one battery at the expense (discharge) of another battery. There is one master battery discharge controller, with the remaining controllers being slave units. A local bus voltage set-point of each slave unit varies under the control of a slave unit current sharing amplifier which compares its own discharge current to the average discharge current, and an error signal modifies the reference voltage in the local bus control amplifier to allow equal discharge current from all batteries. | 2008-10-23 |
20080258686 | Method for Detecting Removal of a Battery from a Battery Charger - A method for detecting removal of a battery from a battery charger includes 1) incrementing an event counter and resetting an interval counter each time the voltage present at the output node exceeds a predetermined voltage; 2) resetting the event counter each time the interval counter exceeds a predetermined maximum time between events; and 3) asserting a signal indicating the absence of a battery connected between the positive and negative output nodes each time event counter exceeds a predetermined number of events. | 2008-10-23 |
20080258687 | High Efficiency PWM Switching Mode with High Accuracy Linear Mode Li-Ion Battery Charger - A battery charger includes: a step-down switching converter connected to provide power at a predetermined average current from an input voltage V+ to an output node V | 2008-10-23 |
20080258688 | Battery Charging Systems and Methods with Adjustable Current Limit - Embodiments of the present invention include techniques for charging a battery using a regulator. In one embodiment, the present invention includes an electronic circuit comprising a regulator having an input coupled to a power source for receiving a voltage and a current and an output for providing an output current, an input voltage detection circuit coupled to the power source, and an adjustable current limit circuit for controlling the input or output current of the regulator, wherein input voltage detection circuit monitors the voltage from the power source and the adjustable current limit circuit changes the input or output current of the regulator to optimize the power drawn from power source. | 2008-10-23 |
20080258689 | Charging Method and Circuit Using Indirect Current Sensing - The present invention relates to a charging circuit and method for generating a charging current supplied to an output terminal ( | 2008-10-23 |
20080258690 | Thermal switching element and method for manufacturing the same - The present invention provides a thermal switching element that has a quite different configuration from that of a conventional technique and can control heat transfer by the application of energy, and a method for manufacturing the thermal switching element. The thermal switching element includes a first electrode, a second electrode, and a transition body arranged between the first electrode and the second electrode. The transition body includes a material that causes an electronic phase transition by application of energy. The thermal conductivity between the first electrode and the second electrode is changed by the application of energy to the transition body. | 2008-10-23 |
20080258691 | OVER VOLTAGE AND OVER CURRENT PROTECTION INTEGRATED CIRCUIT - An integrated circuit is disclosed including a primary input for receiving an input voltage, a battery voltage input for receiving a battery voltage signal and an output for providing an output voltage higher than the battery voltage. First circuitry responsive to the input voltage is provided for turning off the output voltage responsive to an input over voltage condition. Second circuitry responsive to the battery voltage signal is provided for turning off the output voltage responsive to a battery over voltage condition. Third circuitry provides for over current protection. | 2008-10-23 |
20080258692 | Zero crossing detection for an electric power generation system - One system of the present application includes an electric power generation device structured to provide an AC electric power output at a target frequency. This device includes: an electric power generator; a sensing arrangement structured to provide samples corresponding to magnitude of the AC electric power output; and a controller including operational logic responsive to the sensing arrangement to calculate a peak amplitude as a function of a waveform period corresponding to the target frequency and two of the samples separated in time by a target duration of 20 to 30 percent of the waveform period and determine a zero crossing of the output from the peak amplitude and the target frequency. The operating logic is further structured to control operation of the device in accordance with the zero crossing. | 2008-10-23 |
20080258693 | Method for Controlling an Electromagnetic Retarder and System Including Retarder and a Control Unit - A method for controlling an electromagnetic retarder from a control unit said retarder including an electrical generator. The inventive method is used to determine an excitation current intensity to be injected into the primary coils of the generator of the retarder, said retarder including a rotary shaft bearing the secondary windings of the generator a n d field coils which are supplied b y the secondary windings. The rotation speed of the rotary shaft is taken into account in order to select a lower intensity if the rotation speed of the shaft is higher. The invention is suitable for use in the field of electromagnetic retarders which are intended for heavy vehicles such as trucks. | 2008-10-23 |
20080258694 | Methods and apparatuses for power generation in enclosures - An apparatus for generating power in an enclosure includes a power generation device configured to operate in the environmental conditions of the enclosure, a first power storage device connected to the power generation device and configured to store power generated by the power generation device, a power converter connected to the power storage device and configured to output power at a voltage different than that output by the power storage device, and a second power storage device connected directly or indirectly to the power converter and configured to store power output by the power converter. The second power storage device may then provide power for at least one component of an environmental monitoring system. | 2008-10-23 |
20080258695 | Switching device integrated with light emitting device - A light emitting component can include a substrate, a light emitting device supported by the substrate, wherein the light-emitting device has first and second terminals, and a switching element supported by the substrate and having first and second terminals electrically connected to the first and second terminals of the light-emitting device, respectively. The switching element is configured to, at least in part, divert at least some current away from the light emitting device when the switching element is in a closed state. An electrical connection between the first terminal of the switching element and the first terminal of the light emitting device can have a length of less than 5 cm (e.g., less than 2 cm, less than 1 cm, less than 5 mm, less than 1 mm). A current regulator may be supported by a second substrate and can supply current to the light emitting device. | 2008-10-23 |
20080258696 | SERIES REGULATOR CIRCUIT - A series regulator circuit for reducing current consumption, enabling switching between different current consumption modes, and suppressing output voltage fluctuations. A constant current source | 2008-10-23 |
20080258697 | DYNAMIC GATE DRIVE VOLTAGE ADJUSTMENT - A DC-DC buck converter comprises a high-side power FET having a current path connected in series between an input terminal and an inductor connected to an output terminal supplying an output current to a load. The converter further comprises a low-side power FET having a current path connected between a reference terminal and an interconnection node of the high-side power FET with the inductor. The converter has a pulse width modulation controller receiving a feedback signal from the output terminal and providing pulse width modulated signals, and a gate driver circuit that receives the pulse width modulated signals from the pulse width modulation controller and applies pulse width modulated drive signals to the gates of the power FETs. The gate driver circuit supplies the drive signals to the gates of the power FETs at a variable voltage level adjusted in response to at least the output current, minimizing the power dissipation of the gate driver circuit. | 2008-10-23 |
20080258698 | SOFT START CIRCUIT, POWER SUPPY UNIT AND ELECTRIC EQUIPMENT - A soft start circuit includes a constant current source for generating a constant current, a first current mirror circuit for generating from the constant current a first mirror current, a second current mirror circuit for generating from the constant current a second mirror current smaller than the first mirror current, and a capacitor into which a difference between the first mirror current and the second mirror current is introduced, wherein a divided voltage of a charging voltage thereof is output as a soft start voltage. The soft start circuit provides a gradual soft start voltage. | 2008-10-23 |
20080258699 | Converter Circuit with Improved Efficiency - The present invention relates to a converter circuit and a conversion method for converting an input signal to an output signal of a predetermined value based on a switched operating mode, wherein a first control loop ( | 2008-10-23 |
20080258700 | METHOD AND APPARATUS FOR ADJUSTING ON-CHIP DELAY WITH POWER SUPPLY CONTROL - An apparatus and method are provided for powering an integrated circuit chip with a supply voltage generated externally to the chip. An on-chip clock signal is generated with a ring oscillator fabricated on the integrated circuit chip. The supply voltage is altered as a function of a difference between a frequency of the on-chip clock signal and a reference clock frequency. | 2008-10-23 |
20080258701 | DC-DC converter with improved dynamic response - The invention relates to a control method and a controller for a DC-DC converter, such as a synchronous Buck converter, which exploits the principle of capacitor charge balance to allow the converter to recover from a positive and/or negative load current step in the shortest achievable time, with the lowest possible voltage undershoot/overshoot. The control method may be implemented by either an analog or a digital circuit. The controller may be integrated with existing controller schemes (such as voltage-mode controllers) to provide superior dynamic performance during large-signal transient conditions while providing stable operation during steady state conditions. The invention also relates to a method and a modification of a DC-DC converter topology that comprises connecting a controlled current source between an input terminal and an output terminal of the DC-DC converter; detecting a load current step to a new load current; modifying a duty cycle of the DC-DC converter; and modifying current through a parallel output capacitor of the DC-DC converter by controlling current of the current source. The methods and circuits provided herein are applicable to Buck converters and Buck-derived converters such as forward, push-pull, half-bridge, and full-bridge converters. | 2008-10-23 |
20080258702 | OUTPUT CIRCUIT - An output circuit in accordance with one embodiment of the present invention includes: an input terminal for receiving an input signal; an output transistor connected between a first power supply and an output terminal; a current control circuit connected to the input terminal and the output transistor for controlling current outflow and inflow for the gate of the output transistor based on the input signal; a voltage generating circuit connected to the first power supply; and a switch circuit coupled between the gate of the output transistor and the voltage generating circuit, the switch circuit having alternatively an on state and an off state thereof in response to the input signal; wherein the switch circuit becomes the off state when the potential difference between the gate of the output transistor and the first power supply becomes equal to or below a predetermine value regardless of the voltage level of the input signal. | 2008-10-23 |
20080258703 | Power Supply With Reduced Power Losses During Standby Mode - There is provided a power supply for an electrical device operable in active mode and in standby mode. The power supply comprises a transformer having a primary winding on the primary side and a secondary winding on the secondary side. The primary winding is connectable to an AC voltage supply and is arranged to comprise N turns when the electrical device is in active mode and more than N turns when the electrical device is in standby mode. Circuitry on the secondary side is arranged to provide an output voltage for the electrical device during active mode. | 2008-10-23 |
20080258704 | METHOD AND APPARATUS FOR IDENTIFYING BROKEN PINS IN A TEST SOCKET - A method includes scanning a test socket after removal of a device under test to generate scan data. The scan data is compared to reference data. A presence of at least a portion of a pin in the test socket is identified based on the comparison. A test system includes a test socket, a scanner, and a control unit. The test socket is operable to receive devices under test. The scanner is operable to scan a test socket after removal of a device under test to generate scan data. The control unit is operable to compare the scan data to reference data and identify a presence of at least a portion of a pin in the test socket based on the comparison. | 2008-10-23 |
20080258705 | Method for evaluating the effect of an electric discharge on a composite material - The present invention relates to a method for evaluating the effect of an electric discharge on an aircraft structure through the evaluation of the damage caused by the effect of the thermal heating generated by the mentioned discharge on the structure, comprising the steps of: applying an electric discharge on the material of the aircraft structure by means of an intensity generator; distributing in an electric mesh with resistive electric elements the material of the aircraft structure; calculating the intensities running through the electric mesh of the material of the aircraft structure from the intensity introduced in the generators; calculating with the previous intensities the heat which is dissipated in each of the elements of the electric mesh of the material of the aircraft structure; calculating the distribution of temperatures in each of the elements of the electric mesh of the material of the aircraft structure; determining the elements of the electric mesh of the material of the aircraft structure which, due to the effect of the distribution of temperatures, experience a change of state and evaporate; and determining the damage caused to the material of the aircraft structure due to the effect of the electric discharge | 2008-10-23 |
20080258706 | Wide-Bandwidth Spectrum Analysis of Transient Signals Using a Real-Time Spectrum Analyzer - A system and method for performing wide-band spectral analysis of transient signals using a real-time spectrum analyzer (RTSA). A frequency window is selected for RTSA acquisition, the frequency window being narrower in bandwidth than the frequency spectrum of interest. An RTSA is successively tuned to a plurality of different frequencies within the frequency spectrum of interest, where such successive tuning is controlled based on a characteristic of the signal. The RF signal is received, and, for each of the plurality of different frequencies, power data is acquired for the signal in a band centered on the frequency and having a bandwidth equal to that of the frequency window. A representation of the frequency spectrum of interest is then constructed from the power data acquired during the successive tunings of the RTSA. | 2008-10-23 |
20080258707 | Test Method for Frequency Converters with Embedded Local Oscillators - A method is presented where the phase trace is offset for each sweep such that the first point is always at zero degrees. The resulting traces are then averaged. The average reduces the noise in the phase trace and results in a less noisy group delay trace. | 2008-10-23 |
20080258708 | Control Meter with Safety Deactivation - Control meter for controlling the supply of services, in particular the supply of electric energy, having a support base, anchored with which is a main power supply line, and a metering group detachable from the support base and with a measurement apparatus interposed between the main power supply line and a subscriber line. A safety anchorage is provided for preventing fraudulent manipulations at the control meter and comprises mechanical means associated with the metering group and movable into a locking position for engagement with the support base when the metering group is mounted on the support base, and an interrupter for generating an activation signal upon activation by the mechanical means, wherein the mechanical means is arranged to activate the interrupter when the mechanical means is released from the locking position for detaching the metering group from the support base. The invention allows to positively obstruct acts of fraud and thus to provide a control meter which is able to permit the remote-control of the “open/closed” state in situations of fraud or rather attempted fraud and is capable of unequivocally proving the occurrence of fraud or attempted fraud. | 2008-10-23 |
20080258709 | System and method for detecting the presence of an unsafe line condition in a disconnected power meter - A method of detecting the presence of an unsafe line condition at a power metering device is disclosed. The method comprises the steps of determining if a disconnect switch is in the open position, and measuring a first voltage at a first load contact. The method measures a second voltage at a second load contact and determines if the first voltage is greater than a first voltage threshold or less than a second voltage threshold. The method further determines if the second voltage is greater than the first voltage threshold or less than the second voltage threshold. The method indicates that an unsafe condition exists if either the first voltage is greater than the first voltage threshold, or first voltage is less than the second voltage threshold or the second voltage is greater than the first voltage threshold or the second voltage is less than the second voltage threshold, when the disconnect switch is in the open position. | 2008-10-23 |
20080258710 | Analysis of Liquid Chromatography Eluates - When analysing saccharides by HPAEC, the eluate from the column is typically analysed using a amperometric detector. According to the invention, amperometric detection is coupled with ultraviolet detection, with both methods being applied to the eluate. Thus the invention provides a method for analysing the eluate from a liquid chromatography column, wherein the eluate is analysed by both (a) amperometric detection and (b) ultraviolet detection. The information content derivable from using both sorts of detection advantageously exceeds that derivable from either of the two detection methods alone. | 2008-10-23 |
20080258711 | Power gauge for accurate measurement of load current - According to one exemplary embodiment, a power gauge for accurately measuring current consumed by a load coupled to a power source includes a current sense resistor having a first terminal coupled to the power source and a second terminal coupled to the load. The power gauge further includes a first integrator configured to integrate a voltage at the first terminal of the current sense resistor during a time period and to output a first integrated voltage. The power gauge further includes a second integrator configured to integrate a voltage at the second terminal of the current sense resistor during the time period and to output a second integrated voltage. A difference between the first and second integrated voltages can be used to accurately determine the current consumed by the load during the time period. | 2008-10-23 |
20080258712 | MODULAR INTERFACE - An apparatus for interfacing a test head to a peripheral system is provided. The apparatus includes a first unit having a first connection member for providing electrical communication with the peripheral system, a second unit having a second connection member for providing electrical communication with the test system, and pivot members coupling the first unit and the second unit. The pivot members enable motion in the following sequence as one of the first and second unit moves towards the other: a) pivotal motion between the first connection member and the second connection member; and b) linear motion which decreases linear distance between the first connection member and the second connection member while maintaining respective contact surfaces of the first and second connection members in parallel. | 2008-10-23 |
20080258713 | MODULAR INTERFACE - An apparatus for interfacing a test head to a peripheral system is provided. The apparatus includes a first unit having a first connection member for providing electrical communication with the peripheral system, a second unit having a second connection member for providing electrical communication with the test system, and pivot members coupling the first unit and the second unit. The pivot members enable motion in the following sequence as one of the first and second unit moves towards the other: a) pivotal motion between the first connection member and the second connection member; and b) linear motion which decreases linear distance between the first connection member and the second connection member while maintaining respective contact surfaces of the first and second connection members in parallel. | 2008-10-23 |
20080258714 | Delay circuit and test apparatus - There is provided a delay circuit that delays an input signal to output the delayed signal. The delay circuit includes a first delay element operable to receive the input signal and delay the input signal to output the delayed signal, a buffer operable to receive the delay signal output from the first delay element and correct a dullness of a waveform of the delay signal generated from the first delay element to output the corrected signal, and a second delay element operable to receive the delay signal output from the buffer and delay the delay signal to output the delayed signal. | 2008-10-23 |
20080258715 | Sensor System for Detecting a Differential Angle - The invention relates to a sensor arrangement for detecting a difference angle, comprising at least one magnet field-sensitive sensor element ( | 2008-10-23 |
20080258716 | Magneto-Resistive Sensor With Test Mode Activation - In particular in automotive applications, sensor systems comprising geometrical leak shift sensor elements must fulfill properties and requirements with respect to quality, accuracy and safety. For this, sensors have to be tested and trimmed. According to an exemplary embodiment of the present invention, a magneto-resistive sensor is provided, allowing for a testing and trimming of the sensor elements by applying a homogenous magnetic field to the sensor Advantageously, this allows for the provision of a magneto-resistive sensor, having a simple arrangement. | 2008-10-23 |
20080258717 | Magnetic Induction Tomography System and Method - The present invention relates to a magnetic induction tomography system and method for studying the electromagnetic properties of an object. In order to provide a high resolution MIT technique without the need of increasing the number of coils, a magnetic induction tomography system ( | 2008-10-23 |
20080258718 | PRESSURE SENSING DEVICE FOR ROTATABLY MOVING PARTS AND PRESSURE DETECTION METHOD THEREFOR - A magnetic pressure sensing device for rotatably moving parts, of the type including at least one magnetic field source element associated to said rotatably moving part and a magnetic field sensing element associated to a fixed part to measure parameters of a magnetic field determined by said magnetic field source element, said parameters of the magnetic field being a function of the pressure applied to said rotatably moving part. The magnetic field source element includes means for rotating around at least one axis the direction of said magnetic field as a function of the pressure applied to said rotatably moving part. | 2008-10-23 |
20080258719 | APPARATUS AND METHODS FOR FERROMAGNETIC WALL INSPECTION OF TUBULARS - Apparatus and methods for magnetic wall inspecting materials such as cylindrical and tubular members are disclosed. One apparatus includes a main magnetic coil producing lines of magnetic flux able to traverse a section of a tubular member in a direction generally parallel to a longitudinal axis of the tubular member; and one or more magnetic focusing members positioned along the tubular and able to redirect certain flux lines so that they are more parallel to the tubular. This abstract allows a searcher or other reader to quickly ascertain the subject matter of the disclosure. It will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b). | 2008-10-23 |
20080258720 | Hybrid wound/etched winding constructs for scanning and monitoring - Combined wound and micro-fabricated winding constructs are described for the inspection of materials and the detection and characterization of hidden features or flaws. These constructs can be configured as sensors or sensor arrays that are surface mounted or scanned over conducting and/or magnetizable test materials. The well-defined geometry obtained micro-fabricated windings and from carefully wound coils with known winding positions permits the use of model based inversions of sensed responses into material properties. In a preferred embodiment, the primary winding is a wound coil and the sense elements are etched or printed. The drive or sense windings can also be mounted under fasteners to improve sensitivity to hidden flaws. Ferrites and other means may be used to guide the magnetic flux and enhance the magnetic field in the test material. | 2008-10-23 |
20080258721 | MTJ sensor including domain stable free layer - By subdividing the free layer of a GMR/TMR device into multiple sub-elements that share common top and bottom electrodes, a magnetic detector is produced that is domain stable in the presence of large stray fields, thereby eliminating the need for longitudinal bias magnets. Said detector may be used to measure electric currents without being affected by local temperature fluctuations and/or stray fields. | 2008-10-23 |
20080258722 | Sensor Arrangement - Consistent with an example embodiment, devices comprise sensor arrangements with field detectors for detecting components of magnetic fields in planes of the field detectors. The sensor arrangements further include movable objects for, in response to tilting movements, changing at least parts of the components of the magnetic fields in the planes of the field detectors so that the sensor arrangements are made less sensitive to in-plane stray fields by providing the field detectors with saturated field-dependent elements. The movable object may comprise a movable field generator for generating the magnetic field, or the movable object and the field generator may be different objects. The magnetic field is such that the field-dependent element is saturated. The field generator is smaller than the field detector, and the movable object is larger than the field detector, to reduce alignment problems. The movable object has a pivoting point close to the field detector. | 2008-10-23 |
20080258723 | Magnetic Resonance Imaging Apparatus and Magnetic Resonance Imaging Method - Generation of an artifact in an image under a transition state up to a steady state is suppressed and image quality is improved by executing the following pulse sequence. In the coherent SSFP method, a gradient magnetic field is applied so that an integrated value of time of a gradient magnetic field in a slice selection direction becomes a predetermined value which is not zero in a repetition time. Specifically, a gradient magnetic field Gs | 2008-10-23 |
20080258724 | Magnetic resonance imaging visualization method and system - The present technique provides a system and method for processing an image. Particularly the method comprises acquiring image data in frequency space (k-space) of an imaged volume and obtaining a three-dimensional (3-D) k-space volume representative of the imaged volume based on the acquired k-space data. The method further comprises selecting a two-dimensional (2-D) plane from the 3-D k-space volume and applying an inverse Fourier transform to the selected 2-D plane to obtain a real 2-D X-ray-like (or enhanced rendering) projection of the imaged volume offering insights into the 3-D data. | 2008-10-23 |
20080258725 | Non iterative shimming in magnetic resonance imaging in the presence of high LIPID levels - For the brain, a variety of automated non-iterative shimming methods using phase evolution derived B | 2008-10-23 |
20080258726 | Distinguishing Bound and Unbound Contrast Agents Using Magnetic Resonance - Magnetic resonance monitoring of a target ( | 2008-10-23 |
20080258727 | METHOD FOR PRODUCING A MAGNETIC RESONANCE IMAGE USING AN ULTRA-SHORT ECHO TIME - A method for producing a magnetic resonance image using an ultra-short echo time. The method includes applying a pulse sequence to an object, detecting a spirally encoded and phase encoded magnetic resonance signal associated with the object, and reconstructing the magnetic resonance image based on the spirally encoded and phase encoded magnetic resonance signal. The pulse sequence includes a slab-selective radiofrequency pulse, a slab-selective gradient pulse, a plurality of variable duration slice encoding gradient pulses, a plurality of first spiral encoding gradient pulses, and a plurality of second spiral encoding gradient pulses. The detection of the spirally encoded and phase encoded magnetic resonance signal occurs concurrently with the application of one of the plurality of first spiral encoding gradient pulses and with the application of one of the plurality of second spiral encoding gradient pulses. | 2008-10-23 |
20080258728 | Active Decoupling of Transmitters in Mri - A magnetic resonance imaging system includes a coupling compensation processor ( | 2008-10-23 |
20080258729 | Shim for Imaging Magnets - An arrangement for producing an imaging region of increased maximum radial diameter in a magnetic resonance imaging (MRI) system, comprising a solenoidal magnet arrangement ( | 2008-10-23 |
20080258730 | NUCLEAR MAGNETIC RESONANCE (NMR) PROBE - There is provided a nuclear magnetic resonance probe in which the loss caused by a high frequency cable between a probe coil and a preamplifier is reduced and the sensitivity of an NMR signal is improved. A changeover switch for NMR probe is divided into a switch part including switch elements and a filter part for filtering a switch control signal and an RF transmission signal. The switch part is disposed in a probe body inserted in a magnet of the probe. The filter part is disposed near a measurement apparatus located outside the probe. As for the switch part, a section structure of thickness and width is reduced in conformity with a narrow and slender shape of the probe body. The length of a high frequency cable between the probe coil and the preamplifier is shortened remarkably, and consequently the loss can be reduced. | 2008-10-23 |
20080258731 | High Impedance Differential Input Preamplifier and Antenna for Mri - Antenna assemblies for magnetic resonance signals comprise a non-resonant loop antenna and a high impedance differential amplifier. The amplifier can include first and second high electron mobility transistors that have gates coupled to an antenna loop that is defined on a rigid substrate. The non-resonant loop has an effective length of less than about 1/10 of a wavelength of a signal to be detected. Arrays of such loops can be defined on the rigid substrate, and HEMTs for the loops secured to the substrate. | 2008-10-23 |
20080258732 | MRI APPARATUS AND RF PULSE GENERATING CIRCUIT - An MRI apparatus includes: an RF coil to which analog RF pulse signals are applied; an RF pulse generating circuit which generates said analog RF pulse signals; and a magnetic resonance signal receiving circuit which receives analog magnetic resonance signals and converts these signals into baseband digital magnetic resonance signals, said RF pulse generating circuit comprising: a carrier signal generator which generates a digital carrier signal having a predetermined number of bits; a digital modulator which modulates said digital carrier signal with a digital envelope signal, thus generating digital RF pulse signals; a digital-analog converter which converts said digital RF pulse signals into the analog RF pulse signals; and an inversion unit which generates a digital inverted carrier signal having a two's complement relationship with said digital carrier signal and sends the digital inverted carrier signal to said magnetic resonance signal receiving circuit, said magnetic resonance signal receiving circuit comprising: an analog-digital converter which converts the analog magnetic resonance signals into digital magnetic resonance signals having a predetermined number of bits; and a digital demodulator which demodulates said digital magnetic resonance signals with said digital inverted carrier signal, thus converting these signals into the baseband digital magnetic resonance signals. | 2008-10-23 |
20080258733 | Electromagnetic Wave Resistivity Tool Having a Tilted Antenna for Geosteering Within a Desired Payzone - This invention is directed to a downhole method and apparatus for simultaneously determining the horizontal resistivity, vertical resistivity, and relative dip angle for anisotropic earth formations. The present invention accomplishes this objective by using an antenna configuration in which a transmitter antenna and a receiver antenna are oriented in non-parallel planes such that the vertical resistivity and the relative dip angle are decoupled. Preferably, either the transmitter or the receiver is mounted in a conventional orientation in a first plane that is normal to the tool axis, and the other antenna is mounted in a second plane that is not parallel to the first plane. This invention also relates to a method and apparatus for steering a downhole tool during a drilling operation in order to maintain the borehole within a desired earth formation. The steering capability is enabled by computing the difference or the ratio of the phase-based or amplitude-based responses of the receiver antennas which are mounted in planes that are not parallel to the planes of the transmitter antennas. Although this invention is primarily intended for MWD or LWD applications, this invention is also applicable to wireline and possibly other applications. | 2008-10-23 |
20080258734 | Method for Determining the Internal Resistance of a Battery - A method for determining the internal resistance of a battery, in particular a lead-acid vehicle battery, and an associated device for performing the method are described, in which differential values are calculated from the measured values for the voltage and the current, and these differential values are processed with the aid of a regulator, such as an integrator or a PID regulator. A signal results at the output of the regulator, which corresponds to the reciprocal value of the internal resistance of the battery. This signal is taken into consideration again in each following computing step. The functional capability may be inferred from its internal resistance. | 2008-10-23 |
20080258735 | Non-Metallic Flow-Through Electrodeless Conductivity Sensor and Leak Detector - A non metallic flow through electrodeless conductivity sensor is provided with a conduit having primary and secondary process fluid flowpaths to form a fluid loop. At least one drive and one sense toroid surround the conduit on the fluid loop. Voltage supplied to the drive toroid induces a current in the sense toroid via the fluid loop to eliminate any need for metallic electrodes in contact with the process fluid. At least one additional drive and/or sense toroid is disposed on the fluid loop to enhance induction. Optionally one or more sense coils are disposed about the conduit outside of the fluid loop to cancel out stray electrical noise. An optional conductor disposed along the conduit detects any fluid leakage through changes in resistance thereof. | 2008-10-23 |
20080258736 | Magnetic flowmeter output verification - A magnetic flowmeter transmitter includes a flowtube and measurement circuitry which provides an output related to flow through the flowtube. Output circuitry, such as analog and pulse output circuitry, provides transmitter output(s) related to flow through the flowtube. Output verification circuitry of the transmitter is coupled to the output circuitry and provides verification of proper operation of the output circuitry by analyzing the output signals. | 2008-10-23 |
20080258737 | Insulation Inspection Apparatus - An insulation inspection apparatus includes a chamber in which a stator with a winding can be stored, an electrode movable along the outer circumference of a coil end of the stator winding, a voltage application unit applying voltage between the coil end and electrode, a sensor unit sensing leakage current and/or voltage drop between the coil end and electrode, and a pressure reduction unit reducing the pressure in the chamber. | 2008-10-23 |
20080258738 | CHARACTERIZING TEST FIXTURES - Provided herein are techniques for characterizing a test fixture that is used for connecting a device under test (DUT) to a vector network analyzer (VNA), e.g., to thereby enable de-embedding of the test fixture from measurements of the DUT connected to the test fixture. In an embodiment, the test fixture is separated into 4-port test fixture segments, based on which ports of the DUT have internal coupling. Each test fixture segment has an outer 2-port reference plane and an inner 2-port reference plane. A 4-port calibration is performed at outer planes of the two test fixture segments, while corresponding ports of the inner planes of the test fixture segments are connected together with thru segments, to thereby determine a thru set of S-parameters. A set of S-parameters is determined for each of the 4-port test fixture segments, based on the thru set of S-parameters. | 2008-10-23 |
20080258739 | Position Sensor - A compact position sensor with high operational reliability is provided. This sensor has a tubular detection coil, a magnetic core movable in the detection coil, a drive circuit for the detection coil, a signal processing circuit for converting a change in impedance of the detection coil into an electric signal, and a guide means for guiding a movement of the magnetic core in the detection coil. The guide means has a guide portion connected to the magnetic core and a support portion for slidably supporting the guide portion. The magnetic core can be smoothly displaced in the detection coil without contacting an inner surface of the detection coil by a sliding movement of the guide portion relative to the support portion. | 2008-10-23 |
20080258740 | SELF-CALIBRATING DRIVER - A self-calibration system includes a variable current source to generate a default source current for charging a capacitive load, and a load charge calibrator to detect a voltage associated with the capacitive load when charged by the default source current, and to generate a current control feedback according to the detected voltage and a desired charged voltage of the capacitive load, the current control feedback to indicate to the variable current source a charge current capable of charging the capacitive load to the desired charged voltage. | 2008-10-23 |
20080258741 | Parallel AC measurement method - A method for making electrical measurements of a first and a second DUT, the DUTs being in sufficient proximity to exhibit crosstalk therebetween, the method comprising: applying a first signal to the first DUT; applying a second signal to the second DUT, the first signal and the second signal being contemporaneous and orthogonal to each other; measuring a first DUT response; and measuring a second DUT response. The first and second DUT responses exhibit independence from the second and first signals, respectively. | 2008-10-23 |
20080258742 | Conductivity measurement device, its manufacture and use - The invention relates to a method of manufacturing a device for measuring conductivity of a liquid, in particular ultrapure water, of the kind comprising two conductivity measurement electrodes suitable for defining a cell constant enabling the measurement of the conductivity of the ultrapure liquid, characterized in that it consists of producing each of the electrodes by forming an electrode pattern from electrically conductive material on a substrate of insulating material. | 2008-10-23 |
20080258743 | CONDENSATION SENSOR - A sensor arrangement is provided for attachment to an inside of a windshield in a motor vehicle, including at least a sensor element that determines the relative humidity and a printed circuit board that electrically contacts the sensor element, wherein the sensor element is attached to the printed circuit board in the direction of the windshield, and a compensating film that accommodates the curvature of the window is present at least between the sensor element and the windshield, and the compensating film is an adhesive film. | 2008-10-23 |
20080258744 | Electronic Circuit Testing Apparatus - The present invention has an object to provide an electronic circuit testing apparatus that is preferable for testing an electronic circuit which carries out communications between substrates based on inductive coupling and is capable of testing the electronic circuit without using test pads, wherein a probe | 2008-10-23 |
20080258745 | Probe Guard - It is an object of the present invention to realize sure electrical connection between a contactor and an object to be inspected without influenced by heat, a reduction in the pre-heating time, and an enhanced throughput. | 2008-10-23 |
20080258746 | Probes for a Wafer Test Apparatus - A probe configured for use in the testing of integrated circuits includes a first end portion terminating in a foot ( | 2008-10-23 |
20080258747 | TEST EQUIPMENT FOR AUTOMATED QUALITY CONTROL OF THIN FILM SOLAR MODULES - Provided is a method and test system for identifying a defective region of a photovoltaic cell from among a plurality of photovoltaic cells collectively forming a thin film solar module. A probe includes a plurality of test fingers arranged to be substantially simultaneously placed adjacent to an electric contact provided to different regions of one or more of the plurality of photovoltaic cells, and each of the test fingers is to receive an electrical output from the different regions of the one or more photovoltaic cells. A light source emits light to be converted by the photovoltaic cells into the electrical output during testing. A measurement circuit measures a property of the electrical output received from the different regions of the photovoltaic cells and transmits a measured value signal indicative of the property measured by the measurement circuit. And a control unit receives the measured value signal and generates a visible display indicating that at least one of the different regions of the solar module is a defective region based at least in part on the measured value signal, and also indicates a location of the defective region on the solar module. | 2008-10-23 |
20080258748 | METHOD FOR FABRICATING A PROBING PAD OF AN INTEGRATED CIRCUIT CHIP - A method for fabricating a probing pad is disclosed. A substrate having thereon a dielectric layer is provided. An inlaid metal wiring is formed in the dielectric layer. The inlaid metal wiring and the dielectric layer are covered with a passivation dielectric film. A portion of the passivation dielectric film is then etched away to form a reinforcement pattern on the inlaid metal wiring. The reinforcement pattern has inter-space that exposes a portion of the underlying inlaid metal wiring. A conductive pad is formed over the reinforcement pattern and the passivation dielectric film. The conductive pad fills the inter-space of the reinforcement pattern. | 2008-10-23 |
20080258749 | TEST APPARATUS, AND ELECTRONIC DEVICE - A test apparatus that tests a device under test is provided. The test apparatus includes: a main memory that stores a test data row for testing the device under test; a cache memory that caches the test data row read from the main memory; a pattern generation control section that reads each test data which is not aligned in units of word being a data transfer unit of the main memory and writes the same to cache entries different from each other in the cache memory for each test data; and a pattern generating section that sequentially reads the test data stored of each cache entry in the cache memory and generates a test pattern for testing the device under test. | 2008-10-23 |
20080258750 | METHOD FOR DETERMINING THRESHOLD VOLTAGE VARIATION USING A DEVICE ARRAY - A method of measuring threshold voltage variation using a device array provides accurate threshold voltage distribution values for process verification and improvement. The characterization array imposes a fixed drain-source voltage and a constant channel current at individual devices within the array. Another circuit senses the source voltage of the individual device within the array. The statistical distribution of the threshold voltage is determined directly from the source voltage distribution by offsetting each source voltage by a value determined by completely characterizing one or more devices within the array. The resulting methodology avoids the necessity of otherwise characterizing each device within the array, thus reducing measurement time dramatically. | 2008-10-23 |
20080258751 | On-Chip Power Supply Noise Detector - Techniques for on-chip detection of integrated circuit power supply noise are disclosed. By way of example, a technique for monitoring a power supply line in an integrated circuit includes the following steps/operations. A first signal and a second signal are preconditioned. The first signal is representative of a voltage of the power supply line being monitored. The second signal is representative of a voltage of a reference power supply line. Preconditioning includes shifting respective levels of the voltages such that the voltages are within an input voltage range of comparator circuitry. Then, the preconditioned first signal and the preconditioned second signal are compared in accordance with the comparator circuitry. Comparison includes detecting when a difference exists between the voltage level of the preconditioned first signal and the voltage level of the preconditioned second signal. | 2008-10-23 |
20080258752 | METHOD AND APPARATUS FOR MEASURING DEVICE MISMATCHES - A test structure for statistical characterization of local device mismatches contains densely populated SRAM devices arranged in a row/column addressable array that enables resource sharing of many devices. The test structure includes a built-in sensing mechanism to calibrate or null out sources of error, and current steering to avoid negative effects of current leakage along spurious paths. The gate and drain lines of each column are driven from both the top and bottom to minimizes parasitic effects. The system can handle a large number of devices while still providing high spatial resolution of current measurements. | 2008-10-23 |
20080258753 | SYSTEMS, METHODS AND APPARATUS FOR ANTI-SYMMETRIC QUBIT-COUPLING - Apparatus, articles and methods relate to anti-symmetric superconducting devices for coupling superconducting qubits. | 2008-10-23 |
20080258754 | SECURITY ELEMENT FOR AN INTEGRATED CIRCUIT, INTEGRATED CIRCUIT INCLUDING THE SAME, AND METHOD FOR SECURING AN INTEGRATED CIRCUIT - An integrated circuit including a substrate; a circuit pattern formed over the substrate; and one or more fences formed around edges of the circuit pattern, each of the one or more fences having a determined electrical resistance which is used to detect the addition of malicious circuitry. Each fence has a determined electrical resistance which is used to monitor the validity of the fence. | 2008-10-23 |
20080258755 | Noise Reduction Among Conductors - Noise reduction among conductors, the conductors disposed adjacent to one another, the conductors characterized as two or more aggressor conductors and one or more victim conductors, a least two of the aggressor conductors driven with at least two signals that induce unwanted crosstalk upon at least one of the victim conductors, a programmable delay device disposed in a signal path of each of the at least two signals that induce unwanted crosstalk, including programming a delay period into each programmable delay device; receiving, simultaneously at the programmable delay devices, the at least two signals that induce unwanted crosstalk; and transmitting, on two aggressor conductors, the at least two signals that induce unwanted crosstalk, with the at least two signals separated in time by the delay period. | 2008-10-23 |
20080258756 | Semiconductor apparatus - The on-die termination circuit of the present invention includes a main resistance circuit and an adjustment circuit. The main resistance circuit is provided with a resistance element and a transistor that is turned OFF when the on-die termination circuit is to be placed in the OFF state and turned ON when the on-die termination circuit is to be placed in the ON state. The adjustment circuit is provided with transistors that are both connected together in parallel and connected in parallel to the main resistance circuit, and that are turned ON or OFF when the on-die termination circuit is placed in the ON state so as to adjust the termination resistance of the entire on-die termination circuit. | 2008-10-23 |
20080258757 | INTEGRATED CIRCUIT FEATURE DEFINITION USING ONE-TIME-PROGRAMMABLE (OTP) MEMORY - In one embodiment, a integrated circuit (IC) configurable to have any one of a plurality of different feature sets, the IC including (a) one or more feature blocks adapted to be independently enabled or disabled, (b) a one-time-programmable (OTP) memory cell for each feature block, the OTP memory cell storing a value, and (c) a feature control module for each feature block, each feature control module connected between the corresponding OTP memory cell and the corresponding feature block, and adapted to enable or disable the corresponding feature block based on the value stored in the corresponding OTP memory cell. The OTP memory cells are programmed by a vendor to select the particular feature set for the IC which is to be available to a purchaser. | 2008-10-23 |
20080258758 | EMBEDDED SYSTEM AND CONTROL METHOD THEREFOR - An embedded system having a programmable logic circuit, a plurality of storage devices each storing configuration data defining circuit information of the logic circuit, a setting information storage storing setting information including information of a storage device storing the configuration data and a controller selecting one of the plurality of storage devices based on the setting information and incorporating circuit information defined by configuration data stored in the selected storage device into the logic circuit. | 2008-10-23 |
20080258759 | UNIVERSAL DIGITAL BLOCK INTERCONNECTION AND CHANNEL ROUTING - A programmable routing scheme provides improved connectivity both between Universal Digital Blocks (UDBs) and between the UDBs and other micro-controller elements, peripherals and external Inputs and Outputs (I/Os) in the same Integrated Circuit (IC). The routing scheme increases the number of functions, flexibility, and the overall routing efficiency for programmable architectures. The UDBs can be grouped in pairs and share associated horizontal routing channels. Bidirectional horizontal and vertical segmentation elements extend routing both horizontally and vertically between different UDB pairs and to the other peripherals and I/O. | 2008-10-23 |
20080258760 | SYSTEM LEVEL INTERCONNECT WITH PROGRAMMABLE SWITCHING - Different functional elements are all located on a same integrated circuit wherein at least one of the functional elements comprises a micro-controller. Configuration registers or configuration memory in the integrated circuit store configuration values loaded by the micro-controller. Connectors are configured to connect the integrated circuit to external signals. A system level interconnect also located in the integrated circuit programmably connects together the different functional elements and different connectors according to the configuration values loaded into the configuration registers. | 2008-10-23 |
20080258761 | RUNTIME LOADING OF CONFIGURATION DATA IN A CONFIGURABLE IC - Some embodiments of the invention provide a configurable integrated circuit (IC) that has several configurable circuits for configurably performing different operations. During the operation of the IC, each particular configurable circuit performs a particular operation that is specified by a particular configuration data set for the particular configurable circuit. While the IC operates and a first set of configurable circuits performs a first set of operations, configuration data is loaded from the outside of the IC for configuring a second set of configurable circuits. In some embodiments, the configurable IC includes a configuration network for rapid loading configuration data in the IC from outside of the IC. In some of these embodiments, the configuration network is a pipelined network. Also, the IC of some embodiments includes a configuration controller for retrieving configuration data from outside of the IC, formulating configuration data sets, and routing the configuration data sets to the second set of configurable circuits over the configuration network. | 2008-10-23 |
20080258762 | ASICs HAVING PROGRAMMABLE BYPASS OF DESIGN FAULTS - A relatively small amount of programmable or reprogrammable logic (pro-Logic) is included in a mostly-ASIC device so that such re/programmable logic can be used as a substitute for, or for bypassing a fault-infected ASIC block (if any) either permanently or at times when the fault-infected ASIC block is about to perform a fault-infected operation (bug-infected operation). The substitution or bypass does not have to be a permanent one that is in effect at all times for the entirety of the fault-infected ASIC block. Instead affected outputs of the faulty ASIC block can be disabled from working just at the time they would otherwise initiate or propagate an error. Such fault-infected operations of the temporarily deactivated ASIC block(s) may be substituted for by appropriately programmed pro-Logic at the appropriate times. Thus, a fault-infected ASIC block that is 99% good (for example) and operates improperly just 1% of the time can continue to be gainfully used for that 99% of the time when its operations are fault free and can be blocked from having its erroneous output(s) used only in the 1% time periods (example) when its behavior is faulty. During those faulty times, a relatively small amount of the pro-Logic can be used as a fault-correcting or fault-bypassing substitute for the fault-infected ASIC block. This substitution or bypassing can be activated after initial design of the mostly-ASIC circuitry and/or after pilot production and/or mass production thereby providing for cost saving and faster time to market and/or for repair or maintenance even years after installation and use of the mostly-ASIC device. | 2008-10-23 |
20080258763 | BLOCK SYMMETRIZATION IN A FIELD PROGRAMMABLE GATE ARRAY - An FPGA architecture has top, middle and low levels. The top level is an array of B 16×16 tiles enclosed by I/O blocks. The routing resources in the middle level are expressway routing channels including interconnect conductors. At the lowest level, there are block connect routing channels, local mesh routing channels, and direct connect interconnect conductors to connect the logic elements to further routing resources. Each B1 block includes four clusters of devices. Each of the clusters includes first and second LUT | 2008-10-23 |
20080258764 | Interconnect Structure Enabling Indirect Routing in Programmable Logic - An interconnect structure enables indirect routing in programmable logic. The structure includes a domain comprising a plurality of routing lines and an input line connected to a first routing line in the domain. A switch box is connected to the first routing line and is configured to indirectly connect the input line to the other routing lines in the domain. In some embodiments a domain includes programmable switches that are configured to connect a routing line of one domain to any routing line of the other domains. | 2008-10-23 |
20080258765 | Low-power transceiver architectures for programmable logic integrated circuit devices - High-speed serial interface or transceiver circuitry on a programmable logic device integrated circuit (“PLD”) includes features that permit the PLD to satisfy a wide range of possible user needs or applications. This range includes both high-performance applications and applications in which reduced power consumption by the PLD is important. In the latter case, any one or more of various features can be used to help reduce power consumption. | 2008-10-23 |
20080258766 | Mixed Signal Integrated Circuit - This invention relates to mixed signal integrated circuits, that is, integrated circuits comprising both analogue and digital circuitry. More particularly, it concerns reduction of noise in such a device. When a digital circuit is included in the same integrated circuit device as an analogue circuit, the digital circuit may be an additional source of a considerable amount of noise. This results in cross-talk, electrical interference and signal distortion imposed on the analogue signals. The invention provides an integrated circuit comprising analogue circuitry ( | 2008-10-23 |
20080258767 | Computational nodes and computational-node networks that include dynamical-nanodevice connections - Embodiments of the present invention are employ dynamical, nanoscale devices, including memristive connections between nanowires, for constructing parallel, distributed, dynamical computational networks and systems, including perceptron networks and neural networks. In many embodiments of the present invention, neuron-like computational devices are constructed from silicon-based microscale and/or submicroscale components, and interconnected with one another by dynamical interconnections comprising nanowires and memristive connections between nanowires. In many massively parallel, distributed, dynamical computing systems, including the human brain, there may be a far greater number of interconnections than neuron-like computational nodes. Use of dynamical nanoscale devices for these connections results in enormous design, space, energy, and computational efficiencies. | 2008-10-23 |
20080258768 | METHOD AND CIRCUIT FOR CONTROLLING PIN CAPACITANCE IN AN ELECTRONIC DEVICE - A method of operating an electronic device having an output driver with on die termination legs ODT, and non-ODT legs, includes the step of selectively tri-stating tuning transistors (ZQ trim devices) in the legs as a function of the operational state of the output driver. The tri-stating step is performed such that when a leg is not being utilized, the tuning transistors in the unused leg are placed in a tri-state. For example, during an ODT mode of the output driver, the tuning transistors in the non-ODT legs are tri-stated. During a READ mode of the output driver, the tuning transistors in the ODT legs are tri-stated. During a HiZ mode of the output driver, the tuning transistors in both legs are tri-stated. Tri-stating the tuning transistors in the unused output driver legs can reduce DQ pin capacitance by a total of approximately (Cgd+Cgs+Cgb). A circuit for performing the method includes tri-state components in electrical communication with the tuning transistors, and logic units configured to control the tri-state components. An electronic device includes the output driver having the tri-state components in electrical communication with the logic units. | 2008-10-23 |
20080258769 | Tri-State Circuit Element Plus Tri-State-Multiplexer Circuitry - A Tri-State circuit element ( | 2008-10-23 |
20080258770 | Single Threshold and Single Conductivity Type Logic - A logic assembly ( | 2008-10-23 |
20080258771 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device, has a semiconductor substrate; and a first transistor of a first conductivity type and a second transistor of the first conductivity type, the transistors being connected in series between a first power supply line and a first substrate well provided on the semiconductor substrate, the semiconductor integrated circuit device further comprising a first transistor of a second conductivity type and a second transistor of the second conductivity type, the transistors being connected in series between the second power supply line and a second substrate well provided on the semiconductor substrate. | 2008-10-23 |
20080258772 | CLOCK SIGNAL NETWORKS FOR STRUCTURED ASIC DEVICES - Clock distribution circuitry for a structured ASIC device includes a deterministic portion and configurable portions. The deterministic portion employs a predetermined arrangement of conductor segments and buffers for distributing a clock signal to a plurality of predetermined locations on the device. From each predetermined location, an associated configurable portion of the clock distribution circuitry distributes the clock signal to any clock utilization circuitry needing that clock signal in a predetermined area of the structured ASIC that is served from that predetermined location. | 2008-10-23 |
20080258773 | UNIVERSAL LOGIC GATE UTILIZING NANOTECHNOLOGY - A universal logic gate apparatus is disclosed, which include a plurality of self-assembling chains of nanoparticles having a plurality of resistive connections, wherein the plurality of self-assembling chains of nanoparticles comprise resistive connects utilized to create A plasticity mechanism is also provided, which is based on a plasticity rule for creating stable connections from the plurality of self-assembling chains of nanoparticles for use with the universal, reconfigurable logic gate. The plasticity mechanism can be based, for example, on a 2-dimensional binary input data stream, depending upon design considerations. A circuit is also associated with the plurality of self-assembling chains of nanoparticles, wherein the circuit provides a logic bypass that implements a flip-cycle for second-level logic. Additionally, an extractor logic gate is associated with the plurality of self-assembling chains of nanoparticles, wherein the extractor logic gate provides logic functionalities. | 2008-10-23 |
20080258774 | Semiconductor device with a logic circuit - The logic gate of the present invention is of a configuration that includes a first transistor, a second transistor, and a connection-switching unit. The first transistor receives a first voltage at its source, a first input signal at its gate, and supplies a first output signal from its drain. The second transistor receives a second voltage that is lower than the first voltage at its source, receives a second input signal at its gate, and supplies a second output signal from its drain. The connection-switching unit is connected between the drains of the first transistor and the second transistor for connecting and cutting off the first transistor and the second transistor. | 2008-10-23 |
20080258775 | NAND/NOR Registers - A register receives an input signal and provides output signals that represent true complementary logic values of the input signal. One implementation of the register includes: a first stage circuit and a second stage circuit. After the output signals are derived, the second stage circuit provides feedback signals to block further propagation of the logic value of the input signal from the first stage circuit to the second stage circuit. | 2008-10-23 |
20080258776 | ANALOG SIGNAL TRANSMISSION CIRCUIT - An analog signal transmission circuit includes a sampling switch supplied with an analog signal, a capacitor connected between an output side terminal of the sampling switch and a low-potential power supply, and a differential amplifier connected to an output side terminal of the sampling switch. The circuit samples the analog signal by turning on/off the sampling switch and outputs a signal achieved by amplifying an accumulation voltage of the capacitor in the differential amplifier. The differential amplifier has a differential input portion including a first transistor connected to a first terminal of the capacitor, a second transistor, a constant current source, and an actuating switch that is connected between the constant current source and the differential input portion. The analog signal transmission circuit further includes a pre-charge circuit that pre-charges a wire between the different input portion and the actuating switch. | 2008-10-23 |
20080258777 | Method and Apparatus for Generating Multiple Analog Signals Using a Single Microcontroller Output Pin - A method and apparatus are disclosed for generating multiple separate analog signals using a single microcontroller output pin. The microcontroller generates a waveform that is used to concurrently generate multiple separate analog signals. The microcontroller outputs a waveform that includes a first signal from one of the microcontroller's output pins. The first signal is used to produce a first analog signal. The microcontroller then outputs a delineating signal, as part of the waveform, from the microcontroller's output pin. The delineating signal indicates the start of a next signal in the waveform. The microcontroller then outputs a second signal, as part of the waveform, from its output pin. The second signal is used to produce a second analog signal. The waveform includes the first signal that is followed by the delineating signal that is followed by the second signal. | 2008-10-23 |
20080258778 | CURRENT MIRROR CIRCUIT - The invention relates to a current mirror circuit ( | 2008-10-23 |
20080258779 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit, has a current source having one end connected to a power supply and outputting a reference current; a first MOS transistor having one end connected to an other end of the current source and being diode-connected; a second MOS transistor having a gate connected to a gate of the first MOS transistor and passing an output current obtained by current-mirroring the reference current; a first variable resistor connected between an other end of the first MOS transistor and a ground; a resistive component connected between an other end of the second MOS transistor and the ground; and a first operational amplifier fed with a first potential of the other end of the first MOS transistor and a second potential of the other end of the second MOS transistor and outputting a signal for controlling a resistance value of the first variable resistor to equalize the first potential and the second potential, wherein the resistance value of the first variable resistor is controlled based on the output signal of the first operational amplifier. | 2008-10-23 |
20080258780 | FREQUENCY DIVIDER - A frequency divider using a clock source with a plurality of phase signals of a multi-phase oscillator. In one version, the divider includes a plurality of spot-moving stages that are connected to form a ring. Spot-moving stages are stages that advance a one or a zero, while clearing the previous stage. Depending on the number of stages and the number of phases of the clock to advance a spot through all of the stages, a divider ratio is determined. In another embodiment, a plurality of latch elements is provided with a divided input and each is re-clocked with the phases of a multi-phase oscillator. The outputs of the latch elements are combined in a capacitor array to create the output waveform. An interpolator useful in conjunction with a frequency divider is also disclosed. When the interpolator is placed in the feedback path of a PLL, a fractional frequency multiplier/divider results. | 2008-10-23 |
20080258781 | Multi-Bit Programmable Frequency Divider - A multi-bit, programmable, modular digital frequency divider divides an input frequency by an m-bit integer divisor to produce an output frequency. The integer divisor re-initializes m-number of flip-flop stages with the divisor input at the end of every output clock. Each divisor bit is gated to a D-input through a respective data multiplexer controlled by a clock output. A run/initialize mode controller receives the input frequency and produces the divided output frequency and controls the timing of the re-initialization. | 2008-10-23 |