43rd week of 2008 patent applcation highlights part 47 |
Patent application number | Title | Published |
20080261284 | Method for the production of lactic acid or a salt thereof by simultaneous saccharification and fermentation of starch - The present invention pertains to a method for the production of lactic acid or a salt thereof, wherein starch is subjected to a process of simultaneous saccharification and fermentation, the method comprising saccharifying starch in a medium comprising at least a glucoamylase and simultaneously fermenting the starch using a microorganism, and optionally isolating lactic acid from the medium, characterized in that a moderately thermophilic lactic acid-producing microorganism is used. The invention further relates to a method of performing said process in the presence of a moderately thermophilic lactic acid producing microorganism, which has been adapted to have its maximum performance at the working pH. | 2008-10-23 |
20080261285 | Method for the production of lactic acid or a salt thereof by simultaneous saccharification and fermentation of starch - The present invention pertains to a method for the production of lactic acid or a salt thereof wherein starch is subjected to a process of simultaneous saccharification and fermentation, the method comprising saccharifying starch in a medium comprising at least a glucoamylase and simultaneously fermenting the starch using a microorganism, and optionally isolating lactic acid from the medium, characterized in that a moderately thermophilic lactic acid-producing microorganism is used. The invention further relates to a method of performing said process in the presence of a moderately thermophilic lactic acid producing microorganism, which has been adapted to have its maximum performance at the working pH. | 2008-10-23 |
20080261286 | Methods for producing optically active alpha-hydroxy amides - An objective of the present invention is to provide efficient methods for producing (R)-2-chloromandelamide with high optical purity. Another objective of the present invention is to provide novel methods for producing α-ketoamide reductases that reduce 2-chlorobenzoyl formamide to (R)-2-chloromandelamide with high optical purity, using NADPH as the coenzyme. | 2008-10-23 |
20080261287 | Metabolic Engineering of Xylos Fermentation - The present invention relates to further genetic modifications in eukaryotic host cells that have been transformed to express a xylose isomerase that confers the host cell the ability of isomerising xylose to xylulose. The further genetic modifications are aimed at improving the efficiency of xylose metabolism and include e.g. reduction of unspecific aldose reductase activity, increased xylulose kinase activity and increased flux of the pentose phosphate pathway. The modified host cells of the invention are suitable for the production of a wide variety of fermentation products, including ethanol, in fermentation processes in which a source of xylose or a source of xylose and glucose are used as carbon source. | 2008-10-23 |
20080261288 | Micro-Organ Device - A method for fabricating a micro-organ device comprises providing a microscale support having one or more microfluidic channels and one or more micro-chambers for housing a micro-organ and printing a micro-organ on the microscale support using a cell suspension in a syringe controlled by a computer-aided tissue engineering system, wherein the cell suspension comprises cells suspended in a solution containing a material that functions as a three-dimensional scaffold. The printing is performed with the computer-aided tissue engineering system according to a particular pattern. The micro-organ device comprises at least one micro-chamber each housing a micro-organ; and at least one microfluidic channel connected to the micro-chamber, wherein the micro-organ comprises cells arranged in a configuration that includes microscale spacing between portions of the cells to facilitate diffusion exchange between the cells and a medium supplied from the at least one microfluidic channel. | 2008-10-23 |
20080261289 | COMPOSITIONS COMPRISING VIRUSES AND METHODS FOR CONCENTRATING VIRUS PREPARATIONS - A composition is disclosed comprising virus in a formulation comprising a polyhydroxy hydrocarbon buffered to maintain a pH in a range from about 7 to about 8.5 at a temperature in the range from about 2° C. to 27° C. Methods for concentrating and purifying virus preparations are also disclosed. | 2008-10-23 |
20080261290 | Tetrahymena Heat Inducible Promoters and Their Use - The present invention relates to heat-inducible promoters of the heat shock protein family of the ciliate | 2008-10-23 |
20080261291 | Method of Obtaining Cyanogenic Glycoside and Related Glycosides, as Well as Genin and Sapogenins Derivatives of Plants of the Family Sapotaceae for the Preparation of Cosmetics and Dermatological Compositions - Procedure for the obtaining of genin and sapogenins extracts by enzymatic hydrolysis of kernels derived of the family Sapotaceae, genus | 2008-10-23 |
20080261292 | Method Enabling the Use of Extracellular Ribonucleic Acid (RNA) Extracted from Plasma or Serum to Detect, Monitor or Evaluate Cancer or Premalignant Conditions - This invention relates to the use of tumor-derived or associated extracellular ribonucleic acid (RNA) found circulating in the plasma or serum fraction of blood for the detection, monitoring, or evaluation of cancer or premalignant conditions. Extracellular RNA may circulate as non-bound RNA, protein-bound RNA, lipid-RNA complexes, lipoprotein (proteolipid)-RNA complexes, protein-RNA complexes including within or in association with ribonucleoprotein complexes, nucleosomes, or within apoptotic bodies. Any intracellular RNA found in plasma or serum can additionally be detected by this invention. Specifically, this invention enables the extraction of circulating RNA from plasma or serum and utilizes nucleic acid amplification assays for the identification, detection, inference, monitoring, or evaluation of any neoplasm, benign, premalignant, or malignant, in humans or other animals, which might be associated with that RNA. Further, this invention allows the qualitative or quantitative detection of tumor-derived or associated extracellular RNA circulating in the plasma or serum of humans or animals with or without any prior knowledge of the presence of cancer or premalignant tissue. | 2008-10-23 |
20080261294 | APPARATUS FOR CHEMILUMINESCENT ASSAY AND DETECTION - An apparatus includes a system for guiding chemiluminescence and a system for preventing a variation in dark currents. The apparatus includes a first light shielding BOX having a sample container holder and a shutter unit therein, the shutter unit including a top plate which is partly formed by a movement of a plate member and a second light shielding BOX having a photodetector therein. While a measurement is not implemented, the shutter unit is closed to block entrance of stray light to the photodetector, and while a measurement is implemented, the plate member is moved to open the shutter unit and the tip of the photodetector is inserted into a through hole formed in the top plate, so that the distance between the bottom of the sample container and a sensitive area of the photodetector is reduced to several millimeters or less. | 2008-10-23 |
20080261295 | Cell Sorting System and Methods - Apparatus and Methods are provided for a microfabricated fluorescence activated cell sorter based on a switch for rapid, active control of cell routing through a microfluidic channel network. This sorter enables low-stress, highly efficient sorting of populations of small numbers of cells (i.e., 1000-100,000 cells). The invention includes packaging of the microfluidic channel network in a self-contained plastic cartridge that enables microfluidic channel network to macro-scale instrument interconnect, in a sterile, disposable format. Optical and/or fluidic switching forces are used alone or in combination to effect switching. | 2008-10-23 |
20080261296 | PROCESS CHALLENGE DEVICE FOR ASSESSING THE EFFECTIVE PERFORMANCE OF A BIOCONTAMINATION DEACTIVATION PROCESS - A process challenge device (PCD) for determining the effectiveness of a microbial deactivation process that uses a vaporous deactivating agent (e.g., vaporized hydrogen peroxide) as a deactivating agent. The PCD includes first and second layers that are joined together to form (1) a chamber dimensioned to receive a biological and/or chemical indicator, and (2) first and second conduits fluidly connecting the chamber with a region outside the PCD. Each conduit has one end in communication with the region outside the PCD and another end in communication with the chamber. A removable seal member seals the biological and/or chemical indicator inside the chamber. | 2008-10-23 |
20080261297 | Assay Device - An assay device ( | 2008-10-23 |
20080261298 | Method and device for the multiplex analysis of cells and tissues - This invention is used for the multiplex analysis method of cells or tissues by combination of multiple cubicles and permeable membrane. Utilizing the diffusion based reagents administration; cells and tissues in multiple cubicles receive signals evenly in their cubicles as parallel manner. This device makes efficient multiplex cells or tissues assays with simple plate layout. According to the molecular permeable mechanism, single spike of stimuli as chemical trigger, light activation, electric triggers or temperature shift can induce multiple cells or tissues response at once. Then accompanying with calibrator molecules as for the navigation of stimuli and assisted by suitable computer simulation, accurate kinetic cells or tissues response analysis is achieved. | 2008-10-23 |
20080261299 | Pneumatic Bioreactor - A pneumatic bioreactor having a containment vessel which includes a semi-cylindrical concavity defined by the vessel bottom. A mixing apparatus includes a rotational mixer rotatably mounted within the containment vessel about a horizontal axis. The rotational mixer has buoyancy-driven mixing cavities which are fed by a gas supply beneath the rotational mixer. The mixing apparatus extends into the semi-cylindrical concavity to substantially fill that concavity. The rotational mixer is divided into two wheels with outer paddles extending axially outwardly and inner paddles extending axially inwardly on either side of each ring. Blades between the outer and inner paddles form impellers in the wheels to induce axial flow through the rings in opposite directions. The containment vessel may be of film and supported by a structural housing also having a semi-cylindrical concavity defined by the housing bottom. | 2008-10-23 |
20080261300 | Synthetic genes - The invention provides strategies, methods, vectors, reagents, and systems for production of synthetic genes, production of libraries of such genes, and manipulation and characterization of the genes and corresponding encoded polypeptides. In one aspect, the synthetic genes can encode polyketide synthase polypeptides and facilitate production of therapeutically or commercially important polyketide compounds. | 2008-10-23 |
20080261301 | Antibody Composition-Producing Cell - The present invention relates to a cell for the production of an antibody molecule such as an antibody useful for various diseases having high antibody-dependent cell-mediated cytotoxic activity, a fragment of the antibody and a fusion protein having the Fc region of the antibody or the like, a method for producing an antibody composition using the cell, the antibody composition and use thereof. | 2008-10-23 |
20080261302 | Methods of diagnosing or treating neurological diseases and cell degeneration - The invention discloses an isolated nucleic acid molecule encoding a protein molecule, the function of which is to protect cells against degeneration and/or cell death, wherein the amino acid sequence of the protein comprises the sequence shown in SEQ ID NO. 2 or a functional variant thereof. | 2008-10-23 |
20080261303 | Method and medicament for inhibiting the expression of a given gene - The present invention relates to the specific inhibition of expression of a target gene in mammals using a short double stranded RNA. The dsRNA is less than 49 nucleotides in length and has a nucleotide sequence which is complementary to at least a part of the target gene. The dsRNAs of the present invention are useful for treating diseases, for example, cancer, viral diseases or neurodegenerative diseases. | 2008-10-23 |
20080261304 | METHODS AND COMPOSITIONS FOR ENHANCING DELIVERY OF DOUBLE-STRANDED RNA OR A DOUBLE-STRANDED HYBRID NUCLEIC ACID TO REGULATE GENE EXPRESSION IN MAMMALIAN CELLS - A double-stranded RNA, preferably a small, interfering (si)RNA or a siHybrid, to which cholesterol moieties are linked. | 2008-10-23 |
20080261305 | TGF-beta-MEDIATED OSTEOGENIC DIFFERENTIATION OF MESENCHYMAL STEM CELLS - Methods and compositions are provided for the culture of MSC to provide osteogenic progenitor cells. | 2008-10-23 |
20080261306 | Method for Creating Perfusable Microvessel Systems - A method for creating networks of perfusable microvessels in vitro. A mandrel is drawn through a matrix to form a channel through the matrix. Cells are injected into the channel. The matrix is incubated to allow the cells to attach inside the channel. The channel is perfused to remove unattached cells to create a parent vessel, where the parent vessel includes a perfusable hollow channel lined with cells in the matrix. The parent vessel is induced to create sprouts into the surrounding matrix gel so as to form a microvessel network. The microvessel network is subjected to luminal perfusion through the parent vessel. | 2008-10-23 |
20080261307 | Method of isolating and proliferating autologous antigen-specific CD8+ T Cell using anti-4-1BB antibodies - Provided are methods of isolating and proliferating antigen-specific CD8+ T cells using anti-4-1BB antibodies. The methods of isolating and proliferating CD8+ T cells may yield cells at a higher recovery rate than a conventional isolation method, and the isolation method using humanized anti-4-1BB antibodies may also yield cells at a high recovery rate. Further, in cell culture, cells may be grown at a high proliferation rate. The antigen-specific CD8+ T cells yielded according to the isolation and proliferation methods may be used to treat cancer without any side-effects. | 2008-10-23 |
20080261308 | DRY POWDER CELL CULTURE PRODUCTS AND METHODS OF PRODUCTION THEREOF - The present invention relates to nutritive medium, medium supplement, media subgroup and buffer formulations. The present invention provides powder nutritive medium, medium supplement and medium subgroup formulations, e.g., cell culture medium supplements (including powdered sera such as powdered fetal bovine serum (FBS)), medium subgroup formulations and cell culture media comprising all of the necessary nutritive factors that facilitate the in vitro cultivation of cells. The invention further provides powder buffer formulations that produce particular ionic and pH conditions upon reconstitution with a solvent. The invention provides methods for production of media, media supplement, media subgroup and buffer formulations, and also provides kits and methods for cultivation of prokaryotic and eukaryotic cells, particularly bacterial cells, yeast cells, plant cells and animal cells (including human cells) using these dry powder nutritive media, media supplement, media subgroup and buffer formulations. | 2008-10-23 |
20080261309 | IN VITRO MULTIPLICATION OF HOODIA PLANTS - A tissue culture micropropagation process for | 2008-10-23 |
20080261310 | IN VITRO ROOTING OF HOODIA PLANTS - An in vitro tissue culture process of rooting | 2008-10-23 |
20080261311 | In vivo incorporation of unnatural amino acids - The invention provides methods and compositions for in vivo incorporation of unnatural amino acids. Also provided are compositions including proteins with unnatural amino acids. | 2008-10-23 |
20080261312 | Methods for matrix cleanup and analysis of drugs and metabolites in biological matrices - The invention is directed to the use of weak anion exchange (WAX) materials for trapping of negative and zwitterionic interferences from biological matrices, and then reduction of the biological matrix effect in the quantitative analysis process of basic and neutral compounds present in the matrix. The sample preparation process includes adding the WAX cleanup step before or after or during the conventional extraction procedures like liquid-liquid extraction, protein precipitation, solid phase extraction and others. Such a step greatly enhances the selectivity of the extraction process via the removal of the majority of the contaminants and reduces the matrix effect in the quantitative analysis. In addition, the WAX-enhanced extraction is very simple, versatile, rug and easy to be operated. | 2008-10-23 |
20080261313 | Apo B measurement system and method - A system and method for measuring apolipoprotein B | 2008-10-23 |
20080261314 | FLUORESCENT PROBE FOR ZINC - A compound represented by the following general formula (I) or a salt thereof: | 2008-10-23 |
20080261315 | Colorimetric and Fluorometric Determination of Homocysteine and Cysteine - Colorimetric and fluorometric methods are disclosed for the rapid, accurate, selective, and inexpensive detection of homocysteine, or of homocysteine and cysteine, or of cysteine. The methods may be employed with materials that are readily available commercially. The novel methods are selective for homocysteine, for cysteine, or for total homocysteine and cysteine, and do not cross-react substantially with chemically-related species such as glutathione. The homocysteine-selective method does not have substantial cross-reactivity to the very closely related species cysteine. The cysteine-selective method does not have substantial cross-reactivity to the very closely related species homocysteine. The methods may be used, for example, in a direct assay of human blood plasma for homocysteine levels. | 2008-10-23 |
20080261316 | Compositions and Methods For Enhancing the Identification of Prior Protein Prpsc - A method for purifying PrP | 2008-10-23 |
20080261317 | Methods of Detecting Myocardial Ischemia and Myocardial Infarction - The disclosed methods address the identification of myocardial ischemia and myocardial infarction using metabolomics, as well as the identification of metabolic products whose differential expression over time is indicative of myocardial ischemia and/or myocardial infarction. | 2008-10-23 |
20080261318 | Signalling Compounds For Use In Methods Of Detecting Hydrogen Peroxide - Methods and compound useful for detecting a source of hydrogen peroxide are disclosed wherein a signalling compound of the formula: | 2008-10-23 |
20080261319 | METHOD FOR DETECTING PRESENCE OF ARISTOLOCHIA MATERIALS IN HERBAL PRODUCTS AND BOTANICALS - A method for detecting herbs or plants of the | 2008-10-23 |
20080261320 | Noninvasive blood sugar level measuring method - A noninvasive blood sugar level measurement method includes a process of changing a blood sugar level of a biological body, a process of noninvasively measuring biological feature amounts at plural measurement points that are timewise shifted from each other, a process of invasively measuring blood sugar levels of the biological body by the number of times that is lesser than the measurement points of the biological feature amount, a process of obtaining an approximate curve indicating temporal change in the actually measured blood sugar level that is obtained by the invasive measurement, a process of obtaining, using the obtained approximate curve, blood sugar levels (interpolation blood sugar levels) that would be obtained by the invasive measurement at the measurement times when the biological feature amounts are noninvasively measured, and a process of associating the values of the biological feature amounts at the times corresponding to the respective measurement points of the biological feature amounts with the interpolation blood sugar levels at the respective times, thereby forming a correlation table having plural sets of the biological feature amounts and the interpolation blood sugar levels. Therefore, even when the change in the biological feature amount relative to the blood sugar level is not monotonous, it is possible to form a precise correlation table without increasing the number of times of the invasive blood sugar level measurement. | 2008-10-23 |
20080261321 | Methods and Compositions for Detecting and Isolating Phosphorylated Molecules Using Hydrated Metal Oxides - The invention provides methods for detecting and isolating phosphomolecules using phosphoaffinity materials that comprise a hydrated metal oxide. In an embodiment, a method for detecting a phosphomolecule in a sample involves (a) contacting a sample with a phosphoaffinity material comprising a hydrated metal oxide, under conditions wherein a phosphomolecule is capable of binding to the phosphoaffinity material to form a phosphomolecule-phosphoaffinity material complex, and (b) detecting formation of a phosphomolecule-phosphoaffinity material complex, thereby detecting a phosphomolecule in the sample. In another embodiment, a method for isolating a phosphomolecule from a sample involves (a) contacting a sample with a phosphoaffinity material comprising a hydrated metal oxide, under conditions wherein a phosphomolecule is capable of binding to the phosphoaffinity material to form a phosphomolecule-phosphoaffinity material complex, wherein the hydrated metal oxide comprises yttrium, and (b) separating the phosphomolecule-phosphoaffinity material complex from the sample, thereby isolating the phosphomolecule from the sample. | 2008-10-23 |
20080261322 | Nitric Oxide Detection - The present invention relates to a method for amplifying the detected signal in a gas sensor. More specifically, the present invention relates to a method for increasing the concentration of the gas which is being detected in a sample or increasing the concentration of a gas which is directly obtained from the gas in the sample by chemical reaction. The gas which is to be detected is nitric oxide (NO). In particular, the method concerns the selective conversion of NO to NO2 which allows a threefold amplification of the number of analyte molecules in NO trace gas analysis in a single amplification cycle. Subsequent reduction or thermal decomposition of the obtained NO2 can provide NO again, which can again be introduced in a new amplification cycle. Multiple (n) amplification cycles can provide a sensitivity amplification by a factor 3 | 2008-10-23 |
20080261323 | Photo-Swichable Surfaces with Controllable Physico-Chemical Properties - Photochromic materials, such as spiropyran dyes, are disclosed that can be used for high-density optical storage and molecular switches. According to the disclosure these compounds can be used as transducers in optical sensors. When the spiropyran dye absorbs UV light it switches to the merocyanine form, and this structure has an active binding site for cations. When cations bind to the site, the resulting colored complex has a new absorption band in the visible spectrum. By shining white or green light on the colored complex, the dye is reverted to the closed spiropyran form, and the cation is released. The disclosure optimizes the immobilization of the spiropyran dye onto a polymer substrate via long chain alkyl groups. These long chain alkyl linkers enable the dye to reversibly form the preferred merocyanine (2):(1) cation sandwich complex. | 2008-10-23 |
20080261324 | System, Device and Method for Reducing Luminescence Output Shifts - Devices, systems, and methods for conducting chemiluminescent immunoassay testing and, more particularly, to initiating and monitoring a chemiluminescent reaction in a plurality of such assays, of different types, on a single immunoassay instrument, in a single procedure, using a plurality of labels and a triggering reagent combination are disclosed. Moreover, by including a base reagent injector assembly having an “e-channel” to provide a swirling turbulence to the base reagent immediately before it is introduced into the well of a cuvette containing a sample and an acid reagent. The added turbulence addresses the phenomenon referred to as “RLU shift,” in which the luminescence output can increase or decrease between assays. | 2008-10-23 |
20080261325 | Method and Device for Dispensing Dry Powders - The inventive method for dispersing a dry powder sample ( | 2008-10-23 |
20080261326 | Drop-on-demand manufacturing of diagnostic test strips - A drop-on-demand system for manufacturing diagnostic test strips includes a drop-on-demand mechanism, and a drop volume feedback subsystem and/or a vision subsystem. The drop-on-demand mechanism dispenses one or more reagents on the diagnostic test strips in one or more desired volumes and at one or more desired locations. The drop volume feedback subsystem control volumes of the reagents dispensed by the drop-on-demand mechanism so that the drop-on-demand mechanism dispenses the reagents on the diagnostic test strips in the desired volumes. The vision subsystem aligns the drop-on-demand mechanism in relation to the diagnostic test strips so that the drop-on-demand mechanism dispenses the reagents on the diagnostic test strips at the desired locations. | 2008-10-23 |
20080261327 | Cell Free Assay for Determining a Substance of Interest and Molecular Complexes Used Therefore - The invention involves receptor complexes which include, inter alia, a receptor protein, and a reporter molecule. There is at least one unnatural, or non-naturally occurring amino acid in the receptor molecule. When a ligand interacts with the receptor, the interaction causes the reporter to generate a detectable signal. The complexes are useful in cell free, assay systems and may be used as part of micelles. | 2008-10-23 |
20080261328 | Method of preventing precipitation of a reactive substance-bound microparticle, and reagent containing the micro particle - According to the present invention, precipitation of a reactive substance-bound microparticle can be prevented in a dispersion liquid, to make a concentration of the reactive substance-bound microparticle uniform in the dispersion liquid. The present invention provides a method of preventing precipitation of a reactive substance-bound microparticle. The method includes coexisting at least one selected from the group consisting of polyanion or its salt, dextran, cyclodextrin, polyethylene glycol, and glycerol, with the microparticle in a dispersion liquid. | 2008-10-23 |
20080261329 | Method of analysis of a mixture of biological and/or chemical components with the use magnetic particles and apparatus for its embodiment - Technical field: analysis of mixtures, predominantly of biologic origin, for the contents of biological and/or chemical components, and analysis of mixtures, which parameters determine vital functions of biologic objects. | 2008-10-23 |
20080261330 | Apparatus Components and Methods of Using Apparatus Components to Detect the Presence of an Analyte - Apparatus components including rigid supports suitable for use in an affinity column, affinity columns, and an affinity columns in fluid communication with an analytical column, such as in a high pressure liquid chromatography (HPLC) column, are disclosed. Methods of using the apparatus components to detect the presence of one or more analytes are also disclosed. | 2008-10-23 |
20080261331 | MRAM AND METHOD OF MANUFACTURING THE SAME - A magnetic memory device comprising, a magneto-resistance effect element that is provided at an intersection between a first write line and a second write line. And the magneto-resistance effect element having, an easy axis that extends in a direction of extension of the first write line, and a first conductive layer for electrical connection to the magneto-resistance effect element, the first conductive layer having sides which are in flush with sides of the magneto-resistance effect element. | 2008-10-23 |
20080261332 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - The present invention provides a method for manufacturing a semiconductor device, including the steps of: forming a ferroelectric film on a first conductive film by a sol-gel method; forming a first conductive metal oxide film on the ferroelectric film; carrying out a first annealing on the first conductive metal oxide film; forming a second conductive metal oxide film on the first conductive metal oxide film, so that the first and second conductive films serve as a second conductive film; and forming a capacitor by patterning the first conductive film, the ferroelectric film and the second conductive film. In the step of forming the first conductive metal oxide film, ferroelectric characteristics are adjusted with a flow rate ratio of oxygen by utilizing the fact that the ferroelectric characteristics of the ferroelectric film improve as the flow rate ratio of oxygen in a sputtering gas increases. | 2008-10-23 |
20080261333 | Methods of forming a material film, methods of forming a capacitor, and methods of forming a semiconductor memory device using the same - A method of forming a material (e.g., ferroelectric) film, a method of manufacturing a capacitor, and a method of forming a semiconductor memory device using the method of forming the (e.g., ferroelectric) film are provided. Pursuant to an example embodiment of the present invention, a method of forming a ferroelectric film includes preparing a substrate, depositing an amorphous ferroelectric film on the substrate, and crystallizing the amorphous ferroelectric film by irradiating it with a laser beam. According to still another example embodiment of the present invention, a method of forming a ferroelectric film may reduce the thermal damage to other elements because the ferroelectric film may be formed at a temperature lower than about 500° C. to about 550° C. | 2008-10-23 |
20080261334 | Method of Processing Semiconductor Wafers - A method of processing semiconductor waters comprises forming a pattern of recesses in an exposed surface of each water in a lot, prior to an epitaxy step. At least one recessed test structure is included in the pattern of recesses. At least one dimension of the recessed test structure is determined prior to the epitaxy step, then a corresponding dimension of an epitaxial structure grown above the recessed test structure in the epitaxy step is measured. A deviation between the dimension of the recessed test structure and the dimension of the epitaxial structure is determined and, from the deviation, the process temperature at which the epitaxy step was performed is determined. In case the deviation exceeds a predetermined limit, the temperature in the process chamber is adjusted for a subsequent lot of waters to be processed. | 2008-10-23 |
20080261335 | ENDPOINT DETECTION FOR PHOTOMASK ETCHING - Apparatus and method for endpoint detection are provided for photomask etching. The apparatus provides a plasma etch chamber with a substrate support member. The substrate support member has at least two optical components disposed therein for use in endpoint detection. Enhanced process monitoring for photomask etching are achieved by the use of various optical measurement techniques for monitoring at different locations of the photomask. | 2008-10-23 |
20080261336 | Semiconductor device and manufacturing method thereof - A method of manufacturing a semiconductor device using a wiring substrate is provided which can facilitate the handling of the wiring substrate. The method includes the steps of forming a peelable resin layer on a silicon substrate, forming the wiring substrate on the peelable resin layer, mounting semiconductor chips on the wiring substrate, forming semiconductor devices by sealing the plurality of semiconductor chips by a sealing resin, individualizing the semiconductor devices by dicing the semiconductor devices from the sealing resin side but leaving the silicon substrate, peeling each of the individualized semiconductor devices from the silicon substrate between the silicon substrate and the peelable resin layer, and exposing terminals on the wiring substrate by forming openings through the peelable resin layer or by removing the peelable resin layer. | 2008-10-23 |
20080261337 | LOW VOLTAGE ELECTRON SOURCE WITH SELF ALIGNED GATE APERTURES, FABRICATION METHOD THEREOF, AND LUMINOUS DISPLAY USING THE ELECTRON SOURCE - A method of fabricating an electron source having a self-aligned gate aperture is disclosed. A substrate is deposited on a first conductive layer. Over the first conductive layer an emitter layer is deposited. The emitter layer includes one or a plurality of spaced-apart nano-structures and a solid surface with nano-structures protruding above the surface. An insulator is conformally deposited over the emitter layer surface and forms a post from each protruding nano-structure. A second conductive layer is deposited over the insulator and the second conductive layer and the insulator are removed from the nano-structures such that apertures are formed in the second conductive layer and at least the ends of the nano-structures are exposed at the centers of said apertures. | 2008-10-23 |
20080261338 | Method For Manufacturing an Electronics Module Comprising a Component Electrically Connected to a Conductor-Pattern Layer - Method for manufacturing an electronic module, which electronic module includes a component ( | 2008-10-23 |
20080261339 | PACKAGING METHOD TO MANUFACTURE PACKAGE FOR A HIGH-POWER LIGHT EMITTING DIODE - A packaging method to manufacture a package for a high-power light emitting diode (LED) has steps of (a) obtaining a metal board, (b) treating the metal board, (c) molding a cell matrix with multiple reflective bases, (d) attaching LED chips onto the dissipating boards and bonding conductive wires in each corresponding reflective base of the cell matrix, (e) encapsulating the LED chips and conductive wires in the reflective base of the cell matrix to form a after-packaging board and (f) cutting off the after-packaging board to form multiple individual high-power LED packages. Most heat from the LED chips is conducted via the dissipating board thereby improving thermal conduction efficiency and allowing more powerful and numerous LED chips to operate per package so increasing applications of LEDs. Therefore, the present invention provides different pass ways for conducting heat and electricity to improve heat conduction of the LED. | 2008-10-23 |
20080261340 | SURFACE-ROUGHENING METHOD - The method is disclosed as applied to roughening the light-emitting surface of an LED wafer for reduction of the internal total reflection of the light generated. A masking film of silver is first deposited on the surface of a wafer to be diced into LED chips. Then the masking film is heated to cause its coagulation into discrete particles. Then, using the silver particles as a mask, the wafer surface is dry etched to create pits therein. The deposition of silver on the wafer surface and its thermal coagulation into particles may be either successive or concurrent. | 2008-10-23 |
20080261341 | Method for fabricating a light emitting diode chip - A method for fabricating substrate-free LED chips has a multilayer semiconductor structure at least 10 microns thick provided on a growth substrate. One or more arrays of parallel streets are etched into the multilayer semiconductor structure using a first pulsed laser beam. By scanning a second pulsed laser beam through the growth substrate to the multilayer semiconductor structure, the LED chips are detached from the growth substrate while simultaneously forming surface features on the chips. | 2008-10-23 |
20080261342 | Chemical Sensor Using Semiconducting Metal Oxide Nanowires - Indium oxide nanowires are used for determining information about different chemicals or Biologics. Chemicals are absorbed to the surface of the nanowires, and cause the semiconducting characteristics of the Nanowires to change. These changed characteristics are sensed, and used to determine either the presence of the materials and/or the concentration of the materials. The nanowires may be between 10 and 30 nm in diameter, formed using a comparable size particle of catalyst material. The nanowires may then be used as part of the channel of a field effect transistor, and the field effect transistor is itself characterized. | 2008-10-23 |
20080261343 | VACUUM PACKAGED SINGLE CRYSTAL SILICON DEVICE - A method for forming a vibrating micromechanical structure having a single crystal silicon (SCS) micromechanical resonator formed using a two-wafer process, including either a Silicon-on-insulator (SOI) or insulating base and resonator wafers, wherein resonator anchors, capacitive air gap, isolation trenches, and alignment marks are micromachined in an active layer of the base wafer; the active layer of the resonator wafer is bonded directly to the active layer of the base wafer; the handle and dielectric layers of the resonator wafer are removed; windows are opened in the active layer of the resonator wafer; masking the active layer of the resonator wafer with photoresist; a SCS resonator is machined in the active layer of the resonator wafer using silicon dry etch micromachining technology; and the photoresist is subsequently dry stripped. A patterned SCS cover is bonded to the resonator wafer resulting in hermetically sealed chip scale wafer level vacuum packaged devices. | 2008-10-23 |
20080261344 | VACUUM PACKAGED SINGLE CRYSTAL SILICON DEVICE - A method for forming a vibrating micromechanical structure having a single crystal silicon (SCS) micromechanical resonator formed using a two-wafer process, including either a Silicon-on-insulator (SOI) or insulating base and resonator wafers, wherein resonator anchors, capacitive air gap, isolation trenches, and alignment marks are micromachined in an active layer of the base wafer; the active layer of the resonator wafer is bonded directly to the active layer of the base wafer; the handle and dielectric layers of the resonator wafer are removed; windows are opened in the active layer of the resonator wafer; masking the active layer of the resonator wafer with photoresist; a SCS resonator is machined in the active layer of the resonator wafer using silicon dry etch micromachining technology; and the photoresist is subsequently dry stripped. A patterned SCS cover is bonded to the resonator wafer resulting in hermetically sealed chip scale wafer level vacuum packaged devices. | 2008-10-23 |
20080261345 | METHOD FOR MANUFACTURING A SEMICONDUCTOR PRESSURE SENSOR - Method for manufacturing a semiconductor pressure sensor, wherein, in a silicon substrate, trenches are dug and delimit walls; a closing layer is epitaxially grown, that closes the trenches at the top and forms a suspended membrane; a heat treatment is performed so as to cause migration of the silicon of the walls and to form a closed cavity underneath the suspended membrane; and structures are formed for transducing the deflection of the suspended membrane into electrical signals. | 2008-10-23 |
20080261346 | SEMICONDUCTOR IMAGE DEVICE PACKAGE WITH DIE RECEIVING THROUGH-HOLE AND METHOD OF THE SAME - The present invention discloses a structure of package comprising: a substrate with a die receiving through hole, a connecting through hole structure and a first contact pad; a die having micro lens area disposed within the die receiving through hole; a transparent cover covers the micro lens area; a surrounding material formed under the die and filled in the gap between the die and sidewall of the die receiving though hole; a dielectric layer formed on the die and the substrate; a re-distribution layer (RDL) formed on the dielectric layer and coupled to the first contact pad; a protection layer formed over the RDL; and a second contact pad formed at the lower surface of the substrate and under the connecting through hole structure. | 2008-10-23 |
20080261347 | METHOD OF MANUFACTURING SEMICONDUCTOR FILM AND METHOD OF MANUFACTURING PHOTOVOLTAIC ELEMENT - A method of manufacturing a semiconductor film capable of inhibiting the quality of a semiconductor film from destabilization is obtained. This method of manufacturing a semiconductor film includes steps of introducing source gas for a semiconductor, controlling the pressure of an atmosphere formed by the source gas to a prescribed level, heating a catalytic wire to at least a prescribed temperature after controlling the pressure of the atmosphere to the prescribed level and forming a semiconductor film by decomposing the source gas with the heated catalytic wire. | 2008-10-23 |
20080261348 | METHOD OF MANUFACTURING SEMICONDUCTOR FILM AND METHOD OF MANUFACTURING PHOTOVOLTAIC ELEMENT - A method of manufacturing a semiconductor film capable of suppressing difficulty in temperature control of a catalytic wire is obtained. This method of manufacturing a semiconductor film includes steps of heating a catalytic wire to at least a prescribed temperature and forming a semiconductor film by introducing source gas for a semiconductor and decomposing the source gas with the heated catalytic wire after heating the catalytic wire to at least the prescribed temperature. | 2008-10-23 |
20080261349 | PROTECTIVE COATING FOR PLANARIZATION - Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane. | 2008-10-23 |
20080261350 | SOLDER INTERCONNECTION ARRAY WITH OPTIMAL MECHANICAL INTEGRITY - A method for assembling, and the resultant electronic module, includes attaching a chip to a substrate using a first solder interconnection array, and attaching a board to the substrate using a second solder interconnection array, which may be a single-melt or a dual-melt solder array. The second solder interconnection array resides entirely within a space defined between the board and substrate. A creep resistant structure is provided within this space for maintaining the defined space and optimizing integrity of the second solder interconnection array. The creep resistant structure may include an underfill material, balls, brackets, frames, collars or combinations thereof. Wherein the creep resistant structure is an underfill material, it is crucial that the substrate be attached to the board before either entirely encapsulating the second interconnection array with underfill material, or partially encapsulating the second solder interconnection array at discrete locations with underfill material. | 2008-10-23 |
20080261351 | WAFER SAWING METHOD - A wafer sawing method for sawing a wafer by using a cutting tool is provided. Sawing paths are formed on a surface of the wafer. In the wafer sawing method, a carrier on which strip-shaped adhesives or at least a fiducial mark is formed is firstly provided. The dimension of the carrier is greater than the dimension of the wafer. Next, the surface of the wafer is bonded to the carrier, and the strip-shaped adhesives or the fiducial mark is extended or located outside a bonding region between the wafer and the carrier. Here, the surface of the wafer faces the carrier. The cutting tool and the carrier are positioned according to the strip-shaped adhesives or the fiducial mark outside the bonding region. The wafer is then sawed by using the cutting tool. The wafer sawing method provides a precise and rapid sawing process and achieves superior productive yield. | 2008-10-23 |
20080261352 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THEREOF, CIRCUIT BOARD AND ELECTRONIC APPARATUS - A semiconductor device is provided comprising: a semiconductor element including a plurality of electrodes; first wirings coupled to the electrodes and directed toward a center of the semiconductor element from a portion coupled to the electrodes; second wirings coupled between the first wirings and external terminals, the second wirings being directed to an outer area of the semiconductor element relative to the center; and at least one resin layer formed between the first wirings and the second wirings. | 2008-10-23 |
20080261353 | Underfill film having thermally conductive sheet - An underfill film for an electronic device includes a thermally conductive sheet. The electronic device may include a printed circuit board, an electrical component, an underfill, and the thermally conductive sheet. The underfill is situated between the circuit board and the component. The thermally conductive sheet is situated within the underfill, and together with the underfill, constitutes the underfill film. The device may include solder bumps affixing the component to the circuit board, the underfill film having holes within which the solder bumps are aligned. There may be solder bumps on the underside of the circuit board promoting heat dissipation. There may be heat sinks on the circuit board to which the thermally conductive sheet is affixed promoting heat dissipation. The thermally conductive sheet may be affixed to a chassis promoting heat dissipation. The thermally conductive sheet thus promotes heat dissipation from the component to at least the circuit board. | 2008-10-23 |
20080261354 | STRUCTURE AND METHOD OF FABRICATING A HYBRID SUBSTRATE FOR HIGH-PERFORMANCE HYBRID-ORIENTATION SILICON-ON-INSULATOR CMOS DEVICES - The present invention provides a method of integrating semiconductor devices such that different types of devices are formed upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. Specifically, the present invention provides a method of integrating semiconductor devices such that pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane of a planar hybrid substrate. The method of the present invention also improves the performance of creating SOI-like devices with a combination of a buried insulator and counter-doping layers. The present invention also relates to semiconductor structures that are formed utilizing the method of the present invention. | 2008-10-23 |
20080261355 | METHOD OF MAKING A SEMICONDUCTOR DEVICE WITH A STRESSOR - First and second transistors are formed adjacent to each other. Both transistors have gate sidewall spacers removed. A stressor layer is formed overlying the first and second transistors. Stress in the stressor layer that overlies the first transistor is modified. Stress in the stressor layer that overlies the second transistor is permanently transferred to a channel of the second transistor. The stressor layer is removed except adjacent the gate electrode sidewalls of the first transistor and the second transistor where the stressor layer is used as gate sidewall spacers. Electrical contact to electrodes of the first transistor and the second transistor is made while using the gate sidewall spacers for determining a physical boundary of current electrodes of the first and second transistors. Subsequently formed first and a second stressors are positioned close to transistor channels of the first and second transistors. | 2008-10-23 |
20080261356 | METHOD OF FORMING THIN FILM TRANSISTOR - A thin film transistor including a gate, a gate insulating layer, a semiconductor layer and a source/drain is provided. The gate is disposed over a substrate and includes at least one molybdenum-niobium alloy nitride layer. The gate insulating layer is formed over the substrate to cover the gate. The semiconductor layer is disposed over the gate insulating layer above the gate. The source/drain is disposed over the semiconductor layer. | 2008-10-23 |
20080261357 | METHOD FOR FABRICATION OF SEMICONDUCTOR DEVICE - After forming a source-drain material film on an insulator layer, an opening portion reaching the insulator layer is formed in the source-drain material film. Then, a channel having desired thickness and a gate insulator are sequentially formed on the insulator layer and the source-drain material film in the opening portion. Thereafter, a gate material film embedding the opening portion is formed on the gate insulator. Subsequently, a cap film is formed on the gate material film, thereby forming the gate made of the gate material film. Then, a mask layer is formed on the source-drain material film. Next, the source-drain material film not protected by the mask layer is removed while protecting the gate by the cap film, thereby leaving the source-drain material film on both sides of the gate. The source-drain material film on one side becomes the source and that on the other side becomes the drain. | 2008-10-23 |
20080261358 | Manufacture of Lateral Semiconductor Devices - A method of manufacturing a lateral semiconductor device comprising a semiconductor body ( | 2008-10-23 |
20080261359 | LDMOS Transistor Device, Integrated Circuit, and Fabrication Method Thereof - An LDMOS transistor device in an integrated circuit comprises a semiconductor substrate ( | 2008-10-23 |
20080261360 | METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE - In a method of manufacturing a semiconductor device, a gate insulation layer is formed on a substrate including a first channel of a first conductive type and a second channel of a second conductive type different from the first conductive type. A first conductive layer including a first metal is formed on the gate insulation layer, and a second conductive layer including a second metal different from the first metal is formed on the first conductive layer formed over the second channel. The second conductive layer is partially removed by a wet etching process to form a second conductive layer pattern over the second channel. | 2008-10-23 |
20080261361 | Shallow trench isolation for SOI structures combining sidewall spacer and bottom liner - A method for making a semiconductor device is provided which comprises (a) providing a layer stack comprising a semiconductor layer ( | 2008-10-23 |
20080261362 | METHOD OF MAKING A SEMICONDUCTOR DEVICE USING A STRESSOR - A method for forming a semiconductor device includes providing a substrate and forming a p-channel device and an n-channel device, each of the p-channel device and the n-channel device comprising a source, a drain, and a gate, the p-channel device having a first sidewall spacer and the n-channel device having a second sidewall spacer. The method further includes forming a liner and forming a tensile stressor layer over the liner and removing a portion of the tensile stressor layer from a region overlying the p-channel device. The method further includes transferring a stress characteristic of an overlying portion of a remaining portion of the tensile stressor layer to a channel of the n-channel device. The method further includes using the remaining portion of the tensile stressor layer as a hard mask, forming a first recess and a second recess adjacent the gate of the p-channel device. | 2008-10-23 |
20080261363 | DUAL GATED FINFET GAIN CELL - A memory gain cell for a memory circuit, a memory circuit formed from multiple memory gain cells, and methods of fabricating such memory gain cells and memory circuits. The memory gain cell includes a storage device capable of holding a stored electrical charge, a write device, and a read device. The read device includes a fin of semiconducting material, electrically-isolated first and second gate electrodes flanking the fin, and a source and drain formed in the fin adjacent to the first and the second gate electrodes. The first gate electrode is electrically coupled with the storage device. The first and second gate electrodes are operative for gating a region of the fin defined between the source and the drain to thereby regulate a current flowing from the source to the drain. When gated, the magnitude of the current is dependent upon the electrical charge stored by the storage device. | 2008-10-23 |
20080261364 | METHOD FOR FORMING STACK CAPACITOR - A method for forming a stack capacitor includes providing a substrate with a bottom layer, a BPSG layer, a USG layer and a top layer thereon; using the top layer as a hard mask and the substrate as a first etching stop layer to perform a dry etching process to form a tapered trench in the bottom layer, the BPSG layer and the USG layer; removing the top layer to perform a selective wet etching process to partially remove the BPSG layer; depositing conformally a poly-Si layer and filling the trench with a sacrificial layer; removing the poly-Si layer unmasked by the sacrificial layer; using the bottom layer as a second etching stop layer to perform a wet etching process to remove the USG layer and BPSG layer; performing a static drying process; and depositing a dielectric layer and a conductive material to form the stack capacitor. | 2008-10-23 |
20080261365 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A technology realizing decreases of capacitance between the adjoining floating gates and of the threshold voltage shift caused by interference between the adjoining memory cells in a nonvolatile semiconductor memory device with the advances of miniaturization in the period following the 90 nm generation. By having the floating gate | 2008-10-23 |
20080261366 | NON-VOLATILE MEMORY DEVICE HAVING IMPROVED ERASE EFFICIENCY AND METHOD OF MANUFACTURING THE SAME - A non-volatile memory device having an improved erase efficiency and a method of manufacturing the same are provided. The method includes: forming a stack structure of a tunnel dielectric layer, a charge trapping layer, a charge blocking layer and a gate on a semiconductor substrate; and performing a post treatment of the gate using an oxygen or CF | 2008-10-23 |
20080261367 | METHOD FOR PROCESS INTEGRATION OF NON-VOLATILE MEMORY CELL TRANSISTORS WITH TRANSISTORS OF ANOTHER TYPE - A method for making a semiconductor device having non-volatile memory cell transistors and transistors of another type is provided. In the method, a substrate is provided having an NVM region, a high voltage (HV) region, and a low voltage (LV) region. The method includes forming a gate dielectric layer on the HV and LV regions. A tunnel oxide layer is formed over the substrate in the NVM region and the gate dielectric in the HV and LV regions. A first polysilicon layer is formed over the tunnel dielectric layer and gate dielectric layer. The first polysilicon layer is patterned to form NVM floating gates. An ONO layer is formed over the first polysilicon layer. A single etch removal step is used to form gates for the HV transistors from the first polysilicon layer while removing the first polysilicon layer from the LV region. | 2008-10-23 |
20080261368 | WORK FUNCTION ADJUSTMENT WITH THE IMPLANT OF LANTHANIDES - Semiconductor devices and fabrication methods are provided, in which fully silicided transistor gates are provided for MOS transistors. A lanthanide series metal is implanted into the gate electrode layer prior to silicidation and diffuses into the gate dielectric during an activation anneal. This process and resultant structure provides adjustment of the gate electrode work function, thereby tuning the threshold voltage of the resulting transistor. | 2008-10-23 |
20080261369 | STRUCTURE AND METHOD FOR MOSFET WITH REDUCED EXTENSION RESISTANCE - The present invention provides a method in which a low-resistance connection between the MOS channel and silicided source/drain regions is provided that has an independence from the extension ion implant process as well as device overlap capacitance. The method of the present invention broadly includes selectively removing outer spacers of an MOS structure and then selectively plating a metallic or intermetallic material on exposed portions of a semiconductor substrate that were previously protected by the outer spacers. The present invention also provides a semiconductor structure that is formed utilizing the method. The semiconductor structure includes a low-resistance connection between the silicided source/drain regions and the channel regions which includes a selectively plated metallic or intermetallic material. | 2008-10-23 |
20080261370 | Semiconductor device and method of fabricating the same - According to the present invention, there is provided a semiconductor device fabrication method comprising:
| 2008-10-23 |
20080261371 | VERTICAL BIPOLAR TRANSISTOR WITH A MAJORITY CARRIER ACCUMULATION LAYER AS A SUBCOLLECTOR FOR SOI BiCMOS WITH REDUCED BURIED OXIDE THICKNESS FOR LOW-SUBSTRATE BIAS OPERATION - The present invention provides a “subcollector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped subcollector. Instead, the inventive vertical SOI BJT uses a back gate-induced, majority carrier accumulation layer as the subcollector when it operates. The SOI substrate is biased such that the accumulation layer is formed at the bottom of the first semiconductor layer. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS. A back-gated CMOS device is also provided. | 2008-10-23 |
20080261372 | METHOD OF MANUFACTURING VIBRATING MICROMECHANICAL STRUCTURES - A method for fabrication of single crystal silicon micromechanical resonators using a two-wafer process, including either a Silicon-on-insulator (SOI) or insulating base and resonator wafers, wherein resonator anchors, a capacitive air gap, isolation trenches, and alignment marks are micromachined in an active layer of the base wafer; the active layer of the resonator wafer is bonded directly to the active layer of the base wafer; the handle and dielectric layers of the resonator wafer are removed; viewing windows are opened in the active layer of the resonator wafer; masking the single crystal silicon semiconductor material active layer of the resonator wafer with photoresist material; a single crystal silicon resonator is machined in the active layer of the resonator wafer using silicon dry etch micromachining technology; and the photoresist material is subsequently dry stripped. | 2008-10-23 |
20080261373 | Method of fabricating semconductor device - A method of fabricating a semiconductor device includes forming a buffer insulating film over a semiconductor substrate including a conductive pattern. The buffer insulating film is etched using a storage node mask to form a buffer insulating pattern exposing the conductive pattern. The buffer insulating pattern defines a region wider than a storage node region. An etch stop film is formed over the conductive pattern and the buffer insulating pattern. An interlayer insulating film is formed over the etch stop film. The interlayer insulating film is etched using the storage node mask to expose the etch stop film. The exposed etch stop film is etched to form the storage node region exposing conductive pattern. A lower storage node is formed over the storage node region. | 2008-10-23 |
20080261374 | SEPARATE LAYER FORMATION IN A SEMICONDUCTOR DEVICE - A semiconductor device is formed. A first gate dielectric layer is formed over the semiconductor layer. A first conductive layer is formed over the first gate dielectric. A first separation layer is formed over the first conductive layer. A trench is formed in the semiconductor layer to separate the first mesa and the second mesa. The trench is filled with an isolation material to a height above a top surface of the first conductive layer. The first conductive layer is removed from the second mesa. A second conductive layer is formed over the first separation layer of the first mesa and over the second mesa. A planarizing etch removes the second conductive layer from over the first mesa. A first transistor of a first type is formed in the first mesa, and a second transistor of a second type is formed in the second mesa. | 2008-10-23 |
20080261375 | Method of Forming a Semiconductor Device Having a Dummy Feature - A method for forming a semiconductor device includes identifying an area that comprises an active device region, wherein the area has a perimeter at a first location and at least a portion of the edge of the active device region is coincident with at least a portion of the perimeter, expanding the perimeter to a first distance away from the first location, wherein the first distance defines a first point of a dummy feature, determining a second point of the dummy feature, adding the dummy feature to a layout using the first point and the second point, and using the layout to form a layer in a semiconductor device. | 2008-10-23 |
20080261376 | Method of manufacturing SOI substrate - To provide an SOI substrate with an SOI layer that can be put into practical use, even when a substrate with a low allowable temperature limit such as a glass substrate is used, and to provide a semiconductor substrate formed using such an SOI substrate. In order to bond a single-crystalline semiconductor substrate to a base substrate such as a glass substrate, a silicon oxide film formed by CVD with organic silane as a source material is used as a bonding layer, for example. Accordingly, an SOI substrate with a strong bond portion can be formed even when a substrate with an allowable temperature limit of less than or equal to 700° C. such as a glass substrate is used. A semiconductor layer separated from the single-crystalline semiconductor substrate is irradiated with a laser beam so that the surface of the semiconductor layer is planarized and the crystallinity thereof is recovered. | 2008-10-23 |
20080261377 | METHOD OF FORMING A DEVICE WAFER WITH RECYCLABLE SUPPORT - A method for forming a device wafer with a recyclable support by providing a wafer having first and second surfaces, with at least the first surface of the wafer comprising a semiconductor material that is suitable for receiving or forming electronic devices thereon, providing a supporting substrate having upper and lower surfaces, and providing the second surface of the wafer or the upper surface of the supporting substrate with void features in an amount sufficient to enable a connecting bond therebetween to form a construct wherein the bond is formed at an interface between the wafer and the substrate and is suitable to maintain the wafer and supporting substrate in association while forming or applying electronic devices to the first surface of the wafer, but which connecting bond is severable at the interface due to the void features to separate the substrate from the wafer so that the substrate can be reused. | 2008-10-23 |
20080261378 | Method for Growth of Gan Single Crystal, Method for Preparation of Gan Substrate, Process for Producing Gan-Based Element, and Gan-Based Element - A GaN-based thin film (thick film) is grown using a metal buffer layer grown on a substrate. (a) A metal buffer layer ( | 2008-10-23 |
20080261379 | Method for manufacturing SOI substrate and semiconductor device - It is an object of the present invention to provide a method for manufacturing an SOI substrate having an SOI layer that can be used in practical applications with high yield even when a flexible substrate such as a glass substrate or a plastic substrate is used. Further, it is another object of the present invention to provide a method for manufacturing a thin semiconductor device using such an SOI substrate with high yield. When a single-crystal semiconductor substrate is bonded to a flexible substrate having an insulating surface and the single-crystal semiconductor substrate is separated to manufacture an SOI substrate, one or both of bonding surfaces are activated, and then the flexible substrate having an insulating surface and the single-crystal semiconductor substrate are attached to each other. | 2008-10-23 |
20080261380 | Semiconductor Layer Structure And Method Of Making The Same - A method of forming a semiconductor structure includes providing a substrate and providing a detach region which is carried by the substrate. A device structure which includes a stack of crystalline semiconductor layers is provided, wherein the detach region is positioned between the device structure and substrate. The stack is processed to form a vertically oriented semiconductor device. | 2008-10-23 |
20080261381 | Method for manufacturing bonded substrate - When manufacturing a bonded substrate using an insulator substrate as a handle wafer, there is provided a method for manufacturing a bonded substrate which can be readily removed after carried and after mounted by roughening a back surface of the bonded substrate (corresponding to a back surface of the insulator substrate) and additionally whose front surface can be easily identified like a process of a silicon semiconductor wafer in case of the bonded substrate using a transparent insulator substrate as a handle wafer. | 2008-10-23 |
20080261382 | WAFER DICING USING A FIBER MOPA - Silicon wafer dicing apparatus includes a master oscillator power amplifier (MOPA) arrangement wherein the master oscillator includes a continuous wave (CW) laser the output of which modulated by an external modulator to provide optical pulses to be amplified in the power amplifier. In one example of the apparatus the power amplifier includes at least one amplification stage including an optical fiber gain-medium. | 2008-10-23 |
20080261383 | SEMICONDUCTOR WORKPIECE CARRIERS AND METHODS FOR PROCESSING SEMICONDUCTOR WORKPIECES - Semiconductor workpiece carriers and methods for processing semiconductor workpieces are disclosed herein. In one embodiment, a semiconductor workpiece carrier assembly includes (a) a support structure having an opening sized to receive at least a portion of a semiconductor workpiece, and (b) a replaceable carrier positioned at the opening. The replaceable carrier includes a base and an adhesive layer on the base. The base has a surface, and the adhesive layer covers only a section of the surface of the base. The adhesive layer releasably attaches the replaceable carrier to the support structure. | 2008-10-23 |
20080261384 | METHOD OF REMOVING PHOTORESIST LAYER AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING THE SAME - A method of removing a photoresist layer is provided. An ion implantation process has been performed on the photoresist layer to transform a surface of the photoresist layer to a crust and a soft photoresist layer remains within the crust. The method includes performing a first removing step to remove the crust, such that the soft photoresist layer is exposed. Thereafter, a second removing step is performed to remove the soft photoresist layer. The first and the second removing steps are performed in difference chambers, and a temperature for performing the first removing step is lower than that for performing the second removing step and lower than a gasification temperature of a solvent in the soft photoresist layer. | 2008-10-23 |