43rd week of 2010 patent applcation highlights part 27 |
Patent application number | Title | Published |
20100271837 | VEHICULAR ILLUMINATION DEVICE - In a vehicular illumination device which illuminates a lower part around an opened part of a door at a side of a vehicle, a side sill garnish is provided below the door-opened part, and a lamp and a lamp garnish which retains the lamp are arranged on a lower face of the side sill garnish. As the lamp is retained by the lamp garnish, the lamp can efficiently and appropriately illuminate an underfoot floor when a person rides on and off the vehicle. Moreover, the lamp garnish has a recess, and an edge which is provided around an opened part of the recess. As the lamp is arranged in the recess, the lamp is not visually recognized directly from the exterior of edge parts, thereby preventing a following vehicle from falsely recognizing the lamp as a backup lamp. | 2010-10-28 |
20100271838 | Surface Light Source Device and Display - A surface light source device illuminating a displaying member of a display comprises stacked first and second light guide plates between which a low-refractive-index-layer is interposed. The light guide plates are disposed so that side end faces of light incidence sides of the light guide plates located oppositely to each other and an emission face of the first light guide plate is opposite to a back face of the second light guide plate across the low-refractive-index-layer interposed between the light guide plates. Each of light guide plates has an emission-restraint-region, an emission-gradual-increase-region and an emission-promotion-region which are formed as to be located in order away from an incidence side toward a distal end face. Although each of light source groups consists of at least two point-like-light-sources emitting light of different colors, light of various colors undergoes color mixing in each emission-restraint-region, thereby preventing emission from the emission face of the second light guide plate from showing color unevenness. | 2010-10-28 |
20100271839 | LIGHT GUIDE DISPLAY WITH MULITPLE LIGHT GUIDE LAYERS - A light guide display includes a printed overlay layer, a first light guide layer, and a second light guide layer. The printed overlay layer includes an input region with a symbol that is at least partially translucent. The first light guide layer is disposed on a back side of the printed overlay layer to illuminate the symbol of the printed overlay layer in response to illumination of the first light guide layer. The second light guide layer is disposed on a front side of the printed overlay layer, opposite the first light guide layer. The second light guide layer includes a separate symbol that is distinct from the symbol of the printed overlay layer. The second light guide layer illuminates the separate symbol of the second light guide layer in response to illumination of the second light guide layer. | 2010-10-28 |
20100271840 | OPTICAL SHEET, SURFACE LIGHT SOURCE AND DISPLAY DEVICE - An optical sheet is structured to have a translucent substrate | 2010-10-28 |
20100271841 | LED Lighting With Light Guide Plate Having Side Reflector - A light guide plate having a top surface through which light is emitted, a bottom surface opposite to the top surface and a side surface between the top and bottom surfaces, a bottom reflector on the bottom surface for reflecting light at the bottom surface back into the light guide plate, light emitting diodes at the side surface and a side reflector on the side surface for reflecting light at the side surface back into the light guide plate, wherein the side reflector on the side surface has an opening corresponding to at least one of the light emitting diodes | 2010-10-28 |
20100271842 | MULTI-COLOR ILLUMINATING BACK LIGHT STRUCTURE - In an embodiment, the invention provides a multi-color illuminating back light structure comprising a light guide, a reflector, at least one LED and a wavelength converter material. Micro-structures are formed on a first surface of the light guide. The reflector is attached to the first surface of the light guide. A wavelength converter material is deposited on a second surface of the light guide. At least one LED is optically coupled to at least one side of the light guide. A portion of light reflected from the micro-structures and the reflector is converted into light having at least one wavelength different from the wavelength of the reflected light. The light leaving the wavelength converter material comprises light with at least first and second wavelengths. | 2010-10-28 |
20100271843 | ILLUMINATION SYSTEM, LUMINAIRE AND BACKLIGHTING UNIT - The invention relates to an illumination system ( | 2010-10-28 |
20100271844 | LIGHT-GUIDING STRUCTURE WITH PHOSPHOR MATERIAL LAYERS - A light-guiding structure with phosphor material layers includes a light-guiding unit, a light-emitting unit and a phosphor unit. The light-emitting unit is disposed beside an outer lateral side of the light-guiding unit. The phosphor unit is connected with the light-guiding unit and is disposed between the light-guiding unit and the light-emitting unit. In addition, the phosphor unit is formed or pasted on the lateral side of the light-guiding unit, and the light-emitting unit has a PCB substrate and a plurality of light-emitting elements electrically disposed on the PCB substrate and facing the light-guiding unit. Hence, light beams generated by the light-emitting elements of the light-emitting unit pass through the phosphor unit to form another light beams, and the light beams are guided into the light-guiding unit. Finally, the light beams are projected out from a light-exiting face of the light-guiding unit. | 2010-10-28 |
20100271845 | SIDE LIGHT TYPE BACKLIGHT MODULE WITH BACK PLATE ASSEMBLY - A back plate assembly utilized in a side light type backlight module includes two cases each including a main plate, a side plate extending upwardly extending from an end of the main plate and a pressing plate inwardly extending from a free end of the side plate. An opposite end of the main plate of one of the cases has a first stepped portion extending inwardly from a top portion thereof, and an opposite end of the main plate of the other one of the cases has a second stepped portion extending inwardly from a bottom portion thereof. A plurality of bolts extend through the second and first stepped portions and secure the cases together. A space is defined between the first and second cases for receiving a light guiding plate and a reflection plate between the main plates and the light guiding plate. | 2010-10-28 |
20100271846 | STRUCTURE OF LAMP COMBINED WITH PICTURE FRAME AND ESSENCE - A structure of lamp is combined with a picture frame and a mass of essence. The structure includes a picture frame body that receives and holds therein a picture or photo and forms a lighting chamber that receives and holds the lamp. The lighting chamber has a wall portion in which ventilation holes are defined. The picture frame body also forms an essence compartment that receives and holds the mass of essence that gives off a scent smell. The lamp, when lit, generates heat that causes the mass of essence to give off the scent that spreads through the ventilation holes of the lighting chamber. Thus, besides receiving and holding a picture, the picture frame also provides the functions of nighttime lighting and scent spreading for improving air quality of the surroundings. | 2010-10-28 |
20100271847 | Field bendable line voltage track lighting system - A bendable line voltage track lighting system includes a track having a conductor subassembly and first and second bendable sheaths that engage the conductor subassembly. The conductor subassembly includes first and second insulators that receive first and second bus-bars, respectively, and a compression gasket for biasing the two insulators into engagement with guide grooves in the bendable sheaths. Power is fed to the track by power connectors that engage the bus-bars contained within the conductor subassembly. Light fixtures are powered by making electrical contact with the bus-bars of the conductor subassembly. | 2010-10-28 |
20100271848 | CIRCUIT CONFIGURATION FOR OPERATING A HOUSEHOLD APPLIANCE - A circuit for operating a household appliance, having a switching power supply for transforming a grid voltage of a supply grid to a direct current supply voltage, a controller for controlling processes of the household appliance that can be coupled to the switching power supply and supplied by the DC supply voltage, and a button by means of which the switching power supply can be coupled to the supply grid by closing an electrical switch. The switch has two mechanically stable states and can be transitioned from one mechanically stable state to the other by actuating the button and/or by an at least indirect energy input from the controller. | 2010-10-28 |
20100271849 | Flyback constant voltage converter having both a PWFM mode and a PWM mode - A flyback AC/DC switching converter has a constant voltage (CV) mode. The CV mode has sub-modes. In one sub-mode (“mid output power sub-mode”), the output voltage (VOUT) of the converter is regulated using both pulse width modulation and pulse frequency modulation. Both types of modulation are used simultaneously. In a second sub-mode (“low output power sub-mode”), VOUT is regulated using pulse width modulation, but the converter switching frequency is fixed at a first frequency. By setting the first frequency at a frequency above the frequency limit of human hearing, an undesirable audible transformer humming that might otherwise occur is avoided. In some embodiments, the converter has a third sub-mode (“high output power sub-mode”), in which pulse width modulation is used but the switching frequency is fixed at a second frequency. By proper setting of the second frequency, undesirable EMI radiation and other problems that might otherwise occur are avoided. | 2010-10-28 |
20100271850 | POWER TRANSISTOR CHIP WITH BUILT-IN ENHANCEMENT MODE METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR AND APPLICATION CIRCUIT THEREOF - A power transistor chip with built-in enhancement mode metal oxide semiconductor field effect transistor and application circuit thereof provides an enhancement mode metal oxide semiconductor field effect transistor in association with two series connected resistors to act as a start-up circuit for the AC/DC voltage converter. The start-up circuit can be shut off after the pulse width modulation circuit of the AC/DC voltage converter circuit works normally and still capable of offering a function of brown out detection for the pulse width modulation circuit as well. Besides, the enhancement mode metal oxide semiconductor field effect transistor is built in the power transistor chip without additional masks and processes during the power transistor chip being fabricated such that the entire manufacturing process is simplified substantively with the economical production cost. | 2010-10-28 |
20100271851 | SELF-BOOTSTRAPPING FIELD EFFECT DIODE STRUCTURES AND METHODS - A two terminal device which can be used for the rectification of the current. Internally it has a regenerative coupling between MOS gates of opposite type and probe regions. This regenerative coupling allows to achieve performance better than that of ideal diode. | 2010-10-28 |
20100271852 | Power conversion circuit - A power conversion circuit converting DC electric power into AC electric power and sending the AC power to an inductive load, includes a first switching device connected to the positive pole side of the DC power supply to exhibit a conductive state and an interrupted state of a current; a second switching device connected to the negative pole side of the DC power supply to exhibit a conductive state and an interrupted state of the current; a first inductor provided between the first switching device and the inductive load; a second inductor provided between the second switching device and the inductive load; and a clamping diode connected between a first connection point between the first switching device and the first inductor, and a second connection point between the second switching device and the second inductor. Thus, conduction is provided from the second connection point to the first connection point. | 2010-10-28 |
20100271853 | CONTROLLER OF POWER CONVERTER - A controller of a power converter including an inverter that includes plural semiconductor switching elements. The controller suppresses an error between a voltage command and an inverter output voltage and responds to a voltage command at a high speed. The controller includes a voltage command generator that generates a voltage command signal and a switching pattern calculator that calculates and outputs, based on the voltage command signal, a switching pattern of a synchronous PWM system in which an average value of an inverter output voltage matches the voltage command signal. | 2010-10-28 |
20100271854 | Ternary Content Addressable Memory Having Reduced Leakage Effects - A column of ternary content addressable memory (TCAM) cells includes a bit line pair that is twisted at a location at or near the center of the column. Data is written to (and read from) TCAM cells located above the twist location with a first bit line polarity. Data is written to (and read from) TCAM cells located below the twist location with a second bit line polarity, opposite the first bit line polarity. As a result, read leakage currents introduced by TCAM cells storing ‘Don't Care’ values are reduced. | 2010-10-28 |
20100271855 | MEMORY CELL ARRANGEMENTS - In an embodiment, a memory cell arrangement is provided. The memory cell arrangement may include a first memory cell and a second memory cell, a first source/drain line coupled to a first source/drain region of the first memory cell and a second source/drain line coupled to a second source/drain region of the first memory cell, and a third source/drain line coupled to a first source/drain region of the second memory cell and a fourth source/drain line coupled to a second source/drain region of the second memory cell, wherein the third source/drain line is disposed proximate to the second source/drain line, and wherein the third source/drain line is disposed in the same metallization level as the second source/drain line. | 2010-10-28 |
20100271856 | SEMICONDUCTOR MEMORY DEVICE HAVING HIERARCHICALLY-CONSTRUCTED I/O LINES - To provide main I/O lines(MIOX) arranged along an X direction; a plurality of I/O nodes(ND) arranged along the X direction; an amplifier circuit area(AMPA) including a plurality of amplifier circuits(AMP); a plurality of main I/O lines(MIOY) arranged along a Y direction, which respectively connect each of the main I/O lines(MIOX) and each of the corresponding I/O nodes(ND). Among the main I/O lines(MIOY) allocated to the amplifier circuits different from one another, that having a longer wire length is connected more closely to a center of the corresponding main I/O line(MIOX); and that having a shorter wire length is connected more closely to an end of the corresponding main I/O line(MIOX). Accordingly, the difference in wire length for each signal route becomes smaller, and also the wire length of the longest wire route is reduced. | 2010-10-28 |
20100271857 | TECHNIQUES FOR PROVIDING A DIRECT INJECTION SEMICONDUCTOR MEMORY DEVICE - Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for biasing a direct injection semiconductor memory device. The method may comprise applying a first voltage potential to a first N-doped region via a bit line and applying a second voltage potential to a second N-doped region via a source line. The method may also comprise applying a third voltage potential to a word line, wherein the word line is spaced apart from and capacitively coupled to a body region that is electrically floating and disposed between the first N-doped region and the second N-doped region. The method may further comprise applying a fourth voltage potential to a P-type substrate via a carrier injection line. | 2010-10-28 |
20100271858 | TECHNIQUES FOR PROVIDING A DIRECT INJECTION SEMICONDUCTOR MEMORY DEVICE HAVING GANGED CARRIER INJECTION LINES - Techniques for providing a direct injection semiconductor memory device having ganged carrier injection lines are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a first region coupled to a bit line and a second region coupled to a source line. The apparatus may also comprise a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The apparatus may further comprise a third region coupled to a constant voltage source via a carrier injection line configured to inject charges into the body region through the second region. | 2010-10-28 |
20100271859 | NONVOLATILE MEMORY ELEMENT, NONVOLATILE SEMICONDUCTOR MEMORY APPARATUS, AND READING METHOD AND WRITING METHOD THEREFOR - A nonvolatile memory element ( | 2010-10-28 |
20100271860 | DRIVING METHOD OF VARIABLE RESISTANCE ELEMENT, INITIALIZATION METHOD OF VARIABLE RESISTANCE ELEMENT, AND NONVOLATILE STORAGE DEVICE - A method of driving a variable resistance element includes: a writing step performed by applying a writing voltage pulse having a first polarity to a variable resistance layer to change a resistance state of the layer from high to low; and an erasing step performed by applying an erasing voltage pulse having a second polarity to the layer to change the state from low to high. Here, |Vw1|>|Vw2| where Vw1 represents a voltage value of the writing voltage pulse for first to N-th writing steps (N≧ | 2010-10-28 |
20100271861 | VARIABLE-RESISTANCE MEMORY DEVICE AND ITS OPERATION METHOD - A variable-resistance memory device includes: memory cells; first wires; a second wire; a drive/control section; and a sense amplifier. | 2010-10-28 |
20100271862 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes resistive memory devices in a three-dimensional structure. A block select circuit generates a block select signal for selecting a memory block. In response to the block select signal, local word line selection units connected to each memory block connect global word lines connected to a word line decoder and local word lines, and local bit line selection units connected to each memory block connect global bit lines connected to a sense amplifier and local bit lines. Each memory block includes local word lines which extend in a first direction and are stacked in a second direction perpendicular to the first direction on a second plane perpendicular to a first plane. Local bit lines extend in the second direction to cross local word lines. Memory cells are formed at cross-points where local word lines and local bit lines cross one another. | 2010-10-28 |
20100271863 | Memory Cells, Memory Cell Programming Methods, Memory Cell Reading Methods, Memory Cell Operating Methods, and Memory Devices - Embodiments disclosed include memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. In one embodiment, a memory cell includes a wordline, a first bitline, a second bitline, and a memory element. The memory element is electrically connected to the wordline and selectively electrically connected to the first bitline and the second bitline. The memory element stores information via a resistive state of the memory element. The memory cell is configured to convey the resistive state of the memory element via either a first current flowing from the first bitline through the memory element to the wordline or a second current flowing from the wordline through the memory element to the second bitline. | 2010-10-28 |
20100271864 | SEMICONDUCTOR DEVICE - A high-speed and low-voltage DRAM memory cell capable of operating at 1 V or less and an array peripheral circuit are provided. A DRAM cell is comprised of a memory cell transistor and planar capacitor which utilize a FD-SOI MOST structure. Since there is no junction leakage current, loss of stored charge is eliminated, and the low-voltage operation can be realized. Further, a gate and a well in a cross-coupled type sense amplifier using FD-SOI MOSTs are connected. By this means, a threshold value dynamically changes and high-speed sensing operation can be realized. | 2010-10-28 |
20100271865 | Semiconductor Memory and Program - A memory wherein the bit reliability of the memory cells can be dynamically varied depending on the application or the memory status, the operation stability is ensured, and thereby a low power consumption and a high reliability are realized. Either a mode (a 1-bit/1-cell mode) in which one bit is composed of one memory cell or a mode (a 1-bit/n-cell mode) in which | 2010-10-28 |
20100271866 | NONVOLATILE LATCH CIRCUIT - A nonvolatile latch circuit includes: first and second inverters cross-coupled to hold 1-bit data; first and second magnetoresistive elements each having first to third terminals; and a current supply circuitry configured to supply a magnetization reversal current for changing the magnetization states of the first and second maqnetoresistive elements in response to the 1-bit data. The power terminal of the first inverter is connected to the first terminal of the first magnetoresistive element and the power terminal of the second inverter is connected to the first terminal of the second magnetoresistive element. The current supply circuitry is configured to supply the magnetization reversal current to the second terminals of the first and second magnetoresistive elements. The third terminal of the first magnetoresistive element is electrically connected to the third terminal of the second magnetoresistive element. | 2010-10-28 |
20100271867 | Variable resistive memory device compensating bit line resistance - Provided is a variable resistance memory device. The variable resistance memory device may include first and second memory cells connected to different lengths of bit lines, respectively, and a select circuit, configured to select the first and second memory cells, which is connected to the first and second memory cells through word lines. The select circuit is configured to compensate for a difference of resistances in the different of the lengths of the bit lines. | 2010-10-28 |
20100271868 | Phase change memory devices and memory systems including the same - A phase change memory device includes a memory cell array having a plurality of phase change memory cells, a read bias generating circuit, a clamping circuit and a clamping control signal generating circuit (CCSGC). The read bias generating circuit provides a sensing node with a read bias for reading a resistance level of a selected phase change memory cell. The clamping circuit controls an amount of clamping current flowing into a bit line connected with the selected phase change memory cell. The CCSGC provides the clamping control signal to the clamping circuit and adjusts a level of the clamping control signal. | 2010-10-28 |
20100271869 | PHASE CHANGE MEMORY DEVICE HAVING DECENTRALIZED DRIVING UNITS - A phase change memory device includes a plurality of intersecting bit lines and word lines. A cell array including a plurality of unit phase change resistance cells is formed at intersections of the plurality of bit lines and the plurality of word lines. A plurality of sub word line driving units are configured to drive the word lines in response to a plurality of sub word line signals. A plurality of main word line driving units are configured to drive the sub word line driving units in response to a main word line signal. A precharge unit is configured to precharge the word lines. In the phase change memory device, the driving units are is decentralized. | 2010-10-28 |
20100271870 | MAGNETIC STACK HAVING ASSIST LAYER - A magnetic memory cell having a ferromagnetic free layer and a ferromagnetic pinned reference layer, each having an out-of-plane magnetic anisotropy and an out-of-plane magnetization orientation and switchable by spin torque. The cell includes a ferromagnetic assist layer proximate the free layer, the assist layer having a low magnetic anisotropy less than about 500 Oe. The assist layer may have in-plane or out-of-plane anisotropy. | 2010-10-28 |
20100271871 | METHODS FOR PROGRAMMING A MEMORY DEVICE AND MEMORY DEVICES USING INHIBIT VOLTAGES THAT ARE LESS THAN A SUPPLY VOLTAGE - Methods for programming a memory array and memory devices are disclosed. In one such method, inhibited bit lines are charged to an inhibit voltage that is less than a supply voltage. The word lines of memory cells to be programmed are biased at a programming preparation voltage that is less than a nominal programming preparation voltage as used in the conventional art. Programming pulses can be applied to selected word lines of the memory cells to be programmed when the uninhibited bit lines are at 0V. | 2010-10-28 |
20100271872 | ANALOG READ AND WRITE PATHS IN A SOLID STATE MEMORY DEVICE - A memory array in a memory device is coupled to an analog I/O data interface that enables analog voltage levels to be written to the memory array. The I/O interface comprises a plurality of analog data paths that each includes a capacitor for storing charge corresponding to a target voltage to which a selected memory cell, coupled to its respective data path, is to be programmed. A plurality of comparators can be included in the I/O interface, with each such comparator coupled to a respective bit line. Such a comparator can compare a threshold voltage of a selected memory cell to its target voltage and inhibits further programming when the threshold voltage equals or exceeds the target voltage. | 2010-10-28 |
20100271873 | 3-LEVEL NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DRIVING THE SAME - A page buffer for a non-volatile semiconductor memory device includes a switch configured to couple a first bitline coupled to a first memory cell to a second bitline coupled to a second memory cell, a first latch block coupled to the first bitline and configured to transfer a first latch data to the first memory cell, and a second latch block coupled to the second bitline and the first latch block, and configured to transfer a second latch data to the second memory cell. | 2010-10-28 |
20100271874 | READ DISTURB MITIGATION IN NON-VOLATILE MEMORY - Read disturb is reduced in non-volatile storage. In one aspect, when a read command is received from a host for reading a selected word line, a word line which is not selected for reading is randomly chosen and its storage elements are sensed to determine optimized read compare levels for reading the selected word line. Or, a refresh operation may be indicated for the entire block based on an error correction metric obtained in reading the storage elements of the chosen word line. This is useful especially when the selected word line is repeatedly selected for reading, exposing the other word lines to additional read disturb. In another aspect, when multiple data states are stored, one read compare level is obtained from sensing, e.g., from a threshold voltage distribution, and other read compare levels are derived from a formula. | 2010-10-28 |
20100271875 | Compensating for Variations in Memory Cell Programmed State Distributions - Method and apparatus for compensating for variations in memory cell programmed state distributions, such as but not limited to a non-volatile memory formed of NAND configured Flash memory cells. In accordance with various embodiments, a memory block is formed from a plurality of memory cells that are arranged into rows and columns within the memory block, each memory cell configured to have a programmed state. A selected row of the memory block is read by concurrently applying a stepped sequence of threshold voltages to each memory cell along the selected row while sequentially decoupling read current from groups of memory cells along the selected row as the programmed states of said groups of cells are successively determined. | 2010-10-28 |
20100271876 | SEMICONDUCTOR MEMORY DEVICE WITH MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE AND MEMORY SYSTEM - A semiconductor memory device includes first memory cell transistors, a memory block, and word lines. Each of the first memory cell transistors has a stacked gate including a charge accumulation layer and a control gate and is capable of holding M bits (M≠2 | 2010-10-28 |
20100271877 | METHOD, APPARATUS, AND SYSTEM FOR ERASING MEMORY - Methods, apparatus, and systems may operate to perform a pre-programming operation on a plurality of multiple level memory cells of a memory device. An example of applying such a pre-programming operation involves applying a series of voltage pulses to the plurality of multiple level memory cells, verifying a charge stored in the plurality of multiple level memory cells, and erasing the plurality of multiple level memory cells of the memory block based on a result from verifying the charge stored in the plurality of multiple level memory cells. | 2010-10-28 |
20100271878 | INJECTION METHOD WITH SCHOTTKY SOURCE/DRAIN - An injection method for non-volatile memory cells with a Schottky source and drain is described. Carrier injection efficiency is controlled by an interface characteristic of silicide and silicon. A Schottky barrier is modified by controlling an overlap of a gate and a source/drain and by controlling implantation, activation and/or gate processes. | 2010-10-28 |
20100271879 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit includes a memory cell array including a plurality of planes each including a plurality of memory cells, a power supply voltage generating circuit including a common voltage generating circuit which maintains a fixed voltage supply capability, and a plurality of voltage generating circuits which are disposed in accordance with a number of the plurality of planes, and a control circuit configured to control the power supply voltage generating circuit. | 2010-10-28 |
20100271880 | TECHNIQUES FOR CONTROLLING A DIRECT INJECTION SEMICONDUCTOR MEMORY DEVICE - Techniques for controlling a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for controlling a direct injection semiconductor memory device. The method may comprise applying a first voltage potential to a first region via a bit line and applying a second voltage potential to a second region of the memory device via a source line. The method may also comprise applying a control voltage potential to a body region of the memory device via a word line that is spaced apart and capacitively coupled to the body region, wherein the body region is electrically floating and disposed between the first region and the second region. The method may further comprise applying a third voltage potential to a third region of the memory device via a carrier injection line in order to bias at least one of the first region, the second region, the third region, and the body region to perform one or more operations. | 2010-10-28 |
20100271881 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device includes a memory cell array including a plurality of planes each including a plurality of memory cells, a power supply voltage generating circuit including a voltage generating circuit configured to generate a power supply voltage common to the plurality of planes, a select number detection circuit configured to detect a number of selected planes of the plurality of planes, and a resistance variable circuit configured to vary a wiring resistance between the plurality of planes and the voltage generating circuit in accordance with the number of selected planes, which is reported from the select number detection circuit, and a control circuit configured to control the power supply voltage generating circuit. | 2010-10-28 |
20100271882 | NONVOLATILE SEMICONDUCTOR MEMORY APPARATUS COMPRISING CHARGE ACCUMULATION LAYER AND CONTROL GATE - A nonvolatile semiconductor memory apparatus includes memory cell strings, first and second bit lines, a first buffer, a second buffer, and a controlling unit. The memory cell strings each include memory cells. The first and second bit lines connected to the memory cell strings. The first buffer connects to the first bit line and holds first data. The second buffer connects to the second bit line and holds second data. The controlling unit includes first and second latches and controls timing to output the first and second data according to an internal terminal, a second signal, and a third signal, and transfers a control signal synchronized with the timing of the first and second data to the external terminal. The controlling unit allows the first latch to hold the first and second data, and transfers the first data, and thereafter transfers the second data. | 2010-10-28 |
20100271883 | METHOD OF ERASING IN NON-VOLATILE MEMORY DEVICE - An erasing method in a nonvolatile memory device is disclosed. The method includes post-programming dummy memory cells; verifying whether threshold voltages of the dummy memory cells are greater than or equal to a first voltage; post-programming normal memory cells; and verifying whether threshold voltages of the normal memory cells are greater than or equal to a second voltage. The first voltage is different from the second voltage, and the post-programming of the dummy memory cells comprises: applying a program voltage to a plurality of dummy word lines coupled to the dummy memory cells to post-program the dummy memory cells; and applying a pass voltage to a plurality of normal word lines coupled to the normal memory cells so that the normal memory cells are not post-programmed. | 2010-10-28 |
20100271884 | COMMUNICATION DEVICE AND METHOD FOR ERASING DATA FROM A COMMUNICATION DEVICE - A communication device and method for erasing data include setting erasing parameters and initializing the erasing parameters, erasing data in a target data block of the flash memory once, and calculate a current erasing count of the erased block, setting a first bit of the erased block as “0”. The communication device and method further determines whether other bits except the first bit of the erased block are all “1”, determines whether the current erasing count is less than the max erasing time if any bit except the first bit of the erased block is not “1”, and prompts an output if the current erasing count equals to the max erasing time. | 2010-10-28 |
20100271885 | Reduced complexity array line drivers for 3D matrix arrays - A method of biasing a nonvolatile memory array. The nonvolatile memory array includes a first and second plurality of Y lines, a plurality of X lines, a first and second plurality of two terminal memory cells. Each first and second memory cell is coupled to one of the first or second plurality of Y lines and one of the plurality of X lines, respectively. Substantially all of the first plurality and second plurality of Y lines are driven to a Y line unselect voltage. At least one selected Y line of the first plurality of Y lines is driven to a Y line select voltage while floating remaining Y lines of the first plurality of Y lines and while driving substantially all of the second plurality of Y lines to the Y line unselect voltage. | 2010-10-28 |
20100271886 | Semiconductor memory device and latency signal generating method thereof - A latency signal generating method and a corresponding semiconductor memory device, among other things, are disclosed. Such a method includes: receiving a clock signal for the semiconductor memory device; receiving a mode characterization signal; providing the DQS; and adapting the duration of a preamble state of the DQS according to the mode characterization signal to promote conformance of a strobe state of the DQS with the clock signal. | 2010-10-28 |
20100271887 | SEMICONDUCTOR MEMORY DEVICE COMPRISING VARIABLE DELAY UNIT - A semiconductor memory device comprises a variable delay unit and a data trainer. The variable delay unit is configured to generate a write data signal by delaying a write data driving signal by different amounts of time depending on whether the semiconductor memory device is in a data training mode or a normal operating mode, and further configured to generate a read data driving signal by delaying a read data signal by different amounts of time in the data training mode and the normal operating mode. The data trainer is configured to be activated in the data training mode, and while activated, receive the write data signal, compare the write data signal with a predetermined write pattern, perform a data training mode operation, and output the read data signal with a predetermined read pattern. | 2010-10-28 |
20100271888 | System and Method for Delaying a Signal Communicated from a System to at Least One of a Plurality of Memory Circuits - A system and method are provided for delaying a signal communicated from a system to a plurality of memory circuits. Included is a component in communication with a plurality of memory circuits and a system. Such component is operable to receive a signal from the system and communicate the signal to at least one of the memory circuits after a delay. In other embodiments, the component is operable to receive a signal from at least one of the memory circuits and communicate the signal to the system after a delay. | 2010-10-28 |
20100271889 | DELAY LOCKED LOOP CIRCUIT AND METHOD - Delay locked loop circuits and methods are disclosed. In the embodiments, a delay locked loop may include a phase detector to detect a phase difference between a clock signal and a reference clock signal, and a charge pump that receives the detected phase difference. A low pass filter may filter an output from the charge pump. The delay locked loop may further include a delay line having a plurality of delay elements, the plurality of delay elements including a first selectable group and a second selectable group that is larger than the first selectable group. A first clock signal from the first group of delay elements may be provided to the phase detector to first synchronize the delay locked loop, and following the synchronization, a second clock signal from the second group may be employed to synchronize the delay locked loop. | 2010-10-28 |
20100271890 | DATA I/O CONTROL SIGNAL GENERATING CIRCUIT IN A SEMICONDUCTOR MEMORY APPARATUS - A circuit for generating a data I/O control signal used in a semiconductor memory apparatus comprises a delay block for generating a delay signal having a relatively short delay value and a delay signal having a relatively long delay values, and a selection block for selecting any one of the delay signals according to an operational mode. The selection block selects an output signal of the first delay unit in a high-speed operation mode and selects an output signal of the second delay unit in a low-speed operation mode. | 2010-10-28 |
20100271891 | Accessing Memory Cells in a Memory Circuit - Techniques for accessing a memory cell in a memory circuit include: receiving a request to access a selected memory cell in the memory circuit; determining whether the selected memory cell corresponds to a normal memory cell or a weak memory cell in the memory circuit; accessing the selected memory cell using a first set of control parameters when the selected memory cell corresponds to a normal memory cell, wherein the selected memory cell provides correct data under prescribed operating specifications when accessed using the first set of control parameters; and accessing the selected memory cell using a second set of control parameters when the selected memory cell corresponds to a weak memory cell, wherein the selected memory cell provides correct data under the prescribed operating specifications when accessed using the second set of control parameters and provides incorrect data under the prescribed operating specifications when accessed using the first set of control parameters. | 2010-10-28 |
20100271892 | PRECHARGE METHOD OF SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE USING THE SAME - A precharge method of a semiconductor memory device that controls a precharge start time of each bank during a bank precharge operation, and a semiconductor memory device using the method, are provided. The device may latch an active or write order of respective banks and differently control precharge start times of the respective banks according to the latched active or write order during a plural-bank precharge operation to allow a plurality of banks to start precharge operations at different times. | 2010-10-28 |
20100271893 | SEMICONDUCTOR MEMORY DEVICE AND DATA WRITE AND READ METHODS THEREOF - A semiconductor memory device having a first memory cell array block including a memory cell having a floating body, the memory cell coupled to a word line, a first bit line, and a first source line, a second memory cell array block including a reference memory cell having a floating body, the reference memory cell coupled to a reference word line, a second bit line, and a second source line, a first isolation gate portion configured to selectively transmit a signal between the first bit line and at least one of a sense bit line and an inverted sense bit line, a second isolation gate portion configured to selectively transmit a signal between the second bit line and at least one of the sense bit lines, and a sense amplifier configured to amplify voltages of the sense bit line and the inverted sense bit line to first and second sense amplifying voltage levels. | 2010-10-28 |
20100271894 | METHODS AND APPARATUS FOR EXTENDING THE EFFECTIVE THERMAL OPERATING RANGE OF A MEMORY - Apparatus and systems are provided for thermal regulation of a memory integrated circuit (“IC”). The apparatus and systems may include a thermal sensor on a memory IC, and a heating element coupled to the thermal sensor. The heating element is adapted to heat the memory IC in response to a signal from the thermal sensor. Other aspects are also provided. | 2010-10-28 |
20100271895 | SRAM compatible embedded DRAM system with hidden refresh and dual port capabilities - An SRAM compatible embedded DRAM system with hidden refresh and dual port capabilities includes a memory cell array comprised of a plurality of single-port memory cells with dual-port capability, a first and a second port access units connected to the memory cell array in order to access the memory cells, and an access arbiter connected to the first and the second port access units in order to arbitrate a first port access request, a second port access request and a hidden refresh request. | 2010-10-28 |
20100271896 | MEMORY MALFUNCTION PREDICTION SYSTEM AND METHOD - A memory malfunction prediction system and method, such as those that sequentially stress each row of memory cells in an array by decreasing the refresh rate of the row. Prior to doing so, the data stored in the row can be copied to a holding row, and a CRC value for the data can be generated and stored. After the test, the data stored in the row being tested can be read, and a CRC value for the data can then be generated. This after test CRC value can be compared to the stored pre-test CRC value. In the event of a match, the row can be considered to be functioning properly, and the next row can then be tested. If the CRC values do not match, a predicted malfunction of the row can be considered to exist, and corrective action can be taken, such as by repairing the row by substituting a redundant row of memory cells. | 2010-10-28 |
20100271897 | Anti-fuse memory cell and semiconductor memory device - An anti-fuse memory cell includes: a first transistor connected with a word line and configured to output a second voltage based on a first voltage supplied to the word line in a write mode; a second transistor connected with a bit line, and configured to output a third voltage supplied to the bit line when the second voltage is supplied to a gate of the second transistor in the write mode; and an anti-fuse element connected to a ground line, and having an insulator film. The insulator film is set to a conductive state with the third voltage supplied from the second transistor. | 2010-10-28 |
20100271898 | ACCESS TO MULTI-PORT DEVICES - Mechanisms for improving static noise margin and/or reducing misread current in multi-port devices are disclosed. In some embodiments related to dual port SRAM a suppress device (e.g., transistor) is provided at each word line port. When both ports are activated, both suppress devices are on and lower the voltage level of these ports, which in turn lower the voltage level at the node storing the data for the memory. As the voltage level at the data node is lowered, noise margin is improved and read disturb can be avoided. | 2010-10-28 |
20100271899 | DIGITAL FILTERS FOR SEMICONDUCTOR DEVICES - A memory device that, in certain embodiments, includes a memory element and a digital filter. The digital filter may include a counter and a divider, where the divider is configured to divide a count from the counter by a divisor. | 2010-10-28 |
20100271900 | MIXER COMPRISING MIXING TOOLS WHICH ARE DRIVEN BY THE ROTATION OF THE BOWL - The invention relates to a mixer comprising tools ( | 2010-10-28 |
20100271901 | KNEADING DEGREE ADJUSTING MECHANISM, EXTRUDER, CONTINUOUS MIXER, KNEADING DEGREE ADJUSTING METHOD, AND KNEADING METHOD - The degree of kneading of a material to be kneaded is to be capable of being adjusted with a high accuracy. | 2010-10-28 |
20100271902 | APPARATUS AND METHOD FOR PREMIXING LOST CIRCULATION MATERIAL - There is provided herein a system for premixing LCM with drilling mud for use in drilling. In the preferred embodiment, a hopper will contain apertures that release pressurized mud in such a way as to create a swirling vortex of drilling mud and LCM within a central hopper, with the drilling mud/LCM mixture preferably rotating between about 50 and 70 rpm. Adding the LCM to the hopper will mix it thoroughly with the drilling mud before it is introduced into a mud pit, thereby insuring that the final product will well-mixed and further improving the throughput of the overall process. | 2010-10-28 |
20100271903 | Extending the Coverage of VSP/CDP Imaging by Using First-Order Downgoing Multiples - First-order free-surface multiples recorded in VSP data or reverse VSP data are processed using VSP/CDP method to produce an image of the subsurface. This image produces a larger coverage than that obtained in 3-C 3-D processing of reflection data acquired in the VSP. | 2010-10-28 |
20100271904 | SEPARATING SEISMIC SIGNALS PRODUCED BY INTERFERING SEISMIC SOURCES - A technique includes obtaining seismic data acquired by seismic sensors of a composite seismic signal that is produced by the firings of multiple seismic sources. The technique includes modeling the seismic data as being a function of models for the sources and linear operators and defining desired constraints on the models. The technique includes simultaneously determining the models based on the modeling and the desired constraints. The datasets are generated based on the determined models. Each dataset is indicative of a component of the composite seismic signal and is attributable to a different one of the seismic sources. | 2010-10-28 |
20100271905 | WEAPON IDENTIFICATION USING ACOUSTIC SIGNATURES ACROSS VARYING CAPTURE CONDITIONS - A computer implemented method for automatically detecting and classifying acoustic signatures across a set of recording conditions is disclosed. A first acoustic signature is received. The first acoustic signature is projected into a space of a minimal set of exemplars of acoustic signature types derived from a larger set of exemplars using a wrapper method. At least one vector distance is calculated between the projected acoustic signature and each exemplar of the minimal set of exemplars. An exemplar is selected from the minimal set of exemplars having the smallest vector distance to the projected acoustic signature as a class corresponding to and classifying the first acoustic signature. The first acoustic signature and the plurality of acoustic signatures may correspond to one of gunshots, musical instruments, songs, and speech. The minimal set of exemplars may correspond to a hierarchy of acoustic signature types. | 2010-10-28 |
20100271906 | DIGITAL TRANSCRIPTION SYSTEM UTILIZING ACCOUSTICAL DETECTORS HAVING APERTURES WITH A VERTICAL ORIENTATION RELATIVE TO THE WORK SURFACE - A pen transcription system and method for using the same are disclosed. The pen transcription system includes a receiver having first and second acoustical sensors mounted on a planar base and separated from one another, an EM detector, and a controller. The first and second acoustical sensors detect an acoustical signal emitted by a moveable signal source. The EM detector detects an EM signal that is synchronized with the acoustical signal. The controller measures the difference in time of detection between the EM signal and the acoustical signals detected by the first and second acoustical sensors. The acoustical sensors include a detector and a housing surrounding the detector, the housing having an aperture defined by an axis. The acoustical sensor has a reception function that is symmetrical about the axis and the axis is substantially perpendicular to the base surface. | 2010-10-28 |
20100271907 | Electroacoustic Underwater Antenna - In the case of an electroacoustic underwater antenna, which has a reflector ( | 2010-10-28 |
20100271908 | Tectonic discharger - The structure for severe earthquakes prevention includes :
| 2010-10-28 |
20100271909 | Perfect Egg Timer - A timing device for the cooking of eggs, comprising timing means, apt to compute a temperature, signaling means, actuatable by the timing means to signal that the time interval has elapsed, and temperature sensitive means, apt to be arranged in proximity of the eggs and to determine the starting of computing of the time interval by the timing means at a pre-determined temperature. | 2010-10-28 |
20100271910 | METHOD AND APPARATUS FOR NEAR FIELD PHOTOPATTERNING AND IMPROVED OPTICAL COUPLING EFFICIENCY - This invention relates to near field assemblies with improved optical coupling efficiency suitable for near field photolithography and heat assisted magnetic recording with fluid bearing structures. Masters for photolithography are fabricated using a fluid bearing suspended at a near field distance using hydrostatic bearings. Near field features fabricated on a fluidized slider emit a radiated laser to develop a photo-resist layer deposited on the master replicator. A plurality of near field assemblies is etched on a wafer. Each of the near field assemblies includes a planar solid immersion mirror, at least one grating, and a near field transducer. The features created during the etching step are used to guide at least one milling tool to machine at least one surface on one or more of the planar solid immersion mirror, the at least one grating, and the near field transducer. The features created during the machining step are used to guide at least one polishing tool to polish at least one surface on one or more of the planar solid immersion mirror, the at least one grating, and the near field transducer. The wafer is cut to create a plurality of discrete near field assemblies. | 2010-10-28 |
20100271911 | TRACKING CONTROL DEVICE, TRACKING CONTROL METHOD, AND OPTICAL DISC DEVICE - An object of this invention is to improve stability of tracking control and improve recording and reproduction performance. The tracking control device comprises a main push-pull signal generation section, which generates a main push-pull signal based on a signal obtained by photoelectric conversion of return light of the main beam; a microcomputer, which detects an other-layer stray light signal component included in a signal obtained by photoelectric conversion of return light of the sub-beam; a signal correction section, which corrects the signal obtained by photoelectric conversion of the return light of the sub-beam, based on the other-layer stray light signal component; and a sub-push-pull signal generation section, which generates a sub-push-pull signal based on the corrected signal obtained by photoelectric conversion of the return light of the sub-beam. | 2010-10-28 |
20100271912 | 3D ACTUATOR FOR OTPICAL DISC SYSTEM - An optical pick-up actuator ( | 2010-10-28 |
20100271913 | INFORMATION PROCESSOR, OPTICAL DISC FAILURE ANALYSIS METHOD, AND COMPUTER PRODUCT - According to one embodiment, an information processor includes an optical disc drive, an acquiring module, a storage module, and a determination module. The acquiring module acquires identification information that uniquely identifies an optical disc loaded in the optical disc drive based on information read from the optical disc. The storage module obtains information related to failure analysis of the optical disc contained in state information indicating reading state or writing state upon reading from or writing to the optical disc, and stores the information related to failure analysis in association with the identification information. The determination module calculates values each indicating a level of failure of the optical disc based on pieces of information related to failure analysis of the optical disc stored until just recently in association with the identification information and, when the values satisfy a predetermined condition, determines that there is a risk of failure in the optical disc. | 2010-10-28 |
20100271914 | DRIVE APPARATUS - The present invention relates to a drive apparatus ( | 2010-10-28 |
20100271915 | SYSTEM AND METHOD FOR GENERATING OUTPUT SIGNALS INDICATING SPECIFIC AREAS ON AN OPTICAL DISC UTILIZING A PROTECTION MEANS - A system for generating an output signal indicating a specific area on an optical disc is disclosed. The system includes: a detecting circuit, a header signal generator, a protection circuit, a counter and an output signal generator. The detecting circuit detects pre-recorded address information on the optical disc to generate a detection signal. The header signal generator detects headers on the optical disc to generate a header signal. The protection circuit computes a first counter value and reloads the first counter value according to the detection signal and the header signal, wherein the protection circuit does not reload the first counter value twice successively due to the header signal. The counter computes a second counter value and reloads the second counter value according to the first counter value. The output signal generator generates the output signal according to the first counter value. | 2010-10-28 |
20100271916 | Optical Disc Apparatus - An optical-disc apparatus comprising: a laser-light source; an objective lens; an aberration-correction lens to be moved in an optical-axis direction according to a cover-layer thickness of an optical disc; a stepping motor; a driving unit to generate a driving pulse for the motor; a storage unit to store current-position information of the aberration-correction lens based on the number of the pulse; and a control unit to control the driving unit so that the aberration-correction lens is moved between a first position set in a mechanical-movable range of the aberration-correction lens and a second position set on the objective-lens side relative to the first position, the driving unit being controlled so that the aberration-correction lens is moved to the second position when stop of disc rotation occurs, and is moved to a start position between the first-and-second positions according to the thickness based on the information when the stop is cancelled. | 2010-10-28 |
20100271917 | TEST-WRITE METHOD, INFORMATION RECORDING METHOD, AND INFORMATION RECORDING APPARATUS - A test-write method for accurately and quickly determining recording conditions, and an apparatus suitable therefor. In a 2T-based strategy, recording pulse conditions are determined by separately test-writing an even-number length mark and an odd-number length mark, and then the relative positions of the even-number length mark and the odd-number length mark at the recording pulse start time are adjusted. | 2010-10-28 |
20100271918 | METHOD FOR DETERMINING TYPE OF DISK AND APPARATUS THEREOF - A method for determining a type of a disk and an optical storage apparatus thereof are provided. The method includes when the disk placed in the optical storage device is not a blank disk, determining whether the phases between a first signal and a second signal of the disk are the same or not; and determining that the disk is a low to high (LTH) data disk or a high to low data disk (HTL) data disk upon whether the phases of the first signal and the second signal are the same or not. Therefore, the reading parameters are correspondingly loaded in the optical storage device according to the type of the disk. | 2010-10-28 |
20100271919 | INFORMATION PROCESSOR, FAILURE PREDICTION METHOD, AND COMPUTER PRODUCT - According to one embodiment, an information processor includes an optical disc drive, a recorder, and a determination module. The optical disc drive includes a loading mechanism that loads and ejects an optical disc. The recorder obtains state information indicating the operating state of the loading mechanism to record the state information. The determination module determines that, when a value related to failure prediction of the loading mechanism satisfies a predetermined condition, there is a risk of failure in the loading mechanism. The value is calculated from a combination of a plurality of indices contained in the state information. | 2010-10-28 |
20100271920 | RECORDING APPARATUS - A recording apparatus having a reproduction means to play digital data from a recording medium recorded with that digital data and retrieval information, a recording means to write the digital data reproduced by the reproduction means and record the retrieval information on a control table, and a control circuit to search the control table by using the retrieval information when the digital data from the reproduction means is written by the recording means, to permit the writing of digital data recorded on the medium with the recording means when the retrieval information is not recorded on the control table, and to prohibit the writing of digital data recorded on the medium with the recording means when the retrieval information is already recorded on the control table, and also prevent the mistaken duplicate copying of the digital data with the recording means. | 2010-10-28 |
20100271921 | OPTICAL INFORMATION RECORDING MEDIUM, OPTICAL INFORMATION RECORDING/REPRODUCING DEVICE AND OPTICAL INFORMATION RECORDING/REPRODUCING METHOD - A holographic recording medium in which information can be reproduced by phase conjugate beam without requiring a mirror for obtaining the phase conjugate beam and its driving part and recording density is not reduced. The recording medium includes a recording layer in which an interference pattern is recorded and a light absorption/transmission layer which can be reversibly changed to be in a first state where signal beam and reference beam passed through the recording layer are absorbed at the time of recording of information and a second state where the reference beam is transmitted at the time of reproduction of information, and the reference beam transmitted through the light absorption/transmission layer is reflected by a reflection layer to produce the phase conjugate beam. | 2010-10-28 |
20100271922 | HOLOGRAM RECORDING DEVICE - A hologram recording device that records a hologram by passing recording light and reference light through the same objective lens and irradiating a recording medium, includes: a light splitter for dividing light from a light source into the recording light and the reference light; a light combining member for combining the recording light and the reference light, which have been divided by the light splitter, so as to be coaxial, and causing these light beams to advance to the objective lens; first and second lenses, positioned on an optical paths of the recording light and reference light, between the light splitter and the light combining member; a first aperture that narrows the recording light which has passed through the first lens; and, a second aperture that narrows the reference light which has passed through the second lens, the first and second lenses being configured to have different optical magnifications. | 2010-10-28 |
20100271923 | Optical pickup - An optical-pickup hologram element has six regions on an x-y plane, divided as follows: the first region with a first line (an x-axis) and a second line that connects points (−xa, 0) and (−xb, yb); the second region with the first and second lines and a third line connecting points (xa, 0) and (xb, yb); the third region with the first and third lines; the fourth region with the first line and a fourth line connecting the point (xa, 0) and a point (xb, −yb); the fifth region with the first and fourth lines and a fifth line connecting the point (−xa, 0) and a point (−xb, −yb); and the sixth region with the first and fifth lines (xa2010-10-28 | |
20100271924 | OPTICAL APPARATUS - An optical apparatus according to the present invention comprises an optical base having a bonding surface, and an optical component fixedly bonded to the bonding surface with an adhesive. The optical base has an open hole formed in the bonding surface. The open hole is filled with the adhesive. The optical component contacts the open hole so that a part of the open hole is left unclosed. | 2010-10-28 |
20100271925 | OPTICAL HEAD, OPTICAL ELEMENT WITH DIFFRACTION GRATING, OPTICAL DISC DEVICE AND INFORMATION PROCESSING DEVICE - An optical head ( | 2010-10-28 |
20100271926 | OPTICAL PICKUP DEVICE AND OPTICAL DISC DEVICE - An optical pickup device imparts different astigmatisms from each other to light fluxes in four light flux areas formed around an optical axis of laser light, out of the laser light reflected on a disc. The optical pickup device also changes the propagating directions of the light fluxes in the light flux areas to separate the light fluxes in the light flux areas each other. A signal light area where only signal light exists is defined on a detection surface of a photodetector. Eight sensing portions are arranged at a position corresponding to the signal light area. According to this arrangement, only the signal light is received by the sensing portions to thereby suppress deterioration of a detection signal resulting from stray light. Further, a push-pull signal, whose DC component is suppressed, is obtained by computing an output from the eight sensing portions by a predetermined formula. | 2010-10-28 |
20100271927 | OPTICAL PICKUP, OPTICAL DISC APPARATUS, OPTICAL PICKUP MANUFACTURING METHOD, AND OPTICAL PICKUP CONTROL METHOD - An optical pickup includes: first and second objective lenses focusing light beams of different wavelengths on first and second optical discs having different thickness protection layers; a coma aberration generating unit generating coma aberration in the light beams; a collimating lens between a light source and the first objective lens; and a collimating lens driving unit. The protection layer thickness of the plastic first optical disc is smaller than that of the second optical disc. The first objective lens satisfies a lens tilt coma aberration sensitivity of 0 to 0.3[λrms/°]. An optical axis of the light beam approximately coincides with an optical axis of the first objective lens. The optical pickup is inclined to the optical disc so that initial coma aberration with respect to the first optical disc is optimally corrected. The coma aberration generating unit is used for obtaining optimal reproducing environment when reproducing the second optical disc. | 2010-10-28 |
20100271928 | ULTRASHORT PULSE LIGHT SOURCE AND TWO-PHOTON ABSORPTION RECORDING MEDIUM RECORDING APPARATUS HAVING THE SAME - Providing a soliton mode-locked solid-state laser that includes a resonator, a first end of which is formed of a semiconductor saturable absorption mirror, a solid-state laser medium, a negative group velocity dispersion compensator for compensating for group velocity dispersion within the resonator, and an excitation optical system that outputs excitation light for exciting the solid-state laser medium, and oscillates soliton pulse laser light with a repetition frequency of not less than 1 GHz, an intensity modulator that includes a waveguide electrooptic modulator for modulating intensity of the soliton pulse laser light and a driver for applying a voltage to the waveguide electrooptic modulator according to desired information, and a nonlinear optical element for converting the intensity-modulated soliton pulse laser light to a second harmonic wave. | 2010-10-28 |
20100271929 | CONSTELLATION RE-ARRANGEMENT AND BIT GROUPING - Methods and systems for subpacket generation using a convolutional turbo code in hybrid automatic repeat request re-transmissions that includes separating a codeword into subblocks of bits, interleaving the subblocks, and performing a permutation to group the bit streams and rearrange a symbol constellation such that bits are assigned to bit positions based on a number of re-transmissions. | 2010-10-28 |
20100271930 | SCATTERED PILOT PATTERN AND CHANNEL ESTIMATION METHOD FOR MIMO-OFDM SYSTEMS - Methods and apparatus are provided for inserting data symbols and pilot symbols in an OFDM (orthogonal frequency division multiplexing) transmission resource utilizing frequency hopping patterns for the data symbols and/or the pilot symbols. Data symbols and pilot symbols are allocated for down link (base station to mobile station) and up link (mobile station to bases station) transmission resources in a two-dimensional time-frequency pattern. For each antenna of a MIMO-OFDM (multiple input multiple output OFDM) communication system, pilot symbols are inserted in a scattered pattern in time-frequency and data symbols are inserted in an identical frequency-hopping pattern in time-frequency as that of other antennas. | 2010-10-28 |
20100271931 | CHANNEL STATE INFORMATION RECONSTRUCTION FROM SPARSE DATA - Accurate downlink channel estimates are calculated based on infrequently transmitted Channel State Information (CSI) feedback data from a UE | 2010-10-28 |
20100271932 | APPARATUS AND METHOD FOR COMPENSATING FOR PHASE ERROR IN WIRELESS COMMUNICATION SYSTEM - An apparatus and method for compensating for a phase error in a wireless communication system are provided. The apparatus includes a reception modem, a transmission modem, a Common Phase Error (CPE) compensator, a first channel estimator, a phase compensator, and a second channel estimator. The reception modem demodulates and decodes a signal received. The transmission modem encodes and modulates a signal for transmission. The CPE compensator compensates for phase errors of at least two symbols constituting a signal. The first channel estimator estimates channels for respective bursts. The phase compensator compares phases for the channels for the respective bursts with each other and compensates for a phase difference between at least two bursts. The second channel estimator estimates an interference channel. | 2010-10-28 |
20100271933 | METHOD, SYSTEM, AND APPARATUS FOR NETWORK DEVICE TO ACCESS PACKET SWITCHED NETWORK - A method for a network device to access a packet switched network is applied to a system in which the network device accesses the packet switched network by connecting to PEs in an active-standby mode. The method includes: an active PE and a standby PE each sends a fault detection message to the network device through an interface connected to the network device; the active PE sets the state of the interface to “up” and advertises a route to a remote PE if a fault detection response returned by the network device is received through the interface within a preset period; otherwise, the active PE sets the state of the interface to “down”, and withdraws the advertised route; and the standby PE sets the state of the interface to “up” and advertises another route to the remote PE after receiving a fault detection response through the interface connected to the network device. | 2010-10-28 |
20100271934 | METHOD AND APPARATUS TO ENABLE A HYBRID SYNCHRONOUS/ASYNCHRONOUS ROUTING PROTOCOL - A hybrid routing protocol may be provided. A disruption tolerant mechanism may be provided for analyzing a network, detecting a disruption between nodes of the network, and activating a disruption tolerance mechanism in response to the network disruption. The disruption tolerance mechanism may comprise designating a non-disrupted network node as a cache node and routing traffic addressed to the disrupted node to the cache node for storage. Once the disrupted network node recovers from the disruption, the cache node may deliver the stored traffic to the disrupted network node. | 2010-10-28 |
20100271935 | PROTECTING AN ETHERNET NETWORK HAVING A RING ARCHITECTURE - Delivering multicast data traffic over a communication network includes a first network node delivering multicast data traffic to second network nodes. The first and second network nodes are connected by a transmission network in a ring architecture and implement a point-to-multipoint layer 2 protocol. A method includes at the first network node: collecting alarms signals indicative of a failure along the whole ring and of the second network nodes. Based on a current state of the alarm signals, delivering the multicast data traffic either in a first delivery direction along the ring, or in a second delivery direction along the ring opposite to the first delivery direction, or in both the first and second delivery directions. At each of the second network nodes: collecting alarm signals indicative of a failure of the transmission network locally to the second network node and of the second network node. Based on a current state of the local alarm signals either receiving the multicast data traffic delivered by the first network node from the first direction, forwarding the multicast data traffic in the first direction and transmitting local data traffic to the first network node along the second delivery direction, or receiving the data traffic delivered by the first network node from the second direction, forwarding the multicast data traffic in the second direction and transmitting the local data traffic to the first network node along the first delivery direction. | 2010-10-28 |
20100271936 | Pre-Computing Alternate Forwarding State in a Routed Ethernet Mesh Network - A set of critical nodes or links is identified on the network and alternate forwarding state is pre-computed and disseminated within a node such that, upon failure of one of the critical nodes/links, a minimal trigger will cause the alternate forwarding state to be used to forward traffic on the routed Ethernet mesh network. In one embodiment rather than storing full tables of alternate forwarding state, only the changes to the forwarding state required by an identified failure is stored by the network nodes. Upon occurrence of a failure on the network, the identified failure is used to select the alternate forwarding state. | 2010-10-28 |