43rd week of 2010 patent applcation highlights part 58 |
Patent application number | Title | Published |
20100274944 | SERIAL INTERFACE COMMUNICATION TEST APPARATUS AND TEST METHOD USING THE SAME - A test apparatus for testing quality of serial interface communication between two CPUs of a dual-mode handset includes a processor module and a switch module. The processor module includes two serial ports, each serial port includes an output connector and an input connector, and the two input connectors respectively connected to the two CPUs. The output connector of either serial port connected to either CPU via the switch module. The processor module controls the CPU connected to the output connector to work when the switch module is switched on, and checks data transmission between the two CPUs via the two input connectors when the switch module is switched off. | 2010-10-28 |
20100274945 | AUTOMATIC SELF-ADDRESSING METHOD FOR WIRED NETWORK NODES - A method and system for addressing nodes in a multi-drop wired network are disclosed. In an embodiment nodes communicate via a two-way communication bus. Upon receipt of an address command, a first node assigns itself a first address, closes a switch to activate an output port of the first node to enable a second node to receive communications from the first node, and sends a second address onto the two-way communication bus. The second address is received by all previously addressed nodes, including a controller if used, as well as the second node, which is as yet unaddressed. Upon receipt of the second address, the second node repeats the process. If a node does not receive an acknowledgement that a subsequent node has addressed itself, that node deactivates its output port and terminates the network. | 2010-10-28 |
20100274946 | INTEGRATED CIRCUIT AND INFORMATION PROCESSING DEVICE - In an LSI system using an on-chip bus, when a transfer on the bus is delayed due to a fully loaded buffer in a destination module, a source module cannot proceed to the next processing. Such an unwanted situation is eliminated by plural transferring buffers which are provided in an on-chip bus on the LSI for temporarily storing transfer data. With the transferring buffers, even if a buffer within a slave module, specified as the destination, is fully loaded and cannot accept any more transfer, a bus master can transfer data to a transferring buffer provided on the on-chip bus. Thus, the bus master is not kept waiting for execution of a transfer, irrespective of the state of the buffer within the slave. With the provision of plural transferring buffers, input/output operations can be performed in parallel. | 2010-10-28 |
20100274947 | MEMORY MANAGEMENT METHOD, MEMORY MANAGEMENT PROGRAM, AND MEMORY MANAGEMENT DEVICE - In a virtual machine system built from a plurality of virtual machines, the utilization efficiency of utilized physical memory is raised. A memory management method in which a virtual machine environment, constituted by having one or several virtual machines and a hypervisor part for operating the same virtual machines, is built on a physical machine and in which: a virtual machine operates an allocation processing part and an application part, application part making a physical memory processing part allocate unallocated physical memory to a memory area and allocation processing part transmitting, when unallocated physical memory is scarce, an instruction for the release, from memory areas utilized by each application part, of memory pages for which physical memory is assigned but not used. | 2010-10-28 |
20100274948 | COPY-PROTECTED SOFTWARE CARTRIDGE - A cartridge preferably for use with a game console. The cartridge comprises a ROM, a non-volatile memory, a processor and a dispatcher. An application running on the console may communicate with the dispatcher using predefined addresses, which enables the dispatcher to access the ROM, the non-volatile memory, or the processor, as the case may be. The invention improves on the prior art copy protection as no generic copy method may be found if the addresses are changed from one cartridge to another. In addition, to copy the software, the processor must be emulated. | 2010-10-28 |
20100274949 | DATA ACCESS METHOD FOR FLASH MEMORY AND STORAGE SYSTEM AND CONTROLLER USING THE SAME - A data access method for accessing a flash memory storage system, a storage system and a controller using the same are provided. A flash memory has a plurality of physical blocks, which are grouped into a system area, a data area, and a spare area. One or more variable tables are established to record transient information of each set of mother-child blocks of the data area and the spare area. The number of the variable table could be adjusted adaptively according to time required for writing the variable table into the system area, such that an overall data access efficiency of the flash memory storage system is enhanced. | 2010-10-28 |
20100274950 | MEMORY SYSTEM - A controller executes first processing for writing a plurality of data in a sector unit in the first storing area; second processing for flushing the data stored in the first storing area to the first input buffer in a first management unit twice or larger natural number times as large as the sector unit; third processing for flushing the data stored in the first storing area to the second input buffer in a second management unit twice or larger natural number times as large as the first management unit; fourth processing for relocating a logical block in which all pages are written in the first input buffer to the second storing area; fifth processing for relocating a logical block in which all pages are written in the second input buffer to the third storing area; and sixth processing for flushing a plurality of data stored in the second storing area to the second input buffer in the second management unit. | 2010-10-28 |
20100274951 | ELECTRONIC STORAGE DEVICE WITH IMPROVED STORAGE METHOD - An electronic storage device includes a first memory segment having at least one source block to store information, a second memory segment having at least one backup block corresponding to the source block to make a backup of the information in a LSB memory page of the source block and a control unit connecting with said first memory segment and second memory segment. The control unit reads/writes the first memory segment and second memory segment through two different signal channels respectively. The information can be simultaneously written into the first and second memory segment to get a backup of the information so that the information can be stored safely. The control unit recycles the backup block of the second memory segment not only after the source block of the first memory segment entirely finishes writing the information but also after the source block is erased up in order to release the storage space of the backup block. | 2010-10-28 |
20100274952 | CONTROLLER, DATA STORAGE DEVICE AND DATA STORAGE SYSTEM HAVING THE CONTROLLER, AND DATA PROCESSING METHOD - A controller, a data storage device and a data storage system including the controller, and a data processing method are provided. The controller may process a plurality of instructions in parallel by including a plurality of address translation central processing units (CPUs) in a multi-channel parallel array structure, thereby improving the performance of a semiconductor memory system. | 2010-10-28 |
20100274953 | DATA STORAGE DEVICE AND INFORMATION PROCESSING SYSTEM INCORPORATING DATA STORAGE DEVICE - A data storage device comprises a plurality of memory devices and a memory controller. The memory controller exchanges data with the memory devices via a plurality of channels. The memory controller decodes an external command to generate a driving power mode and accesses the memory devices according to the driving power mode. | 2010-10-28 |
20100274954 | PROGRAM UPDATE SYSTEM AND ELECTRONIC DEVICE WITH PROGRAM UPDATE FUNCTION - A manufacturing cost of an integrated circuit chip used in a program update system or in an electronic device with program update function is reduced. A first integrated circuit chip has a USB interface circuit, a compression decoder, a CPU and a mask ROM. The first integrated circuit chip is a single chip consolidating a microcomputer with a USB host function and the compression decoder. A second integrated circuit chip has a CPU and an FROM, and serves as a system microcomputer to control the whole system of a car audio. A control program stored in the mask ROM is updated using the FROM incorporated in the second integrated circuit chip. | 2010-10-28 |
20100274955 | Flash Memory Storage System and Method - A flash memory storage system includes a memory array containing a plurality of memory cells and a controller for controlling the flash memory array. The controller dedicates a first group of memory cells to operate with a first number of bits per cell and a second, separate group of memory cells to operate with a second number of bits per cell. A mechanism is provided to apply wear leveling techniques separately to the two groups of cells to evenly wear out the memory cells. | 2010-10-28 |
20100274956 | SYSTEMS AND APPARATUS FOR MAIN MEMORY - A computing system is disclosed that includes a memory controller in a processor socket normally reserved for a processor. A plurality of non-volatile memory modules may be plugged into memory sockets normally reserved for DRAM memory modules. The non-volatile memory modules may be accessed using a data communication protocol to access the non-volatile memory modules. The memory controller controls read and write accesses to the non-volatile memory modules. The memory sockets are coupled to the processor socket by printed circuit board traces. The data communication protocol to access the non-volatile memory modules is communicated over the printed circuit board traces and through the sockets normally used to access DRAM type memory modules. | 2010-10-28 |
20100274957 | SYSTEM AND APPARATUS WITH A MEMORY CONTROLLER CONFIGURED TO CONTROL ACCESS TO RANDOMLY ACCESSIBLE NON-VOLATILE MEMORY - An apparatus includes a printed circuit board with a plurality of printed circuit board traces, a memory controller mounted on the printed circuit board coupled to one or more of the plurality of printed circuit board traces, a plurality of non-volatile type of memory integrated circuits coupled to the printed circuit board, and a plurality of support integrated circuits coupled between the memory controller and the plurality of non-volatile type of memory integrated circuits. | 2010-10-28 |
20100274958 | METHODS OF ASSEMBLY OF A COMPUTER SYSTEM WITH RANDOMLY ACCESSIBLE NON-VOLATILE MEMORY - An apparatus includes a printed circuit board with a plurality of printed circuit board traces, a memory controller mounted on the printed circuit board coupled to one or more of the plurality of printed circuit board traces, a plurality of non-volatile type of memory integrated circuits coupled to the printed circuit board, and a plurality of support integrated circuits coupled between the memory controller and the plurality of non-volatile type of memory integrated circuits. | 2010-10-28 |
20100274959 | METHODS FOR MAIN MEMORY WITH NON-VOLATILE TYPE MEMORY MODULES - A computing system is disclosed that includes a memory controller in a processor socket normally reserved for a processor. A plurality of non-volatile memory modules may be plugged into memory sockets normally reserved for DRAM memory modules. The non-volatile memory modules may be accessed using a data communication protocol to access the non-volatile memory modules. The memory controller controls read and write accesses to the non-volatile memory modules. The memory sockets are coupled to the processor socket by printed circuit board traces. The data communication protocol to access the non-volatile memory modules is communicated over the printed circuit board traces and through the sockets normally used to access DRAM type memory modules. | 2010-10-28 |
20100274960 | MEMORY CONTROL METHOD OF MEMORY DEVICE AND MEMORY CONTROL SYSTEM THEREOF - One exemplary memory control method of a memory device includes: determining at least a physical row partition including a plurality of physical rows selected from the memory device; and for each physical row partition, mapping interleaved virtual rows to the selected physical rows. Each physical row partition is a portion of the memory device. Bank addresses of adjacent virtual rows are different. Another exemplary memory control method of a memory device includes: assigning an indicator to each physical row partition in the memory device for indicating if the corresponding physical row partition is to be refreshed; and controlling a partial refresh operation of the memory device according to the indicator of each physical row partition. Each physical row partition is a portion of the memory device. | 2010-10-28 |
20100274961 | PHYSICALLY-INDEXED LOGICAL MAP TABLE - Techniques and systems are described herein to maintain a mapping of logical to physical registers—for example, in the context of a multithreaded processor that supports renaming. A mapping unit may have a plurality of entries, each of which stores rename information for a dedicated one of a set of physical registers available to the processor for renaming. This physically-indexed mapping unit may support multiple threads, and may comprise a content-addressable memory (CAM) in certain embodiments. The mapping unit may support various combinations of read operations (to determine if a logical register is mapped to a physical register), write operations (to create or modify one or more entries containing mapping information), thread flush operations, and commit operations. More than one of such operations may be performed substantially simultaneously in certain embodiments. | 2010-10-28 |
20100274962 | METHOD AND APPARATUS FOR IMPLEMENTING A CACHING POLICY FOR NON-VOLATILE MEMORY - The present disclosure relates to methods, devices and computer-readable medium for implementing a caching policy and/or a cache flushing policy in a peripheral non-volatile storage device operatively coupled to a host device. In some embodiments, data is stored to a cache area of a non-volatile memory within the peripheral non-volatile storage device in accordance with a historical rate at which other data was received by the peripheral storage device from the host device and/or a historical average time interval between successive host write requests received and/or an assessed rate at which data is required to be written to the non-volatile memory and/or a detecting by the peripheral non-volatile memory device that the host has read the storage ready/busy flag. In some embodiments, data is copied from a cache storage area of the non-volatile memory to a main storage area in accordance with the historical rate and/or the historical average time interval. | 2010-10-28 |
20100274963 | STORAGE SYSTEM AND OPERATION METHOD OF STORAGE SYSTEM - The present invention is able to improve the processing performance of a storage system by respectively virtualizing the external volumes and enabling the shared use of such external volumes by a plurality of available virtualization storage devices. By virtualizing and incorporating the external volume of an external storage device, a first virtualization storage device is able to provide the volume to a host as though it is an internal volume. When the load of the first virtualization storage device increases, a second virtualization storage device | 2010-10-28 |
20100274964 | STORAGE SYSTEM FOR CONTROLLING DISK CACHE - A storage system coupled to a host computer, including: a non-volatile medium that stores data; a disk cache that temporarily stores data stored in the non-volatile medium, where the disk cache is divided into a plurality of independent disk cache partitions; a control unit that controls an input and an output of data to and from the non-volatile medium; and a memory unit that stores information used by the control unit, including consistency control information setting respective commands permitted for each of the disk cache partitions, to guarantee consistency of the data; wherein the control unit is configured to determine whether or not to execute a requested command for a given disk cache partition, by referring to the consistency control information setting respective commands permitted for each of the disk cache partitions. | 2010-10-28 |
20100274965 | REDUNDANT SOLID STATE DISK SYSTEM VIA INTERCONNECT CARDS - A first interconnect card is configured, wherein a first controller is included in the first interconnect card. A second interconnect card coupled to the first interconnect card is configured, wherein a second controller is included in the second interconnect card. In response to a failure of the first controller included in the first interconnect card, the first interconnect card is controlled via the second controller included in the second interconnect card. In response to a failure of the second controller included in the second interconnect card, the second interconnect card is controlled via the first controller included in the first interconnect card. | 2010-10-28 |
20100274966 | HIGH AVAILABILTY LARGE SCALE IT SYSTEMS WITH SELF RECOVERY FUNCTIONS - Storage Systems in the IT system provide information of the status of its components to the System Monitoring Server. System Monitoring Server calculates storage availability of storage systems based on information using failure rates of the components, and determines whether the volumes of the storage system should be migrated based on a predetermined policy. If migration is required, System Monitoring Server selects the target storage system based on storage availability of storage systems, and requests migration to be performed. | 2010-10-28 |
20100274967 | MANAGING STORAGE ARRAY OPERATIONS THAT CAUSE LOSS OF ACCESS TO MIRRORED DATA - Storage array operations, such as code downloads and other operations of the type that cause loss of access to portions of the storage array, are managed in a manner that preserves access to other portions of the storage array so that other storage array operations, such as data synchronization, can continue. | 2010-10-28 |
20100274968 | Performing data operations using non-volatile third dimension memory - Performing data operations using non-volatile third dimension memory is described, including a storage system having a non-volatile third dimension memory array configured to store data, the data including an address indicating a file location on a disk drive, and a controller configured to process an access request associated with the disk drive, the access request being routed to the non-volatile third dimension memory array to perform a data operation, wherein data from the data operation is used to create a map of the disk drive. In some examples, an address in the non-volatile third dimension memory array provides an alias for another address in a disk drive. | 2010-10-28 |
20100274969 | ACTIVE-ACTIVE SUPPORT OF VIRTUAL STORAGE MANAGEMENT IN A STORAGE AREA NETWORK ("SAN") - Methods and apparatuses are provided for active-active support of virtual storage management in a storage area network (“SAN”). When a storage manager (that manages virtual storage volumes) of the SAN receives data to be written to a virtual storage volume from a computer server, the storage manager determines whether the writing request may result in updating a mapping of the virtual storage volume to a storage system. When the writing request does not involve updating the mapping, which happens most of the time, the storage manager simply writes the data to the storage system based on the existing mapping. Otherwise, the storage manager sends an updating request to another storage manager for updating a mapping of the virtual storage volume to a storage volume. Subsequently, the storage manager writes the data to the corresponding storage system based on the mapping that has been updated by the another storage manager. | 2010-10-28 |
20100274970 | Robust Domain Name Resolution - A recursive DNS nameserver system and related domain name resolution techniques are disclosed. The DNS nameservers utilize a local cache having previously retrieved domain name resolution to avoid recursive resolution processes and the attendant DNS requests. If a matching record is found with a valid (not expired) TTL field, the nameserver returns the cached domain name information to the client. If the TTL for the record in the cache has expired and the nameserver is unable to resolve the domain name information using DNS requests to authoritative servers, the recursive DNS nameserver returns to the cache and accesses the resource record having an expired TTL. The nameserver generates a DNS response to the client device that includes the domain name information from the cached resource record. In various embodiments, subscriber information is utilized to resolve the requested domain name information in accordance with user-defined preferences. | 2010-10-28 |
20100274971 | Multi-Core Processor Cache Coherence For Reduced Off-Chip Traffic - Technologies are generally described herein for maintaining cache coherency within a multi-core processor. A first cache entry to be evicted from a first cache may be identified. The first cache entry may include a block of data and a first tag indicating an owned state. An owner eviction message for the first cache entry may be broadcasted from the first cache. A second cache entry in a second cache may be identified. The second cache entry may include the block of data and a second tag indicating a shared state. The broadcasted owner eviction message may be detected with the second cache. An ownership acceptance message for the second cache entry may be broadcasted from the second cache. The broadcasted ownership acceptance message may be detected with the first cache. The second tag in the second cache entry may be transformed from the shared state to the owned state. | 2010-10-28 |
20100274972 | SYSTEMS, METHODS, AND APPARATUSES FOR PARALLEL COMPUTING - Systems, methods, and apparatuses for parallel computing are described. In some embodiments, a processor is described that includes a front end and back end. The front includes an instruction cache to store instructions of a strand. The back end includes a scheduler, register file, and execution resources to execution the strand's instructions. | 2010-10-28 |
20100274973 | DATA REORGANIZATION IN NON-UNIFORM CACHE ACCESS CACHES - Embodiments that dynamically reorganize data of cache lines in non-uniform cache access (NUCA) caches are contemplated. Various embodiments comprise a computing device, having one or more processors coupled with one or more NUCA cache elements. The NUCA cache elements may comprise one or more banks of cache memory, wherein ways of the cache are horizontally distributed across multiple banks. To improve access latency of the data by the processors, the computing devices may dynamically propagate cache lines into banks closer to the processors using the cache lines. To accomplish such dynamic reorganization, embodiments may maintain “direction” bits for cache lines. The direction bits may indicate to which processor the data should be moved. Further, embodiments may use the direction bits to make cache line movement decisions. | 2010-10-28 |
20100274974 | SYSTEM AND METHOD FOR REPLACING DATA IN A CACHE - A system and method for replacing data in a cache utilizes cache block validity information, which contains information that indicates that data in a cache block is no longer needed for processing, to maintain least recently used information of cache blocks in a cache set of the cache, identifies the least recently used cache block of the cache set using the least recently used information of the cache blocks in the cache set, and replaces data in the least recently used cache block of the cache set with data from main memory. | 2010-10-28 |
20100274975 | Forming Multiprocessor Systems Using Dual Processors - In one embodiment, link logic of a multi-chip processor (MCP) formed using multiple processors may interface with a first point-to-point (PtP) link coupled between the MCP and an off-package agent and another PtP link coupled between first and second processors of the MCP, where the on-package PtP link operates at a greater bandwidth than the first PtP link. Other embodiments are described and claimed. | 2010-10-28 |
20100274976 | Method of operating data storage device and device thereof - The method of operating the data storage device includes performing channel distribution non-sequentially based on a logical address included in a data signal and outputting a channel address, and at least one of writing data to and reading stored data from a memory connected to one of a plurality of channels based on the channel address. | 2010-10-28 |
20100274977 | Data Accessing Method And Apparatus For Performing The Same - The present invention discloses a data accessing method and an apparatus for performing the method. Through a newly-defined host logical unit (HLUN), a unique HLUN number is given to each LUN-to-LD/Partition mapping relationship, and the HLUN is present to external hosts. Therefore, all of the hosts in the same storage system may recognize different logical units (i.e., HLUN). Hence, when processing an Input/Output (IO) request issued from any one host, a storage virtualization controller (SVC) can correctly find the corresponding LD/Partition for accessing data without identifying the identity of the host. | 2010-10-28 |
20100274978 | IMAGING APPARATUS - By connecting to or mounting a first storage medium that stores image data as a retrieval object (e.g. first memory card | 2010-10-28 |
20100274979 | STORAGE CONTROLLERS WITH DYNAMIC WWN STORAGE MODULES AND METHODS FOR MANAGING DATA AND CONNECTIONS BETWEEN A HOST AND A STORAGE DEVICE - A method and system for transferring data between a host and a Serial Attached Small Computer Interface (“SAS”) device using a storage controller is provided. The storage controller includes, a World Wide Name (“WWN”) module that includes a table having plural entries, wherein each row includes a WWN address, an initiator tag value field, an input/output counter value that tracks plural commands for a connection. A WWN index value represents the address of a row having plural entries. The method includes, comparing frame elements of incoming frames, including a unique WWN address with the WWN module entries; and if there is a match, updating a counter value for a connection between the storage controller and a device sending frames. The counter value is increased when a command frame is received and decreased when a command is executed and a response is sent to the device. | 2010-10-28 |
20100274980 | TECHNIQUES FOR SYSTEM RECOVERY USING CHANGE TRACKING - Techniques for system recovery using change tracking are disclosed. In one particular exemplary embodiment, the techniques may be realized as a computer implemented method for providing system recovery using change tracking comprising receiving a request to write to electronic storage, identifying a region in the electronic storage region associated with the write request, setting a region indicator identifying the electronic storage region as dirty, and setting one or more portion indicators identifying one or more dirty portions of the electronic storage region. | 2010-10-28 |
20100274981 | METHOD AND SYSTEM FOR MIGRATION BETWEEN PHYSICAL AND VIRTUAL SYSTEMS - A method of migrating a computer system between a virtualized environment and a non-virtualized environment comprises configuring one or more storage volumes for a migration destination in a destination environment based on a migration request containing a backup requirement specifying one or more copy groups, each copy group including storage volumes that store data for at least one of a virtualized device and a non-virtualized device; converting and migrating data from a migration source in a source environment to the one or more configured storage volumes of the migration destination based on copy group information of the one or more copy groups, one of the source environment and the destination environment being a virtualized environment, and another of the source environment and the destination environment being a non-virtualized environment; and migrating backup unit/group information by replacing copy group information in the source environment with copy group information in the destination environment. | 2010-10-28 |
20100274982 | HYBRID DISTRIBUTED AND CLOUD BACKUP ARCHITECTURE - The claimed subject matter provides a system and/or a method that facilitates integration of a distributed backup environment and a online backup environment. A super peer device can be designated from a set of peer devices. The super peer can distribute backup data amongst the set of peer devices based upon availability and storage capacity of the peer devices. In addition, the super peer can transfer portions of backup data from the set of peers to an online backup service. | 2010-10-28 |
20100274983 | INTELLIGENT TIERS OF BACKUP DATA - The claimed subject matter relates to systems and/or methodologies that facilitate intelligent distribution of backup information across storage locations in network-based backup architectures. A virtual layering of backup information across storage locations in the backup architecture can be implemented. Statistical models are utilized to dynamically re-allocate backup information among storage locations and/or layers to ensure availability of data, minimum latency upon restore, and minimum bandwidth utilization upon restore. In addition, heuristics or machine learning techniques can be applied to proactively detect failures or other changes in storage locations such that backup information can be reallocated accordingly prior to a failure. | 2010-10-28 |
20100274984 | MANAGEMENT SERVER DEVICE FOR MANAGING VIRTUAL STORAGE DEVICE, AND METHOD FOR MANAGING VIRTUAL STORAGE DEVICE - The computer system has a plurality of physical server devices, a plurality of physical storage devices, and a management server device, and when migrating at least one of a plurality of first virtual server devices to another physical server device, the management server device compares at least one physical server device in which the plurality of first virtual server devices are disposed after the migration, with at least one physical server device in which a plurality of second virtual server devices are disposed, to calculate a first evaluation value, and also compares at least one physical server device in which the plurality of first virtual server devices are disposed after the migration, with at least one physical server device in which a plurality of third virtual server devices are disposed, to calculate a second evaluation value. Based on the first evaluation value and the second evaluation value, the management server device issues an instruction to migrate the first virtual storage device to the other physical storage device. | 2010-10-28 |
20100274985 | METHOD AND APPARATUS FOR BACKUP AND RECOVERY USING STORAGE BASED JOURNALING - A storage system maintains a journal of journal entries and at lease one snapshot of one or more data volumes. By assigning a unique sequence number to journal and snapshot, it is easy to find a journal which can be applied to the snapshot. A technique is described for detecting an overflow condition of running out of journal space and recovering the journal space. | 2010-10-28 |
20100274986 | CONTROL APPARATUS AND CONTROL METHOD THEREFOR - When a controller receives a new command from a main controller during overwrite-deletion processing for a specific storage apparatus, the received command is stored at least until completion of the overwrite-deletion processing when the received command is a command to the specific storage apparatus. Alternatively, progression of overwrite-deletion process is stored and priority processing of the received command is executed. On the other hand, when the received command is not a command to the specific storage apparatus, processing for the command is executed. | 2010-10-28 |
20100274987 | MAINTAINING VALIDITY OF CACHED ADDRESS MAPPINGS - A method is provided for creating and maintaining the validity of a cache group including one or more cache elements. Each of the cache elements corresponds to a different address space in a virtual memory of a computer system. Each of the cache elements include one or more caches that store mappings from virtual addresses to data or values that are functions of or dependent upon physical addresses that correspond to the virtual addresses. When there is an address space switch from a first address space to a second address space, the cache group is searched to find the cache element corresponding to the second address space, and that found cache element is made the current cache element for virtual memory access through the cache element. Changes in the page tables are also detected and reflected in the caches of the cache group to maintain the caches up-to-date. | 2010-10-28 |
20100274988 | Flexible vector modes of operation for SIMD processor - In addition to the usual modes of SIMD processor operation, where corresponding elements of two source vector registers are used as input pairs to be operated upon by the execution unit, or where one element of a source vector register is broadcast for use across the elements of another source vector register, the new system provides several other modes of operation for the elements of one or two source vector registers. Improving upon the time-costly moving of elements for an operation such as DCT, the present invention defines a more general set of modes of vector operations. In one embodiment, these new modes of operation use a third vector register to define how each element of one or both source vector registers are mapped, in order to pair these mapped elements as inputs to a vector execution unit. Furthermore, the decision to write an individual vector element result to a destination vector register, for each individual element produced by the vector execution unit, may be selectively disabled, enabled, or made to depend upon a selectable condition flag or a mask bit. | 2010-10-28 |
20100274989 | ACCELERATING TRACEBACK ON A SIGNAL PROCESSOR - A method executed by an instruction set on a processor is described. The method includes providing a tbbit instruction, inputting a first index for the tbbit instruction, loading a second value for the tbbit instruction, wherein the second value comprises at least 2 | 2010-10-28 |
20100274990 | Apparatus and Method for Performing SIMD Multiply-Accumulate Operations - An apparatus and method for performing SIMD multiply-accumulate operations includes SIMD data processing circuitry responsive to control signals to perform data processing operations in parallel on multiple data elements. Instruction decoder circuitry is coupled to the SIMD data processing circuitry and is responsive to program instructions to generate the required control signals. The instruction decoder circuitry is responsive to a single instruction (referred to herein as a repeating multiply-accumulate instruction) having as input operands a first vector of input data elements, a second vector of coefficient data elements, and a scalar value indicative of a plurality of iterations required, to generate control signals to control the SIMD processing circuitry. In response to those control signals, the SIMD data processing circuitry performs the plurality of iterations of a multiply-accumulate process, each iteration involving performance of N multiply-accumulate operations in parallel in order to produce N multiply-accumulate data elements. For each iteration, the SIMD data processing circuitry determines N input data elements from said first vector and a single coefficient data element from the second vector to be multiplied with each of the N input data elements. The N multiply-accumulate data elements produced in a final iteration of the multiply-accumulate process are then used to produce N multiply-accumulate results. This mechanism provides a particularly energy efficient mechanism for performing SIMD multiply-accumulate operations, as for example are required for FIR filter processes. | 2010-10-28 |
20100274991 | RISC PROCESSOR DEVICE AND METHOD OF SIMULATING FLOATING-POINT STACK OPERATION THEREOF - An RISC processor device and a method of emulating a floating-point stack operation thereof The processor device comprises: a floating-point register file containing a plurality of floating-point registers; a decoding section for decoding operation instructions of the RISC processor; a floating-point operation section connected to the decoding section; a control register for controlling the status of the floating-point registers and controlling the decoding section and the floating-point operation section to emulate a floating-point register stack using the floating-point register file. The decoding section includes a pointer register for maintaining a stack operation pointer and storing the value of the stack operation pointer; the floating-point operation section includes a pointer operation module for operating the pointer register, emulating the stack operation of the stack pointer of the pointer register, modifying and monitoring the phase of the stack pointer during emulating a floating-point register stack operation. | 2010-10-28 |
20100274992 | APPARATUS AND METHOD FOR HANDLING DEPENDENCY CONDITIONS - Techniques for handling dependency conditions, including evil twin conditions, are disclosed herein. An instruction may designate a source register comprising two portions. The source register may be a double-precision register and its two portions may be single-precision portions, each specified as destinations by two other single-precision instructions. Execution of these two single-precision instructions, especially on a register renaming machine, may result in the appropriate values for the two portions of the source register being stored in different physical locations, which can complicate execution of an instruction stream. In response to detecting a potential dependency, one or more instructions may be inserted in an instruction stream to enable the appropriate values to be stored within one physical double precision register, eliminating an actual or potential evil twin dependency. Embodiments including a compiler that inserts instructions in a generated instruction stream to eliminate dependency conditions are also contemplated. | 2010-10-28 |
20100274993 | LOGICAL MAP TABLE FOR DETECTING DEPENDENCY CONDITIONS - Techniques and structures are described which allow the detection of certain dependency conditions, including evil twin conditions, during the execution of computer instructions. Information used to detect dependencies may be stored in a logical map table, which may include a content-addressable memory. The logical map table may maintain a logical register to physical register mapping, including entries dedicated to physical registers available as rename registers. In one embodiment, each entry in the logical map table includes a first value usable to indicate whether only a portion of the physical register is valid and whether the physical register includes the most recent update to the logical register being renamed. Use of this first value may allow precise detection of dependency conditions, including evil twin conditions, upon an instruction reading from at least two portions of a logical register having an entry in the logical map table whose first value is set. | 2010-10-28 |
20100274994 | PROCESSOR OPERATING MODE FOR MITIGATING DEPENDENCY CONDITIONS - Various techniques for mitigating dependencies between groups of instructions are disclosed. In one embodiment, such dependencies include “evil twin” conditions, in which a first floating-point instruction has as a destination a first portion of a logical floating-point register (e.g., a single-precision write), and in which a second, subsequent floating-point instruction has as a source the first portion and a second portion of the same logical floating-point register (e.g., a double-precision read). The disclosed techniques may be applicable in a multithreaded processor implementing register renaming. In one embodiment, a processor may enter an operating mode in which detection of evil twin “producers” (e.g., single-precision writes) causes the instruction sequence to be modified to break potential dependencies. Modification of the instruction sequence may continue until one or more exit criteria are reached (e.g., committing a predetermined number of single-precision writes). This operating mode may be employed on a per-thread basis. | 2010-10-28 |
20100274995 | PROCESSOR AND METHOD OF CONTROLLING INSTRUCTION ISSUE IN PROCESSOR - One exemplary embodiment includes a processor including a plurality of execution units and an instruction unit. The instruction unit discriminates whether an instruction is a target instruction for which determination about availability of parallel issue based on dependency among instructions is to be made with respect to each instruction contained in an instruction stream. When a first instruction contained in the instruction stream is the target instruction, the instruction unit adjusts the number of instructions to be issued in parallel to the plurality of execution units based on a detection result of dependency among the first instruction and at least one subsequent instruction. Further, when the first instruction is not the target instruction, the instruction unit issues a group of a predetermined fixed number of instructions including the first instruction in parallel to the plurality of execution units unconditionally regardless of a detection result of dependency among the instruction group. | 2010-10-28 |
20100274996 | MICRO-PROCESSOR - A micro-processor includes a clock generator configured to generate a fetch clock, a decoding clock, an execution clock, and a write-back clock that are sequentially enabled; a volatile memory device configured to output pre-stored program data in response to the fetch clock; a command decoder configured to decode the program data in response to the decoding clock and generate a decoding command; an arithmetic device configured to perform an arithmetic operation according to the command of the decoding command in response to the execution clock; and a peripheral circuit device configured to be operated according to the command of the decoding command in response to the write-back clock. | 2010-10-28 |
20100274997 | Executing a Gather Operation on a Parallel Computer - Methods, apparatus, and computer program products are disclosed for executing a gather operation on a parallel computer according to embodiments of the present invention. Embodiments include configuring, by the logical root, a result buffer or the logical root, the result buffer having positions, each position corresponding to a ranked node in the operational group and for storing contribution data gathered from that ranked node. Embodiments also include repeatedly for each position in the result buffer: determining, by each compute node of an operational group, whether the current position in the result buffer corresponds with the rank of the compute node, if the current position in the result buffer corresponds with the rank of the compute node, contributing, by that compute node, the compute node's contribution data, if the current position in the result buffer does not correspond with the rank of the compute node, contributing, by that compute node, a value of zero for the contribution data, and storing, by the logical root in the current position in the result buffer, results of a bitwise OR operation of all the contribution data by all compute nodes of the operational group for the current position, the results received through the global combining network. | 2010-10-28 |
20100274998 | METHOD AND SYSTEM FOR PROVIDING A DATA MODULE LOCK TO DEVICE HARDWARE - Systems and methods for confirming that a circuit card is compatible with a computer in which it is installed includes accessing a list of compatible circuit cards stored in the computer's nonvolatile memory, determining if the circuit card is included in the list of compatible circuit cards; and storing operating software on the circuit card only if the circuit card is included in the list of compatible circuit cards. The list of compatible circuit cards can be the Plug-and-Play Identification (PnP ID) list stored in the computer's BIOS data. Power may be removed from the circuit card if the circuit card is not include in the list of compatible circuit cards. | 2010-10-28 |
20100274999 | CONTROL SYSTEM AND METHOD FOR MEMORY - A control system for a number of memories includes a processor, a control chip, and an expansion chip. The processor is connected to a basic input and output system and the control chip. The control chip is also connected to a number of first memory cards and the expansion chip. The expansion chip is also connected to a number of second memory cards. | 2010-10-28 |
20100275000 | COMPUTER MOTHERBOARD WITH BASIC INPUT OUTPUT SYSTEM CAPABLE OF BUILT-IN CONFIGURATION DISPLAY - The present invention is a computer motherboard with a Basic Input Output System (BIOS) capable of built-in configuration display, characterized in that the BIOS includes a first means and a second means. The first and second means are code internally provided in the BIOS and executable by a CPU of the computer motherboard in an execution environment preset by the BIOS. The first means enables acquisition of CPU configuration data stored on the CPU and configuration data for displaying the CPU. The second means enables acquisition of memory module configuration data stored on at least a memory module and configuration data for displaying the memory module. After the computer motherboard enters a BIOS setup utility, a user selects an option of execution of the first or second means to execute CPU and memory configuration display without using an operating system. | 2010-10-28 |
20100275001 | INFORMATION PROCESSOR - According to one embodiment, an information processor, includes: a storage module which stores a plurality of charging modes associated with a plurality of external devices to be charged when an operating system is not in operation; an input module which receives a charging mode selection request; and a test module which receives the charging mode in the received selection request from the storage module, and tests the charging mode on at least one of the external devices connected to the information processor. | 2010-10-28 |
20100275002 | IMAGING APPARATUS AND START-UP METHOD OF IMAGING APPARATUS - An imaging apparatus includes: an imaging processing unit configured to image a subject and output imaging data; a temporary storage medium configured to temporarily store the imaging data output from the imaging processing unit; an imaging control unit configured to control the imaging processing unit; a storage control unit configured to store, in a storage medium detachably mounted to a device main unit, the imaging data temporarily stored in the temporary storage medium; and a request unit configured to request the device main unit for execution of start-up processing; wherein, upon the start-up processing being requested from the request unit, start-up processing of the imaging control unit and the storage control unit are executed in parallel. | 2010-10-28 |
20100275003 | SYSTEM AND METHOD FOR EXPRESS EXECUTION OF INTERNET SERVICE ACCESSING - A method for express execution of internet service accessing with a touch-control interface for a computer system is provided. A computer system is installed with a first operating system in a data storage therein. The method includes the following steps: the computer system executing the BIOS of the computer system; before loading and executing the first operating system, the computer system detecting and activating a touch-control display device; the touch-control display device displaying executive item icons representing internet service accessing programs; detecting the executive item icon selection by the user; based on the selection, loading and executing the first operating system; and executing the internet service accessing program corresponding to the selected executive item icon. | 2010-10-28 |
20100275004 | SYSTEM AND METHOD FOR EXPRESS EXECUTION OF NAVIGATION FUNCTION - A method for express execution of navigation function is provided. A computer system is installed with a first operating system in a data storage device therein. The method includes the following steps: the computer system executing the BIOS of the computer system; before loading and executing the first operating system, the computer system detecting and activating a touch-control display device; the touch-control display device displaying an executive item icon representing the navigation function; detecting the executive item icon selection by the user; based on the selection, loading and executing the first operating system; and executing the navigation function corresponding to the selected executive item icon. | 2010-10-28 |
20100275005 | Secure Data Storage System And Method - A system and method for the secure storage of data in a network. Data stored on a primary server connected to the network is initially encrypted. The IP address of the primary server is sent to a second server, via the network, and a communication is received from the second server indicating pending instructions. If the instructions indicate that theft of the primary server has occurred, then the data stored on the primary server is re-encrypted and the IP address of the primary server is sent to the second server. if attempted unauthorized access of the primary server is determined, and a predetermined number of consecutive unauthorized attempts to access the primary server are made, then the data stored on the primary server is erased. | 2010-10-28 |
20100275006 | RECEIVER AND RECEIVING METHOD - By deciding procedures for downloading content data and downloading key information, a safe service is provided for a content distributor and a method which can start playback before completion of the downloading of the content data is provided, thereby providing a technique easy for a user. A receiver has: an interface unit being adapted to download encoded content data and key information for decoding the content data from a communication line; a storage unit being adapted to store the downloaded content data and key information from the interface unit; and a control unit which decodes the content data outputted from the storage unit using the key information. The control unit downloads the key information after the content data is downloaded entirely. | 2010-10-28 |
20100275007 | Secure Transmission System and Method - A method is provided for transmitting information from a user to a first network entity over a communications network. The user enters information into a browser executed at a user terminal. The browser generates a first message comprising the information using a first communication protocol for despatch over the network via a network port, the first message including an identifier of the first network entity. A client executed at the user terminal receives the first message before the first message reaches the network port. The first message is wrapped in a second message of a second communication protocol used for transmitting messages between the client and a second network entity. The second message is transmitted to the second network entity over the communications network. The first message is unwrapped from the second message at the second network entity, the identifier of the first network entity translated to a network address of the first network entity and the first message is transmitted to the first network entity over the communications network. | 2010-10-28 |
20100275008 | METHOD AND APPARATUS FOR SECURE PACKET TRANSMISSION - A source endpoint includes a security association database; a processing device and an interface operatively coupled to: receive a first packet requiring security processing; retrieve from the first packet a destination endpoint data address for a destination endpoint that is to receive the first packet; determine an address translation; apply the address translation to the retrieved destination endpoint data address to generate a destination endpoint security address, and create an entry in a storage device, wherein the entry corresponds only to the destination endpoint and comprises the generated destination endpoint security address and a set of security parameters. The source endpoint further indexes the storage device to obtain the security parameters for security processing of the first packet to generate a secured first packet; and sends the secured first packet to the destination endpoint. | 2010-10-28 |
20100275009 | METHOD FOR THE UNIQUE AUTHENTICATION OF A USER BY SERVICE PROVIDERS - The invention relates to a method for unique authentication of a user (U) by at least one service provider (SP), said method including a preliminary identity federation stage of federating an identity (user@sp) of said user for said service provider and an identity (user@idp) of the user (U) for an identity provider (IdP). According to the invention, said preliminary identity federation stage includes the steps of: the user (U) generating a user alias ([alias]) for that service provider (SP) and sending said identity provider (IdP) a masked alias ([alias] | 2010-10-28 |
20100275010 | Method of Authentication of Users in Data Processing Systems - A method of authentication of users in a data processing system is provided. The method includes a “Challenge” univocally associated with a user to be authenticated; processing the “Challenge” to generate an expected answer code, to be compared with an answer code that the user has to provide for authentication; encoding the generated “Challenge” for obtaining an image displayable through a display device; sending the image containing the “Challenge” to the user; displaying the image containing the “Challenge”; through a user device provided with an image-capturing device, optically capturing the displayed image; through the user device, processing the captured image for extracting from the captured image the “Challenge”, and subsequently processing the obtained “Challenge” for generating the answer code; receiving the answer code from the user and comparing it to the expected answer code; and, in case of positive comparison, authenticating the user. One among the actions of generating a “Challenge” and an expected answer code, and the action of processing the captured image that generates the answer code exploit secret information univocally associated with the user. | 2010-10-28 |
20100275011 | METHOD AND APPARATUS FOR SECURE COMMUNICATIONS - The present invention provides a method and apparatus for a trusted service provider (TSP) which assists with the secure exchange of data across the public switched telephone network. Communications are routed via a TSP, which uses cryptographic techniques to conceal the identities (e.g., telephone numbers) of the call initiator and call recipient, thereby preventing traffic analysis attacks. The TSP also performs cryptographic handshakes with the call initiator and call recipient to authenticate callers. The TSP further provides cryptographic keying material which communicants may use to help protect communications and to directly authenticate and identify each other. Although the TSP is trusted to negotiate the connection and is involved in the process, the communicants can perform their own key agreement and authentication for protecting data routed via the TSP. | 2010-10-28 |
20100275012 | SERVER CERTIFICATE ISSUING SYSTEM AND PERSON AUTHENTICATION METHOD - A server certificate issuing system in which existence of a Web server for which a certificate is to be issued can be confirmed and security is further improved is realized, wherein the user authentication is carried out using a test certificate having the SSL certificate format. Servers transmit server certificate request to the registration server which transmits the test certificate request to the test certificate issuing authority. The test certificate issuing server transmits the generated test certificate to the registration server which transmits the test certificate to the corresponding server and requests to install the test certificate. Then, the registration server accesses with SSL protocol to the server and verifies whether or not the session of the SSL protocol has been established. The registration server transmits the CSR to the certificate issuing server only when the SSL protocol has been established. | 2010-10-28 |
20100275013 | Method for Communicating Certificates to Computers - A method includes receiving at a first computer a new certificate which is to replace an old certificate associated with the first computer and associating by the first computer the new certificate with the first computer. In response to the first computer associating the new certificate with the first computer, the first computer accesses an email address book of the first computer having information identifying a second computer as having received the old certificate to determine from the information that the second computer is to associate the new certificate in place of the old certificate with the first computer. In turn, the first computer transmits the new certificate to the second computer for the second computer to associate the new certificate with the first computer. | 2010-10-28 |
20100275014 | METHOD AND APPARATUS TO CREATE A SECURE WEB-BROWSING ENVIRONMENT WITH PRIVILEGE SIGNING - Devices and methods use digital certificates and digital signatures to enable computing devices, such as mobile devices, to trust a server attempting to access a resource on the computing device. The server may present the computing device with a digital certificate issued by a trusted third party which includes information so that the computing device can determine which resources the server should be trusted to access. The computing device can determine that the digital certificate was issued by a trusted third party by examining the chain of digital certificates that may link the server with an inherently trusted authority. | 2010-10-28 |
20100275015 | ANONYMOUS REGISTER SYSTEM AND METHOD THEREOF - A uniform certificate revocation list managing apparatus is provided for managing canceled register information of all believable groups in a believable anonymous register system. Canceled register information includes canceled member information of each believable group, list information of unbelievable groups, and list information of unbelievable register service institutions. The uniform certificate revocation list managing apparatus interacts with each believable group and each register system, so as to update a certificate revocation list of each believable group in real time. | 2010-10-28 |
20100275016 | DATA SECURITY - In one embodiment, a method is provided that may include one or more operations. One of these operations may include, in response, at least in part, to a request to store input data in storage, encrypting, based least in part upon one or more keys, the input data to generate output data to store in the storage. The one or more keys may be authorized by a remote authority. Alternatively or additionally, another of these operations may include, in response, at least in part, to a request to retrieve the input data from the storage, decrypting, based at least in part upon the at least one key, the output data. Many modifications, variations, and alternatives are possible without departing from this embodiment. | 2010-10-28 |
20100275017 | Peer-to-Peer Forwarding for Packet-Switched Traffic - Establishing peer-to-peer tunnels between clients in a mobility domain. In normal operation, clients attached to a network having access nodes connected to a central controller transfer all traffic through the central controller. This traffic is passed using tunnels between the access node and the central controller. Tunnels may be encrypted, and GRE tunnels may be used. A mobility manager operating in the controller tracks access nodes connected to the controller, and clients connected to those access nodes. When the mobility controller recognizes traffic passing between clients in its mobility domain that is eligible for peer-to-peer forwarding, it instructs the access nodes supporting the clients to establish a peer-to-peer tunnel between the nodes, and direct the client traffic through this peer-to-peer tunnel. The peer-to-peer tunnel may be session based, or may be aged. Eligibility of traffic for peer-to-peer tunnels may be controlled by rules, such as limiting peer-to-peer tunnels by source or destination, by port or protocol, and the like. | 2010-10-28 |
20100275018 | SYSTEM AND METHOD FOR CONVERSION AND DISTRIBUTION OF GRAPHICAL OBJECTS - A system for converting a first digital representation of a graphical object defined in two dimensions, such as a floor plan of a building such as a house or an apartment, into a second digital representation of said graphical object, said second digital representation defined in three dimensions, said system comprising means for converting the first digital representation into a vector based representation by means of an computer implemented algorithm, and means for converting said vector based representation of the first digital representation into a three dimensional representation of the graphical object. Furthermore the invention relates to a system for secure administration and/or provision of protected data files in a computer network, such as the Internet or a local LAN, said computer network comprising at least one server and a plurality of clients. Finally the invention relates to a system that allows 3 | 2010-10-28 |
20100275019 | SERVICE PROVIDING METHOD AND INTEGRATED CIRCUIT - An application program relating to a process of an integrated circuit | 2010-10-28 |
20100275020 | COMMUNICATION METHOD, COMMUNICATION SYSTEM, MOBILE NODE AND COMMUNICATION NODE - The invention discloses a technique, by which the number of messages can be decreased when RR (Return Routability) procedure is performed to give authentication between a mobile node (MN) and a correspondent node (CN). According to this technique, CN | 2010-10-28 |
20100275021 | DEFINING ACCESS RIGHTS TO CONTENT - A portion of text associated with a message intended for a group of recipients is encrypted at a computing device. The portion of text may include less than an entirety of the message. Access to the portion of text may be restricted for a first subset of the group of recipients and allowed for a second subset of the group of recipients. | 2010-10-28 |
20100275022 | TRANSMITTER, RECEIVER, AND CONTENT TRANSMITTING AND RECEIVING METHOD - According to one embodiment, a transmitter is configured to transmit content to a receiver. Available dubbing count is set in advance for the content such that the content can be dubbed a plurality of times. The transmitter includes a key exchanger, an encryption processor, and a dubbing management module. The key exchanger performs key exchange to share a common key with the receiver. The encryption processor encrypts, in response to a content request received from the receiver, the content with the common key to transmit the content to the receiver. The dubbing management module reduces, upon receipt of a right transfer request related to the use of the content from the receiver, the available dubbing count by dubbing count indicating the number of times of dubbing of the content. The dubbing count is contained in the right transfer request. | 2010-10-28 |
20100275023 | TRANSMITTER, RECEIVER, AND CONTENT TRANSMITTING AND RECEIVING METHOD - According to one embodiment, a transmitter configured to transmit content to a receiver. Available dubbing count is set in advance for the content such that the content can be dubbed a plurality of times. The transmitter includes a key exchanger, an encryption processor, and a management module. The key exchanger performs key exchange to share a common key with the receiver, and transmits the common key and at least one count label corresponding to the number of times of dubbing to the receiver. The encryption processor encrypts, in response to a content request for the content received from the receiver, the content with the common key to transmit the content to the receiver. The management module reduces the available dubbing count of the content upon each receipt of a right transfer request requesting to transfer right to use the content from the receiver, and transmits permission to the receiver to validate the right to use the content. | 2010-10-28 |
20100275024 | METHOD AND SYSTEM FOR DISPLAYING VERIFICATION INFORMATION INDICATORS ON A NON-SECURE WEBSITE - A method and system of displaying information indicators that help provide security assurances to consumers. The method works by having a plug-in or browser extension that determines the URL of a browsed to website. The browser then initiates a secure connection to the domain associated with the URL of a browsed-to website. The plug-in can then show an indicator based on whether or not a digital certificate exists. If desired, the plug-in can perform further checks to ensure the validity and authenticity of the certificate. The information indicators can be static, pre-selected by the program, or selected by the end user. | 2010-10-28 |
20100275025 | METHOD AND APPARATUS FOR SECURE COMMUNICATION - In a device, method and/or computer-readable medium for secure communication between a client device and a server, the client device includes a browser for accessing a website provided by the server, the client device generates a key according to a key generating cryptographic routine; tags the key with a marker associating the key with the website; and stores the tagged key in a memory associated with the browser. | 2010-10-28 |
20100275026 | METHOD AND APPARATUS FOR IMPROVING CODE AND DATA SIGNING - Methods and computing devices enable code and/or data software on computer devices to be verified using methods and signatures which can be updated by a signing server after distribution. Updated verification methods and signatures may be provided in a second signature file. When a computing device unpacks an application for execution it may check whether a second signature file is associated with the application file. If not it may connect to a signing server to request a second signature file for the software. The signing server then may request information related to the software sufficient to determine if the software is trustworthy. If determined to be trustworthy, the signing server can send a second signature file to the computer device for use in verifying the software henceforth. The second signature file may include new or modified verification methods and a new signature. | 2010-10-28 |
20100275027 | RECEIVED MESSAGE VERIFICATION - A method of verifying the validity of a message received by a telecommunications terminal ( | 2010-10-28 |
20100275028 | VERIFICATION APPARATUS - In an integer partitioning process S | 2010-10-28 |
20100275029 | SYSTEM AND METHOD OF INSTALLING SOFTWARE APPLICATIONS ON ELECTRONIC DEVICES - In at least one embodiment, there is provided a mobile wireless device comprising: a microprocessor and memory, the memory comprising a set of control settings used to control a plurality of device operations; wherein the microprocessor is configured to: receive a first digital signature key for verifying digital signatures on software applications to be installed on the device; determine if any digital signature keys for verifying digital signatures on software applications to be installed on the device exist on the device, and if not, store the received first digital signature key in the memory; receive a software application for installation on the device; verify a digital signature on the received software application using the first digital signature key; and install the software application on the device if the digital signature on the received software application is successfully verified. | 2010-10-28 |
20100275030 | METHOD FOR ENSURING THE VALIDITY OF RECOVERED ELECTRONIC DOCUMENTS FROM REMOTE STORAGE - A method for electronically storing and retrieving at a later date a true copy of a document stored on a remote storage device comprises: sending a document in electronic format from a document owner's computing device to a store entity for storing the document; generating a digest of the document while the document is at the store entity by applying a hash function to the document; signing the digest electronically with a key while said document is at the store entity; generating a receipt that includes the digest and the key; sending the receipt to the document owner; and verifying, at the document owner's computing device, that the received receipt corresponds to the document sent from the owner's computing device. | 2010-10-28 |
20100275031 | METHOD FOR SECURELY TRANSMITTING CONTROL DATA FROM A SECURE NETWORK - This method securely transmits data from a secure control system [ | 2010-10-28 |
20100275032 | SYSTEM AND METHOD FOR CONTROLLING ACCESS TO A PORTABLE DEVICE - An apparatus, system, and method for controlling access to sensitive data in a wireless handset using password protection. The wireless handset comprises an input module, a memory module, a display module, and a control module. The input module is configured to manually receive one or more passwords that are input into the wireless handset and may be associated with a user-requested function. The memory module is configured to store the passwords associated with the user-requested function. The user-requested function comprises a messaging function selected from a messaging group consisting of IM, SMS, MMS, and user contacts data. The user-requested function has a plurality of user-specific data stored on the memory module. The display module displays the stored user-specific data. The control module controls the operation of the input module, the memory module and the display module. The control module controls access to the user-specific data by password protecting the user-specific data with an initial password received with the input module. | 2010-10-28 |
20100275033 | TOUCH SCREEN WITH USER INTERFACE ENHANCEMENT - The present invention is a graphical user interface in a computing device having a processor running an operating system and a display. The graphical user interface comprises a touch screen and a driver coupling the touch screen to the operating system. The driver can display a plurality of icons on the touch screen, or a plurality of screen images having at least one icon, with each of the icons associated with operations on the display and/or the touch screen. Other embodiments include the touch screen having unactivated and activated states, as well as the presence of an application programming interface that enables an application to display at least one image on the touch screen. | 2010-10-28 |
20100275034 | SOFTWARE PROTECTION METHOD - A method of protecting an executable program from reverse engineering and/or tampering. The method includes receiving a copy of the executable program together with a debug database, the database storing the locations of functional blocks within the executable program. A protection code is inserted into the executable program so as to overwrite at least part of a functional block of the executable program. Subsequent execution of the functional block causes the protection code to be executed. The protection code, when executed, performs an operation and executes a copy of the overwritten part of the functional block. | 2010-10-28 |
20100275035 | Cryptographic processing apparatus and method for storage medium - Provided is a cryptographic processing apparatus for a storage medium, including: a location information conversion unit that stores a conversion result in a buffer, the conversion result obtained by performing a conversion process on location information indicating a location of data to be accessed on the storage medium; and a data cryptographic processing unit that performs cryptography processing on the data using the conversion result stored in the buffer, the cryptography processing being one of encryption and decryption. | 2010-10-28 |
20100275036 | RECORDING/REPRODUCING SYSTEM, RECORDING MEDIUM DEVICE, AND RECORDING/REPRODUCING DEVICE - A memory card and a recording/playback device are provided that are capable of deterring a memory card manufacturer from illicitly storing a same media ID on a plurality of memory cards. A memory card ( | 2010-10-28 |
20100275037 | Low-Power USB SuperSpeed Device with 8-bit Payload and 9-bit Frame NRZI Encoding for Replacing 8/10-bit Encoding - A Low-power flash-memory device uses a modified Universal-Serial-Bus (USB) 3.0 Protocol to reduce power consumption. The bit clock is slowed to reduce power and the need for pre-emphasis when USB cable lengths are short in applications. Data efficiency is improved by eliminating the 8/10-bit encoder and instead encoding sync and framing bytes as 9-bit symbols. Data bytes are expanded by bit stuffing only when a series of six ones occurs in the data. Header and payload data is transmitted as nearly 8-bits per data byte while framing is 9-bits per symbol, much less than the standard 10 bits per byte. Low-power link layers, physical layers, and scaled-down protocol layers are used. A card reader converter hub allows USB hosts to access low-power USB devices. Only one flash device is accessed, reducing power compared with standard USB broadcasting to multiple devices. | 2010-10-28 |
20100275038 | Memory Device and Method for Adaptive Protection of Content - A memory device and method for adaptive protection of content are disclosed. In one embodiment, a memory device is provided comprising a memory operative to store content and a controller in communication with the memory. The controller is operative to generate a content protection algorithm that is different from at least one content protection algorithm previously generated by the controller, protect the content in accordance with the content protection algorithm, generate virtual machine code containing instructions on how to unprotect the protected content, and provide the protected content and the virtual machine code to a host in communication with the memory device. In another embodiment, a method for adaptive protection of content is provided comprising generating a content protection algorithm that is different from at least one previously-generated content protection algorithm, protecting content in accordance with the content protection algorithm, generating virtual machine code containing instructions on how to unprotect the protected content, and providing the protected content and the virtual machine code to a host in communication with the memory device. | 2010-10-28 |
20100275039 | SECURE ARCHIVE - Storage apparatus ( | 2010-10-28 |
20100275040 | Systems and Methods for Secure Transaction Management and Electronic Rights Protection - The present invention provides systems and methods for secure transaction management and electronic rights protection. Electronic appliances such as computers equipped in accordance with the present invention help to ensure that information is accessed and used only in authorized ways, and maintain the integrity, availability, and/or confidentiality of the information. Such electronic appliances provide a distributed virtual distribution environment (VDE) that may enforce a secure chain of handling and control, for example, to control and/or meter or otherwise monitor use of electronically stored or disseminated information. Such a virtual distribution environment may be used to protect rights of various participants in electronic commerce and other electronic or electronic-facilitated transactions. Distributed and other operating systems, environments and architectures, such as, for example, those using tamper-resistant hardware-based processors, may establish security at each node. These techniques may be used to support an all-electronic information distribution, for example, utilizing the “electronic highway.” | 2010-10-28 |
20100275041 | COMPUTER POWER SUPPLY AND POWER STATUS SIGNAL GENERATING CIRCUIT THEREOF - A computer power supply includes a system voltage output terminal, a standby voltage output terminal, and a power status signal generating circuit comprising an amplifier and an electrical switch. A terminal of a first resistor is connected to the system voltage output terminal. The other terminal of the first resistor is grounded via a capacitor and connected to a non-inventing terminal of the amplifier. A terminal of a second resistor is connected to the standby voltage output terminal. The other terminal of the second resistor is grounded via the third resistor and connected to an inverting terminal of the amplifier. An output terminal of the amplifier outputs a power status signal. A terminal of a fourth resistor is connected to the system voltage output terminal. The other terminal of the fourth resistor is connected to the output terminal of the amplifier and receives a start signal via the electrical switch. | 2010-10-28 |
20100275042 | COMPUTER AND EXPANDABLE POWER SUPPLY SYSTEM THEREOF - The invention discloses a computer and an expandable power supply system. The expandable power supply system includes N interface units, a determination unit, and a voltage converting unit. N is an integer equal to or more than two. The interface units are electrically connected with at least one power supplies and switching the levels of (N−1) control signals according to conductance of the power supplies. When the interface units are electrically connected with 1 | 2010-10-28 |
20100275043 | NETWORK SYSTEM, NETWORK MONITOR AND METHOD FOR RESETTING NETWORK MONITOR - A network system includes a server computer connected to at least one client device and configured to perform at least one operation corresponding to an operation signal received from the at least one client device, and transmitting result data based on the performed operation to a corresponding client device and the at least one client device configured to transmit the operation signal in response to an input from a user, receive the result data transmitted from the server computer and processing the result data, wherein the at least one of the client devices configured to determine whether the result data from the server computer is normal and perform power halting operation for a predetermined time period based on a determination that the result data is abnormal. | 2010-10-28 |