44th week of 2008 patent applcation highlights part 17 |
Patent application number | Title | Published |
20080265340 | DISPOSABLE PILLARS FOR CONTACT FORMATION - Sacrificial plugs for forming contacts in integrated circuits, as well as methods of forming connections in integrated circuit arrays are disclosed. Various pattern transfer and etching steps can be used to create densely-packed features and the connections between features. A sacrificial material can be patterned in a continuous zig-zag line pattern that crosses word lines. Planarization can create parallelogram-shaped blocks of material that can overlie active areas to form sacrificial plugs, which can be replaced with conductive material to form contacts. | 2008-10-30 |
20080265341 | Manufacture of semiconductor device having insulation film of high dielectric constant - A method contains the steps of (a) heating a silicon substrate in a reaction chamber; and (b) supplying film-forming gas containing source gas, nitridizing gas, and nitridation enhancing gas to a surface of the heated silicon substrate, to deposit on the silicon substrate an Hf | 2008-10-30 |
20080265342 | TWO-BIT FLASH MEMORY CELL AND METHOD FOR MANUFACTURING THE SAME - A two-bit flash memory cell includes a substrate, a gate oxide layer disposed on the substrate, a T-shaped gate on the gate oxide layer. A first charge storage layer is disposed at one side of and under the T-shaped gate. A second charge storage layer, which is separated from the first charge storage layer by a bottom portion of the T-shaped gate and the gate oxide layer, is disposed at the other side of and under the T-shaped gate. An insulating layer is disposed between the T-shaped gate and the gate oxide layer. A first source/drain region is disposed at one side of the T-shaped gate within the substrate. A second source/drain region is disposed at the other side of the T-shaped gate within the substrate. | 2008-10-30 |
20080265343 | FIELD EFFECT TRANSISTOR WITH INVERTED T SHAPED GATE ELECTRODE AND METHODS FOR FABRICATION THEREOF - A semiconductor structure includes an inverted T shaped gate electrode located over a channel region that separates a plurality of source and drain regions within a semiconductor substrate. The inverted T shaped gate electrode may comprise different gate electrode materials in a horizontal portion thereof and a vertical portion thereof. The semiconductor structure may be passivated with an inter-level dielectric (ILD) layer through which may be located and formed a plurality of vias that contact the plurality of source and drain regions. Due to the inverted T shaped gate electrode, the semiconductor structure exhibits a reduced gate electrode to via capacitance. | 2008-10-30 |
20080265344 | METHOD OF SIMULTANEOUSLY SILICIDING A POLYSILICON GATE AND SOURCE/DRAIN OF A SEMICONDUCTOR DEVICE, AND RELATED DEVICE - A method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a first polysilicon layer, a first nitride layer, and a second polysilicon layer), forming a second nitride layer over an active region in the semiconductor substrate adjacent to the gate stack, performing a chemical mechanical polishing that stops on the first nitride layer and on the second nitride layer, removing the first nitride layer and the second nitride layer, and performing a simultaneous silicidation of the first polysilicon layer and the active region. | 2008-10-30 |
20080265345 | Method of Forming a Fully Silicided Semiconductor Device with Independent Gate and Source/Drain Doping and Related Device - A method of forming a fully silicided semiconductor device with independent gate and source/drain doping and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a substrate (the gate stack comprising a polysilicon layer and a blocking layer), and performing an ion implantation into an active region of the substrate adjacent to the gate stack (the blocking layer substantially blocks the ion implantation from the polysilicon layer). | 2008-10-30 |
20080265346 | SEMICONDUCTOR SENSOR AND MANUFACTURING METHOD OF THE SAME - A semiconductor sensor and a manufacturing method of the same capable of making the specific gravity of a weight part to be greater than that of a weight part made of semiconductor material only is disclosed. The semiconductor sensor includes the weight part, a supporting part, a flexible part, and plural piezoresistive elements. The weight part includes a weight part photosensitive resin layer made of photosensitive resin in which metal particles are included. The supporting part surrounds and is separated from the weight part. The flexible part is provided between the weight part and the supporting part to support the weight part. The flexible part includes a flexible part semiconductor layer where the plural piezoresistive elements are formed. This configuration allows the specific gravity of the weight part photosensitive resin layer greater than that of the weight part semiconductor layer due to the metal particles. | 2008-10-30 |
20080265347 | MAGNETORESISTIVE ELEMENT AND MANUFACTURING METHOD THEREOF - A magnetoresistive element includes a first stacked structure formed by sequentially stacking a first fixed layer in which a magnetization direction is fixed and a first nonmagnetic layer, a second stacked structure formed on the first stacked structure by sequentially stacking a free layer in which a magnetization direction is changeable, a second nonmagnetic layer, and a second fixed layer in which a magnetization direction is fixed, and a circumferential wall formed in contact with a circumferential surface of the second stacked structure to surround the second stacked structure, and made of an insulator. A circumferential surface of the first stacked structure is substantially perpendicular. The second stacked structure has a tapered shape which narrows upward. | 2008-10-30 |
20080265348 | Method of Manufacturing an Image Sensor and Image Sensor - A method of manufacturing a back-side ( | 2008-10-30 |
20080265349 | Solid-State Image Sensor - An object of the present invention is to provide a solid-state image sensor including a filter membrane that has excellent light resistance and can be thinned. A solid-state image sensor | 2008-10-30 |
20080265350 | IMAGE CAPTURING DEVICE - An image capturing device includes an image sensor package and a lens module aligned with the image sensor package. The image sensor package includes a substrate, at least one passive component, an insulative layer, and an image sensor. The substrate has a surface facing an object side of the image capturing device, the surface defines a cavity therein. The at least one passive component is disposed within the cavity and electrically connected to the substrate. The insulative layer is received in the cavity and encases the at least one passive component. The image sensor is disposed on the insulative layer and electrically connected to the substrate. The holder has an end connecting with the barrel and an opposite end secured on the substrate. | 2008-10-30 |
20080265351 | Semiconductor device and method of fabricating the same - In fabrication of a semiconductor device mounted on a wiring board, a semiconductor circuit portion is formed over a glass substrate. Then, an interposer having connection terminals are bonded to the semiconductor circuit portion. After that, the glass substrate is peeled off from the semiconductor circuit portion, and a mold resin is poured to cover the periphery of the semiconductor circuit portion from a direction of the separation plane. Then, the mold resin is heated under predetermined conditions to be hardened. | 2008-10-30 |
20080265352 | Solid-state image capturing apparatus, method for manufacturing the same, and electronic information device - An image capturing apparatus has a plurality of solid-state image capturing devices each having light receiving sections laminated in a depth direction of a semiconductor substrate. The devices are sequentially arranged in a direction along a substrate surface. Incident light waves having wavelength bands corresponding to depths of respective light receiving sections are detected there and generate signal charges. Bands are associated with light receiving sections by the wavelength dependence of the optical absorption. Trench sections each reach from a light incident surface or an opposite substrate surface to respective light receiving sections that do not overlap each other in a plane view. Electric charge transfer sections transfer electric charges independently from the light receiving sections via side wall portions of their respective trenches to the light incident surface side or the opposite substrate surface side at the time of driving readout gate electrodes at each trench section. | 2008-10-30 |
20080265353 | Solid-state imaging device and method for fabricating the same related application data - A solid-state imaging device having a plurality of light-receiving sections which are disposed in a substrate and which generate charge in response to incident light, a planarizing layer which covers predetermined elements disposed on the substrate to perform planarization, a plurality of signal lines disposed above the planarizing layer and a waveguide which guides incident light to each of the light-receiving sections, the waveguide passing through the space between the plurality of signal lines. | 2008-10-30 |
20080265354 | Image sensor - An image sensor, in which, a planarized layer is formed on a semiconductor substrate including a pixel array region, an optical black region, and a logic region to cover a photo sensing unit array in the pixel array region, a patterned metal layer is formed on the planarized layer corresponding to the pixel array region and the logic region, but not the optical black region. An optical black layer is formed in the optical black region after a passivation layer is formed and before a color filter array is formed at a temperature less than about 400° C., and preferably contains metal material. | 2008-10-30 |
20080265355 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - In a semiconductor device which has through holes in an end face, in which a semiconductor element is fixedly mounted on a face of a substrate which has a wiring pattern, which is conductive to the wiring portion formed in the through hole, in at least one face, in which electrodes of the semiconductor element are electrically connected to the wiring pattern, and in which the face of the substrate which has the semiconductor element is coated with a resin, the through hole has a through hole land with a width of 0.02 mm or more, which is conductive to the wiring portion, in a substrate face, and the wiring portion and the through hole land are exposed. | 2008-10-30 |
20080265356 | CHIP SIZE IMAGE SENSING CHIP PACKAGE - An image sensing chip package includes an image sensing chip having an image sensor disposed on a circuit side thereof that includes electrical conductive pads. A glue layer is applied to the circuit side and around the image sensor. A flexible film wraps the chip in such a way that an inner surface of the film faces the circuit side of the chip, an opening thereof corresponds to the image sensor, an area of the inner surface near the edges of the opening attaches to the glue layer, an inner end of each of conductors disposed on the inner surface of said film bonds to each of the electrical conductive pads, and an outer end of each of the conductors is exposed to connect with other electrical elements. A light transparent member is disposed on an outer surface of the film to seal the opening of the film. | 2008-10-30 |
20080265357 | Semiconductor optical receiver device, optical receiver module, and method for manufacturing semiconductor optical receiver device - A semiconductor optical receiver device is provided, which a mesa comprising a plurality of semiconductor crystal layers formed on a semiconductor substrate including a pn junction having a first conductive semiconductor crystal layer and a second conductive semiconductor crystal layer and including a first contact layer on the semiconductor substrate, a plurality of electrodes to apply electric field to the pn junction are coupled on the semiconductor substrate, a second contact layer is formed on a buried layer in which the mesa is buried, and the electric field is applied to the pn junction through the first and second contact layers. | 2008-10-30 |
20080265358 | Method for patterning a detector crystal, and a semiconductor detector having a patterned crystal - A semiconductor radiation detector crystal is patterned by using a Q-switched laser to selectively remove material from a surface of said semiconductor radiation detector crystal, thus producing a groove in said surface that penetrates deeper than the thickness of a diffused layer on said surface. | 2008-10-30 |
20080265359 | SEMICONDUCTOR DIVICE - A semiconductor device in the present invention is provided with a cathode layer of an N-type impurity region and an anode layer of a P-type impurity region formed on the cathode layer. A plurality of floating ring layers of the P-type impurity regions which is electrically floating is provided spaced apart from the anode layer on the main surface of the cathode layer. Then, well layers of the N-type impurity regions containing floating ring layers are provided. For example, each well layer can individually be provided to the floating ring layer. In this case, each floating ring layer may be spaced apart or overlapped one another. Accordingly, a semiconductor device serves to downsize a chip without changing a property of on-resistance or a breakdown voltage. | 2008-10-30 |
20080265360 | Semiconductor Layer Structure And Method Of Making The Same - A semiconductor layer structure includes a donor substrate and a detach region carried by the donor substrate. A device structure is carried by the donor substrate and positioned proximate to the detach region. The device structure includes a stack of crystalline semiconductor layers. The stack of crystalline semiconductor layers includes a pn junction. | 2008-10-30 |
20080265361 | METHOD FOR GENERATING A LAYOUT, USE OF A TRANSISTOR LAYOUT, AND SEMICONDUCTOR CIRCUIT - A method for generating a layout, use of a transistor layout, and semiconductor circuit is provided that includes a matching structure, which has a number of transistors, whose structure is similar to one another, metallization levels with geometrically formed traces, which are formed directly above the transistors, and vias (in via levels), which are formed between two of the metallization levels. Whereby, within one and the same metallization level, the geometry of the traces above each transistor is formed the same. | 2008-10-30 |
20080265362 | BUILDING FULLY-DEPLETED AND BULK TRANSISTORS ON SAME CHIP - An integrated circuit having fully-depleted silicon-on-insulator (FD-SOI) transistors and bulk transistors on a semiconductor substrate is disclosed. | 2008-10-30 |
20080265363 | HIGH POWER DEVICE ISOLATION AND INTEGRATION - A structure and method of fabricating the structure. The structure including: a dielectric isolation in a semiconductor substrate, the dielectric isolation extending in a direction perpendicular to a top surface of the substrate into the substrate a first distance, the dielectric isolation surrounding a first region and a second region of the substrate, a top surface of the dielectric isolation coplanar with the top surface of the substrate; a dielectric region in the second region of the substrate; the dielectric region extending in the perpendicular direction into the substrate a second distance, the first distance greater than the second distance; and a first device in the first region and a second device in the second region, the first device different from the second device, the dielectric region isolating a first element of the second device from a second element of the second device. | 2008-10-30 |
20080265364 | Creation of Dielectrically Insulating Soi-Technlogical Trenches Comprising Rounded Edges for Allowing Higher Voltages - The aim of the invention is to integrate low-voltage logic elements and high-voltage power elements in one and the same silicon circuit. Said aim is achieved by dielectrically chip regions having different potentials from each other with the aid of isolation trenches ( | 2008-10-30 |
20080265365 | METHOD FOR PREVENTING THE FORMATION OF ELECTRICAL SHORTS VIA CONTACT ILD VOIDS - Densely spaced gates of field effect transistors usually lead to voids in a contact interlayer dielectric. If such a void is opened by a contact via and filled with conductive material, an electrical short between neighboring contact regions of neighboring transistors may occur. By forming a recess between two neighboring contact regions, the void forms at a lower level. Thus, opening of the void by contact vias is prevented. | 2008-10-30 |
20080265366 | SEMICONDUCTOR DEVICE WITH IMPROVED CONTACT FUSE - One aspect of the invention provides an integrated circuit(IC) [400 | 2008-10-30 |
20080265367 | Magnetically Alignable Integrated Circuit Device - An integrated circuit device includes a semiconductor chip having an active surface with a plurality of chip contact pads, a rewiring substrate and an electrically conductive inductor coil for magnetically aligning the semiconductor chip with the rewiring substrate. | 2008-10-30 |
20080265368 | Integrated Stacked Capacitor and Method of Fabricating Same - An integrated stacked capacitor comprises a first capacitor film ( | 2008-10-30 |
20080265369 | Semiconductor Capacitor Structure - The present invention discloses a capacitor in an integrated circuit which comprises a first and second conductive lines substantially parallel to each other and having a thickness equals substantially to a sum of a via thickness and an interconnect thickness, the first and second conductive lines, the via and the interconnect being formed by a single deposition step, and at least one dielectric material in a space horizontally across the first and second conductive lines, wherein the first and second conductive lines serve as two conductive plates of the capacitor, respectively, and the dielectric material serves as an insulator of the capacitor. | 2008-10-30 |
20080265370 | Semiconductor device - In the semiconductor device according to the present invention, a lower electrode and an upper electrode are relatively positionally deviated from each other through a capacitance film in a direction perpendicular to the laminating direction thereof. Thus, the upper electrode and the lower electrode each have portions opposed to each other through the capacitance film in the laminating direction and portions not opposed to each other. An upper electrode plug is connected to the portion of the upper electrode not opposed to the lower electrode through an upper electrode contact hole passing through an insulating film formed on the upper electrode. Further, a lower electrode plug is connected to the portion of the lower electrode not opposed to the upper electrode through a lower electrode contact hole passing through the insulating film. | 2008-10-30 |
20080265371 | Capacitor Unit and Method of Forming the Same - A capacitor unit includes a first capacitor and a second capacitor. The first capacitor includes a first lower electrode, a first dielectric layer pattern and a first upper electrode sequentially stacked. The first capacitor includes a first control layer pattern for controlling a voltage coefficient of capacitance (VCC) of the first capacitor between the first lower electrode and the first dielectric layer pattern. The second capacitor includes a second lower electrode, a second dielectric layer pattern and a second upper electrode sequentially stacked. The second lower electrode is electrically connected to the first upper electrode, and the second upper electrode is electrically connected to the second lower electrode. The second capacitor includes a second control layer pattern for controlling a VCC of the second capacitor between the second lower electrode and the second dielectric layer pattern. | 2008-10-30 |
20080265372 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - The bottom side of an N type silicon substrate is connected to a power supply terminal, a second P type epitaxial layer is formed on all sides of the N type silicon substrate, and a device forming portion is provided on the second P type epitaxial layer. A first P type epitaxial layer and an interlayer insulating film are provided on the device forming portion and an N well and a P well are formed on the top surface of the first P type epitaxial layer. The second P type epitaxial layer is connected to a ground terminal via the first P type epitaxial layer, the P well, a p | 2008-10-30 |
20080265373 | SEMICONDUCTOR DEVICE - An epitaxial layer is formed in a main surface of a semiconductor substrate of a first conductivity type. The epitaxial layer is partitioned into a first area and a second area by a device isolation area. A PN junction portion, which has a semiconductor layer of a second conductivity type and configures a variable capacitance element, is provided at the surface of the epitaxial layer of the first area. A PN junction portion, which has a semiconductor layer of the second conductivity type whose low portion is formed closer to the semiconductor substrate than the semiconductor layer of the second conductivity type configuring the above variable capacitive PN junction and which is configured as a fixed capacitance, is provided at the surface of the epitaxial layer of the second area. | 2008-10-30 |
20080265374 | (Al, Ga, In)N-BASED COMPOUND SEMICONDUCTOR AND METHOD OF FABRICATING THE SAME - Disclosed are a (Al, Ga, In)N-based compound semiconductor device and a method of fabricating the same. The (Al, Ga, In)N-based compound semiconductor device of the present invention comprises a substrate; a (Al, Ga, In)N-based compound semiconductor layer grown on the substrate; and an electrode formed of at least one material or an alloy thereof selected from the group consisting of Pt, Pd and Au on the (Al, Ga, In)N-based compound semiconductor layer. Further, the method of fabricating the (Al, Ga, In)N-based compound semiconductor device comprises the steps of growing a P layer including P type impurities in a growth chamber; discharging hydrogen and a hydrogen source gas in the growth chamber; lowering the temperature of the (Al, Ga, In)N-based compound semiconductor with the P layer formed thereon to such an extent that it can be withdrawn to the outside from the growth chamber; withdrawing the (Al, Ga, In)N-based compound semiconductor from the growth chamber; and forming an electrode of at least one material or an alloy thereof selected from the group consisting of Pt, Pd and Au on the p layer. According to the present invention, it is possible to sufficiently secure P type conductivity and obtain good ohmic contact characteristics without performing an annealing process. And, no further annealing is necessary when Pt, Pd, Au electrode are used. | 2008-10-30 |
20080265375 | Methods for the single-sided polishing of semiconductor wafers and semiconductor wafer having a relaxed Si1-x GEx Layer - Single-sided polishing of semiconductor wafers provided with a relaxed Si | 2008-10-30 |
20080265376 | Ic Chip and Its Manufacturing Method - It is an object of the present invention to decrease a unit cost of an IC chip and to achieve the mass-production of IC chips. According to the present invention, a substrate having no limitation in size, such as a glass substrate, is used instead of a silicon substrate. This achieves the mass-production and the decrease of the unit cost of the IC chip. Further, a thin IC chip is provided by grinding and polishing the substrate such as the glass substrate. | 2008-10-30 |
20080265377 | AIR GAP WITH SELECTIVE PINCHOFF USING AN ANTI-NUCLEATION LAYER - A method of forming cavities within a semiconductor device is disclosed. The method comprises depositing an anti-nucleating layer on the interior surface of cavities within an ILD layer of the semiconductor device. This anti-nucleating layer prevents subsequently deposited dielectric layers from forming within the cavities. By preventing the formation of these layers, the capacitance is reduced, thereby resulting in improved semiconductor performance. | 2008-10-30 |
20080265378 | Scribe line layout design - A scribe line layout design to reduce the damage caused by sawing the wafer is presented. An embodiment comprises metal plates located within the scribe lines and at least partially within the junctions of the scribe lines. Each of these metal plates has one or more slots to help relieve the pressure. Alternatively, instead of metal plates, grooves that may be filled with metal could be placed into the scribe lines. These metal plates could also be used concurrently with a seal ring for better protection during sawing. | 2008-10-30 |
20080265379 | Laser Diode Orientation on Mis-Cut Substrates - A microelectronic assembly in which a semiconductor device structure is directionally positioned on an off-axis substrate ( | 2008-10-30 |
20080265380 | METHOD FOR FABRICATING A HIGH-K DIELECTRIC LAYER - One inventive aspect relates to a method for fabricating a high-k dielectric layer. The method comprises depositing onto a substrate a layer of a high-k dielectric material having a first thickness. The high-k dielectric material has a bulk density value and the first thickness is so that the high-k dielectric layer has a density of at least the bulk density value of the high-k dielectric material minus about 10%. The method further comprises thinning the high-k dielectric layer to a second thickness. Another inventive aspect relates to a semiconductor device comprising a high-k dielectric layer as fabricated by the method. | 2008-10-30 |
20080265381 | SiCOH DIELECTRIC - A porous composite material useful in semiconductor device manufacturing, in which the diameter (or characteristic dimension) of the pores and the pore size distribution (PSD) is controlled in a nanoscale manner and which exhibits improved cohesive strength (or equivalently, improved fracture toughness or reduced brittleness), and increased resistance to water degradation of properties such as stress-corrosion cracking, Cu ingress, and other critical properties is provided. The porous composite material is fabricating utilizing at least one bifunctional organic porogen as a precursor compound. | 2008-10-30 |
20080265382 | Nonlithographic Method to Produce Self-Aligned Mask, Articles Produced by Same and Compositions for Same - A method for forming a self aligned pattern on an existing pattern on a substrate comprising applying a coating of a solution containing a masking material in a carrier, the masking material having an affinity for portions of the existing pattern; and allowing at least a portion of the masking material to preferentially assemble to the portions of the existing pattern. The pattern may be comprised of a first set of regions of the substrate having a first atomic composition and a second set of regions of the substrate having a second atomic composition different from the first composition. The first set of regions may include one or more metal elements and the second set of regions may include a dielectric. The first and second regions may be treated to have different surface properties. Structures made in accordance with the method. Compositions useful for practicing the method. | 2008-10-30 |
20080265383 | Workpiece with Semiconductor Chips, Semiconductor Device and Method for Producing a Workpiece with Semiconductor Chips - A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer. In the molding compound a contact via is arranged. | 2008-10-30 |
20080265384 | Integrated Circuit Package Device With Improved Bond Pad Connections, a Lead-Frame and an Electronic Device - A semiconductor device package ( | 2008-10-30 |
20080265385 | Semiconductor package using copper wires and wire bonding method for the same - A semiconductor package using copper wires and a wire bonding method for the same are proposed. The package includes a carrier having fingers and a chip mounted on the carrier. The method includes implanting stud bumps on the fingers of the carrier and electrically connecting the chip and the carrier by copper wires with one ends of the copper wires being bonded to bond pads of the chip and the other ends of the copper wires being bonded to the stud bumps on the carrier. The implanted stud bumps on the carrier improve bondability of the copper wires to the carrier and thus prevent stitch lift. With good bonding, residues of copper wires left behind after a bonding process have even tail ends and uniform tail length to enable fabrication of solder balls of uniform size, thereby eliminating a conventional step of implanting stud bumps on the bond pads of chips and preventing ball lift from occurring. | 2008-10-30 |
20080265386 | SEMICONDUCTOR DEVICE - To actualize a reduction in the on-resistance of a small surface mounted package having a power MOSFET sealed therein. A silicon chip is mounted on a die pad portion integrated with leads configuring a drain lead. The silicon chip has, on the main surface thereof, a source pad and a gate pad. The backside of the silicon chip configures a drain of a power MOSFET and bonded to the upper surface of a die pad portion via an Ag paste. A lead configuring a source lead is electrically coupled to the source pad via an Al ribbon, while a lead configuring a gate lead is electrically coupled to the gate pad via an Au wire. | 2008-10-30 |
20080265387 | SMUDGE RESISTANT COATING FOR ELECTRONIC DEVICE DISPLAYS - An apparatus and method is provided for preventing smudges ( | 2008-10-30 |
20080265388 | ULTRA THIN IMAGE SENSING CHIP PACKAGE - An ultra thin image sensing chip package includes an image sensing chip and a flexible and optically transparent film. The chip has an image sensor and a plurality of electrical conductive pads. The flexible and optically transparent film includes a transparent window, and a pattern of conductors formed on a surface thereof and around the transparent window. The film wraps the chip in such a way that the transparent window thereof corresponds to the image sensor of the chip, a sealed space is formed between the transparent window and the image sensor, one end of each of the conductors of the film bonds to each of the electrical conductive pads of the chip, and the other end of each of the conductors of the film is opened so as to electrically connect with other electrical elements. | 2008-10-30 |
20080265389 | Substrate for multi-chip stacking, multi-chip stack package utilizing the substrate and its applications - A substrate for multi-chip stacking and a multi-chip stack package utilizing the substrate and its applications are disclosed. The substrate comprises a first wire-bonding finger, a second wire-bonding finger, a trace configured for electrical transmission and a loop wiring on a same surface. The first wire-bonding finger and the second wire-bonding finger are adjacent each other and to a die-attaching area of the substrate. The loop wiring connects the first wire-bonding finger with the second wire-bonding finger in series and connected to the trace. The loop wiring can be selectively broken or not when at least two chips are stacked on the die-attaching area and electrically connected to the first and second wire-bonding fingers respectively. Accordingly, the chips can operate respectively and independently without mutual interference if one of the chips is fail. Moreover, there is merit to apply the multi-chip stack package utilizing the substrate because it can be repaired after molding and without removing any bonding wire during semiconductor packaging processes. | 2008-10-30 |
20080265390 | SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device including a PMOS transistor and a NMOS transistor is described. The method facilitates obtaining a FUSI phase of a suitable composition for the NMOS transistor and the PMOS transistor respectively, with fewer mask layers and through a fewer number of manufacturing steps. | 2008-10-30 |
20080265391 | ETCHED INTERPOSER FOR INTEGRATED CIRCUIT DEVICES - In one embodiment, a package-to-package stack is assembled comprising a first integrated circuit package, and a second integrated circuit package which are mechanically and electrically connected using an interposer. In one embodiment, the interposer | 2008-10-30 |
20080265392 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device having a through electrode excellent in performance as for an electrode and manufacturing stability is provided. There is provided a through electrode composed of a conductive small diameter plug and a conductive large diameter plug on a semiconductor device. A cross sectional area of the small diameter plug is made larger than a cross sectional area and a diameter of a connection plug, and is made smaller than a cross sectional area and a diameter of the large diameter plug. In addition, a protruding portion formed in such a way that the small diameter plug is projected from the silicon substrate is put into an upper face of the large diameter plug. Further, an upper face of the small diameter plug is connected to a first interconnect. | 2008-10-30 |
20080265393 | STACK PACKAGE WITH RELEASING LAYER AND METHOD FOR FORMING THE SAME - The present invention provides a structure and a of stacked dice package and a process for forming the same, wherein an elastic adhesive layer applied on the first die covering all top surface of the first die and forming rims at the peripheral edges of the first die except the openings formed on the first contacting pads. With this shape of the elastic adhesive layer, the present invention can avoid micro crack happens in the die while performing wire bonding on the contacting pad of the die. | 2008-10-30 |
20080265394 | WAFER LEVEL PACKAGE AND FABRICATING METHOD THEREOF - A wafer level semiconductor package and fabricating method thereof are disclosed. A method of fabricating a wafer level package, which includes depositing a first insulation layer on the outermost layer circuit of the a semiconductor chip and then flattening the surface of the first insulation layer; removing a portion of the first insulation layer to expose a chip pad to the outside; depositing a metal layer directly contacting the chip pad onto the chip pad and the first insulation layer and then removing a portion to form a bump metal having a bump pad electrically connected with the chip pad; and depositing a second insulation layer and a coating layer in order onto the bump metal and then removing portions thereof to expose the bump pad to the outside, where all of the operations are performed by semiconductor fabrication (FAB) equipment, not only enables the forming of higher-precision patterns, but also reduces volume. | 2008-10-30 |
20080265395 | Semiconductor device and method of fabricating the semiconductor device - A semiconductor device includes: a package substrate that includes a recessed portion, with electrode pads that are electrically connected to electrodes of the semiconductor chip being formed inside the recessed portion; a semiconductor chip that is housed in the recessed portion; terminal-use wires that are formed on the surface of the package substrate and are electrically connected to the electrode pads; external connection pads that are formed on a back surface of the package substrate and are electrically connected to the electrode pads; a sealing resin portion that includes a grinded surface that is parallel to the surface of the package substrate, and seals at least the semiconductor chip by a sealing resin; rewiring pads that are formed on the grinded surface; and connecting wires that are formed on the grinded surface and electrically interconnect the terminal-use wires and the rewiring pads. | 2008-10-30 |
20080265396 | QUAD FLAT NO-LEAD CHIP CARRIER WITH STANDOFF - A QFN package with improved joint solder thickness for improved second level attachment fatigue life. The copper leadframe of a QFN chip carrier is provided with rounded protrusions in both the chip attach pad region and the surrounding lead regions before second level attachment. The rounded stand-off protrusions are formed from the copper itself of the copper of the leadframe. This may be achieved by punching dimples into one surface of the copper plate of the leadframe before plating to form protrusions on the opposing surface. This method of forming the rounded protrusions simplifies the process of forming stand-offs. The protrusions provide a structure that increases wetting area and allows the use of a larger quantity of solder for increased solder joint thickness and better die paddle solder joint area coverage. As a result of the increased solder joint thickness, second level fatigue life is significantly improved. As a result of the improved die paddle solder joint area coverage, improved thermal performance of the chip carrier is also significantly improved. | 2008-10-30 |
20080265397 | Chip-Stacked Package Structure - A chip stacked package structure and applications are provided, wherein the chip stacked package structure comprises a substrate, a first chip, a patterned circuit layer and a second chip. The substrate has a first surface and an opposite second surface. The first chip with a first active area and an opposite first rear surface is electrically connected to first surface of substrate by a flip chip bonding process. The patterned circuit layer set on the dielectric layer is electrically connected to the substrate via a bonding wire. The second chip set on the patterned circuit layer has a second active area and a plurality of second pads formed on the second active area, wherein the second bonding pad is electrically connected to the patterned circuit layer. | 2008-10-30 |
20080265398 | SUBSTRATE WITH PIN, WIRING SUBSTRATE AND SEMICONDUCTOR DEVICE - A substrate with pins comprises pins, and a holding substrate in which through holes to which the pins are attached are formed. Head parts of the pins are arranged in the through holes. The pins are attached by pressing the head parts in the through holes. | 2008-10-30 |
20080265399 | Low-cost and ultra-fine integrated circuit packaging technique - A semiconductor package structure and the methods for forming the same are provided. The semiconductor package structure includes an interposer; a first plurality of bonding pads on a side of the interposer; a semiconductor chip; and a second plurality of bonding pads on a side of the semiconductor chip. The first and the second plurality of bonding pads are bonded through metal-to-metal bonds. | 2008-10-30 |
20080265400 | Chip-Stacked Package Structure and Applications Thereof - A chip stacked package structure and applications are provided, wherein the chip stacked package structure comprises a substrate, a first chip, circuit board and a second chip. The substrate has a first surface and an opposite second surface. The first chip having a first active surface and an opposite first rear surface is electrically connected to first surface of substrate serving by a flip chip bonding process. The circuit board has a dielectric layer set on the first rear surface and a patterned conductive layer set on the dielectric layer is electrically connected to the substrate via a bonding wire. The second chip set on the patterned conductive layer has a plurality of second pads formed on a second active surface thereof and eclectically connected to the patterned conductive layer. | 2008-10-30 |
20080265401 | Integrated chip package structure using organic substrate and method of manufacturing the same - An integrated chip package structure and method of manufacturing the same is by adhering dies on an organic substrate and forming a thin-film circuit layer on top of the dies and the organic substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry. | 2008-10-30 |
20080265402 | REWORK PROCESS AND METHOD FOR LEAD-FREE CAPPED MULTI-CORE MODULES WITH ORGANIC SUBSTRATES - A system and method for utilizing lead-free multi-core modules with organic substrates,including a base portion configured to attach a semiconductor chip;and a cap portion further comprising: a bottom portion configured to be sealed to the base portion;and a vacuum port;wherein when a vacuum is drawn at the vacuum port,a re-workable seal between the base portion and the cap portion is provided to enable rework. | 2008-10-30 |
20080265403 | Hybrid Metal Matrix Composite Packages with High Thermal Conductivity Inserts - A hybrid package for heat sinking a device is formed of a graphitic material that defines a plurality of cavities for cast-in-rivets and that defines at least one cavity for a cast-in-rivet via. The graphitic material is pressure infiltrated with a molten metal alloy so as to form a composite material with a plurality of cast-in rivets that increases at least one of the through-plane conductivity and the strength of the hybrid package and that forms at least one cast-in-rivet that increases an in-plane thermal conductivity of the hybrid package. | 2008-10-30 |
20080265404 | Structure and Methods of Processing for Solder Thermal Interface Materials for Chip Cooling - Assemblies for dissipating heat from integrated circuits and circuit chips are disclosed. The assemblies include a low melt solder as a thermal interface material (TIM) for the transfer of heat from a chip to a heat sink (HS), wherein the low melt solder has a melting point below the maximum operating temperature of the chip. Methods for making the assemblies are also disclosed. | 2008-10-30 |
20080265405 | SUBSTRATE WITH MULTI-LAYER INTERCONNECTION STRUCTURE AND METHOD OF MANUFACTURING THE SAME - The invention provides a substrate with multi-layer interconnection structure, which includes a substrate and a multi-layer interconnection structure formed on the substrate. The multi-layer interconnection structure is adhered to the substrate in partial areas. The invention also provides a method of manufacturing and recycling such substrate and a method of packaging electronic devices by using such substrate. The invention also provides a method of manufacturing multi-layer interconnection devices. | 2008-10-30 |
20080265406 | APPARATUS AND METHODS FOR COOLING SEMICONDUCTOR INTEGRATED CIRCUIT CHIP PACKAGES - Apparatus and methods are provided for integrating microchannel cooling modules within high-density electronic modules (e.g., chip packages, system-on-a-package modules, etc.,) comprising multiple high-performance IC chips. Electronic modules are designed such that high-performance (high power) IC chips are disposed in close proximity to the integrated cooling module (or cooling plate) for effective heat extraction. Moreover, electronic modules which comprise large surface area silicon carriers with multiple chips face mounted thereon are designed such that integrated silicon cooling modules are rigidly bonded to the back surfaces of such chips to increase the structural integrity of the silicon carriers. | 2008-10-30 |
20080265407 | WAFER-LEVEL BONDING FOR MECHANICALLY REINFORCED ULTRA-THIN DIE - An embodiment of the present invention is a technique to fabricate a package. A metal sheet having trenches is formed. A thinned wafer supported by a wafer support substrate (WSS) is formed. The metal sheet is bonded to the WSS-supported thinned wafer to form a metal bonded thinned wafer. The thinned wafer is diced to the trenches into die assemblies. | 2008-10-30 |
20080265408 | Highly Reliable Low Cost Structure for Wafer-Level Ball Grid Array Packaging - Methods, systems, and apparatuses for wafer-level integrated circuit (IC) packages are described. An IC package includes an IC chip, an insulating layer on the IC chip, a plurality of vias, a plurality of routing interconnects, and a plurality of bump interconnects. The IC chip has a plurality of terminals configured in an array on a surface of the IC chip. A plurality of vias through the insulating layer provide access to the plurality of terminals. Each of the plurality of routing interconnects has a first portion and a second portion. The first portion of each routing interconnect is in contact with a respective terminal of the plurality of terminals though a respective via, and the second portion of each routing interconnect extends over the insulating layer. Each bump interconnect of the plurality of bump interconnects is connected to the second portion of a respective routing interconnect of the plurality of routing interconnects. | 2008-10-30 |
20080265409 | INTEGRATED CIRCUIT HARD MASK PROCESSING SYSTEM - An integrated circuit hard mask processing system is provided including providing a substrate having an integrated circuit; forming an interconnect layer over the integrated circuit; applying a low-K dielectric layer over the interconnect layer; applying a hard mask layer over the low-K dielectric layer; forming a via opening through the hard mask layer and the low-K dielectric layer to the interconnect layer; applying a first fluid and a second fluid in the via opening for removing an overhang of the hard mask layer; depositing an interconnect metal in the via opening; and chemical-mechanical polishing the interconnect metal and the ultra low-K dielectric layer. | 2008-10-30 |
20080265410 | Wafer level package - A wafer level package includes a substrate, a passivation layer, an elastic layer, a first insulation layer, a metal trace, a second insulation layer, and a bump. The passivation layer is formed on the substrate, and has one pad. The elastic layer is formed on the passivation layer. The first insulation layer is formed on the passivation layer and the elastic layer, and has a junction in contact with the pad. The metal trace is formed on the first insulation layer. The second insulation layer is formed on the metal trace, and a groove is formed correspondingly above the elastic layer. The bump is formed in the groove. An annular trench can be further formed around the bump. A groove can be furthermore formed in the first insulation layer correspondingly below the bump. | 2008-10-30 |
20080265411 | Structure of packaging substrate and method for making the same - A structure of a packaging substrate and a method for making the same are disclosed, wherein the structure comprises: a substrate body having a circuit layer on the surface thereof, wherein the circuit layer has a plurality of conductive pads which are each formed in a flat long shape to enhance the elasticity of circuit layout; a solder mask disposed on the substrate body and having a plurality of openings corresponding to and exposing the conductive pads, wherein the openings are each formed in a flat long shape; and a metal bump disposed in each of the openings of the solder mask and on each of the corresponding conductive pads. | 2008-10-30 |
20080265412 | Semiconductor device and method of manufacturing thereof - A package substrate has wires that electrically connect a semiconductor chip, and surface side terminals that are solid cylindrical and whose one ends are electrically connected to the wires. The semiconductor chip is sealed by a sealing resin. A surface of the sealing resin is made to be a same height (a same surface) as end surfaces of other ends of the surface side terminals, by grinding, from a surface, a resin layer that is formed by molding so as to cover the semiconductor chip. The surface of the sealing resin is a ground surface formed by grinding. The end surfaces of the surface side terminals are exposed at the ground surface of the sealing resin. | 2008-10-30 |
20080265413 | SEMICONDUCTOR CHIP WITH POST-PASSIVATION SCHEME FORMED OVER PASSIVATION LAYER - The invention provides a semiconductor chip comprising an interconnecting structure over said passivation layer. The interconnecting structure comprises a first contact pad connected to a second contact pad exposed by an opening in a passivation layer. A metal bump is on the first contact pad and over multiple semiconductor devices, wherein the metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns | 2008-10-30 |
20080265414 | Electrically Conductive Composite - The present invention provides a conductive composite comprising: suspension matrix, metal nanoparticles suspended within the suspension matrix, wherein the conductive composite has a conductivity greater than 104 S cm | 2008-10-30 |
20080265415 | Nonlithographic Method to Produce Self-Aligned Mask, Articles Produced by Same and Compositions for Same - A method for forming a self aligned pattern on an existing pattern on a substrate comprising applying a coating of a solution containing a masking material in a carrier, the masking material having an affinity for portions of the existing pattern; and allowing at least a portion of the masking material to preferentially assemble to the portions of the existing pattern. The pattern may be comprised of a first set of regions of the substrate having a first atomic composition and a second set of regions of the substrate having a second atomic composition different from the first composition. The first set of regions may include one or more metal elements and the second set of regions may include a dielectric. The first and second regions may be treated to have different surface properties. Structures made in accordance with the method. Compositions useful for practicing the method. | 2008-10-30 |
20080265416 | Metal line formation using advaced CMP slurry - An integrated circuit and methods for forming the same are provided. The method includes providing a semiconductor substrate; forming a low-k dielectric layer over the semiconductor substrate; forming an opening extending from a top surface of the low-k dielectric layer into the low-k dielectric layer; forming a diffusion barrier layer in the opening, wherein the diffusion barrier layer has a top edge substantially level with a top surface of the low-k dielectric layer; filling a metal line in the opening; recessing a top surface of the metal line below a top edge of the diffusion barrier layer to form a recess; and forming a metal cap on the metal line, wherein the metal cap is substantially within the recess. | 2008-10-30 |
20080265417 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device, includes the steps of forming an insulating film on a semiconductor substrate having a silicide layer, forming a hole in the insulating film on the silicide layer, cleaning an inside of the hole and a surface of the silicide layer, forming a titanium layer on a bottom surface and an inner peripheral surface of the hole by a CVD method, forming a copper diffusion preventing barrier metal layer on the titanium layer in the hole, and burying a copper layer in the hole. | 2008-10-30 |
20080265418 | Method of Manufacturing Semiconductor Device, and Semiconductor Device - A semiconductor device including a substrate, a metal wiring on the substrate, an insulation film on the substrate covering the metal wiring, a connection hole in the insulation film which extends to a portion of the metal wiring, a via in the connection hole, and an alloy layer. The metal wiring includes a first metallic material, the alloy layer comprises a portion of the metal wiring and a second metallic material which is different than the first metallic material, and the via extends to the alloy layer. | 2008-10-30 |
20080265419 | SEMICONDUCTOR STRUCTURE COMPRISING AN ELECTRICALLY CONDUCTIVE FEATURE AND METHOD OF FORMING THE SAME - A method of forming a semiconductor structure comprises providing a semiconductor substrate comprising a layer of a dielectric material. A recess is provided in the layer of dielectric material. A first glue layer and a second glue layer are formed over the recess. The first glue layer comprises titanium and the second glue layer comprises tungsten nitride. The recess is filled with a material comprising tungsten. | 2008-10-30 |
20080265420 | METHOD OF FORMING A FULLY SILICIDED SEMICONDUCTOR DEVICE WITH INDEPENDENT GATE AND SOURCE/DRAIN DOPING AND RELATED DEVICE - A method of forming a fully silicided semiconductor device with independent gate and source/drain doping and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a substrate (the gate stack comprising a polysilicon layer and a blocking layer), and performing an ion implantation into an active region of the substrate adjacent to the gate stack (the blocking layer substantially blocks the ion implantation from the polysilicon layer). | 2008-10-30 |
20080265421 | Structure for Electrostatic Discharge in Embedded Wafer Level Packages - A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer. | 2008-10-30 |
20080265422 | STRUCTURE FOR CHARGE DISSIPATION DURING FABRICATION OF INTEGRATED CIRCUITS AND ISOLATION THEREOF - A structure for dissipating charge during fabrication of an integrated circuit. The structure includes: a substrate contact in a semiconductor substrate; one or more wiring levels over the substrate; one or more electrically conductive charge dissipation structures extending from a top surface of an uppermost wiring level of the one or more wiring levels through each lower wiring level of the one or more wiring levels to and in electrical contact with the substrate contact; and circuit structures in the substrate and in the one or more wiring layers, the charge dissipation structures not electrically contacting any the circuit structures in any of the one or more wiring levels, the one or more charge dissipation structures dispersed between the circuit structures. | 2008-10-30 |
20080265423 | LAYERED STRUCTURE FOR CORROSION RESISTANT INTERCONNECT CONTACTS - The present invention is directed to an interconnect for an implantable medical device. The interconnect includes a first conductive layer, a second conductive layer introduced over the first conductive layer, and a third conductive layer introduced over the second conductive layer. One of the first conductive layer, the second conductive layer, and the third conductive layer comprises titanium-niobium (Ti—Nb). | 2008-10-30 |
20080265424 | SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device of this invention includes forming metal pads on a Si substrate through a first oxide film, bonding the Si substrate and a holding substrate which bolsters the Si substrate through a bonding film, forming an opening by etching the Si substrate followed by forming a second oxide film on a back surface of the Si substrate and in the opening, forming a wiring connected to the metal pads after etching the second oxide film, forming a conductive terminal on the wiring, dicing from the back surface of the Si substrate to the bonding film and separating the Si substrate and the holding substrate. | 2008-10-30 |
20080265425 | Semiconductor Device and Method for Manufacturing the Same - A semiconductor device according to an embodiment can include a first group of dummy patterns and a second group of dummy patterns spaced apart from the first group of dummy patterns by a second spacing. The first group of dummy patterns can include a plurality of first dummy patterns formed separated from each other by a first spacing. The second group of dummy patterns can include a plurality of second dummy patterns formed separated from each other by the first spacing. The first dummy patterns and the second dummy patterns can have the same shape and size. | 2008-10-30 |
20080265426 | SEMICONDUCTOR STRUCTURE COMPRISING AN ELECTRICAL CONNECTION AND METHOD OF FORMING THE SAME - A method of forming a semiconductor structure comprises providing a substrate comprising a layer of a first material. A protection layer is formed over the layer of first material. At least one opening is formed in the layer of first material and the protection layer. A layer of a second material is formed over the layer of first material and the protection layer to fill the opening with the second material. A planarization process is performed to remove portions of the layer of second material outside the opening. At least a portion of the protection layer is not removed during the planarization process. An etching process is performed to remove the portions of the protection layer which were not removed during the planarization process. | 2008-10-30 |
20080265427 | Anchoring Structure and Intermeshing Structure - An anchoring structure for a metal structure of a semiconductor device includes an anchoring recess structure having at least one overhanging side wall, the metal structure being at least partly arranged within the anchoring recess structure. | 2008-10-30 |
20080265428 | VIA AND SOLDER BALL SHAPES TO MAXIMIZE CHIP OR SILICON CARRIER STRENGTH RELATIVE TO THERMAL OR BENDING LOAD ZERO POINT - A method of modifying via and solder ball shapes for maximizing semiconductor chip or silicon carrier strengths relative to thermal expansion and bending load zero points. The method entails modifying circular annular vias into elliptical annular vias so as to reduce stress concentration factors in the chip or carrier at the vias and solder balls. The reduction in the stress concentration is effected in the semiconductor chip or silicon carrier in regions proximate the vias and in wiring layers at the ends of the vias. | 2008-10-30 |
20080265429 | ELECTRONIC COMPONENT AND METHOD FOR MANUFACTURING THE SAME - An electronic component is provided with a first conductor, an insulator for covering a surface of the first conductor, a via hole penetrating the insulator, and a second conductor located on a surface of the insulator and electrically connected to the first conductor through the via hole, and includes a shielding film having conductivity, being interposed between the first conductor and the second conductor, and covering an interface between the first conductor and the insulator in the via hole by extending continuously at least from the surface of the first conductor constituting a bottom surface of the via hole to an inner wall surface of the via hole. | 2008-10-30 |
20080265430 | Semiconductor Device an Process for Fabricating the Same - A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiring part, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, and the other surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode, A second insulating layer is formed on one surface of the semiconductor substrate while exposing the forward end of the through-type electrode, and bump electrodes are formed on both electrodes. | 2008-10-30 |
20080265431 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - A semiconductor package and a method of manufacturing the package are provided. The semiconductor package comprises: a mounting substrate including a bond finger; at least one semiconductor chip disposed on the mounting substrate, the semiconductor chip including a bonding pad; a first molding member disposed on the mounting substrate so as to cover the bond finger and the bonding pad, the first molding member including an interconnection path disposed inside the first molding member so as to connect the bond finger to the bonding pad; a conductive element disposed in the interconnection path; and a second molding member overlying the first molding member. The interconnection path can be formed by a laser process. The conductive element can be formed by conductive nanoparticles or metal wires. | 2008-10-30 |
20080265432 | MULTI-CHIP PACKAGE AND METHOD OF MANUFACTURING THE MULTI-CHIP PACKAGE - A multi-chip package includes a mounting substrate, a first semiconductor chip, a second semiconductor chip, a reinforcing member, conductive wires and an encapsulant. The first semiconductor chip is disposed on the mounting substrate. The second semiconductor chip is disposed on the first semiconductor chip. An end portion of the second semiconductor chip protrudes from a side portion of the first semiconductor chip. A reinforcing member is disposed on an overlapping region of the second semiconductor chip where the second semiconductor chip overlaps with the side portion of the first semiconductor chip such that the reinforcing member decreases downward bending of the second semiconductor chip from the side portion of the first semiconductor chip. The conductive wires electrically connect the first and second semiconductor chips to the mounting substrate. The encapsulant is disposed on the mounting substrate to cover the first and second semiconductor chips and the conductive wires. | 2008-10-30 |
20080265433 | INTERPOSER, SEMICONDUCTOR CHIP MOUNTED SUB-BOARD, AND SEMICONDUCTOR PACKAGE - A semiconductor device can be manufactured with a high non-defect ratio, making it possible to easily guarantee the KGD (Known-Good-Die) of semiconductor chips, when configuring one packaged semiconductor device on which a plurality of semiconductor chips is mounted. Utilizing each semiconductor chip is made possible without limits on terminal position, pitch, signal arrangement, and so on. | 2008-10-30 |
20080265434 | SEMICONDUCTOR DEVICE HAVING A SEALING RESIN AND METHOD OF MANUFACTURING THE SAME - The semiconductor device | 2008-10-30 |
20080265435 | STRUCTURE AND METHOD FOR STRESS REDUCTION IN FLIP CHIP MICROELECTRONIC PACKAGES USING UNDERFILL MATERIALS WITH SPATIALLY VARYING PROPERTIES - A structure for a flip chip package assembly includes: a flip chip die with solder attach bumps; a substrate for receiving and solder attaching the flip chip die; an underfill material with spatially varying curing properties applied to fill voids between the flip chip die and the substrate, and for forming a fillet around the perimeter of the flip chip die and extending to the surface of the substrate; and wherein the portion of the underfill material forming the fillets is cured prior to curing the portion of the underfill material that fills the voids between the flip chip die and the substrate. | 2008-10-30 |
20080265436 | Semiconductor for Device and Its Manufacturing Method - An object of the present invention is to provide a semiconductor device by packaging a plurality of semiconductor chips three-dimensionally in a smaller thickness, with a smaller footprint, at the lower cost without using any other components and through a simpler manufacturing process of the semiconductor device than with the conventional methods. | 2008-10-30 |
20080265437 | Package Equipped with Semiconductor Chip and Method for Producing Same - A highly reliable, high-productivity package equipped with a semiconductor chip, and a method for producing the same. In a package ( | 2008-10-30 |
20080265438 | LIQUID EPOXY RESIN COMPOSITION AND SEMICONDUCTOR DEVICE - A liquid epoxy resin composition comprising (A) a liquid epoxy resin, (B) a curing agent, (C) an inorganic filler, (D) a hygroscopic agent, and optionally, (E) a fluxing agent has the advantages of void-free fill, shelf stability and solder connection, and is thus advantageously used in the fabrication of flip chip semiconductor devices by the no-flow method. | 2008-10-30 |
20080265439 | Die bonding agent and a semiconductor device made by using the same - A die bonding agent comprising (A) an epoxy resin, (B) a curing agent, and (C) an inorganic filler, the die bonding agent having a viscosity ratio, V | 2008-10-30 |