44th week of 2013 patent applcation highlights part 50 |
Patent application number | Title | Published |
20130288393 | TECHNIQUES FOR PATTERNING MULTILAYER MAGNETIC MEMORY DEVICES USING ION IMPLANTATION - A method of patterning a substrate includes providing a layer stack comprising a plurality of layers on a base portion of the substrate, where the layer stack includes an electrically conductive layer and a magnetic layer. The method further includes forming a first mask feature on an outer surface of the layer stack above a first protected region and a second mask feature on the outer surface of the layer stack above a second protected region, and directing ions towards the layer stack to magnetically isolate and electrically isolate the first protected region from the second protected region. | 2013-10-31 |
20130288394 | MAGNETIC MEMORY AND METHOD OF FABRICATION - A method of forming a magnetic memory includes providing a layer stack comprising a plurality of magnetic layers and a plurality of electrically conducting layers on a base portion of a substrate; forming a first mask feature on an outer surface of the layer stack above a first protected region and a second mask feature on the outer surface of the layer stack above a second protected region, the first mask feature and second mask feature defining an exposed region of the layer stack in portions of the layer stack therebetween; and directing ions towards exposed the region of the layer stack in an ion exposure that is effective to magnetically isolate the first protected region from the second protected region and to electrically isolate the first protected region from the second protected region without removal of the exposed region of the layer stack. | 2013-10-31 |
20130288395 | MAGNETIC TUNNEL JUNCTION DEVICE FABRICATION - In a particular embodiment, a method of forming a magnetic tunnel junction (MTJ) device includes forming an MTJ cap layer on an MTJ structure and forming a top electrode layer coupled to the MTJ cap layer. The top electrode layer includes at least two layers and one layer of the two layers includes a nitrified metal. | 2013-10-31 |
20130288396 | Embedded Magnetic Random Access Memory (MRAM) - A magnetic random access memory (MRAM) cell includes an embedded MRAM and an access transistor. The embedded MRAM is formed on a number of metal-interposed-in-interlayer dielectric (ILD) layers, which each include metal dispersed there through and are formed on top of the access transistor. A magneto tunnel junction (MTJ) is formed on top of a metal formed in the ILD layers that is in close proximity to a bit line. An MTJ mask is used to pattern the MTJ and is etched to expose the MTJ. Ultimately, metal is formed on top of the bit line and extended to contact the MTJ. | 2013-10-31 |
20130288397 | MAGNETORESISTIVE EFFECT ELEMENT, MAGNETIC MEMORY, AND METHOD OF MANUFACTURING MAGENTORESISTIVE EFFECT ELEMENT - According to one embodiment, a magnetoresistive effect element includes a first magnetic layer including perpendicular anisotropy to a film surface and an invariable magnetization direction, the first magnetic layer having a magnetic film including an element selected from a first group including Tb, Gd, and Dy and an element selected from a second group including Co and Fe, a second magnetic layer including perpendicular magnetic anisotropy to the film surface and a variable magnetization direction, and a nonmagnetic layer between the first magnetic layer and the second magnetic layer. The magnetic film includes amorphous phases and crystals whose particle sizes are 0.5 nm or more. | 2013-10-31 |
20130288398 | METHOD OF MANUFACTURING TUNNELING MAGNETORESISTIVE ELEMENT - [Object] To provide a method of manufacturing a perpendicular magnetization-type magnetic element, which does not need a step of depositing MgO. | 2013-10-31 |
20130288399 | ENERGY BEAM PROCESSING APPARATUS AND ENERGY BEAM PROCESSING METHOD - An energy beam processing apparatus cutting an interconnection by irradiating the interconnection with an energy beam while scanning, the energy beam processing apparatus including an irradiation unit which irradiates the interconnection with the energy beam while scanning; a measurement unit which measures a resistance value of the interconnection; and a control unit which controls a scan and an irradiation of the energy beam by the irradiation unit, the control unit controlling at least one of a scan rate and an irradiation intensity of the energy beam in accordance with a resistance value measured by the measurement unit, and controlling the irradiation unit to stop the irradiation of the energy beam when the resistance value measured by the measurement unit exceeds a prescribed value. | 2013-10-31 |
20130288400 | System and Method for Aligning Substrates for Multiple Implants - A system and method are disclosed for aligning substrates during successive process steps, such as ion implantation steps, is disclosed. Implanted regions are created on a substrate. After implantation, an image is obtained of the implanted regions, and a fiducial is provided on the substrate in known relation to at least one of the implanted regions. A thermal anneal process is performed on the substrate such that the implanted regions are no longer visible but the fiducial remains visible. The position of the fiducial may be used in downstream process steps to properly align pattern masks over the implanted regions. The fiducial also may be applied to the substrate before any ion implanting of the substrate is performed. The position of the fiducial with respect to an edge or a corner of the substrate may be used for aligning during downstream process steps. Other embodiments are described and claimed. | 2013-10-31 |
20130288401 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes: forming a first layer and a second layer in this order on a nitride semiconductor layer on a first main surface side of a substrate, the first and second layers having one of first and second arrangements, the first arrangement having the first layer of any of Au, V and Ta and the second layer of Ni, the second arrangement having the first layer of any of Ti, TiW, Al, W, Mo, Nb, Pt, Ta and V and the second layer of Au; forming a mask on a second main surface side of the substrate, the mask having an opening; applying an etching process to the substrate and the nitride semiconductor layer exposed in the opening of the mask; and determining an endpoint of the etching process by confirming elimination of the first layer in the opening of the mask. | 2013-10-31 |
20130288402 | ORGANIC EL DEVICE MANUFACTURING METHOD AND APPARATUS - An organic EL device manufacturing method includes a vapor deposition step of supplying a substrate, and while moving the substrate with a side thereof, on which an electrode layer is not provided, in contact with a surface of a can roller that rotates, discharging an evaporated organic layer forming material from a nozzle of a vapor deposition source to form an organic layer over a side of the substrate on which the electrode layer is provided, wherein the vapor deposition step is performed while, using a distance measuring section capable of measuring a first distance to the substrate supported by the can roller, and a position adjusting section capable of adjusting a second distance between the nozzle of the vapor deposition source and a surface of the substrate, control is performed by the position adjusting section so that the second distance is constant. | 2013-10-31 |
20130288403 | SYSTEMS AND METHODS OF AUTOMATICALLY DETECTING FAILURE PATTERNS FOR SEMICONDUCTOR WAFER FABRICATION PROCESSES - A system and method of automatically detecting failure patterns for a semiconductor wafer process is provided. The method includes receiving a test data set collected from testing a plurality of semiconductor wafers, forming a respective wafer map for each of the wafers, determining whether each respective wafer map comprises one or more respective objects, selecting the wafer maps that are determined to comprise one or more respective objects, selecting one or more object indices for selecting a respective object in each respective selected wafer map, determining a plurality of object index values in each respective selected wafer map, selecting an object in each respective selected wafer map, determining a respective feature in each of the respective selected wafer, classifying a respective pattern for each of the respective selected wafer maps and using the respective wafer fingerprints to adjust one or more parameters of the semiconductor fabrication process. | 2013-10-31 |
20130288404 | LIGHT EMITTING ELEMENT MANUFACTURING SYSTEM AND MANUFACTURING METHOD AND LIGHT EMITTING ELEMENT PACKAGE MANUFACTURING SYSTEM AND MANUFACTURING METHOD - In manufacturing light emitting element packages by coating the top surfaces of LED elements with the resin containing the fluorescent substance, in a resin supplying operation of discharging to supply the resin onto the LED elements in a wafer state, the light emission characteristics of the light that the resin emits when excitation light from a light source part is irradiated onto a light-passing member on which the resin is test supplied for light emission characteristic measurement are measured, and the appropriate resin supply quantity is revised based on the result of the measurement and light emission characteristics prescribed beforehand, to derive an appropriate resin supply quantity of the resin which should be supplied to the LED elements for practical production. | 2013-10-31 |
20130288405 | METHOD OF MANUFACTURING LIQUID EJECTION HEAD - The method of manufacturing a liquid ejection head includes: forming a first protective layer on one surface of the substrate; forming the wiring layer on another surface of the substrate; forming the insulating layer on the wiring layer, and then partially removing the insulating layer to partially expose the wiring layer; forming the electrode pad on an exposed portion of the wiring layer; forming a flow path member on the another surface of the substrate; forming a second protective layer on the one surface of the substrate after the formation of the flow path member; and partially removing at least one of the first protective layer and the second protective layer, and then forming the supply port leading from the one surface of the substrate to the another surface of the substrate. | 2013-10-31 |
20130288406 | METHOD FOR MANUFACTURING LIGHT EMITTING DIODE PACKAGE HAVING LED DIE FIXED BY ANISOTROPIC CONDUCTIVE PASTE - A method for packaging an LED, includes steps: providing a substrate and forming a plurality of pairs of electrodes on the substrate; positioning anisotropic conductive pastes on the substrate and attaching each anisotropic conductive paste to each pair of the electrodes; positioning an LED die on each anisotropic conductive paste and electrically connecting each LED die to each corresponding pair of the electrodes with the anisotropic conductive paste by hot compressing; forming an encapsulation on the substrate to cover the LED dies; and cutting the substrate to obtain individual LED packages. | 2013-10-31 |
20130288407 | METHOD FOR MANUFACTURING LED PACKAGE - A method for manufacturing an LED package includes providing a substrate including an insulating layer inlayed with first and second electrodes. The first and second electrodes define a chip fastening area. An LED chip is fastened on the chip fastening area and electrically connected to the first and second electrodes. A buffer layer including a shelter and grooves is brought to be located over the substrate wherein the shelter covers the chip fastening area and the grooves are located over portions of the substrate beside the first and second electrodes. A reflecting layer is formed in the grooves of the buffer layer by injecting liquid material into the grooves. The buffer layer is removed after the liquid material is solidified and a through hole is defined. An encapsulant is formed to cover the LED chip by injecting the encapsulant into the through hole and the chip fastening area. | 2013-10-31 |
20130288408 | METHOD FOR MANUFACTURING LED - A method for manufacturing an LED includes steps: providing a base and an LED chip disposed on the base; providing an optical element and disposing the optical element on the base to cover the LED chip; providing a phosphor film and disposing the phosphor film on the optical element; providing a holding plate with capillary holes and disposing the base on the holding plate; providing a mold, wherein the mold and the holding plate cooperatively form a receiving room which receives the base, the LED chip, the optical element and the phosphor film therein; extracting air from the receiving room through the capillary holes of the holding plate, and/or, blowing air toward the phosphor film, whereby the phosphor film is conformably attached onto the optical element; and solidifying the phosphor film on the optical element. | 2013-10-31 |
20130288409 | METHOD FOR MANUFACTURING LIGHT EMITTING DIODE - An exemplary method for manufacturing an LED includes steps: providing a substrate with a first electrode and a second electrode; providing an isosceles trapezoidal LED chip and making the LED chip electrically connecting the first electrode and the second electrode; providing a mold with a cavity and setting the mold on the substrate to make the LED chip received in the cavity, an outer periphery of the LED chip spaced from confronting edges of the mold defining the cavity to define a channel therebetween, and a width of the channel being uniform; providing phosphor glue and filling the phosphor glue in the channel to make the phosphor glue enclose the LED chip therein; solidifying the phosphor glue to form a phosphor layer covering the LED chip and removing the mold. | 2013-10-31 |
20130288410 | METHOD FOR MANUFACTURING LIQUID CRYSTAL PANEL - The present invention relates to a method for manufacturing a liquid crystal panel, which comprises steps of: forming a plurality of array thin films on a first glass substrate in turn to form an array substrate; cleaning the array substrate by ultrasound to eliminate bubbles and dirt between the array thin films. The present invention can change surface properties of each thin film of the array substrate for tightening the combination between the thin films and efficiently decreasing or minimizing bubbles and dirt between the thin films of the liquid crystal panel. | 2013-10-31 |
20130288411 | MANUFACTURING DEVICE AND METHOD OF LIQUID CRYSTAL PANEL - A manufacturing device of a liquid crystal panel includes a lower fixing plate, an upper fixing plate located in a standby position and being separated from the lower fixing plate, or located in a bonding position and being bonded to the lower fixing plate, and at least one ultraviolet light source disposed around the lower fixing plate and located above the lower fixing plate. The sealant is pre-cured after the TFT substrate and the CF substrate are bonded and before the liquid crystal panel is transferred to the next manufacturing device, which improves the corrosion resistance of the sealant to liquid crystals and air, and also reduces or even eliminates the influence to the sealant caused by the corrosion in the following manufacturing process of the sealant. Thus, damage to the liquid crystal panel can be prevented even the transferring device breakdowns when the liquid crystal panel is transferred. | 2013-10-31 |
20130288412 | HIGH YIELD SUBSTRATE ASSEMBLY - High yield substrate assembly. In accordance with a first method embodiment, a plurality of piggyback substrates are attached to a carrier substrate. The edges of the plurality of the piggyback substrates are bonded to one another. The plurality of piggyback substrates are removed from the carrier substrate to form a substrate assembly. The substrate assembly is processed to produce a plurality of integrated circuit devices on the substrate assembly. The processing may use manufacturing equipment designed to process wafers larger than individual instances of the plurality of piggyback substrates. | 2013-10-31 |
20130288413 | ORGANIC LIGHT-EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - An organic light-emitting display device including a substrate; at least one thin-film transistor (TFT) formed on the substrate; a planarizing layer covering the TFT; a pixel electrode, which is formed on the planarizing layer and is connected to the TFT; a protective layer surrounding an edge of the pixel electrode; a pixel defining layer (PDL), which has an overhang (OH) structure protruding more than the top surface of the protective layer, covers the protective layer and the edge of the pixel electrode, and exposes a portion of the pixel electrode surrounded by the protective layer; a counter electrode facing the pixel electrode; and an intermediate layer, which is interposed between the pixel electrode and the counter electrode and includes a light-emitting layer and at least one organic layer, where the thickness of the intermediate layer is greater than the thickness of the protective layer. | 2013-10-31 |
20130288414 | ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - An organic light-emitting display apparatus and a method of manufacturing the same, the apparatus including: a substrate; a first electrode formed on the substrate; an intermediate layer formed on the first electrode, including an organic emissive layer; a second electrode formed on the intermediate layer; and an insulating member interposed between the intermediate layer and the second electrode, on an edge of the first electrode. | 2013-10-31 |
20130288415 | LASER INDUCED THERMAL IMAGING APPARATUS AND FABRICATING METHOD OF ORGANIC LIGHT EMITTING DIODE USING THE SAME - A laser induced thermal imaging apparatus and a fabricating method of organic light emitting diodes using the same, which laminate an acceptor substrate and a donor film using a magnetic force in vacuum, and are used to form a pixel array on the acceptor substrate. A substrate stage includes a magnet or magnetic substance. The acceptor substrate has a pixel region for forming first, second, and third sub-pixels, and the donor film has an organic light emission layer to be transferred to the pixel region. A laser oscillator irradiates a laser to the donor film. A contact frame is adapted to be disposed between the substrate stage and the laser oscillator, and is used to form a magnetic force with the substrate stage. The contact frame includes an opening through which the laser passes. A contact frame feed mechanism moves the contact frame in a direction of the substrate stage. | 2013-10-31 |
20130288416 | SOLID STATE LIGHTING DEVICES AND ASSOCIATED METHODS OF MANUFACTURING - Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state light device includes a light emitting diode with an N-type gallium nitride (GaN) material, a P-type GaN material spaced apart from the N-type GaN material, and an indium gallium nitride (InGaN) material directly between the N-type GaN material and the P-type GaN material. At least one of the N-type GaN, InGaN, and P-type GaN materials has a non-planar surface. | 2013-10-31 |
20130288417 | SEMICONDUCTOR DEVICES HAVING NANOCHANNELS CONFINED BY NANOMETER-SPACED ELECTRODES - Semiconductor devices having integrated nanochannels confined by nanometer spaced electrodes, and VLSI (very large scale integration) planar fabrication methods for making the devices. A semiconductor device includes a bulk substrate and a first metal layer formed on the bulk substrate, wherein the first metal layer comprises a first electrode. A nanochannel is formed over the first metal layer, and extends in a longitudinal direction in parallel with a plane of the bulk substrate. A second metal layer is formed over the nanochannel, wherein the second metal layer comprises a second electrode. A top wall of the nanochannel is defined at least in part by a surface of the second electrode and a bottom wall of the nanochannel is defined by a surface of the first electrode. | 2013-10-31 |
20130288418 | METHOD FOR FABRICATING A THREE-DIMENSIONAL THIN-FILM SEMICONDUCTOR SUBSTRATE FROM A TEMPLATE - A method is presented for fabrication of a three-dimensional thin-film solar cell semiconductor substrate from a template. A semiconductor template having three-dimensional surface features comprising a top surfaces substantially aligned along a (100) crystallographic plane of semiconductor template and a plurality of inverted pyramidal cavities defined by sidewalls substantially aligned along a (111) crystallographic plane is formed according to an anisotropic etching process. A dose of relatively of high energy light-mass species is implanted in the template at a uniform depth and parallel to the top surfaces and said sidewalls defining the inverted pyramidal cavities of the template. The semiconductor template is annealed to convert the dose of relatively of high energy light-mass species to a mechanically-weak-thin layer. The semiconductor template is cleaved along the mechanically-weak-thin layer to release a three-dimensional thin-film semiconductor substrate from the semiconductor template. | 2013-10-31 |
20130288419 | SOLID-STATE IMAGING DEVICE, MANUFACTURING METHOD THEREOF, ELECTRONIC APPARATUS, AND SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a region including a semiconductor element on the substrate, and at least one guard ring structure provided around the region. The guard ring structure includes a guard ring and at least one portion comprised of the substrate. | 2013-10-31 |
20130288420 | FABRICATING METHOD OF SEMICONDUCTOR DEVICE - A method of making a semiconductor device includes forming wiring on a first surface of a first substrate, removing a portion of a second surface of the first substrate to reduce a thickness of the first substrate, forming an oxide film on the second surface of the first substrate based on an oxidation process performed within a temperature range, and removing the oxide film. The temperature range may be below a melting temperature of the wiring, and the oxide film is formed to a depth that includes one or more defects below the second surface of the first substrate. Removal of the oxide film results in removing a portion of the first substrate that includes the one or more effects. | 2013-10-31 |
20130288421 | METHOD OF FABRICATING A DIFFERENTIAL DOPED SOLAR CELL - A method of fabricating a differential doped solar cell is provided. The method comprises the steps of (a) providing a light doped semiconductor substrate; (b) forming a heavy doped layer having the same type of dopant used in step (a) on a front surface of the semiconductor substrate; and (c) forming an emitter layer having a different type of dopant used in step (a) on a surface of the heavy doped layer to constitute a p-n junction with the heavy doped layer. | 2013-10-31 |
20130288422 | SOLID-STATE IMAGE SENSOR, METHOD OF MANUFACTURING THE SAME, AND IMAGE PICKUP APPARATUS - Disclosed is a solid-state image sensor including a photoelectric converter, a charge detector, and a transfer transistor. The photoelectric converter stores a signal charge that is subjected to photoelectric conversion. The charge detector detects the signal charge. The transfer transistor transfers the signal charge from the photoelectric converter to the charge detector. In the solid-state image sensor, the transfer transistor includes a gate insulating film, a gate electrode formed on the gate insulating film, a first spacer formed on a sidewall of the gate electrode on a side of the photoelectric converter, and a second spacer formed on another sidewall of the gate electrode on a side of the charge detector. The first spacer is longer than the second spacer. | 2013-10-31 |
20130288423 | METHOD OF MANUFACTURING SOLAR CELL AND SOLAR CELL - Provided is a method capable of easily manufacturing a back contact solar cell with high photoelectric conversion efficiency. A semiconductor layer having a first conductivity which is the same as that of a semiconductor substrate is formed substantially entirely on the principal surface of the semiconductor substrate inclusive of a surface of an insulation layer. A portion of the semiconductor layer located on the insulation layer is removed, and thereby an opening is formed. The insulation layer exposed through the opening is removed while the semiconductor layer is used as a mask, and thereby a surface of a first semiconductor region is partially exposed. Electrodes which are electrically connected to the surface of the first semiconductor region and to a surface of the semiconductor layer respectively are formed. | 2013-10-31 |
20130288424 | CONTACT AND INTERCONNECT METALLIZATION FOR SOLAR CELLS - A fabrication line includes a texturizing module configured to texture a substrate, an emitter module configured to form an emitter region, a passivation layer module configured to form a passivation layer, a barrier contact module configured to form a barrier contact region, a firing module configured to anneal the barrier contact region, a top metal contact module configured to form a top metal contact region, and a soldering module configured to solder the barrier contact region to the top metal contact region. The modules are integrated by one or more automated substrate handlers into a single fabrication line. A method for fabricating a solar cell includes sequentially, in an automated fabrication line: doping a dopant in a substrate; disposing a passivation layer; disposing and annealing a barrier metal paste to form a barrier contact; and disposing and annealing a metal contact paste to form a top metal contact region. | 2013-10-31 |
20130288425 | END POINT DETECTION FOR BACK CONTACT SOLAR CELL LASER VIA DRILLING - Methods and structures for fabricating photovoltaic back contact solar cells having multi-level metallization using laser via drilling end point detection are provided. | 2013-10-31 |
20130288426 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - In a semiconductor device in which transistors are formed in a plurality of layers to form a stack structure, a method for manufacturing the semiconductor device formed by controlling the threshold voltage of the transistors formed in the layers selectively is provided. Further, a method for manufacturing the semiconductor device by which oxygen supplying treatment is effectively performed is provided. First oxygen supplying treatment is performed on a first oxide semiconductor film including a first channel formation region of a transistor in the lower layer. Then, an interlayer insulating film including an opening which is formed so that the first channel formation region is exposed is formed over the first oxide semiconductor film and second oxygen supplying treatment is performed on a second oxide semiconductor film including a second channel formation region over the interlayer insulating film and the exposed first channel formation region. | 2013-10-31 |
20130288427 | Methods Of Fabricating Dielectric Films From Metal Amidinate Precursors - Described are methods for atomic layer deposition of films comprising mixed metal oxides using metal amidinate precursors. The mixed metal oxide films may comprise a lanthanide and a transition metal such as hafnium, zirconium or titanium. Such mixed metal oxide films may be used as dielectric layers in capacitors, transistors, dynamic random access memory cells, resistive random access memory cells, flash memory cells and display panels. | 2013-10-31 |
20130288428 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - A method for producing a semiconductor device, including a semiconductor chip, for improving production efficiency and the flexibility of production design is provided. The method comprises: preparing a semiconductor chip having a first main surface on which an electroconductive member is formed; preparing a supporting structure in which, over a support configured to transmit radiation, a radiation curable pressure-sensitive adhesive layer and a first thermosetting resin layer are laminated in this order; arranging the semiconductor chips on the first thermosetting resin layer to face the first thermosetting resin layer to a second main surface of the semiconductor chips opposite to the first main surface; laminating a second thermosetting resin layer over the first thermosetting resin layer to cover the semiconductor chips; and curing the radiation curable pressure-sensitive adhesive layer by irradiating from the support side to peel the radiation curable pressure-sensitive adhesive layer from the first thermosetting resin layer. | 2013-10-31 |
20130288429 | METHOD OF ENCAPSULATION OF A MICROCOMPONENT - A method for encapsulating a microcomponent positioned on a substrate, including: a) production of an electrical contact pad on the substrate; b) production of a portion of sacrificial material covering the microcomponent and the electrical contact pad; c) production of an encapsulation layer covering the sacrificial material and a first face of the substrate; d) production, through the substrate, of a hole aligned with the electrical contact pad and emerging at the portion of sacrificial material; e) elimination of the portion of sacrificial material through the hole; f) production, in the hole, of a conductive portion electrically connected to the electrical contact pad, forming a conductive via. | 2013-10-31 |
20130288430 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF - A semiconductor device which includes a first semiconductor chip, a second semiconductor chip flip-chip bonded to the first semiconductor chip, a resin portion for sealing the first semiconductor chip and the second semiconductor chip such that a lower surface of the first semiconductor chip and an upper surface of the second semiconductor chip are exposed and a side surface of the first semiconductor chip is covered, and a post electrode which pierces the resin portion and is connected to the first semiconductor chip, and a manufacturing method thereof are provided. | 2013-10-31 |
20130288431 | PACKAGE SUBSTRATES, SEMICONDUCTOR PACKAGES HAVING THE SAME, AND METHODS OF FABRICATING THE SEMICONDUCTOR PACKAGES - A package substrate, a semiconductor package having the same, and a method for fabricating the semiconductor package. The semiconductor package includes a semiconductor chip, a package substrate, and a molding layer. The package substrate provides a region mounted with the semiconductor chip. The molding layer is configured to mold the semiconductor chip. The package substrate includes a first opening portion that provides an open region connected electrically to the semiconductor chip and extends beyond sides of the semiconductor chip to be electrically connected to the semiconductor chip. | 2013-10-31 |
20130288432 | METHOD OF MANUFACTURING LEADLESS INTEGRATED CIRCUIT PACKAGES HAVING ELECTRICALLY ROUTED CONTACTS - A method of manufacturing a leadless integrated circuit (IC) package comprising an IC chip mounted on a metal leadframe and a plurality of electrical contacts electrically coupled to the IC chip. The IC chip, the electrical contacts, and a portion of the metal leadframe are covered with an encapsulation compound, with portions of the electrical contacts exposed on a bottom surface of the encapsulation compound. The electrical contacts of the IC package having metal traces connecting bonding areas on a top surface thereof and contact areas on a bottom surface thereof, wherein at least some of the bonding areas are laterally disposed from the contact areas connected thereto. | 2013-10-31 |
20130288433 | HIGH DENSITY CHIP PACKAGES, METHODS OF FORMING, AND SYSTEMS INCLUDING SAME - Methods and devices for multi-chip stacks are shown. A method is shown that assembles multiple chips into stacks by stacking wafers prior to dicing into individual chips. Methods shown provide removal of defective chips and their replacement during the assembly process to improve manufacturing yield. | 2013-10-31 |
20130288434 | COLLAPSABLE GATE FOR DEPOSITED NANOSTRUCTURES - A disposable material layer is first deposited on a graphene layer or a carbon nanotube (CNT). The disposable material layer includes a material that is less inert than graphene or CNT so that a contiguous dielectric material layer can be deposited at a target dielectric thickness without pinholes therein. A gate stack is formed by patterning the contiguous dielectric material layer and a gate conductor layer deposited thereupon. The disposable material layer shields and protects the graphene layer or the CNT during formation of the gate stack. The disposable material layer is then removed by a selective etch, releasing a free-standing gate structure. The free-standing gate structure is collapsed onto the graphene layer or the CNT below at the end of the selective etch so that the bottom surface of the contiguous dielectric material layer contacts an upper surface of the graphene layer or the CNT. | 2013-10-31 |
20130288435 | CET AND GATE CURRENT LEAKAGE REDUCTION IN HIGH-K METAL GATE ELECTRODE STRUCTURES BY HEAT TREATMENT AFTER DIFFUSION LAYER REMOVAL - When forming high-k metal gate electrode structures by providing the gate dielectric material in an early manufacturing stage, the heat treatment or anneal process may be applied after incorporating work function metal species and prior to capping the gate dielectric material with a metal-containing electrode material. In this manner, the CET for a given physical thickness for the gate dielectric layer may be significantly reduced. | 2013-10-31 |
20130288436 | Aqueous Cleaning Techniques and Compositions for use in Semiconductor Device Manufacturing - Some embodiments relate to a manufacturing method for a semiconductor device. In this method, a semiconductor workpiece, which includes a metal gate electrode thereon, is provided. An opening is formed in the semiconductor workpiece to expose a surface of the metal gate. Formation of the opening leaves a polymeric residue on the workpiece. To remove the polymeric residue from the workpiece, a cleaning solution that includes an organic alkali component is used. | 2013-10-31 |
20130288437 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device including a semiconductor substrate having a logic formation region where a logic device is formed; a first impurity region formed in an upper surface of the semiconductor substrate in the logic formation region; a second impurity region formed in an upper surface of the semiconductor substrate in the logic formation region; a third impurity region formed in an upper surface of the first impurity region and having a conductivity type different from that of the second impurity region; a fourth region formed in an upper surface of the second impurity region and having a conductivity type different from that of the second impurity region; a first silicide film formed in an upper surface of the third impurity region; a second silicide film formed in an upper surface of the fourth impurity region and having a larger thickness than the first silicide film. | 2013-10-31 |
20130288438 | SELECTIVE LASER ANNEALING PROCESS FOR BURIED REGIONS IN A MOS DEVICE - Laser anneal to melt regions of a microelectronic device buried under overlying materials, such as an interlayer dielectric (ILD). Melting temperature differentiation is employed to selectively melt a buried region. In embodiments a buried region is at least one of a gate electrode and a source/drain region. Laser anneal may be performed after contact formation with contact metal coupling energy into the buried layer for the anneal. | 2013-10-31 |
20130288439 | Zener Diode Structure and Process - A vertically stacked, planar junction Zener diode is concurrently formed with epitaxially grown FET raised S/D terminals. The structure and process of the Zener diode are compatible with Gate-Last high-k FET structures and processes. Lateral separation of diode and transistor structures is provided by modified STI masking. No additional photolithography steps are required. In some embodiments, the non-junction face of the uppermost diode terminal is silicided with nickel to additionally perform as a copper diffusion barrier. | 2013-10-31 |
20130288440 | MINIMIZING LEAKAGE CURRENT AND JUNCTION CAPACITANCE IN CMOS TRANSISTORS BY UTILIZING DIELECTRIC SPACERS - A semiconductor structure and method for forming dielectric spacers and epitaxial layers for a complementary metal-oxide-semiconductor field effect transistor (CMOS transistor) are disclosed. Specifically, the structure and method involves forming dielectric spacers that are disposed in trenches and are adjacent to the silicon substrate, which minimizes leakage current. Furthermore, epitaxial layers are deposited to form source and drain regions, wherein the source region and drain regions are spaced at a distance from each other. The epitaxial layers are disposed adjacent to the dielectric spacers and the transistor body regions (i.e., portion of substrate below the gates), which can minimize transistor junction capacitance. Minimizing transistor junction capacitance can enhance the switching speed of the CMOS transistor. Accordingly, the application of dielectric spacers and epitaxial layers to minimize leakage current and transistor junction capacitance in CMOS transistors can enhance the utility and performance of the CMOS transistors in low power applications. | 2013-10-31 |
20130288441 | METHOD FOR FORMING IMPURITY REGION OF VERTICAL TRANSISTOR AND METHOD FOR FABRICATING VERTICAL TRANSISTOR USING THE SAME - A method for forming an impurity region of a vertical transistor includes forming an impurity ion junction region within a semiconductor substrate, and forming a trench by etching the semiconductor substrate in which the impurity ion junction region is formed. The etching process is performed to remove a portion of the impurity ion junction region, so that a remaining portion of the impurity ion junction region is exposed to a lower side wall of the trench to serve as a buried bit line junction region. | 2013-10-31 |
20130288442 | METHOD FOR FORMING IMPURITY REGION OF VERTICAL TRANSISTOR AND METHOD FOR FABRICATING VERTICAL TRANSISTOR USING THE SAME - A method for forming an impurity region of a vertical transistor includes forming an impurity ion junction region within a semiconductor substrate, and forming a trench by etching the semiconductor substrate in which the impurity ion junction region is formed. The etching process is performed to remove a portion of the impurity ion junction region, so that a remaining portion of the impurity ion junction region is exposed to a lower side wall of the trench to serve as a buried bit line junction region. | 2013-10-31 |
20130288443 | Methods for Reduced Gate Resistance FINFET - Methods for forming reduced gate resistance finFETs. Methods for a metal gate transistor structure are disclosed including forming a plurality of semiconductor fins formed over a semiconductor substrate, the fins being arranged in parallel and spaced apart; a metal containing gate electrode formed over the semiconductor substrate and overlying a channel gate region of each of the semiconductor fins, and extending over the semiconductor substrate between the semiconductor fins; an interlevel dielectric layer overlying the gate electrode and the semiconductor substrate; and a plurality of contacts disposed in the interlevel dielectric layer and extending through the interlevel dielectric layer to the gate electrode; a low resistance metal strap formed over the interlevel dielectric layer and coupled to the gate electrode by the plurality of contacts; wherein the plurality of contacts are spaced apart from the channel gate regions of the semiconductor fins. Additional methods are disclosed. | 2013-10-31 |
20130288444 | High-Voltage Transistor Architectures, Processes Of Forming Same, And Systems Containing Same - An apparatus includes a first device with a metal gate and a drain well that experiences a series resistance that drops a drain contact voltage from 10 V to 4-6 V at a junction between the drain well and a channel under the gate. The apparatus includes an interlayer dielectric layer (ILD0) disposed above and on the drain well and a salicide drain contact in the drain well. The apparatus also includes a subsequent device that is located in a region different from the first device that operates at a voltage lower than the first device. | 2013-10-31 |
20130288445 | SEMICONDUCTOR DEVICE WITH GATE ELECTRODE INCLUDING A CONCAVE PORTION - A method of manufacturing a semiconductor device including a transistor. The method includes forming a channel region by implanting impurity ions of a second conductive type into an element forming region that is formed on one side of a substrate and is partitioned by an element isolation insulating film, forming a trench in said channel region formed on said one side of said substrate, covering side faces and a bottom face of said trench with a gate insulating film by forming said gate insulating film on said one side of said substrate, forming a gate electrode so as to bury an inside of said trench, patterning said gate electrode in a predetermined shape; and forming a source region and a drain region by implanting impurity ions of a first conductive type on both sides of said channel region. | 2013-10-31 |
20130288446 | SEMICONDUCTOR STRUCTURE AND METHOD FOR SLIMMING SPACER - A semiconductor structure including a substrate and a gate structure disposed on the substrate is disclosed. The gate structure includes a gate dielectric layer disposed on the substrate, a gate material layer disposed on the gate dielectric layer and an outer spacer with a rectangular cross section. The top surface of the outer spacer is lower than the top surface of the gate material layer. | 2013-10-31 |
20130288447 | VERTICAL POLYSILICON-GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR - A vertical heterojunction bipolar transistor (HBT) includes doped polysilicon having a doping of a first conductivity type as a wide-gap-emitter with an energy bandgap of about 1.12 eV and doped single crystalline Ge having a doping of the second conductivity type as the base having the energy bandgap of about 0.66 eV. Doped single crystalline Ge having of doping of the first conductivity type is employed as the collector. Because the base and the collector include the same semiconductor material, i.e., Ge, having the same lattice constant, there is no lattice mismatch issue between the collector and the base. Further, because the emitter is polycrystalline and the base is single crystalline, there is no lattice mismatch issue between the base and the emitter. | 2013-10-31 |
20130288448 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. A semiconductor substrate is provided. The semiconductor substrate has a patterned isolation layer and the patterned isolation layer has an opening exposing a silicon area of the semiconductor substrate. A silicon rich layer is formed on the sidewalls of the opening. An epitaxial process is performed to form an epitaxial structure on the silicon area in the opening. | 2013-10-31 |
20130288449 | SEMICONDUCTOR DIODE AND METHOD OF MANUFACTURE | 2013-10-31 |
20130288450 | SHALLOW TRENCH FORMING METHOD - A method for forming a trench filled with an insulator crossing a single-crystal silicon layer and a first SiO | 2013-10-31 |
20130288451 | SOI DEVICE WITH DTI AND STI - A method of forming an SOI structure which includes providing a semiconductor on insulator (SOI) substrate having an SOI layer, an intermediate buried oxide (BOX) layer and a bottom substrate; patterning the SOI layer to form first and second openings in the SOI layer; extending the first openings into the bottom substrate; enlarging the first openings within the bottom substrate; filling the first and second openings with an insulator material to form deep trench isolations (DTIs) from the first openings and shallow trench isolations (STIs) from the second openings; implanting in the bottom substrate between the DTIs to form wells; and forming semiconductor devices in the SOI layer between the DTIs with each semiconductor device being separated from an adjacent semiconductor device by an STI. | 2013-10-31 |
20130288452 | CORNER TRANSISTOR SUPPRESSION - The threshold voltage of parasitic transistors formed at corners of shallow trench isolation regions is increased and mobility decreased by employing a high-K dielectric material. Embodiments include STI regions comprising a liner of a high-K dielectric material extending proximate trench corners. Embodiments also include STI regions having a recess formed in the trench, wherein the recess contains a high-K dielectric material, in the form of a layer or spacer, extending proximate trench corners. | 2013-10-31 |
20130288453 | METHOD OF MANUFACTURING LAMINATED WAFER BY HIGH TEMPERATURE LAMINATING METHOD - A method of manufacturing a laminated wafer is provided by forming a silicon film layer on a surface of an insulating substrate comprising the steps in the following order of: applying a surface activation treatment to both a surface of a silicon wafer or a silicon wafer to which an oxide film is layered and a surface of the insulating substrate followed by laminating in an atmosphere of temperature exceeding 50° C. and lower than 300° C., applying a heat treatment to a laminated wafer at a temperature of 200° C. to 350° C., and thinning the silicon wafer by a combination of grinding, etching and polishing to form a silicon film layer. | 2013-10-31 |
20130288454 | METHOD FOR SEPARATING A PRODUCT SUBSTRATE FROM A CARRIER SUBSTRATE - The invention relates to a method for stripping a product substrate from a carrier substrate which is connected to the product substrate by an interconnect layer with the following steps, especially the following sequence:
| 2013-10-31 |
20130288455 | METHOD OF FORMING A FREESTANDING SEMICONDUCTOR WAFER - A method of forming a freestanding semiconductor wafer includes providing a semiconductor substrate including a semiconductor layer having a back surface and an upper surface opposite the back surface, wherein the semiconductor layer comprises at least one permanent defect between the upper surface and back surface, removing a portion of the back surface of the semiconductor layer and the permanent defect from the semiconductor layer, and forming a portion of the upper surface after removing a portion of the back surface and the permanent defect. | 2013-10-31 |
20130288456 | SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A manufacturing method of a semiconductor device comprises the following steps. First, a substrate is provided, at least one fin structure is formed on the substrate, and a metal layer is then deposited on the fin structure to form a salicide layer. After depositing the metal layer, the metal layer is removed but no RTP is performed before the metal layer is removed. Then a RTP is performed after the metal layer is removed. | 2013-10-31 |
20130288457 | METHOD FOR MAKING EPITAXIAL STRUCTURE - A method for making epitaxial structure is provided. The method includes providing a substrate having an epitaxial growth surface, placing a graphene layer on the epitaxial growth surface, and epitaxially growing an epitaxial layer on the epitaxial growth surface. The graphene layer includes a number of apertures to expose a part of the epitaxial growth surface. The epitaxial layer is grown from the exposed part of the epitaxial growth surface and through the aperture. | 2013-10-31 |
20130288458 | METHOD FOR MAKING EPITAXIAL STRUCTURE - A method for making epitaxial structure is provided. The method includes providing a substrate having an epitaxial growth surface, growing a buffer layer on the epitaxial growth surface; placing a graphene layer on the buffer layer; epitaxially growing an epitaxial layer on the buffer layer; and removing the substrate. The graphene layer includes a number of apertures to expose a part of the buffer layer. The epitaxial layer is grown from the exposed part of the buffer layer and through the apertures. | 2013-10-31 |
20130288459 | METHOD FOR MAKING EPITAXIAL STRUCTURE - A method for making epitaxial structure is provided. The method includes providing a substrate having an epitaxial growth surface, patterning the epitaxial growth surface; placing a graphene layer on the patterned epitaxial growth surface, and epitaxially growing an epitaxial layer on the epitaxial growth surface. The graphene layer includes a number of apertures to expose a part of the patterned epitaxial growth surface. The epitaxial layer is grown from the exposed part of the patterned epitaxial growth surface and through the aperture. | 2013-10-31 |
20130288460 | PROCESS CHAMBER HAVING SEPARATE PROCESS GAS AND PURGE GAS REGIONS - Embodiments of the present invention generally relate to chambers and methods of processing substrates therein. The chambers generally include separate process gas and purge gas regions. The process gas region and purge gas region each have a respective gas inlet and gas outlet. The methods generally include positioning a substrate on a substrate support within the chamber. The plane of the substrate support defines the boundary between a process gas region and purge gas region. Purge gas is introduced into the purge gas region through at least one purge gas inlet, and removed from the purge gas region using at least one purge gas outlet. The process gas is introduced into the process gas region through at least one process gas inlet, and removed from the process gas region through at least one process gas outlet. The process gas is thermally decomposed to deposit a material on the substrate. | 2013-10-31 |
20130288461 | Metal-Oxide-Semiconductor High Electron Mobility Transistors and Methods of Fabrication - A method of fabricating Group III-V semiconductor metal oxide semiconductor (MOS) and III-V MOS devices are described. | 2013-10-31 |
20130288462 | TELLURIUM COMPOUNDS USEFUL FOR DEPOSITION OF TELLURIUM CONTAINING MATERIALS - Precursors for use in depositing tellurium-containing films on substrates such as wafers or other microelectronic device substrates, as well as associated processes of making and using such precursors, and source packages of such precursors. The precursors are useful for deposition of Ge | 2013-10-31 |
20130288463 | METHOD FOR PRODUCING THIN LAYERS OF CRYSTALLINE OR POLYCRYSTALLINE MATERIALS - Method for making thin crystalline or polycrystalline layers. The method includes electrochemically etching a crystalline silicon template to form a porous double layer thereon, the double layer including a highly porous deeper layer and a less porous shallower layer. The shallower layer is irradiated with a short laser pulse selected to recrystallize the shallower layer resulting in a crystalline layer. Silicon is deposited on the recrystallized shallower layer and the silicon is irradiated with a short laser pulse selected to crystalize the silicon leaving a layer of crystallized silicon on the template. Thereafter, the layer of crystallized silicon is separated from the template. The process of the invention can be used to make optoelectronic devices. | 2013-10-31 |
20130288464 | METHOD FOR MAKING EPTAXIAL STRUCTURE - A method for making an epitaxial structure includes following steps. A substrate having an epitaxial growth surface is provided. A first epitaxial layer is epitaxially grown on the epitaxial growth surface. A graphene layer is applied on the first epitaxial layer. A second epitaxial layer is epitaxially grown on the first epitaxial layer. | 2013-10-31 |
20130288465 | METHODS FOR FILLING HIGH ASPECT RATIO FEATURES ON SUBSTRATES - Methods for filling high aspect ratio features are provided herein. In some embodiments, method of filling a high aspect ratio feature formed in a substrate includes implanting a first species using a first plasma into first surfaces of a first layer formed along the surfaces of the high aspect ratio feature to form implanted first surfaces such that a second species subsequently deposited atop the first layer has an increased mobility along the implanted first surfaces relative to the first surfaces, wherein the first layer substantially prevents the second species from diffusing completely through the first layer; and subsequently filling the high aspect ratio feature with the second species. | 2013-10-31 |
20130288466 | Methods of Forming Doped Regions in Semiconductor Substrates - Some embodiments include methods of forming one or more doped regions in a semiconductor substrate. Plasma doping may be used to form a first dopant to a first depth within the substrate. The first dopant may then be impacted with a second dopant to knock the first dopant to a second depth within the substrate. In some embodiments the first dopant is p-type (such as boron) and the second dopant is neutral type (such as germanium). In some embodiments the second dopant is heavier than the first dopant. | 2013-10-31 |
20130288467 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device capable of suppressing generation of a high electric field and preventing a dielectric breakdown from occurring, and a method of manufacturing the same. The method of manufacturing a semiconductor device includes (a) preparing an n+ substrate to be a ground constituted by a silicon carbide semiconductor of a first conductivity type, (b) forming a recess structure surrounding an element region on the n+ substrate by using a resist pattern, and (c) forming a guard ring injection layer to be an impurity layer of a second conductivity type in a recess bottom surface and a recess side surface in the recess structure by impurity injection through the resist pattern, and a corner portion of the recess structure is covered with the impurity layer. | 2013-10-31 |
20130288468 | METHODS OF FORMING SELF-ALIGNED CONTACTS FOR A SEMICONDUCTOR DEVICE FORMED USING REPLACEMENT GATE TECHNIQUES - One illustrative method disclosed herein involves forming an etch stop layer above a plurality of sacrificial gate structures, performing an angled ion implant process to implant an etch-inhibiting species into less than an entirety of the etch stop layer, and forming a layer of insulating material above the etch stop layer. The method further includes removing the sacrificial gate structures, forming replacement gate structures, forming a hard mask layer above the replacement gate structures and layer of insulating material, forming a patterned hard mask layer, performing another etching process through the patterned hard mask layer to define an opening in the layer of insulating material to expose a portion of the etch stop layer, performing another etching process on the exposed portion to define a contact opening therethrough that exposes a doped region and forming a conductive contact in the opening that is conductively coupled to the doped region. | 2013-10-31 |
20130288469 | METHODS AND APPARATUS FOR IMPLANTING A DOPANT MATERIAL - Methods and apparatus for implanting a dopant material are provided herein. In some embodiments, a method of processing a substrate disposed within a process chamber may include (a) implanting a dopant material into a surface of the substrate to form a doped layer in the substrate and an elemental dopant layer atop the doped layer; (b) removing at least some of the elemental dopant layer from atop the surface of the substrate; and (c) implanting the dopant material into the doped layer of the substrate; wherein (a)-(c) are performed without removing the substrate from the process chamber; and wherein (a)-(c) are repeated until at least one of a desired dopant implantation depth or a desired dopant implantation density is achieved. | 2013-10-31 |
20130288470 | IMPURITY DIFFUSION METHOD, SUBSTRATE PROCESSING APPARATUS, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The impurity diffusion method includes: transferring an object on which the thin film is formed into a processing chamber (operation | 2013-10-31 |
20130288471 | METHODS OF FORMING SELF-ALIGNED CONTACTS FOR A SEMICONDUCTOR DEVICE - One illustrative method disclosed herein involves forming gate structures for first and second spaced-apart transistors above a semiconducting substrate, forming an etch stop layer above the substrate and the gate structures, performing at least one angled ion implant process to implant at least one etch-inhibiting species into less than an entirety of the etch stop layer, after performing at least one angled ion implant process, forming a layer of insulating material above the etch stop layer, performing at least one first etching process to define an opening in the layer of insulating material and thereby expose a portion of the etch stop layer, performing at least one etching process on the exposed portion of the etch stop layer to define a contact opening therethrough that exposes a doped region formed in the substrate, and forming a conductive contact in the opening that is conductively coupled to the doped region. | 2013-10-31 |
20130288472 | METHODS OF FABRICATING SEMICONDUCTOR DEVICES HAVING BURIED CHANNEL ARRAY - A method of fabricating a semiconductor device comprises forming a first and a second parallel field regions in a substrate, the parallel field regions are extended in a first direction, forming a first and a second gate capping layer in a first and a second gate trench formed in the substrate respectively, removing the gate capping layers partially so that a first landing pad hole is expanded to overlap the gate capping layers buried in the substrate partially, forming a landing pad material layer in the first space, and forming a bit line contact landing pad by planarizing the landing pad material layer to the level of top surfaces of the capping layers. | 2013-10-31 |
20130288473 | Electrical Connection Structure - A structure comprises a top metal connector formed underneath a bond pad. The bond pad is enclosed by a first passivation layer and a second passivation layer. A polymer layer is further formed on the second passivation layer. The dimension of an opening in the first passivation layer is less than the dimension of the top metal connector. The dimension of the top metal connector is less than the dimensions of an opening in the second passivation layer and an opening in the polymer layer. | 2013-10-31 |
20130288474 | METHODS FOR FABRICATING DUAL DAMASCENE INTERCONNECT STRUCTURES - Methods for fabricating dual damascene interconnect structures are provided herein. In some embodiments, a method for fabricating a dual damascene interconnect structure may include etching a via into a substrate through a first photoresist layer; patterning a second photoresist layer atop the substrate to define a trench pattern, wherein the via is aligned within the trench pattern, and wherein a portion of undeveloped photoresist remains in the via after patterning; and etching the trench into the substrate to form a dual damascene pattern in the substrate. | 2013-10-31 |
20130288475 | METHOD FOR OBTAINING A PALLADIUM SURFACE FINISH FOR COPPER WIRE BONDING ON PRINTED CIRCUIT BOARDS AND IC-SUBSTRATES - The present invention relates to a method of bonding a copper wire to a substrate, particularly a printed circuit board and an IC-substrate, possessing a layer assembly comprising a copper bonding portion and a palladium or palladium alloy layer and a substrate having a copper wire bonded to aforementioned layer assembly. | 2013-10-31 |
20130288476 | ELECTROCHEMICAL ETCHING OF SEMICONDUCTORS - Semiconductors are electrochemically etched in solutions containing sources of bifluoride and nickel ions. The electrochemical etching may form pores in the surface of the semiconductor in the nanometer range. The etched semiconductor is then nickel plated. | 2013-10-31 |
20130288477 | APPARATUS AND METHOD FOR DEPOSITING A LAYER ONTO A SUBSTRATE - Apparatus ( | 2013-10-31 |
20130288478 | HIGHLY DILUTABLE POLISHING CONCENTRATES AND SLURRIES - The present disclosure provides a concentrate for use in chemical mechanical polishing slurries, and a method of diluting that concentrate to a point of use slurry. The concentrate comprises abrasive, complexing agent, and corrosion inhibitor, and the concentrate is diluted with water and oxidizer. These components are present in amounts such that the concentrate can be diluted at very high dilution ratios, without affecting the polishing performance. | 2013-10-31 |
20130288479 | Combination, Method, and Composition for Chemical Mechanical Planarization of a Tungsten-Containing Substrate - A combination, composition and associated method for chemical mechanical planarization of a tungsten-containing substrate are described herein which afford tunability of tungsten/dielectric selectivity and low selectivity for tungsten removal in relation to dielectric material. Removal rates for both tungsten and dielectric are high and stability of the slurry (e.g., with respect to pH drift over time) is high. | 2013-10-31 |
20130288480 | METHOD OF EPITAXIAL GERMANIUM TIN ALLOY SURFACE PREPARATION - Methods of preparing a clean surface of germanium tin or silicon germanium tin layers for subsequent deposition are provided. An overlayer of Ge, doped Ge, another GeSn or SiGeSn layer, a doped GeSn or SiGeSn layer, an insulator, or a metal can be deposited on a prepared GeSn or SiGeSn layer by positioning a substrate with an exposed germanium tin or silicon germanium tin layer in a processing chamber, heating the processing chamber and flowing a halide gas into the processing chamber to etch the surface of the substrate using either thermal or plasma assisted etching followed by depositing an overlayer on the substantially oxide free and contaminant free surface. Methods can also include the placement and etching of a sacrificial layer, a thermal clean using rapid thermal annealing, or a process in a plasma of nitrogen trifluoride and ammonia gas. | 2013-10-31 |
20130288481 | Device and Method for Stopping Etching Process - A method for etching a layer assembly, the layer assembly including an intermediate layer sandwiched between an etch layer and a stop layer, the method including a step of etching the etch layer using a first etchant and a step of etching the intermediate layer using a second etchant. The first etchant includes a first etch selectivity of at least 5:1 with respect to the etch layer and the intermediate layer. The second etchant includes a second etch selectivity of at least 5:1 with respect to the intermediate layer and the stop layer. The first etchant being is different from the second etchant. | 2013-10-31 |
20130288482 | METHODS OF FORMING A PATTERN - In a method of forming a pattern, a photoresist pattern is formed on a substrate including an etching target layer. A surface treatment is performed on the photoresist pattern to form a guide pattern having a higher heat-resistance than the photoresist pattern. A material layer including a block copolymer including at least two polymer blocks is coated on a portion of the substrate exposed by the guide pattern. A micro-phase separation is performed on the material layer to form a minute pattern layer including different polymer blocks arranged alternately. At least one polymer block is removed from the minute pattern layer to form a minute pattern mask. The etching target layer is etched by using the minute pattern mask to form a pattern. Minute patterns may be formed utilizing a less complex process that those employed during conventional processes of forming a minute pattern. | 2013-10-31 |
20130288483 | METHODS AND APPARATUS FOR CONTROLLING SUBSTRATE UNIFORMITY - A dynamically tunable process kit, a processing chamber having a dynamically tunable process kit, and a method for processing a substrate using a dynamically tunable process kit are provided. The dynamically tunable process kit allows one or both of the electrical and thermal state of the process kit to be changed without changing the phyisical construction of the process kit, thereby allowing plasma properties, and hence processing results, to be easily changed without replacing the process kit. The processing chamber having a dynamically tunable process kit includes a chamber body that includes a portion of a conductive side wall configured to be electrically controlled, and a process kit. The processing chamber includes a first control system operable to control one or both of an electrical and thermal state of the process kit and a second control system operable to control an electrical state of the portion of the side wall. | 2013-10-31 |
20130288484 | USE OF SURFACTANTS HAVING AT LEAST THREE SHORT-CHAIN PERFLUORINATED GROUPS RF FOR MANUFACTURING INTEGRATED CIRCUITS HAVING PATTERNS WITH LINE-SPACE DIMENSIONS BELOW 50 NM - The use of surfactants A, the 1% by weight aqueous solutions of which exhibit a static surface tension <25 mN/m, the said surfactants A containing at least three short-chain perfluorinated groups Rf selected from the group consisting of trifluoromethyl, pentafluoroethyl, 1-heptafluoropropyl, 2-heptafluoropropyl, heptafluoroisopropyl, and pentafluorosulfanyl; for manufacturing integrated circuits comprising patterns having line-space dimensions below 50 nm and aspect ratios >3; and a photolithographic process making use of the surfactants A in immersion photoresist layers, photoresist layers exposed to actinic radiation, developer solutions for the exposed photoresist layers and/or in chemical rinse solutions for developed patterned photoresists comprising patterns having line-space dimensions below 50 nm and aspect ratios >3. By way of the surfactants A, pattern collapse is prevented, line edge roughness is reduced, watermark defects are prevented and removed and defects are reduced by removing particles. | 2013-10-31 |
20130288485 | DENSIFICATION FOR FLOWABLE FILMS - A method of forming a dielectric layer is described. The method first deposits an initially-flowable layer on a substrate. The initially-flowable layer is then densified by exposing the substrate to a high-density plasma (HDP). Essentially no additional material is deposited on the initially-flowable layer, in embodiments, but the impact of the accelerated ionic species serves to condense the layer and increase the etch tolerance of the processed layer. | 2013-10-31 |
20130288486 | METHOD OF DEPOSITING SILICONE DIOXIDE FILMS - The invention relates to a method of depositing silicon dioxide films using plasma enhanced chemical vapour deposition (PECVD) and more particularly using tetraethyl orthosilicate (TEOS). The process can be carried out at standard temperatures and also at low temperatures which is useful for manufacturing wafers with through silicon vias. | 2013-10-31 |
20130288487 | METHOD AND SYSTEM FOR CONTROLLING A SPIKE ANNEAL PROCESS - Provided is a method and system for controlling a spike anneal process on a substrate, comprising selecting one or more objectives, one or more absorbance layers, a technique of modifying absorption of the selected one or more absorbance layers, one or more wavelengths used in a heating device. A substrate modified with the selected technique of modifying absorption is provided. The spike anneal process is performed on the substrate using the selected heating device and selected spike anneal process variables. One or more of the spike anneal process variables, the selected technique of the modifying absorption, the selected one or more wavelengths, and/or the selected heating device are adjusted in order to meet the one or more objectives of the spike anneal process. | 2013-10-31 |
20130288488 | OZONE PLENUM AS UV SHUTTER OR TUNABLE UV FILTER FOR CLEANING SEMICONDUCTOR SUBSTRATES - A quartz window with an interior plenum is operable as a shutter or UV filter in a degas chamber by supplying the plenum with an ozone-containing gas. Pressure in the plenum can be adjusted to block UV light transmission into the degas chamber or adjust transmittance of UV light through the window. When the plenum is evacuated, the plenum allows maximum transmission of UV light into the degas chamber. | 2013-10-31 |
20130288489 | Method and Apparatus to Fabricate Vias in Substrates for Gallium Nitride MMICs - A system for fabricating vias in SiC and CVD diamond substrates through controlled laser ablation using short pulse lengths and short wavelengths. | 2013-10-31 |
20130288490 | ROTATABLE ELECTRICAL PLUG - The present invention discloses a rotatable electrical plug. The rotatable electrical plug includes a housing, a first conductor, a second conductor, a third conductor, and a rotator. The first conductor, the second conductor, and the third conductor are provided in a first conductive region, a second conductive region, and a third conductive region in the housing respectively, wherein the projection regions of the first conductive region and the second conductive region in the normal direction of the housing are overlapped. Both of the first conductor and the second conductor are of a tubular form formed by a single metal sheet, and the first conductor, the second conductor, and the third conductor are electrically contacted to a first contactor, a second contactor, and a third conductor in the inner side of the rotator respectively. The volume of the rotatable electrical plug is greatly reduced so as to enhance the convenience. | 2013-10-31 |
20130288491 | DISABLEMENT OF CONNECTION BETWEEN CONNECTION MODULE AND BATTERY - Embodiments herein relate to disablement of a connection between a battery and a connection module. In an embodiment, a connection between the battery and a connection module may be disabled if the connection module is drawing current from the battery or if a monitored signal transitions from a high logic level to the low logic level. The connection module is to draw the current or pull the signal down to a low logic level in response to one or more components related to the device becoming exposed or an enclosure related to the device being breached or opened. | 2013-10-31 |
20130288492 | FOLDING SO-DIMM SOCKET - Sockets that provide easy access for users to change cards while allowing the use of thinner device enclosures. One example provides a socket having two positions. When the socket is in an open state, the card may be oriented in a direction substantially away from the main logic board. When the socket is in a closed state, the card moves such that it is oriented at least closer to being in parallel to the main logic board. | 2013-10-31 |