44th week of 2012 patent applcation highlights part 43 |
Patent application number | Title | Published |
20120276629 | METHODS FOR ISOLATING STEM CELLS - Disclosed is a method for isolating stem cells. The method uses a specially designed apparatus including: a container containing an aspirate; a piston having an outer diameter corresponding to the inner diameter of the container and having at least one through-hole; and a connection tube adapted to feed an enzyme or a washing solution into the container through the through-hole, having a tip connected to the through-hole, and connected to an external tube or another container containing the enzyme or washing solution at the other end thereof. The method includes pulling the piston backward to form a negative pressure in the container containing the aspirate and to allow the enzyme or washing solution to enter the container containing the aspirate through the connection tube and the through-hole of the piston. | 2012-11-01 |
20120276630 | DRY POWDER CELLS AND CELL CULTURE REAGENTS AND METHODS OF PRODUCTION THEREOF - The present invention relates generally to nutritive medium, medium supplement, media subgroup and buffer formulations. Specifically, powdered nutritive medium, supplement, subgroup formulations, cell culture media comprising all of the necessary nutritive factors for in vitro cell cultivation, buffer formulations that produce particular ionic and pH conditions upon reconstitution with a solvent are provided. Particularly, methods of production of these media, supplement, subgroup, buffer formulations and kits, and methods for the cultivation of prokaryotic and eukaryotic cells using these dry powdered nutritive media, supplement, subgroup and buffer formulations are provided. Methods of producing sterile, powdered media or supplement (e.g., powdered FBS, powdered transferrin, powdered insulin, powdered organ extracts, powdered growth factors), media subgroup and buffer formulations by gamma irradiation are provided. Methods for producing dry cell powders, comprising spray-drying a cell suspension, and cells, media, media supplement, media subgroup and buffer powders produced by these methods are provided. | 2012-11-01 |
20120276631 | METHODS FOR CONTROLLING THE GALACTOSYLATION PROFILE OF RECOMBINANTLY-EXPRESSED PROTEINS - The present invention relates to methods for modulating the glycosylation profile of recombinantly-expressed proteins. In particular, the present invention relates to methods of controlling the galactosylation profile of recombinantly-expressed proteins by supplementing production medium, e.g., a hydrolysate-based or a chemically defined medium, with manganese and/or D-galactose. | 2012-11-01 |
20120276632 | PLASMA-FREE PLATELET LYSATE FOR USE AS A SUPPLEMENT IN CELL CULTURES AND FOR THE PREPARATION OF CELL THERAPEUTICS - The present invention provides a cell culture medium supplement comprising plasma-free platelet lysate and medium supplemented with this supplement. The present invention further provides a method for preparing the supplement comprising the steps of (a) preparing platelet rich plasma; (b) removing the plasma; and (c) lysing the platelets. | 2012-11-01 |
20120276633 | SUPPLYING TREATED EXHAUST GASES FOR EFFECTING GROWTH OF PHOTOTROPHIC BIOMASS - There is provided a process for growing a phototrophic biomass in a reaction zone. The process includes treating an operative carbon dioxide supply-comprising gaseous material feed so as to effect production of a carbon dioxide-rich product material. The carbon dioxide concentration of the carbon dioxide-rich product material is greater than the carbon dioxide concentration of the operative carbon dioxide supply-comprising gaseous material feed. Production of at least a fraction of the operative carbon dioxide supply-comprising gaseous material feed is effected by a gaseous exhaust material producing process. At least a fraction of the carbon dioxide-rich product material is supplied to the reaction zone so as to effect growth of the phototrophic biomass by photosynthesis in the reaction zone. | 2012-11-01 |
20120276634 | SOMATIC EMBRYOGENESIS AND EMBRYO HARVESTING AND METHOD AND APPARATUS FOR PREPARING PLANT EMBRYOS FOR PLANT PRODUCTION - Described herein are methods and media for facilitating somatic embryogenesis and for collecting, conditioning, and transferring the washed embryos onto a substrate and into an environment suitable for conditioning the embryos for a desired period of time so they become germination-competent for plant production. The described plant embryo cleaning apparatus and method are used for preparing multiple plant embryos for plant production. The apparatus and method can use a cleaning fluid source, a fluid-conditioning system, a fluid-delivery structure, a cleaning station, an outlet mechanism, a negative pressure source, and a controller. | 2012-11-01 |
20120276635 | FLUIDIC DEVICE - A fluidic device for cell electroporation, cell lysis, and cell electrofusion based on constant DC voltage and geometric variation is provided. The fluidic device can be used with prokaryotic or eukaryotic cells. In addition, the device can be used for electroporative delivery of compounds, drugs, and genes into prokaryotic and eukaryotic cells on a microfluidic platform. | 2012-11-01 |
20120276636 | METHOD FOR IMPROVING INDUCED PLURIPOTENT STEM CELL GENERATION EFFICIENCY - The present invention provides a method for improving iPS cell generation efficiency, which comprises a step of introducing a Myc variant having the following features: (1) having an activity to improve iPS cell generation efficiency which is comparative to, or greater than that of c-Myc; and (2) having a transformation activity which is lower than that of c-Myc; or a nucleic acid encoding the variant, in a nuclear reprogramming step. Also, the present invention provides a method for preparing iPS cells, which comprises a step of introducing the above Myc variant or a nucleic acid encoding the variant and a combination of nuclear reprogramming factors into somatic cells. Moreover, the present invention provides iPS cells comprising the nucleic acid encoding the Myc variant which can be obtained by the above method, and a method for preparing somatic cells which comprises inducing differentiation of the iPS cells. | 2012-11-01 |
20120276637 | GENETICALLY ENGINEERED CYANOBACTERIA - The disclosed embodiments provide cyanobacteria spp. that have been genetically engineered to have increased production of carbon-based products of interest. These genetically engineered hosts efficiently convert carbon dioxide and light into carbon-based products of interest such as long chained hydrocarbons. Several constructs containing polynucleotides encoding enzymes active in the metabolic pathways of cyanobacteria are disclosed. In many instances, the cyanobacteria strains have been further genetically modified to optimize production of the carbon-based products of interest. The optimization includes both up-regulation and down-regulation of particular genes. | 2012-11-01 |
20120276638 | Methods of Improving the Introduction of DNA Into Bacterial Cells - The present invention relates to methods of improving the introduction of DNA into bacterial host cells. | 2012-11-01 |
20120276639 | GENETICALLY ENGINEERED RECOMBINANT ESCHERICHIA COLI PRODUCING L-TRYPTOPHAN HAVING ORIGINALLY L-PHENYLALANINE PRODUCTIVITY, AND METHOD FOR PRODUCING L-TRYPTOPHAN USING THE MICROORGANISM - The present invention relates to a microorganism having L-tryptophan productivity and a method for producing L-tryptophan using the same. More precisely, the present invention relates to the recombinant | 2012-11-01 |
20120276640 | Polypeptides Having Cellobiohydrolase Activity And Polynucleotides Encoding Same - The present invention relates to isolated polypeptides having cellobiohydrolase activity and isolated polynucleotides encoding the polypeptides. The invention also relates to nucleic acid constructs, vectors, and host cells comprising the polynucleotides as well as methods of producing and using the polypeptides. | 2012-11-01 |
20120276641 | MICROFLUIDIC DEVICE PROVIDING DEGASSING DRIVEN FLUID FLOW - A device for blood-plasma separation and plasma-based blood analysis is described. The device uses blood samples smaller than 5 μL, (directly from the finger) and flow is achieved with a degassing-driven flow technique that causes blood to flow spontaneously into air-filled dead-end channels without external pumping mechanisms. | 2012-11-01 |
20120276642 | USING SQUARAINE DYES AS NEAR INFRARED FLUORESCENT SENSORS FOR PROTEIN DETECTION - Squaraine dyes are used to detect the presence of protein in a test sample, which is a substance that may contain protein. A squarine dye is placed in water, and in some instances joined with an aggregation agent, to create an aqueous dye solution. That dye solution is joined with a test sample. When the dye solution is joined with the test sample and the resultant test solution is excited by the application of photons, a resulting fluorescence or absence thereof reveals if protein was present in the test sample. | 2012-11-01 |
20120276643 | Method for Specific Cleavage of N-CA Bond in Peptide Main Chain - The present invention provides a peptide degradation reagent with the following characteristics: 1) it has no marked toxicity such as carcinogenicity, 2) it does not produce metastable peaks resulting from excessive degradation property, 3) it does not produce multiply-charged ion peaks which are interference peaks, and 4) it can secure separation and sharpness of peaks. The present invention also provides a method for specifically cleaving N—Cα bonds on a peptide backbone using the above-described reagent, and a method of determining the amino acid sequence of a peptide utilizing this specific cleavage. A method for specifically cleaving N—Cα bonds on the backbone of a peptide, comprising irradiating the peptide with laser light in the presence of 5-amino salicylic acid. A method for determining the amino acid sequence of a peptide, comprising irradiating the peptide with laser light in the presence of 5-amino salicylic acid to thereby specifically cleave N—Cα bonds on the peptide backbone. A reagent for specifically cleaving N—Cα bonds on a peptide backbone; a hydrogen radical-releasing reagent; a matrix reagent for MALDI-ISD; a matrix for MALDI-ISD; a peptide ionization reagent for MALDI-ISD; and a kit for MALDI-ISD. | 2012-11-01 |
20120276644 | Method for Detecting Endogenous Biomolecules - Provided is a method for the real-time visualization of an endogenous biomolecule to clarify the mechanisms of various diseases and enable diagnosis and treatment of these diseases. Specifically provided is a novel method for visualizing an endogenous biomolecule by using a magnetic resonance method (including Overhauser MRI and the electron spin resonance method). The aforesaid visualization method, whereby an endogenous biomolecule is visualized on a real-time basis, comprises: a step for treating a living organism to be examined by a magnetic resonance method and thus acquiring data of the endogenous biomolecule; a step for processing the data of the endogenous biomolecule thus obtained to give imaging data; and a step for displaying the imaging data thus obtained. | 2012-11-01 |
20120276645 | OPTICAL SENSOR-BASED CUPRIC REDUCING ANTIOXIDANT CAPACITY (CUPRAC) ASSAY - An example embodiment is an apparatus for measuring antioxidant presence comprising a solid media, and a reagent carried by the media, the reagent reactive with at least one antioxidant to cause changes in light that is incident upon the reagent while carried by the solid media. | 2012-11-01 |
20120276646 | METHODS AND REAGENTS FOR ANALYZING RIBOSWITCHES USING FRET - The present invention is provides isolated riboswitches with FRET pairs for distinguishing changes in regulatory interactions controlled by the expression platform domain found in riboswitches. The invention further provides methods of using those riboswitches to detect structural changes in the expression platform domain and to identify potential antibiotics. | 2012-11-01 |
20120276647 | Intelligent Pigments and Plastics - A chemical indicator comprises a particulate inorganic substrate, and at least one reactive dye or ink coated on and/or impregnated within the particulate inorganic substrate. Coating and/or impregnating at least one reactive dye or ink on or within a particulate inorganic substrate improves the storage stability and/or thermal stability of the at least one reactive dye or ink, which typically comprises relatively unstable compounds. This allows the present indicators to be incorporated into thermoplastic polymer materials and processed conventionally while maintaining the efficacy and stability of the new indicators. The indicators provide simple, reliable, and cost effective detection means for detecting analytes such as ammonia, carbon dioxide, and oxygen, and may find use in applications such as food packaging and medical applications. | 2012-11-01 |
20120276648 | ELECTROSTATICALLY STABILIZED METAL SULFIDE NANOPARTICLES FOR COLORIMETRIC MEASUREMENT OF HYDROGEN SULFIDE - Methods and related apparatuses and mixtures are described for spectroscopic detection of hydrogen sulfide in a fluid, for example a formation fluid downhole. A reagent mixture is combined with the fluid. The reagent mixture includes metal ions for reacting with hydrogen sulfide forming a metal sulfide, and a solvent that stabilizes the metal sulfide nanoparticles and assist in preventing precipitation by electrostatic stabilization. The solvent includes a property having a density above 1 kg/l. Further, dissolving the metal ions into the solvent to create the reagent mixture, and mixing the reagent mixture with the hydrogen sulfide sample in a formation. So, the metal ions of the reagent mixture react with the hydrogen sulfide sample to form the metal sulfide nanoparticles, resulting in the metal sulfide nanoparticles having properties with a density from 1 kg/l to about 8 kg/l. | 2012-11-01 |
20120276649 | THIOL DETECTION - Embodiments of compounds for selectively detecting a thiol are disclosed. In some embodiments, the compounds are bridged viologens, and the compounds are capable of reacting with homocysteine and/or glutathione in a buffered solution to produce a change in the solution's absorbance spectrum and/or emission spectrum. Also disclosed are embodiments of methods and kits for detecting homocysteine and/or glutathione with the disclosed bridged viologens. | 2012-11-01 |
20120276650 | METHOD FOR DETERMINING TURBIDITY POINT AND FREE CARBOHYDRATE BUFFER COEFFICIENT OF IRON-CARBOHYDRATE COMPLEX - A method for determining a turbidity point and a free carbohydrate buffer coefficient of an iron-carbohydrate complex. The method includes: (1) contacting the complex with an acid; (2) determining hydrogen ion concentrations and solution turbidities of the complex in acid degradation; and (3) mathematically fitting the data, to obtain the turbidity point of the complex and the free carbohydrate buffer coefficient through mathematical treatment. A method for evaluating the safety of the iron-carbohydrate complex with the turbidity point and the free carbohydrate buffer coefficient. | 2012-11-01 |
20120276651 | FLUORESCENT NANOPROBE FOR DETECTING HYDROGEN PEROXIDE AND FABRICATION METHOD THEREOF - The present disclosure relates to a sulfonated benzene compound emitting fluorescence by reaction with hydrogen peroxide, aqueous-dispersed fluorescent nanoprobes applicable for real-time detection of hydrogen peroxide, and a fluorescent nanoprobe fabrication method. The fluorescent nanoprobe contains the following sulfonated benzene compound and water. | 2012-11-01 |
20120276652 | METHOD FOR QUALIFYING A NON-PARTICULATE ION-EXCHANGER ADSORBER - The present invention relates to a method for the validation of a non-particulate ion exchange adsorber and a kit for the validation of a non-particulate ion exchange adsorber. | 2012-11-01 |
20120276653 | Detection Device and Method of Using the Same - A detection device ( | 2012-11-01 |
20120276654 | USE OF FLUID ASPIRATION/DISPENSING TIP AS A MICROCENTRIFUGE TUBE - A fluid aspirating/dispensing member includes a sample cavity for sample acquisition and a sealable cavity that, once sealed, permits the separation of particles from the remainder of a fluid sample within the sample cavity after centrifugation or other separation means. The fluid aspirating/dispensing members, either individually or as part of an array, increase the efficiency of sample processing before analysis by a clinical analyzer. | 2012-11-01 |
20120276655 | DETECTION OF ANTIBODIES - The present invention relates to a method of detecting a target antibody, particularly a target autoantibody, in a sample, using a small molecule fluorophore-labelled target antigen, or a functional fragment, functional variant or functional derivative thereof that specifically binds to the target antibody. Detection is typically carried out using immunodiffusion or immunoelectrophoresis. The invention also relates to methods of diagnosing disease, particularly autoimmune disease, using small molecule fluorophore labelled target antigens and autoantigens. Small molecule fluorophore labelled target antigens, including autoantigens, are also disclosed, as are uses such. | 2012-11-01 |
20120276656 | Multiplexed Assay Methods - The present invention is directed to methods for conducting multiplexed assays. The methods are particularly well suited for measuring a plurality of analytes that may be present in very different abundances. The invention also relates to systems, devices, equipment, kits and reagents for use in such methods. | 2012-11-01 |
20120276657 | METHOD OF PATTERNING OF MAGNETIC TUNNEL JUNCTIONS - Embodiments of the invention generally relate to methods for fabricating devices on semiconductor substrates. More specifically, embodiments of the invention relate to methods of patterning magnetic materials. Certain embodiments described herein use a reducing chemistry containing a hydrogen gas or hydrogen containing gas with an optional dilution gas at temperatures ranging from 20 to 300 degrees Celsius at a substrate bias less than 1,000 DC voltage to reduce the amount of sputtering and redeposition. Exemplary hydrogen containing gases which may be used with the embodiments described herein include NH | 2012-11-01 |
20120276658 | METHOD OF ETCHING A WORKPIECE - A workpiece is implanted to a first depth to form a first amorphized region. This amorphized region is then etched to the first depth. After etching, the workpiece is implanted to a second depth to form a second amorphized region below a location of the first amorphized region. The second amorphized region is then etched to the second depth. The implant and etch steps may be repeated until structure is formed to the desired depth. The workpiece may be, for example, a compound semiconductor, such as GaN, a magnetic material, silicon, or other materials. | 2012-11-01 |
20120276659 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An impurity-doped PZT film in an amorphous state doped with La, Ca, Sr, Si, Nb and/or the like is formed on a Pt film composing a bottom electrode film. Next, crystallization annealing for the impurity-doped PZT film is performed. Next, a PZT film is formed on the impurity-doped PZT film by an MOCVD method. Thereafter, an IrO | 2012-11-01 |
20120276660 | SYSTEM FOR NON RADIAL TEMPERATURE CONTROL FOR ROTATING SUBSTRATES - Embodiments of the present invention provide apparatus and method for reducing non uniformity during thermal processing. One embodiment provides an apparatus for processing a substrate comprising a chamber body defining a processing volume, a substrate support disposed in the processing volume, wherein the substrate support is configured to rotate the substrate, a sensor assembly configured to measure temperature of the substrate at a plurality of locations, and one or more pulse heating elements configured to provide pulsed energy towards the processing volume. | 2012-11-01 |
20120276661 | HIGH SENSITIVITY EDDY CURRENT MONITORING SYSTEM - A method of chemical mechanical polishing a substrate includes polishing a metal layer on the substrate at a polishing station, monitoring thickness of the metal layer during polishing at the polishing station with an eddy current monitoring system, and controlling pressures applied by a carrier head to the substrate during polishing of the metal layer at the polishing station based on thickness measurements of the metal layer from the eddy current monitoring system to reduce differences between an expected thickness profile of the metal layer and a target profile, wherein the metal layer has a resistivity greater than 700 ohm Angstroms. | 2012-11-01 |
20120276662 | EDDY CURRENT MONITORING OF METAL FEATURES - A method of chemical mechanical polishing a substrate includes polishing a plurality of discrete separated metal features of a layer on the substrate at a polishing station, using an eddy current monitoring system to monitor thickness of the metal features in the layer, and controlling pressures applied by a carrier head to the substrate during polishing of the layer at the polishing station based on thickness measurements of the metal features from the eddy current monitoring system to reduce differences between an expected thickness profile of the metal feature and a target profile. | 2012-11-01 |
20120276663 | EQUIPMENT AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to an embodiment, equipment for manufacturing a semiconductor device includes a first block, a plurality of stamp pins, a second block and a plurality of springs. The first block includes a plurality of first through-holes penetrating from a first major surface to a second major surface. The stamp pins are inserted into each of the first through-holes from the first major surface, each of the stamp pins having an end projected from the second major surface and being capable of moving forward and backward in the insertion direction. The second block has a plurality of second through-holes with an inner diameter larger than an inner diameter of the first through-holes, the second through-holes being disposed so as to overlap with the first through-holes; and the springs are disposed in each of the second through-holes, for biasing the stamp pins in the insertion direction. | 2012-11-01 |
20120276664 | METHODS OF INSPECTING AND MANUFACTURING SEMICONDUCTOR WAFERS - A method of manufacturing a plurality of semiconductor wafers comprising micro-inspecting at least one location within at least one micro-inspected pattern field and determining at least one parameter value representing a property of the wafer at the micro-inspected location, macro-inspecting a plurality of locations within the at least one micro-inspected pattern field and determining, for each macro-inspected location of the macro-inspected pattern field, at least one parameter value representing the property of the wafer at the macro-inspected location based on the light intensity recorded for the macro-inspected location and on the at least one parameter value representing the property of the wafer at the micro-inspected location of this pattern field. | 2012-11-01 |
20120276665 | APPARATUS AND METHOD FOR ELECTRICAL CHARACTERIZATION BY SELECTING AND ADJUSTING THE LIGHT FOR A TARGET DEPTH OF A SEMICONDUCTOR - The present disclosure provides methods and apparatus that enable characterization of an electrical property of a semiconductor specimen, e.g., dopant concentration of a near-surface region of the specimen. In exemplary method, a target depth for measurement is selected. This thickness may, for example, correspond to a nominal production thickness of a thin active device region of the specimen. A light is adjusted to an intensity selected to characterize a target region of the specimen having a thickness no greater than the target depth and a surface of the specimen is illuminated with the light. An AC voltage signal induced in the specimen by the light is measured and this AC voltage may be used to quantify an aspect of the electrical property, e.g., to determine dopant concentration, of the target region. | 2012-11-01 |
20120276666 | METHOD FOR MAKING LIGHT EMITTING DIODE - A method for making light emitting diode, the method includes the following steps. First, a substrate having an epitaxial growth surface is provided. Second, a carbon nanotube layer is suspended above the epitaxial growth surface. Third, a first semiconductor layer, an active layer and a second semiconductor layer are grown on the epitaxial growth surface in that order. Fourth, a portion of the second semiconductor layer and the active layer is etched to expose a portion of the first semiconductor layer. Fifth, a first electrode is prepared on the first semiconductor layer and a second electrode is prepared on the second semiconductor layer. | 2012-11-01 |
20120276667 | PACKAGING METHOD OF LIGHT EMITTING DEVICE - A packaging method includes the following steps. A cover substrate is provided. A blocking dam having a first height is formed in the peripheral region of the cover substrate. The blocking dam has a second height after being hardened. A sealant surrounding the blocking dam and having a third height is formed. An encapsulation glue is filled in the active region of the cover substrate, and blocked by the blocking dam. A device substrate is provided, and a compression process is performed on the device substrate and the cover substrate. After the compression process, a buffer space is formed between the blocking dam and the sealant and between the cover substrate and the device substrate to accommodate the encapsulation glue spilling out of the active region of the cover substrate. The sealant is hardened, so that the cover substrate and the device substrate are bonded together through the sealant. | 2012-11-01 |
20120276668 | METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE - In one embodiment, a method is disclosed for manufacturing a semiconductor light emitting device. The method can include forming a plurality of light emitting regions on a major surface of a support substrate. The method can include forming V-shaped grooves by anisotropic etching between the plurality of light emitting regions in the major surface of the support substrate. In addition, the method can include dividing the support substrate at positions of the grooves to separate the light emitting regions. | 2012-11-01 |
20120276669 | METHOD FOR MAKING LIGHT EMITTING DIODE - A method of making a LED includes following steps. A substrate is provided, and the substrate includes an epitaxial growth surface. A carbon nanotube layer is placed on the epitaxial growth surface. A first semiconductor layer, an active layer, and a second semiconductor layer are grown in that order on the substrate. A reflector and a first electrode are deposited on the second semiconductor layer in that order. The substrate is removed. A second electrode is deposited on the first semiconductor layer. | 2012-11-01 |
20120276670 | METHOD FOR MAKING LIGHT EMITTING DIODE - A method of fabricating a light emitting diode includes following steps. A substrate is provided, and the substrate includes an epitaxial growth surface. A carbon nanotube layer is located on the epitaxial growth surface. A first semiconductor layer, an active layer, and a second semiconductor layer grow in that order on the substrate. An upper electrode is deposited on the second semiconductor layer. The substrate is removed. A lower electrode is deposited on the first semiconductor layer. | 2012-11-01 |
20120276671 | METHOD FOR MAKING LIGHT EMITTING DIODE - A method of making a LED includes following steps. A substrate with an epitaxial growth surface is provided. A carbon nanotube layer is placed on the epitaxial growth surface. A semiconductor epitaxial layer is grown on the epitaxial growth surface, and the semiconductor epitaxial layer includes an N-type semiconductor layer, an active layer, a P-type semiconductor layer. The semiconductor epitaxial layer is etched to expose part of the carbon nanotube layer. A first electrode is formed on a surface of the semiconductor epitaxial layer which is away from the substrate. A second electrode is formed to electrically connect with the part of the carbon nanotube layer which is exposed. | 2012-11-01 |
20120276672 | METHOD FOR MAKING LIGHT EMITTING DIODE - A method for making a light emitting diode comprises the following steps. First, a substrate having an epitaxial growth surface is provided. Second, a carbon nanotube layer is located on the epitaxial growth surface. Third, a first semiconductor layer, an active layer, and a second semiconductor layer is grown on the epitaxial growth surface. Fourth, a portion of the second semiconductor layer and the active layer is etched to expose a portion of the first semiconductor layer. Fifth, a first electrode is electrically connected to the first semiconductor layer, and a second electrode electrically is connected to the second semiconductor layer. | 2012-11-01 |
20120276673 | METHOD FOR MAKING LIGHT EMITTING DIODE - A method for making a light emitting diode, the method includes the following steps. First, a substrate having an epitaxial growth surface is provided. Second, a carbon nanotube layer is placed on the epitaxial growth surface. Third, a first semiconductor layer, an active layer and a second semiconductor layer are grown on the epitaxial growth surface. Fourth, a portion of the second semiconductor layer and the active layer is etched to expose a portion of the first semiconductor layer. Fifth, a first electrode is prepared on the first semiconductor layer and a second electrode is prepared on the second semiconductor layer. Sixth, the carbon nanotube layer is removed. | 2012-11-01 |
20120276674 | Three-Axis Accelerometers and Fabrication Methods - MEMS accelerometers have a substrate, and a proof mass portion thereof which is separated from the substrate surrounding it by a gap. An electrically-conductive anchor is coupled to the proof mass, and a plurality of electrically-conductive suspension anus that are separated from the proof mass extend from the anchor and are coupled to the substrate surrounding the proof mass. A plurality of sense and actuation electrodes are separated from the proof mass by gaps and are coupled to processing electronics. The fabrication methods use deep reactive ion etch bulk micromachining and surface micromachining to form the proof mass, suspension arms and electrodes. The anchor, suspension arms and electrodes are made in the same process steps from the same electrically conductive material, which is different from the substrate material. | 2012-11-01 |
20120276675 | APPARATUS AND METHOD FOR MEASURING LOCAL SURFACE TEMPERATURE OF SEMICONDUCTOR DEVICE - An apparatus and method is described for measuring a local surface temperature of a semiconductor device under stress. The apparatus includes a substrate, and a reference MOSFET. The reference MOSFET may be disposed closely adjacent to the semiconductor device under stress. A local surface temperature of the semiconductor device under stress may be measured using the reference MOSFET, which is not under stress. The local surface temperature of the semiconductor device under stress may be determined as a function of drain current values of the reference MOSFET measured before applying stress to the semiconductor device and while the semiconductor device is under stress. | 2012-11-01 |
20120276676 | EPITAXIAL LIFT OFF IN INVERTED METAMORPHIC MULTIJUNCTION SOLAR CELLS - The present disclosure provides a process for manufacturing a solar cell by selectively freeing an epitaxial layer from a single crystal substrate upon which it was grown. In some embodiments the process includes, among other things, providing a first substrate; depositing a separation layer on said first substrate; depositing on said separation layer a sequence of layers of semiconductor material forming a solar cell; mounting and bonding a flexible support on top of the sequence of layers; etching said separation layer while applying an agitating action to the etchant solution so as to remove said flexible support with said epitaxial layer from said first substrate. | 2012-11-01 |
20120276677 | METHOD AND STRUCTURE OF WAFER LEVEL ENCAPSULATION OF INTEGRATED CIRCUITS WITH CAVITY - The present invention is related shielding integrated devices using CMOS fabrication techniques to form an encapsulation with cavity. The integrated circuits are completed first using standard IC processes. A wafer-level hermetic encapsulation is applied to form a cavity above the sensitive portion of the circuits using IC-foundry compatible processes. The encapsulation and cavity provide a hermetic inert environment that shields the sensitive circuits from EM interference, noise, moisture, gas, and corrosion from the outside environment. | 2012-11-01 |
20120276678 | NANOWIRE MULTIJUNCTION SOLAR CELL - A solar cell includes a substrate layer and a plurality of nanowires grown outwardly from the substrate layer, at least two of the nanowires including a plurality of sub-cells. The solar cell also includes one or more light guiding layers formed of a transparent, light scattering material and filling the area between the plurality of nanowires. | 2012-11-01 |
20120276679 | Method of making a CMOS image sensor and method of suppressing dark leakage and crosstalk for a CMOS image sensor - A CMOS image sensor, in which an implantation process is performed on substrate under isolation structures each disposed between two adjacent photosensor cell structures. The implantation process is a destructive implantation to form lattice effects/trap centers. No defect repair process is carried out after the implantation process is performed. The implants can reside at the isolation structures or in the substrate under the isolation structures. Dark leakage and crosstalk are thus suppressed. | 2012-11-01 |
20120276680 | SOLID-STATE IMAGING DEVICE, MANUFACTURING METHOD FOR THE SAME, AND IMAGING APPARATUS - A solid-state imaging device includes: a pixel section including, in a semiconductor substrate, plural photoelectric conversion sections that photoelectrically convert incident light to generate signal charges; metal wirings formed, on a first insulating film formed on the semiconductor substrate, above regions among the photoelectric conversion sections and above the periphery of the pixel section; a second insulating film formed on the first insulating film to cover the metal wirings; a first light shielding film formed on the second insulating film and having an opening above the pixel section; and a second light shielding film formed above the metal wirings above the pixel section and having thickness smaller than that of the first light shielding film. | 2012-11-01 |
20120276681 | SERIAL CONNECTION OF THIN-LAYER SOLAR CELLS - The invention relates to a serial connection of thin layer solar cells. The aim of the invention is to provide a structuring method which provides a reliable and effective connection, prevents short-circuits and enlarges usable solar cell surfaces. The aim of the invention is achieved according to claims | 2012-11-01 |
20120276682 | METHOD AND SYSTEM FOR LARGE SCALE MANUFACTURE OF THIN FILM PHOTOVOLTAIC DEVICES USING SINGLE-CHAMBER CONFIGURATION - A system for large scale manufacture of thin film photovoltaic cells includes a chamber comprising a plurality of compartments in a common vacuum ambient therein. Additionally, the system includes one or more shutter screens removably separating each of the plurality of compartments. The system further includes one or more transfer tools configured to transfer a substrate from one compartment to another without breaking the common vacuum ambient. The substrate is optically transparent and is characterized by a lateral dimension of about 1 meter or greater for a solar module. Embodiments of the invention provide compartments configured to subject the substrate to one or more thin film processes to form a Cu-rich Cu—In composite material overlying the substrate and at least one of the plurality of compartments is configured to subject the Cu-rich Cu—In composite material to a thermal process to form a chalcogenide structured material. | 2012-11-01 |
20120276683 | METHOD FOR PREPARING TITANIA PASTES FOR USE IN DYE-SENSITIZED SOLAR CELLS - A new, more economical method for preparing titania pastes for use in more efficient dye-sensitized solar cells is disclosed. The titania pastes are prepared by mixing titania nanoparticles with a titania sol including a titanium precursor. The disclosed method enables the control of titania nanoparticle concentration and morphology in the titania paste and is economical due to the relatively low reaction temperatures. The performances of dye-sensitized solar cells prepared using the disclosed titania pastes are also disclosed. | 2012-11-01 |
20120276684 | PATTERNED ASSEMBLY FOR MANUFACTURING A SOLAR CELL AND A METHOD THEREOF - Apparatuses and methods for manufacturing a solar cell are disclosed. In a particular embodiment, the solar cell may be manufactured by disposing a solar cell in a chamber having a particle source; disposing a patterned assembly comprising an aperture and an assembly segment between the particle source and the solar cell; and selectively implanting first type dopants traveling through the aperture into a first region of the solar cell while minimizing introduction of the first type dopants into a region outside of the first region. | 2012-11-01 |
20120276685 | BACKSIDE CONTACT SOLAR CELL WITH FORMED POLYSILICON DOPED REGIONS - A solar cell includes abutting P-type and N-type doped regions in a contiguous portion of a polysilicon layer. The polysilicon layer may be formed on a thin dielectric layer, which is formed on a backside of a solar cell substrate (e.g., silicon wafer). The polysilicon layer has a relatively large average grain size to reduce or eliminate recombination in a space charge region between the P-type and N-type doped regions, thereby increasing efficiency. | 2012-11-01 |
20120276686 | CONDUCTIVE CHANNEL OF PHOTOVOLTAIC PANEL AND METHOD FOR MANUFACTURING THE SAME - An electrically conductive ribbon, which is soldered on an electrically conductive busbar of a photovoltaic panel, includes a cooper core and a tin based solder. The tin based solder fully wraps an outer surface of the cooper core, and has a convex solder surface, which has a first curvature to be fitted with a second curvature of a concave solder surface of the electrically conductive busbar. | 2012-11-01 |
20120276687 | NICKEL COMPLEXES FOR FLEXIBLE TRANSISTORS AND INVERTERS - The design and synthesis of six nickel charge transfer (CT) complexes are described herein. The six nickel CT complexes have a nickel center, two organic ligands coordinated with the nickel center to form a dianionic square planar supramolecule and an organic counter-cation. The ligands and counter-cations are selected to optimize properties, such as molecular alignment, film morphology, and molecular packaging. Described herein, the ligands can be 2,3-pyrazinedithiol (L | 2012-11-01 |
20120276688 | METHOD FOR FORMING A SELF-ALIGNED BIT LINE FOR PCRAM AND SELF-ALIGNED ETCH BACK PROCESS - A method of forming bit line aligned to a phase change material that includes forming a pedestal of a sacrificial material on a portion of a lower electrode and forming at least one dielectric material adjacent to the sacrificial material, wherein the at least one dielectric material has an upper surface substantially coplanar with an upper surface of the pedestal of the sacrificial material. The pedestal of the sacrificial material is removed selective to the at least one dielectric material and the lower electrode to provide an opening to an exposed surface of the lower electrode. A phase change material is formed on the exposed surface of the lower electrode, and the opening is filled with a conductive fill material. A self-aligned etch back process is also provided. | 2012-11-01 |
20120276689 | Glass Wafers for Semiconductor Fabrication Processes and Methods of Making Same - The present disclosure is directed to the use of glass wafers as carriers, interposers, or in other selected applications in which electronic circuitry or operative elements, such as transistors, are formed in the creation of electronic devices. The glass wafers generally include a glass having a coefficient of thermal expansion equal to or substantially equal to a coefficient of thermal expansion of semiconductor silicon, an indexing feature, and a coating on at least a portion of one face of the glass. | 2012-11-01 |
20120276690 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a method for manufacturing a semiconductor device, by which a transistor including an active layer, a gate insulating film in contact with the active layer, and a gate electrode overlapping the active layer with the gate insulating film therebetween is provided; an impurity is added to a part of a first region overlapped with the gate electrode with the gate insulating film therebetween in the active layer and a second region but the first region in the active layer by adding the impurity to the active layer from one oblique direction; and the second region is situated in the one direction relative to the first region. | 2012-11-01 |
20120276691 | Wafer Level Die Integration and Method - In a wafer level chip scale package (WLSCP), a semiconductor die has active circuits and contact pads formed on its active surface. A second semiconductor die is disposed over the first semiconductor die. A first redistribution layer (RDL) electrically connects the first and second semiconductor die. A third semiconductor die is disposed over the second semiconductor die. The second and third semiconductor die are attached with an adhesive. A second RDL electrically connects the first, second, and third semiconductor die. The second RDL can be a bond wire. Passivation layers isolate the RDLs and second and third semiconductor die. A plurality of solder bumps is formed on a surface of the WLSCP. The solder bumps are formed on under bump metallization which electrically connects to the RDLs. The solder bumps electrically connect to the first, second, or third semiconductor die through the first and second RDLs. | 2012-11-01 |
20120276692 | Method for Assemblying a Semiconductor Chip Package with Deflection-Resistant Leadfingers - Embodiments of the invention relate to methods for semiconductor chip package assembly. An embodiment of the invention includes providing a metallic leadframe with a chip mounting surface and a plurality of leadfingers. The leadfingers have a proximal end for receiving one or more wirebonds and a distal end for providing an electrical path from the proximal end. One or more of the leadfingers also has an offset portion and underlying heat spreader, increasing the stiffness of the leadfinger, and increasing leadfinger deflection-resistance and spring-back. The offset is in the direction opposite the plane of a heat spreader thermally coupled to the mounting surface. A semiconductor chip is affixed to the mounting surface and a plurality of bond pads of the chip are wirebonded to the offset portions of the proximal ends of individual leadfingers. The chip, the bondwires, portions of the heat spreader and leadfingers are encapsulated. | 2012-11-01 |
20120276693 | Module Comprising a Semiconductor Chip - A module includes a semiconductor chip having at least a first terminal contact surface and a second terminal contact surface. A first bond element made of a material on the basis of Cu is attached to the first terminal contact surface, and a second bond element is attached to the second terminal contact surface. The second bond element is made of a material different from the material of the first bond element or is made of a type of bond element different from the type of the first bond element. | 2012-11-01 |
20120276694 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device using an oxide semiconductor is provided with stable electric characteristics to improve the reliability. In a manufacturing process of a transistor including an oxide semiconductor film, an oxide semiconductor film containing a crystal having a c-axis which is substantially perpendicular to a top surface thereof (also called a first crystalline oxide semiconductor film) is formed; oxygen is added to the oxide semiconductor film to amorphize at least part of the oxide semiconductor film, so that an amorphous oxide semiconductor film containing an excess of oxygen is formed; an aluminum oxide film is formed over the amorphous oxide semiconductor film; and heat treatment is performed thereon to crystallize at least part of the amorphous oxide semiconductor film, so that an oxide semiconductor film containing a crystal having a c-axis which is substantially perpendicular to a top surface thereof (also called a second crystalline oxide semiconductor film) is formed. | 2012-11-01 |
20120276695 | Strained thin body CMOS with Si:C and SiGe stressor - A method is disclosed which is characterized as being process integration of raised source/drain and strained body for ultra thin planar and FinFET CMOS devices. NFET and PFET devices have their source/drain raised by selective epitaxy with in-situ p-type doped SiGe for the PFET device, and in-situ n-type doped Si:C for the NFET device. Such raised source/drains offer low parasitic resistance and they impart a strain onto the device bodies of the correct sign for respective carrier, electron or hole, mobility enhancement. | 2012-11-01 |
20120276696 | VERTICAL STRUCTURE NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A vertical structure non-volatile memory device in which a gate dielectric layer is prevented from protruding toward a substrate; a resistance of a ground selection line (GSL) electrode is reduced so that the non-volatile memory device is highly integrated and has improved reliability, and a method of manufacturing the same are provided. The method includes: sequentially forming a polysilicon layer and an insulating layer on a silicon substrate; forming a gate dielectric layer and a channel layer through the polysilicon layer and the insulating layer, the gate dielectric layer and the channel layer extending in a direction perpendicular to the silicon substrate; forming an opening for exposing the silicon substrate, through the insulating layer and the polysilicon layer; removing the polysilicon layer exposed through the opening, by using a halogen-containing reaction gas at a predetermined temperature; and filling a metallic layer in the space formed by removing the polysilicon layer. | 2012-11-01 |
20120276697 | MANUFACTURING METHOD OF ARRAY SUBSTRATE - A manufacturing method of an array substrate, comprising the following steps: S1 forming a gate signal line and a gate electrode on a base substrate, successively depositing a gate insulating layer, an active layer, and a metal layer, faulting a mask formed of photoresist on the metal layer, and removing the metal layer outside a region for forming a data line and source/drain electrodes through the mask; S2. simultaneously etching the active layer and ashing the photoresist so as to expose the metal layer within a channel region; S3. etching the active layer exposed by the photoresist after being ashed after the step S2; S4. removing the metal layer within the channel region. | 2012-11-01 |
20120276698 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device includes a first transistor, a second transistor, an insulation interlayer pattern and a capacitor. The first transistor is formed in a first region of a substrate. The first transistor has a pillar protruding upwardly from the substrate and an impurity region provided in an upper portion of the pillar. The second transistor is formed in a second region of the substrate. The insulation interlayer pattern is formed on the first region and the second region to cover the second transistor and expose an upper surface of the pillar. The insulation interlayer pattern has an upper surface substantially higher than the upper surface of the pillar in the first region. The capacitor is formed on the impurity region in the upper portion of the pillar and is electrically connected to the impurity region. | 2012-11-01 |
20120276699 | MEMORY ARRAY WITH ULTRA-THIN ETCHED PILLAR SURROUND GATE ACCESS TRANSISTORS AND BURIED DATA/BIT LINES - A memory array with data/bit lines extending generally in a first direction formed in an upper surface of a substrate and access transistors extending generally upward and aligned generally atop a corresponding data/bit line. The access transistors have a pillar extending generally upward with a source region formed so as to be in electrical communication with the corresponding data/bit line and a drain region formed generally at an upper portion of the pillar and a surround gate structure substantially completely encompassing the pillar in lateral directions and extending substantially the entire vertical extent of the pillar and word lines extending generally in a second direction and in electrical contact with a corresponding surround gate structure at at least a first surface thereof such that bias voltage applied to a given word line is communicated substantially uniformly in a laterally symmetric extent about the corresponding pillar via the surround gate structure. | 2012-11-01 |
20120276700 | READ-ONLY MEMORY AND METHOD OF MANUFACTURE THEREOF - A mask-defined read-only memory array is formed on a substrate, and includes a first ROM bit and a second ROM bit of opposite polarities. The first ROM bit has a first MOS transistor and a first block layer formed over a first region of the substrate. A second source/drain region of the first MOS transistor and a first diffusion region are formed in a first region of the substrate on opposite sides of the first block layer. The second ROM bit includes a second MOS transistor. | 2012-11-01 |
20120276701 | Superjunction Structures for Power Devices and Methods of Manufacture - A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type. | 2012-11-01 |
20120276702 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a channel region, forming a buffer layer on the channel region, and heat-treating the channel region by using a gas containing halogen atoms. | 2012-11-01 |
20120276703 | METHOD OF FORMING AN INSULATED GATE FIELD EFFECT TRANSISTOR DEVICE HAVING A SHIELD ELECTRODE STRUCTURE - A method for forming a transistor having insulated gate electrodes and insulated shield electrodes within trench regions includes forming dielectric stack overlying a substrate. The dielectric stack includes a first layer of one material overlying the substrate and a second layer of a different material overlying the first layer. Trench regions are formed adjacent to the dielectric stack. | 2012-11-01 |
20120276704 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An electrostatic discharge protection device includes a substrate where an active region is defined by an isolation layer, a gate electrode simultaneously crossing both the isolation layer and the active region, and a junction region formed in the active region at both sides of the gate electrode and separated from the isolation layer by a certain distance in a direction where the gate electrode is extended. The electrostatic discharge protection device is able to prevent the increase of a leakage current while securing an electrostatic discharge protection property that a semiconductor device requires. | 2012-11-01 |
20120276705 | METHOD OF MAKING A SEMICONDUCTOR DEVICE AS A CAPACITOR - Forming a capacitor structure includes forming a first dielectric layer over a conductive region, wherein the first dielectric layer has a first conductive layer at a top surface of the first dielectric layer; forming a first opening in the first dielectric layer over the conductive region, wherein the first opening exposes a first sidewall of the first conductive layer; forming a second conductive layer within the first opening, wherein the second conductive layer contacts the first sidewall of the first conductive layer; removing a portion of the second conductive layer from the bottom of the first opening; forming an insulating layer within the first opening; removing a portion of the insulating layer from the bottom of the first opening; extending the first opening through the first dielectric layer to expose the conductive region; and filling the first opening with a conductive material, wherein the conductive material contacts the conductive region. | 2012-11-01 |
20120276706 | DAMASCENE METAL-INSULATOR-METAL (MIM) DEVICE IMPROVED SCALEABILITY - A present method of fabricating a memory device includes the steps of providing a dielectric layer;, providing an opening in the dielectric layer, providing a first conductive body in the opening, providing a switching body in the opening, the first conductive body and switching body Filling the opening, and providing a second conductive body over the switching body. In an alternate embodiment, a second dielectric layer is provided over the first-mentioned dielectric layer, and the switching body is provided in an opening in the second dielectric layer. | 2012-11-01 |
20120276707 | METHOD FOR FORMING TRENCH ISOLATION - A method for forming a trench isolation is disclosed, comprising, providing a substrate comprising a trench, forming a polysilicon layer in the trench, and subjecting the substrate to a treating process to convert the polysilicon layer to an isolating layer, wherein the treating process is fine tuned for the isolating layer on opposite sidewalls of the trench to expand to contact with each other so that the isolating layer fills the trench. | 2012-11-01 |
20120276708 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method includes: forming an device isolation region in a substrate to divide the device isolation region into first and second diffusion regions; forming a target film on the substrate; forming a hard mask layer and a first resist layer on the film; forming a first pattern on the first resist layer; etching the hard mask layer by using the first pattern as a mask; forming a second resist layer on the hard mask layer; forming a second pattern including a first space on the second resist layer for isolating the first pattern; forming a third pattern including a second space shrunk from the first space on the hard mask layer by carrying out size conversion etching by using the second pattern formed on the second resist layer as a mask; and etching the film to be processed by using the third pattern formed on the hard mask layer. | 2012-11-01 |
20120276709 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method includes: forming an device isolation region in a substrate to divide the device isolation region into a first and a second diffusion regions; forming a target film on the substrate; forming a hard mask layer and a first resist layer on the film; forming a first pattern on the first resist layer; etching the hard mask layer using the first pattern as a mask; forming a second resist layer on the hard mask layer; forming a second pattern including a first space on the second resist layer for isolating the first pattern; forming a third pattern including a second space shrunk from the first space on the hard mask layer by carrying out size conversion etching by using the second pattern formed on the second resist layer as a mask; and etching the film to be processed by using the third pattern formed on the hard mask layer. | 2012-11-01 |
20120276710 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device includes a first transistor including a first source/drain region and a first sidewall spacer, and a second transistor including a second source/drain region and a second sidewall spacer, the first sidewall spacer has a first width and the second sidewall spacer has a second width wider than the first width, and the first source/drain region has a first area and the second source/drain region has a second area larger than the first area. | 2012-11-01 |
20120276711 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE HAVING SPACER WITH AIR GAP - A semiconductor device having a spacer with an air gap is manufactured by forming a first conductive pattern over a semiconductor substrate; forming a spacer on sidewalls of the first conductive pattern; forming a sacrifice layer on sidewall of the spacer, the sacrifice layer having a different etching selectivity with the spacer; forming a second conductive pattern to fill a space between the first conductive pattern and the first conductive pattern; and forming an air gap between the first and second conductive patterns by selectively removing the sacrifice layer. | 2012-11-01 |
20120276712 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - According to one embodiment, a semiconductor device having a Ge— or SiGe-fin structure includes a convex-shaped active area formed along one direction on the surface region of a Si substrate, a buffer layer of Si | 2012-11-01 |
20120276713 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Disclosed is a method for manufacturing a semiconductor device, which provides an isolation region in which a dense silicon oxide film is formed in a trench that requires high aspect ratio. The method includes forming an isolation trench using, as an etching mask, a nitride mask film formed on a substrate, forming a liner nitride film in the isolation trench, depositing a flowable silazane compound by a CVD method such that the height of the flowable silazane compound is higher than the upper surface of the nitride mask film from the upper portion of the trench, performing heat treatment under an oxidizing atmosphere to convert the flowable silazane compound film into a silicon oxide film and simultaneously densifying therefor, and planarizing the silicon oxide film to the height of the upper surface of the nitride mask film. | 2012-11-01 |
20120276714 | METHOD OF OXIDIZING POLYSILAZANE - A method of oxidizing polysilazane is disclosed, comprising providing a substrate, comprising a trench, forming a polysilazane layer in the trench, and treating the polysilazane layer in an acid containing solution applied with mega-sonic waves to oxidize the polysilazane layer, wherein the acid containing solution comprises phosphoric acid, sulfuric acid, H | 2012-11-01 |
20120276715 | METHOD FOR MANUFACTURING COMBINED SUBSTRATE HAVING SILICON CARBIDE SUBSTRATE - A connected substrate having a supporting portion and first and second silicon carbide substrates is prepared. The first silicon carbide substrate has a first backside surface connected to the supporting portion, a first front-side surface, and a first side surface connecting the first backside surface and the first front-side surface to each other. The second silicon carbide substrate has a second backside surface connected to the supporting portion, a second front-side surface, and a second side surface connecting the second backside surface and the second front-side surface to each other and forming a gap between the first side surface and the second side surface. A filling portion for filling the gap is formed. Then, the first and second front-side surfaces are polished. Then, the filling portion is removed. Then, a closing portion for closing the gap is formed. | 2012-11-01 |
20120276716 | SEMICONDUCTOR WAFER-TO-WAFER BONDING FOR DISSIMILAR SEMICONDUCTOR DIES AND/OR WAFERS - A process for wafer-to-wafer bonding of a first wafer having a first set of dies of a first die size to a reconstituted wafer of a second set of dies having a second die size different than the first die size. The process includes aligning the second set of dies such that a second set of interconnects on the second set of dies aligns with a first set of interconnects on the first set of dies. The second set of dies includes a spacing between the second set of dies based on parameters of the first set of dies. The process also includes coupling the reconstituted wafer with the first wafer to create a wafer stack. | 2012-11-01 |
20120276717 | ORGANOPOLYSILOXANE, TEMPORARY ADHESIVE COMPOSITION CONTAINING ORGANOPOLYSILOXANE, AND METHOD OF PRODUCING THINNED WAFER USING THE SAME - The present invention provides a non-aromatic saturated hydrocarbon group-containing organopolysiloxane containing the following units (I) to (III):
| 2012-11-01 |
20120276718 | METHOD OF FABRICATING GRAPHENE-BASED FIELD EFFECT TRANSISTOR - The present invention provides a method of fabricating a graphene-based field effect transistor, which includes steps of: providing a semiconductor substrate on which a non-functionized graphene layer is formed; forming a metal oxide film as a nucleation layer through a reaction between a metal source and water which acts as oxidizer and is physically absorbed to a surface of the graphene layer; and generating a HfO | 2012-11-01 |
20120276719 | METHODS OF FORMING SEMICONDUCTOR MEMORY DEVICES HAVING VERTICALLY STACKED MEMORY CELLS THEREIN - Methods of forming vertical nonvolatile memory devices utilize carbon-blocking sacrificial capping layers to increase device yield by reducing the likelihood that one or more vertically-stacked layers of materials will lift-off during fabrication. These capping layers may be provided to cover carbon-containing sacrificial layers that are highly polymerized. | 2012-11-01 |
20120276720 | CONTROL OF THRESHOLD VOLTAGES IN HIGH-K METAL GATE STACK AND STRUCTURES FOR CMOS DEVICES - A high-k metal gate stack and structures for CMOS devices and a method for forming the devices. The gate stack includes a germanium (Ge) material layer formed on the semiconductor substrate, a diffusion barrier layer formed on the Ge material layer, a high-k dielectric having a high dielectric constant greater than approximately 3.9 formed over the diffusion barrier layer, and a conductive electrode layer formed above the high-k dielectric layer. | 2012-11-01 |
20120276721 | METHOD OF FORMING AN OXIDE LAYER AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE INCLUDING THE OXIDE LAYER - A method of forming an oxide layer. The method includes: forming a layer of reaction-inhibiting functional groups on a surface of a substrate; forming a layer of precursors of a metal or a semiconductor on the layer of the reaction-inhibiting functional groups; and oxidizing the precursors of the metal or the semiconductor in order to obtain a layer of a metal oxide or a semiconductor oxide. According to the method, an oxide layer having a high thickness uniformity may be formed and a semiconductor device having excellent electrical characteristics may be manufactured. | 2012-11-01 |
20120276722 | METHOD FOR GROWING SEMIPOLAR NITRIDE - A method for growing a semipolar nitride comprises steps: forming a plurality of parallel discrete trenches on a silicon substrate , each discrete trenches having a first wall and a second wall, wherein a tilt angle is formed between the surface of the silicon substrate and the first wall; forming a buffer layer on the silicon substrate and the trenches, wherein the buffer layer on the first wall has a plurality of growing zones and a plurality of non-growing zones among the growing zones and complementary to the growing zones; forming a cover layer on the buffer layer and revealing the growing zones; and growing a semipolar nitride from the growing zones of the buffer layer and covering the cover layer. Thereby cracks caused by thermal stress between the silicon substrate and semipolar nitride are decreased and the quality of the semipolar nitride film is improved. | 2012-11-01 |
20120276723 | ION INJECTION SIMULATION METHOD, ION INJECTION SIMULATION DEVICE, METHOD OF PRODUCING SEMICONDUCTOR DEVICE, AND METHOD OF DESIGNING SEMICONDUCTOR DEVICE - An ion injection simulation method includes: calculating a reinjection dose injected into a substrate and a structure formed on the substrate and reinjected from a side face of the structure; and calculating concentration distribution of impurities injected into the substrate from a distribution function and reinjection conditions of the reinjection dose. | 2012-11-01 |
20120276724 | SPIN-ON FORMULATION AND METHOD FOR STRIPPING AN ION IMPLANTED PHOTORESIST - A spin-on formulation that is useful in stripping an ion implanted photoresist is provided that includes an aqueous solution of a water soluble polymer containing at least one acidic functional group, and at least one lanthanide metal-containing oxidant. The spin-on formulation is applied to an ion implanted photoresist and baked to form a modified photoresist. The modified photoresist is soluble in aqueous, acid or organic solvents. As such one of the aforementioned solvents can be used to completely strip the ion implanted photoresist as well as any photoresist residue that may be present. A rinse step can follow the stripping of the modified photoresist. | 2012-11-01 |
20120276725 | METHODS OF SELECTIVELY FORMING METAL-DOPED CHALCOGENIDE MATERIALS, METHODS OF SELECTIVELY DOPING CHALCOGENIDE MATERIALS, AND METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES INCLUDING SAME - Methods of selectively forming a metal-doped chalcogenide material comprise exposing a chalcogenide material to a transition metal solution, and incorporating transition metal of the transition solution into the chalcogenide material without substantially incorporating the transition metal into an adjacent material. The chalcogenide material is not silver selenide. Another method comprises forming a chalcogenide material adjacent to and in contact with an insulative material, exposing the chalcogenide material and the insulative material to a transition metal solution, and diffusing transition metal of the transition metal solution into the chalcogenide material while substantially no transition metal diffuses into the insulative material. A method of doping a chalcogenide material of a memory cell with at least one transition metal without using an etch or chemical mechanical planarization process to remove the transition metal from an insulative material of the memory cell is also disclosed, wherein the chalcogenide material is not silver selenide. | 2012-11-01 |
20120276726 | METHOD FOR FABRICATING SEMICONDUCTOR POWER DEVICE - A method for fabricating a semiconductor power device includes the following steps. First, a substrate having thereon at least a semiconductor layer and a pad layer is provided. Then, at least a trench is etched into the pad layer and the semiconductor layer followed by depositing a dopant source layer in the trench and on the pad layer. A process is carried out thermally driving in dopants of the dopant source layer into the semiconductor layer. A rapid thermal process is performed to mend defects in the dopant source layer and defects between the dopant source layer and the semiconductor layer. Finally, a polishing process is performed to remove the dopant source layer from a surface of the pad layer. | 2012-11-01 |
20120276727 | METHOD OF FORMING GATE PATTERN AND SEMICONDUCTOR DEVICE - This disclosure relates to a method of forming a gate pattern and a semiconductor device. The gate pattern comprises a plurality of parallel gate bars, and each gate bar is broken up by gaps. The method comprises: making an etching characteristic of a gate material layer at least at positions where the gaps are to be formed different from that at remaining positions; forming a plurality of parallel openings in a second resist layer; performing a first etching process on the gate material layer with the second resist layer as a mask, wherein portions of the gate material layer at least at the positions where the gaps are to be formed are selectively left; and performing a second etching process on the gate material layer so as to selectively remove the portions. This method can more accurately control the shape and size of the gate pattern. | 2012-11-01 |
20120276728 | TRENCH TYPE SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME - The trench type semiconductor device includes a gate insulating film placed on the bottom surface and the sidewall surface of the trench formed from the surface of a first base layer; a gate electrode placed on the gate insulating film and fills up into a trench; an interlayer insulating film covering the gate electrode; a second base layer placed on the surface of the first base layer, and is formed more shallowly than the bottom surface of the trench; a source layer placed on the surface of the second base layer; a source electrode connected to the second base layer in the bottom surface of a self-aligned contact trench formed in the second base layer by applying the interlayer insulating film as a mask, and is connected to the source layer in the sidewall surface; a drain layer placed at the back side of the first base layer; and a drain electrode placed at the drain layer, for achieving the minute structure by the self-alignment, reducing the on resistance, and improving the breakdown capability, and providing a fabrication method for the same. | 2012-11-01 |