45th week of 2008 patent applcation highlights part 13 |
Patent application number | Title | Published |
20080272421 | METHODS, CONSTRUCTIONS, AND DEVICES INCLUDING TANTALUM OXIDE LAYERS - Methods, constructions, and devices that include tantalum oxide layers adjacent to niobium nitride are disclosed herein. In certain embodiments, the niobium nitride is crystalline and has a hexagonal close-packed structure. Optionally, the niobium nitride can have a surface that includes niobium oxide adjacent to at least a portion thereof. In certain embodiments, the tantalum oxide layer is crystallographically textured and has a hexagonal structure. | 2008-11-06 |
20080272422 | Transistor Providing Different Threshold Voltages and Method of Fabrication Thereof - A transistor includes a channel region with a first portion and a second portion. A length of the first portion is smaller than a length of the second portion. The first portion has a higher threshold voltage than the second portion. The lower threshold voltage of the second portion allows for an increased ON current. Despite the increase attained in the ON current, the higher threshold voltage of the first portion maintains or lowers a relatively low OFF current for the transistor. | 2008-11-06 |
20080272423 | Conductive structures, non-volatile memory device including conductive structures and methods of manufacturing the same - Conductive structures in an integrated circuit device including an integrated circuit substrate and first conductive layer patterns on the substrate. Second conductive layer patterns are on the substrate extending between respective ones of the first conductive layer patterns. Adjacent ones of the first and second conductive layer patterns are on different horizontal planes relative to the substrate to reduce parasitic capacitance therebetween. | 2008-11-06 |
20080272424 | Nonvolatile Memory Device Having Fast Erase Speed And Improved Retention Characteristics And Method For Fabricating The Same - Disclosed herein is a nonvolatile memory device that includes a substrate, a tunneling layer over the substrate, a charge trapping layer over the tunneling layer, an insulating layer for improving retention characteristics over the charge trapping layer, a blocking layer over the insulating layer, and a control gate electrode over the blocking layer. Also disclosed herein is a method of making the device. | 2008-11-06 |
20080272425 | Semiconductor Storage Element and Manufacturing Method Thereof - A semiconductor storage element includes: a semiconductor layer constituted of a line pattern with a predetermined width formed on a substrate; a quantum dot forming an electric charge storage layer formed on the semiconductor layer through a first insulating film serving as a tunnel insulating film; an impurity diffusion layer formed in a surface layer of the semiconductor layer so as to sandwich the quantum dot therebetween; and a control electrode formed on the quantum dot through a second insulating film. | 2008-11-06 |
20080272426 | Nonvolatile Memory Transistors Including Active Pillars and Related Methods and Arrays - Nonvolatile memory transistors including active pillars having smooth side surfaces with an acute inward angle are provided. The transistor has an active pillar having smooth side surfaces with an acute inward angle and protrudes from semiconductor substrate. A gate electrode surrounds the side surfaces of the active pillar. A charge storage layer is provided between the active pillar and the gate electrode. Nonvolatile memory arrays including the transistor and related methods of fabrication are also provided. | 2008-11-06 |
20080272427 | Sonos Memory Device With Reduced Short-Channel Effects - A non-volatile memory device on a semiconductor substrate having a semiconductor surface layer ( | 2008-11-06 |
20080272428 | Semiconductor Device Structure With a Tapered Field Plate and Cylindrical Drift Region Geometry - A vertically oriented self terminating discrete trench MOS device ( | 2008-11-06 |
20080272429 | SUPERJUNCTION DEVICES HAVING NARROW SURFACE LAYOUT OF TERMINAL STRUCTURES AND METHODS OF MANUFACTURING THE DEVICES - Superjunction semiconductor devices having narrow surface layout of terminal structures and methods of manufacturing the devices are provided. The narrow surface layout of terminal structures is achieved, in part, by connecting a source electrode to a body contact region within a semiconductor substrate at a body contact interface comprising at least a first side of the body contact region other than a portion of a first main surface of the semiconductor substrate. | 2008-11-06 |
20080272430 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes an active region defined in a substrate, the active region having a trench extending below a surface of the substrate; an impurity region provided along a bottom surface and a lower sidewall of the trench, wherein an upper portion of the impurity region is spaced apart from the surface of the substrate and an upper portion of the trench; a gate insulating layer provided along an inner surface of the trench; and a gate electrode provided in the trench. | 2008-11-06 |
20080272431 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING RECESS GATE STRUCTURE WITH VARYING RECESS WIDTH FOR INCREASED CHANNEL LENGTH - A varying-width recess gate structure having a varying-width recess formed in a semiconductor device can sufficiently increase the channel length of the transistor having a gate formed in the varying-width recess, thereby effectively reducing the current leakage and improving the refresh characteristics. In the method of manufacturing the recess gate structure, etching is performed twice or more, so as to form a gate recess having varying width in the substrate, and a gate is formed in the gate recess. | 2008-11-06 |
20080272432 | ACCUMULATION MODE MOS DEVICES AND METHODS FOR FABRICATING THE SAME - Accumulation mode MOS transistors and methods for fabricating such transistors are provided. A method comprises providing an SOI layer disposed overlying a substrate with an insulating layer interposed therebetween. The SOI layer is impurity doped with a first dopant of a first conductivity type and spacers and a gate stack having a sacrificial polycrystalline silicon gate electrode is formed on the SOI layer. A first and a second silicon region are impurity doped with a second dopant of the first conductivity type. The first silicon region and the second silicon region are aligned to the gate stack and spacers. The sacrificial polycrystalline silicon gate electrode is removed and a metal-comprising gate electrode is formed from a metal-comprising material having a mid-gap work function. | 2008-11-06 |
20080272433 | DUAL METAL GATES FOR MUGFET DEVICE - Exemplary embodiments provide methods and structures for controlling work function values of dual metal gate electrodes for transistor devices. Specifically, the work function value of one of the PMOS and NMOS metal gate electrodes can be controlled by a reaction between stacked layers deposited on a gate dielectric material. The stacked layers can include a first-metal-containing material such as Al | 2008-11-06 |
20080272434 | NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile memory device and a method of manufacturing the same are disclosed. In the non-volatile memory device, first gate structures and first impurity diffusion regions are formed on a substrate. A first insulating interlayer is formed on the substrate. A semiconductor layer including second gate structures and second impurity diffusion regions is formed on the first insulating interlayer. A second insulating interlayer is formed on the semiconductor layer. A contact plug connecting the first impurity diffusion regions to the second impurity diffusion regions is formed. A common source line connected to the contact plug is formed on the second insulating interlayer. The common source line connected to the first and second impurity diffusion regions is formed over a top semiconductor layer. | 2008-11-06 |
20080272435 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes a first gate structure including a gate dielectric layer directly contacting the substrate, a bottom electrode on the gate dielectric layer and a top electrode on the bottom electrode, and a second gate structure including a gate dielectric layer directly contacting the substrate and a gate electrode on the gate dielectric layer. | 2008-11-06 |
20080272436 | Semiconductor device and method of fabricating the same - A semiconductor device includes a first stress film covering a first gate electrode and first source/drain areas of a first transistor area and at least a portion of a third gate electrode of an interface area, a second stress film covering a second gate electrode and second source/drain areas of a second transistor area and overlapping at least a portion of the first stress film on the third gate electrode of the interface area, and an interlayer insulating film formed on the first and the second stress film. The semiconductor device further includes a plurality of first contact holes formed through the interlayer insulating film and the first stress film in the first transistor area to expose the first gate electrode and the first source/drain areas, a plurality of second contact holes formed through the interlayer insulating film and the second stress film in the second transistor area to expose the second gate electrode and the second source/drain areas, and a third contact hole formed through the interlayer insulating film, the second stress film, and the first stress film in the interface area to expose the third gate electrode. A depth of a recessed portion of an upper side of the third gate electrode in which the third contact hole is formed is equal to or larger than a depth of a recessed portion of an upper side of the first gate electrode in which the first contact hole is formed. | 2008-11-06 |
20080272437 | Threshold Adjustment for High-K Gate Dielectric CMOS - A CMOS structure is disclosed in which a first type FET has an extremely thin oxide liner. This thin liner is capable of preventing oxygen from reaching the high-k dielectric gate insulator of the first type FET. A second type FET device of the CMOS structure has a thicker oxide liner. As a result, an oxygen exposure is capable to shift the threshold voltage of the second type of FET, without affecting the threshold value of the first type FET. The disclosure also teaches methods for producing the CMOS structure in which differing type of FET devices have differing thickness liners, and the threshold values of the differing type of FET devices is set independently from one another. | 2008-11-06 |
20080272438 | CMOS Circuits with High-K Gate Dielectric - A CMOS structure is disclosed in which a first type FET contains a liner, which liner has oxide and nitride portions. The nitride portions are forming the edge segments of the liner. These nitride portions are capable of preventing oxygen from reaching the high-k dielectric gate insulator of the first type FET. A second type FET device of the CMOS structure has a liner without nitride portions. As a result, an oxygen exposure is capable to shift the threshold voltage of the second type of FET, without affecting the threshold value of the first type FET. The disclosure also teaches methods for producing the CMOS structure in which differing type of FET devices have their threshold values set independently from one another. | 2008-11-06 |
20080272439 | SMALL GEOMETRY MOS TRANSISTOR WITH THIN POLYCRYSTALLINE SURFACE CONTACTS AND METHOD FOR MAKING - Process for fabrication of MOS semiconductor structures and transistors such as CMOS structures and transistors with thin gate oxide, polysilicon surface contacts having thickness on the order of 500 Angstroms or less and with photo-lithographically determined distances between the gate surface contact and the source and drain contacts. Semiconductor devices having polysilicon surface contacts wherein the ratio of the vertical height to the horizontal dimension is approximately unity. Small geometry Metal-Oxide-Semiconductor (MOS) transistor with thin polycrystalline surface contacts and method and process for making the MOS transistor. MOS and CMOS transistors and process for making. Process for making transistors using Silicon Nitride layer to achieve strained Silicon substrate. Strained Silicon devices and transistors wherein fabrication starts with strained Silicon substrate. Strained Silicon devices which use a Silicon Nitride film applied to the substrate at high temperature and which use differential thermal contraction rates during cooling to achieve strained Silicon. | 2008-11-06 |
20080272440 | SEMICONDUCTOR DEVICE CAPABLE OF AVOIDING LATCHUP BREAKDOWN RESULTING FROM NEGATIVE VARIATION OF FLOATING OFFSET VOLTAGE - A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper surface of an n-type impurity region, a p | 2008-11-06 |
20080272441 | Method and circuit for down-converting a signal - Methods, systems, and apparatuses for down-converting an electromagnetic (EM) signal by aliasing the EM signal are described herein. Briefly stated, such methods, systems, and apparatuses operate by receiving an EM signal and an aliasing signal having an aliasing rate. The EM signal is aliased according to the aliasing signal to down-convert the EM signal. The term aliasing, as used herein, refers to both down-converting an EM signal by under-sampling the EM signal at an aliasing rate, and down-converting an EM signal by transferring energy from the EM signal at the aliasing rate. In an embodiment, the EM signal is down-converted to an intermediate frequency signal. In another embodiment, the EM signal is down-converted to a demodulated baseband information signal. In another embodiment, the EM signal is a frequency modulated (FM) signal, which is down-converted to a non-FM signal, such as a phase modulated signal or an amplitude modulated signal. | 2008-11-06 |
20080272442 | N+ POLY ON HIGH-K DIELECTRIC FOR SEMICONDUCTOR DEVICES - The present invention facilitates semiconductor fabrication by providing methods of fabrication that employ high-k dielectric layers. An n-type well region ( | 2008-11-06 |
20080272443 | Field effect transistor having field plate electrodes - A field effect transistor includes an active layer formed on a semiconductor substrate, source and drain electrodes formed apart from each other on the active layer, a gate electrode formed between the source and drain electrodes, a first interlayer film formed on the active layer, a first field plate (FP) electrode connected to the gate electrode and provided on the first interlayer film between the gate and drain electrodes, a second interlayer film formed on the first interlayer film, and a second FP electrode connected to the source electrode and provided on the second interlayer film between the first FP and drain electrodes. The field effect transistor is provided which exhibits a comparatively high gain factor at high frequencies. | 2008-11-06 |
20080272444 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device of the present invention is a method of manufacturing a semiconductor device that is provided with a step of successively forming a gate insulating film and a gate electrode on a semiconductor substrate and a step of forming a silicon nitride film that covers at least the gate insulating film and the side portions of the gate electrode, in which the silicon nitride film is formed by laminating a plurality of silicon nitride layers by repeating a step of forming a silicon nitride layer of a predetermined thickness by the low-pressure chemical vapor deposition method and a step of exposing the silicon nitride layer to nitrogen. | 2008-11-06 |
20080272445 | LOW-K DISPLACER FOR OVERLAP CAPACITANCE REDUCTION - Source/drain extensions and source and drain regions are formed in a semiconductor substrate utilizing an optional temporary first gate spacer and a temporary second gate spacer. After forming a gate silicide and a source and drain silicide in a silicidation process, the optional temporary first gate spacer and a temporary second gate spacer are removed. Low-k dielectric material is disposed directly on the sidewalls of the gate electrode. The low-k dielectric material may form a portion of a lower gate spacer. Alternatively, the low-k dielectric material may form a layer that contacts and covers the source and drain regions. The low-k material displaces the optional temporary first gate spacer and the temporary second gate spacer to lower the overlap capacitance between the gate electrode and the source/drain extensions. A continuous mobile ion diffusion barrier dielectric layer is formed over the low-k material. | 2008-11-06 |
20080272446 | Packaged MEMS device assembly - A packaged micro-electromechanical systems (MEMS) device assembly includes a MEMS device, a substrate within which the MEMS device is disposed, and a lid disposed over the substrate. The assembly may include one or more first cavities within the lid having a predetermined volume satisfying packaging specifications for the packaged MEMS device assembly. The assembly may include one or more second cavities within the lid and one or more corresponding overflow areas within the lid, where each second cavity contains a material and each corresponding overflow area is adapted to catch overflow of the material. The assembly may include one or more third cavities within the lid and one or more channels within one of the substrate and the lid to fluidically connect the MEMS device to the third cavities. | 2008-11-06 |
20080272447 | METHOD FOR MANUFACTURING A MICRO-ELECTRO-MECHANICAL DEVICE, IN PARTICULAR AN OPTICAL MICROSWITCH, AND MICRO-ELECTRO-MECHANICAL DEVICE THUS OBTAINED - A method for manufacturing a micro-electro-mechanical device, which has supporting parts and operative parts, includes providing a first semiconductor wafer, having a first layer of semiconductor material and a second layer of semiconductor material arranged on top of the first layer, forming first supporting parts and first operative parts of the device in the second layer, forming temporary anchors in the first layer, and bonding the first wafer to a second wafer, with the second layer facing the second wafer. After bonding the first wafer and the second wafer together, second supporting parts and second operative parts of said device are formed in the first layer. The temporary anchors are removed from the first layer to free the operative parts formed therein. | 2008-11-06 |
20080272448 | INTEGRATED CIRCUIT HAVING A MAGNETIC TUNNEL JUNCTION DEVICE - An integrated circuit having a magnetic tunnel junction device is disclosed. In one embodiment, the device includes: a spin transfer torque magnetization reversal structure including a first ferromagnetic structure, a second ferromagnetic structure, and a tunnel barrier structure between the first ferromagnetic structure and the second ferromagnetic structure. | 2008-11-06 |
20080272449 | Solid-state image pickup device, solid-state image pickup device manufacturing method and camera - A solid-state image pickup device | 2008-11-06 |
20080272450 | PORTABLE OPTICAL DETECTION CHIP AND MANUFACTURING METHOD THEREOF - A portable optical detection chip comprises a substrate, a plurality of avalanche-type photosensitive device modules and a plurality of plane mirrors. The plurality of avalanche-type photosensitive device modules are formed on the substrate, and each of them comprises a plurality of avalanche-type photosensitive devices and a plurality of lenses. Each of the lenses is stacked on one of the avalanche-type photosensitive devices. The plurality of plane mirrors are disposed between the avalanche-type photosensitive device modules. That is, the avalanche-type photosensitive device modules are separated from each other by the plane mirrors. | 2008-11-06 |
20080272451 | Image Sensor and Method of Manufacturing The Same - An image sensor and method of manufacturing the same are provided. The image sensor can include a semiconductor substrate having unit pixels; an interlayer dielectric layer formed on the semiconductor substrate and including metal interconnections; a first protective layer comprising an oxide layer formed on the interlayer dielectric layer; a second protective layer comprising an oxide-nitride layer formed on the first protective layer; and a microlens formed on the second protective layer. | 2008-11-06 |
20080272452 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - An image sensor that includes a hard mask layer formed in the upper surface region of the planarization layer and under a microlens to protect an underlying planarization layer from chemicals used during performing a cleaning process after formation of the microlens. The microlens is composed of inorganic materials to prevent cracking by physical impacts. | 2008-11-06 |
20080272453 | OPTICAL DEVICE COOLING APPARATUS AND METHOD - An optical device cooling apparatus includes an image sensor array and a MEMS fan. The MEMS fan is formed integrally with the image sensor array, and cools the image sensor array. | 2008-11-06 |
20080272454 | Light-Collecting Device, Solid-State Imaging Apparatus and Method of Manufacturing Thereof - It is realized a high sensitive solid-state imaging apparatus which corresponds to an optical system having a short focal length (an optical system having a large incident angle θ). | 2008-11-06 |
20080272455 | SOLID-STATE IMAGING DEVICE - An n/p semiconductor substrate is formed in such a manner that an n type semiconductor layer is deposited on a p | 2008-11-06 |
20080272456 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device comprises a buffer layer | 2008-11-06 |
20080272457 | Formation Of Dummy Features And Inductors In Semiconductor Fabrication - A structure and a method for forming the same. The structure includes (a) a substrate which includes a top substrate surface which defines a reference direction perpendicular to the top substrate surface, (b) N semiconductor regions on the substrate, and (c) P semiconductor regions on the substrate, N and P being positive integers. The N semiconductor regions comprise dopants. The P semiconductor regions do not comprise dopants. The structure further includes M interconnect layers on top of the substrate, the N semiconductor regions, and the P semiconductor regions, M being a positive integer. The M interconnect layers include an inductor. (i) The N semiconductor regions do not overlap and (ii) the P semiconductor regions overlap the inductor in the reference direction. A plane perpendicular to the reference direction and intersecting a semiconductor region of the N semiconductor regions intersects a semiconductor region of the P semiconductor regions. | 2008-11-06 |
20080272458 | POST LAST WIRING LEVEL INDUCTOR USING PATTERNED PLATE PROCESS - A semiconductor structure. The semiconductor structure includes: a substrate having a metal wiring level within the substrate; a capping layer on and above the substrate; an insulative layer on and above the capping layer; a first layer of photo-imagable material on and above the insulative layer; a layer of oxide on and above the first layer of photo-imagable material; a second layer of photo-imagable material on and above the layer of oxide; an inductor; and a wire bond pad. A first portion of the inductor is in the second layer of photo-imagable material, the layer of oxide, the first layer of photo-imagable material, the insulative layer, and the capping layer. A second portion of the inductor is in only the second layer of photo-imagable material. The wire bond pad in only the first layer of photo-imagable material, the insulative layer, and the capping layer. | 2008-11-06 |
20080272459 | Semiconductor Device and Manufacturing Method of Semiconductor Device - A semiconductor device and method of manufacturing the same are provided. According to certain embodiments, a device layer structure can be formed above a metal wiring line by using a stepped portion of the wiring line as an alignment key. The stepped portion can be provided by a height difference between a first insulating layer and the metal wiring line formed in a trench of the first insulating layer. In one embodiment, the stepped portion can be formed by removing a thickness from a top surface of the first insulating layer after forming the metal wiring line in the trench. | 2008-11-06 |
20080272460 | THIN FILM RESISTORS INTEGRATED AT TWO DIFFERENT METAL INTERCONNECT LEVELS OF SINGLE DIE - An integrated circuit includes a first thin film resistor on a first dielectric layer. A first layer of interconnect conductors on the first dielectric layer includes a first and second interconnect conductors electrically contacting the first thin film resistor. A second dielectric layer is formed on the first dielectric layer. A second thin film resistor is formed on the second dielectric layer. A third dielectric layer is formed on the second dielectric layer. A second layer of interconnect conductors on the third dielectric layer includes a third interconnect conductor extending through an opening in the second and third dielectric layers to contact the first interconnect conductor, a fourth interconnect conductor extending through an opening in the second and third dielectric layers to contact the second interconnect conductor, and two interconnect conductors extending through openings in the third dielectric layer of the second thin film resistor. A fifth interconnect conductor extends through an opening in the first dielectric layer to contact a circuit element. | 2008-11-06 |
20080272461 | Capture of residual refractory metal within semiconductor device - There is provided a semiconductor device with a configuration in which a dummy silicide area 11 is provided in the vicinity of a non-silicide area 2 to easily capture residual refractory metals, resulting in an improved yield by preventing the trapping of residual refractory metals into a non-silicide area and thereby reducing a junction leakage within the non-silicide area. | 2008-11-06 |
20080272462 | Nitride-Based Semiconductor Device and Method for Fabricating the Same - A nitride-based semiconductor device according to the present invention includes a semiconductor multilayer structure supported on a substrate structure | 2008-11-06 |
20080272463 | Method and Apparatus for Growing a Group (III) Metal Nitride Film and a Group (III) Metal Nitride Film - A process and apparatus for growing a group (III) metal nitride film by remote plasma enhanced chemical vapour deposition are described. The process comprises heating an object selected from the group consisting of a substrate and a substrate comprising a buffer layer in a growth chamber to a temperature in the range of from about 400° C. to o about 750° C., producing active neutral nitrogen species in a nitrogen plasma remotely located from the growth chamber and transferring the active neutral nitrogen species to the growth chamber. A reaction mixture is formed in the growth chamber, the reaction mixture containing a species of a group (III) metal that is capable of reacting with the nitrogen species so as to form a group (III) metal nitride film and a film of group (III) s metal nitride is formed on the heated object under conditions whereby the film is suitable for device purposes. Also described is a group (III) metal nitride film which exhibits an oxygen concentration below 1.6 atomic %. | 2008-11-06 |
20080272464 | Semiconductor Wafer Having Through-Hole Vias on Saw Streets with Backside Redistribution Layer - A semiconductor wafer contains a plurality of die with contact pads disposed on a first surface of each die. Metal vias are formed in trenches in the saw street guides and are surrounded by organic material. Traces connect the contact pads and metal vias. The metal vias can be half-circle vias or full-circle vias. The metal vias are surrounded by organic material. Redistribution layers (RDL) are formed on a second surface of the die opposite the first surface. The RDL and THV provide expanded interconnect flexibility to adjacent die. Repassivation layers are formed between the RDL on the second surface of the die for electrical isolation. The die are stackable and can be placed in a semiconductor package with other die. The RDL provide electrical interconnect to the adjacent die. Bond wires and solder bumps also provide electrical connection to the semiconductor die. | 2008-11-06 |
20080272465 | Semiconductor Die with Through-Hole Via on Saw Streets and Through-Hole Via in Active Area of Die - A semiconductor wafer contains a plurality of die with contact pads disposed on a first surface of each die. Metal vias are formed in trenches in the saw street guides and are surrounded by organic material. Traces connect the contact pads and metal vias. The metal vias can be half-circle vias or full-circle vias. Metal vias are also formed through the contact pads on the active area of the die. Redistribution layers (RDL) are formed on a second surface of the die opposite the first surface. Repassivation layers are formed between the RDL for electrical isolation. The die are stackable and can be placed in a semiconductor package with other die. The vias through the saw streets and vias through the active area of the die, as well as the RDL, provide electrical interconnect to the adjacent die. | 2008-11-06 |
20080272466 | SEMICONDUCTOR SUBSTRATES INCLUDING VIAS OF NONUNIFORM CROSS SECTION AND ASSOCIATED STRUCTURES - Methods for forming a via and a conductive path are disclosed. The methods include forming a via within a wafer with cyclic etch/polymer phases, followed by an augmented etch phase. The resulting via may include a first portion having a substantially uniform cross section and a second portion in the form of a hollow ball, extending laterally further within the wafer than the first portion. Backgrinding the wafer to the second portion of the via may create a vent. A conductive path may be formed by filling the via with a conductive material, such as solder. Flux gases may escape through the vent. The wafer surrounding the second portion of the via may be removed, exposing a conductive element in the shape of a ball, the shape of the second portion of the via. Semiconductor devices including the conductive paths of the present invention are also disclosed. | 2008-11-06 |
20080272467 | Method for Forming Fine Pattern of Semiconductor Device - A method for forming a fine pattern of a semiconductor device includes forming a deposition film over a substrate having an underlying layer. The deposition film includes first, second, and third mask films. The method also includes forming a photoresist pattern over the third mask film, patterning the third mask film to form a deposition pattern, and forming an amorphous carbon pattern at sidewalls of the deposition pattern. The method further includes filling a spin-on-carbon layer over the deposition pattern and the amorphous carbon pattern, polishing the spin-on-carbon layer, the amorphous carbon pattern, and the photoresist pattern to expose the third mask pattern, and performing an etching process to expose the first mask film with the amorphous carbon pattern as an etching mask. The etching process removes the third mask pattern and the exposed second mask pattern. The method also includes removing the spin-on-carbon layer and the amorphous carbon pattern, and forming a first mask pattern with the second mask pattern as an etching mask. | 2008-11-06 |
20080272468 | GROUNDED SHIELD FOR BLOCKING ELECTROMAGNETIC INTERFERENCE IN AN INTEGRATED CIRCUIT PACKAGE - An integrated circuit package for blocking electromagnetic interference includes a top layer formed in a package substrate. A first plurality of via groups is formed in the top layer surrounding an area on the top layer for an integrated circuit die. At least one lower layer is formed in the package substrate. A lower via group is formed in the lower layer below each of the first plurality of via groups, respectively. An electrical connection is formed in the lower layer between each lower via group and the first plurality of via groups, respectively. A ground connection is formed in the integrated circuit package for each lower via group to connect each lower via group to an electrical ground to block electromagnetic interference. | 2008-11-06 |
20080272469 | SEMICONDUCTOR DIE PACKAGE AND INTEGRATED CIRCUIT PACKAGE AND FABRICATING METHOD THEREOF - A semiconductor die package includes a substrate, a semiconductor die mounted on the substrates a molding covering the semiconductor die and which is formed on the substrate and a conductive layer laminated on the molding. | 2008-11-06 |
20080272470 | Same Size Through-Hole Via Die Stacked Package - A semiconductor package includes a substrate or leadframe structure. A plurality of interconnected dies, each incorporating a plurality of through-hole vias (THVs) disposed along peripheral surfaces of the plurality of dies, are disposed over the substrate or leadframe structure. The plurality of THVs are coupled to a plurality of bond pads through a plurality of a metal traces. A top surface of a first THV is coupled to a bottom surface of a second THV. An encapsulant is formed over a portion of the substrate or leadframe structure and the plurality of dies. | 2008-11-06 |
20080272471 | ELECTRO-OPTICAL DEVICE AND ELECTRONIC APPARATUS - An electro-optical device includes an electro-optical panel having a substrate; a plurality of input terminals that are arranged in a first direction on the substrate; and a semiconductor device provided with a plurality of input bumps electrically connected to the input terminals through conductive organic members. The input terminals connected to the input bumps that are positioned substantially at the center of the semiconductor device in the first direction have allowable connection resistance values smaller than those of the other input terminals. | 2008-11-06 |
20080272472 | Semiconductor packaging device comprising a semiconductor chip including a MOSFET - A thin semiconductor device difficult to cause breakage of a semiconductor chip is disclosed. The semiconductor device comprises a sealing member, a semiconductor chip positioned within the sealing member, the semiconductor chip having a source electrode and a gate electrode on a first main surface thereof and a drain electrode on a second main surface as a back surface thereof, a first electrode plate (drain electrode plate) having an upper surface and a lower surface, a part of the upper surface of the first electrode plate being exposed to an upper surface of the sealing member and the lower surface portions of end portions of the first electrode plate being exposed to a lower surface of the sealing member, and second electrode plates (source electrode plate and gate electrode plate) each having a lower surface exposed to the lower surface of the sealing member and an upper surface positioned within the sealing member, wherein the drain electrode of the semiconductor chip is electrically connected to the drain electrode plate through an adhesive, one or plural stud type bump electrodes are formed by gold wire on the surface of each of the source electrode and gate electrode of the semiconductor chip, the bump electrode(s) being covered with an electrically conductive adhesive, the bump electrode(s) and the source and gate electrode plates are electrically connected with each other through the adhesive, and the bump electrode(s) and the source and gate electrode plates are not in contact with each other. | 2008-11-06 |
20080272473 | OPTICAL DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention provides an optical device ( | 2008-11-06 |
20080272474 | APPARATUS FOR INTEGRATED CIRCUIT COOLING DURING TESTING AND IMAGE BASED ANALYSIS - An apparatus for implementing integrated circuit cooling during testing and image-based analysis thereof includes a lid configured to define a cavity surrounding an integrated circuit die, the die mounted to a module substrate. One or more fluid passages are defined within the lid, wherein the passages facilitate the flow of a cooling liquid through said cavity and over the integrated circuit die, and a transparent window is formed within the lid so as to facilitate viewing of the integrated circuit die. | 2008-11-06 |
20080272475 | Air Cavity Package for a Semiconductor Die and Methods of Forming the Air Cavity Package - A die package ( | 2008-11-06 |
20080272476 | Through-Hole Via On Saw Streets - A semiconductor device is manufactured by, first, providing a wafer designated with a saw street guide. The wafer is taped with a dicing tape. The wafer is singulated along the saw street guide into a plurality of dies having a plurality of gaps between each of the plurality of dies. The dicing tape is stretched to expand the plurality of gaps to a predetermined distance. An organic material is deposited into each of the plurality of gaps. A top surface of the organic material is substantially coplanar with a top surface of a first die of the plurality of dies. A plurality of via holes is formed in the organic material. Each of the plurality of via holes is patterned to each of a plurality of bond pad locations on the plurality of dies. A conductive material is deposited in each of the plurality of via holes. | 2008-11-06 |
20080272477 | Package-on-Package Using Through-Hole Via Die on Saw Streets - A semiconductor package-on-package (PoP) device includes a first die incorporating a through-hole via (THV) disposed along a peripheral surface of the first die. The first die is disposed over a substrate or leadframe structure. A first semiconductor package is electrically connected to the THV of the first die, or electrically connected to the substrate or leadframe structure. An encapsulant is formed over a portion of the first die and the first semiconductor package. | 2008-11-06 |
20080272478 | Circuit and method for interconnecting stacked integrated circuit dies - Signals are routed to and from identical stacked integrated circuit dies by selectively coupling first and second bonding pads on each of the dies to respective circuits fabricated on the dies through respective transistors. The transistors connected to the first bonding pads of an upper die are made conductive while the transistors connected to the second bonding pads of the upper die are made non-conductive. The transistors connected to the second bonding pads of a lower die are made conductive while the transistors connected to the first bonding pads of the lower die are made non-conductive. The second bonding pads of the upper die are connected to the second bonding pads of the lower die through wafer interconnects extending through the upper die. Signals are routed to and from the circuits on the first and second dies through the first and second bonding pads, respectively. | 2008-11-06 |
20080272479 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DEVICE CAVITY - An integrated circuit package system is provided including connecting an integrated circuit die with an external interconnect, forming a first encapsulation having a device cavity with the integrated circuit die therein, mounting a device in the device cavity over the integrated circuit die, and forming a cover over the device and the first encapsulation. | 2008-11-06 |
20080272480 | Land grid array semiconductor package - An LGA (Land Grid Array) semiconductor package mainly comprises a substrate, a chip, a soldering layer and a foot stand. The chip is disposed on a top surface of the substrate and is electrically connected to a plurality of metal pads formed on a bottom surface of the substrate. The soldering layer is disposed on the metal pads with a first thickness slightly protruded from the bottom surface of the substrate. Additionally, the foot stand is disposed under the substrate with a second thickness protruded from the bottom surface of the substrate, wherein the second thickness is greater than the first thickness. Therefore, the soldering layer of the LGA semiconductor package is free from scratches and damages during shipping and handling processes. Moreover, the LGA semiconductor package can be surface-mounted to a printed circuit board with pre-applied solder or pre-mounted solder balls to increase the implementations of LGA semiconductor packages. | 2008-11-06 |
20080272481 | Pin grid array package substrate including slotted pins - An electrically conductive pin comprising a pin stem and a pin head attached to the pin stem. The pin head is adapted to be mounted onto a surface of a microelectronic substrate to support the pin stem. The pin head defines at least one slot therein, the at least one slot being configured to allow gases to escape therethrough from a region at an underside of the pin head. | 2008-11-06 |
20080272482 | Integrated Circuit Package With Top-Side Conduction Cooling - An IC package that employs top-side conduction cooling. The IC package has a low thermal resistance between a substrate housed within the package and the lid of the package. Thermal resistance is decreased by increasing the conduction cross-sections laterally through the package and lid and vertically from the package into the lid. The lid may also be modified with an extended mesa portion that reduces the gap between the lid and the IC. A thermally conductive spacer may also be interposed between the IC and the lid. Also, the package housing body and lid may be made from high thermal conductivity materials having thermal conductivities of 50 W/mK or greater with matching CTE between the lid and the package. | 2008-11-06 |
20080272483 | High power package with dual-sided heat sinking - An assembly includes a semiconductor die disposed between an upper substrate and a lower substrate. A circuit board that defines a through hole is spaced axially below the upper substrate to define a gap between the upper substrate and the circuit board. An upper heat sink is thermally connected to the upper substrate by an upper thermal interface material to transfer heat in a first dissipation path to the upper heat sink. A lower heat sink is thermally connected to the lower substrate by a lower thermal interface material to transfer heat in a second dissipation path to the lower heat sink. A plurality of first interconnectors are disposed in the gap to solder the upper substrate to the circuit board. The assembly is distinguished by a plurality of second interconnectors that are disposed between the upper substrate and the lower substrate to position the lower substrate in the through hole of the circuit board. | 2008-11-06 |
20080272484 | Liquid cooled power electronic circuit comprising a stacked array of directly cooled semiconductor chips - A stacked array of channeled semiconductor chips defining a power electronic circuit is mounted in a sealed container provided with inlet and outlet passages for liquid coolant. Leadframe terminals supported by the container engage selected terminals of the semiconductor chips and form leads for mounting the container on a circuit board having electrical and fluid interconnects. | 2008-11-06 |
20080272485 | Liquid cooled power electronic circuit comprising stacked direct die cooled packages - A plurality of direct die cooled semiconductor power device packages are vertically stacked with both coolant and electrical interfacing to form a liquid cooled power electronic circuit. The packages are individually identical, and selectively oriented prior to stacking in order to form the desired circuit connections and laterally stagger the package leads. | 2008-11-06 |
20080272486 | CHIP PACKAGE STRUCTURE - A chip package structure includes a carrier, an interposer, a plurality of electrically conductive elements, a first sealant, a chip, and a second sealant. The interposer is disposed on the carrier. The electrically conductive elements electrically connect the interposer and the carrier. The first sealant seals the electrically conductive elements. A plurality of bumps of the chip is connected to the interposer. The second sealant seals the bumps. A first glass transition temperature of the first sealant is higher than a second glass transition temperature of the second sealant. Since glass transition temperatures of the first sealant and the second sealant are different, and the first glass transition temperature of the first sealant is higher than the second glass transition temperature of the second sealant, the inner stress will be lowered and the yield is promoted. | 2008-11-06 |
20080272487 | SYSTEM FOR IMPLEMENTING HARD-METAL WIRE BONDS - A wire bond system including providing an integrated circuit die with a bond pad thereon, forming a soft bump on the bond pad, and wire bonding a hard-metal wire on the soft bump. | 2008-11-06 |
20080272488 | Semiconductor Device - A semiconductor device according to the present invention includes a semiconductor chip having a functional surface formed with a functional element, an electrode pad provided directly on the functional element on the functional surface of the semiconductor chip, a protective resin layer laminated on the functional surface of the semiconductor chip, an external connection terminal provided on the protective resin layer in opposed relation to the electrode pad, and a post extending through the protective resin layer in a direction in which the electrode pad and the external connection terminal are opposed to each other for connection between the electrode pad and the external connection terminal. | 2008-11-06 |
20080272489 | Package substrate and its solder pad - A semiconductor chip substrate with solder pad includes: a core layer and at least one conductive structure formed on the surface of the core layer; an insulation layer with at least one patterned opening covering the conductive structure, wherein the patterned opening has a center portion and a plurality of wing portions on the peripheral edge of the center portion to define the exposed area of the conductive structure as the solder pad. The solder pad with wing will improve the adhesion effect between the solder pad and the solder ball. | 2008-11-06 |
20080272490 | Semiconductor device including ruthenium electrode and method for fabricating the same - A semiconductor device includes a semiconductor substrate, an insulation pattern on the semiconductor substrate, and an etch stop layer on the insulating pattern, the insulation pattern and the etch stop layer defining a contact hole that exposes the substrate, a first plug filled in a portion of the contact hole, a diffusion barrier layer formed above the first plug and in a bottom portion and on sidewalls of a remaining portion of the contact hole, a second plug formed on the diffusion barrier layer and filled in the contact hole, and a storage node coupled to and formed on the second plug. | 2008-11-06 |
20080272491 | MANUFACTURING OF A SEMICONDUCTOR DEVICE AND THE MANUFACTURING METHOD - A technology that improves the reliability of a semiconductor device and realizes a high performance by a laminated structure that has enough barrier properties against copper, reduces the wire delay time by lowering the capacitance between wirings and improves the adhesion between wirings is provided. There is a semiconductor device having: a first copper wiring layer, a first barrier layer on the first copper wiring layer, a silicon oxide series porous insulating layer on the first barrier layer, a second barrier layer on the silicon oxide series porous insulating layer, and a second copper wiring layer on the second barrier layer, wherein at least one of the first barrier layer and the second barrier layer consists of an amorphous carbon film, wherein a silicon oxide series insulating layer is directly connected between the amorphous carbon film and any of the first copper wiring layer or the second copper wiring layer. | 2008-11-06 |
20080272492 | METHOD OF BLOCKING A VOID DURING CONTACT FORMATION PROCESS AND DEVICE HAVING THE SAME - An electronic device can include conductive regions. A void can extend between different portions of an insulating layer. Different openings can intersect the void. A liner layer can substantially block the void, substantially preventing subsequently forming an electrical leakage path along the void. In one aspect, a stressor layer can be deposited over the conductive regions prior to forming the insulating layer. The liner layer can be formed over the stressor layer within the different openings through the insulating layer. In another aspect, an etch-stop layer can be formed over a silicide layer prior to forming the insulating layer. After removing a portion of the liner layer, a portion of the etch-stop layer can be removed to expose the silicide layer within the different openings. In yet another aspect, a nitride layer can lie between a substrate and the insulating layer and include a section of the openings. | 2008-11-06 |
20080272493 | Semiconductor device - A semiconductor device is disclosed. The device includes a substrate, a first porous SiCOH dielectric layer, a second porous SiCOH dielectric layer, and an oxide layer. The first porous SiCOH dielectric layer overlies the substrate. The second porous SiCOH dielectric layer overlies the first porous SiCOH dielectric layer. The oxide layer overlies the second porous SiCOH dielectric layer. The atomic percentage of carbon in the second porous SiCOH dielectric layer is between 16% and 22% of that in the first porous SiCOH dielectric layer. | 2008-11-06 |
20080272494 | Semiconductor device - A semiconductor device is provided, including: a first barrier metal film provided by a PVD process in a recess formed in at least one insulating film, and containing at least one metal element belonging to any of the groups 4-A, 5-A, and 6-A; a second barrier metal film continuously provided by at least one of CVD and ALD processes on the first barrier metal film without being opened to atmosphere, and containing at least one metal element belonging to any one of the groups 4-A, 5-A, and 6-A; a third barrier metal film continuously provided by the PVD process on the second barrier metal film without being opened to the atmosphere, and containing at least one metal element belonging to any one of the groups 4-A, 5-A, and 6-A; and a first Cu film continuously provided on the third barrier metal film without being opened to the atmosphere and thereafter heated. | 2008-11-06 |
20080272495 | SEMICONDUCTOR DEVICE HAVING HIGH-FREQUENCY INTERCONNECT - Provided is a semiconductor device including high-frequency interconnect and dummy conductor patterns (second dummy conductor patterns). The dummy conductor patterns are disposed in a interconnect layer different from a interconnect layer in which the high-frequency interconnect is disposed. The dummy conductor patterns are disposed so as to keep away from a region overlapping the high-frequency interconnect in plan view. The semiconductor device further includes dummy conductor patterns (first dummy conductor patterns) in the interconnect layer in which the high-frequency interconnect is disposed. | 2008-11-06 |
20080272496 | PLANAR INTERCONNECT STRUCTURE FOR HYBRID CIRCUITS - Described herein is an electronic device in which one or more planar interconnect structure are interposed between two substrates each incorporating a hybrid circuit. The planar interconnect structure has a plurality of conductive traces formed on one of its faces for electrically connecting sets of interconnection points of each of the hybrid circuits. | 2008-11-06 |
20080272497 | METHODS OF FORMING CONDUCTIVE VIAS THROUGH SUBSTRATES, AND STRUCTURES AND ASSEMBLIES RESULTING THEREFROM - Methods of forming conductive elements on and in a substrate include forming a layer of conductive material over a surface of a substrate prior to forming a plurality of vias through the substrate from an opposing surface of the substrate to the layer of conductive material. In some embodiments, a temporary carrier may be secured to the layer of conductive material on a side thereof opposite the substrate prior to forming the vias. Structures, including workpieces formed using such methods are also disclosed. | 2008-11-06 |
20080272498 | Method of fabricating a semiconductor device - A method for fabricating a semiconductor device. A preferred embodiment comprises forming a via in a semiconductor substrate, filling the via with a disposable material such as amorphous carbon, forming a dielectric layer on the substrate covering the via, performing a back side etch to expose the disposable material in the via. A back side dielectric layer is then depositing, covering the exposed via. A small opening is then formed, and the disposable material is removed, for example by an isotropic etch process. The via may now be filled with a metal and used as a conductor or a dielectric material. The via may also be left unfilled to be used as an air gap. | 2008-11-06 |
20080272499 | Through-wafer vias - A through-wafer via interconnect region is in a circuit portion of a wafer, the circuit portion including at least one electrically conducting metal layer and configured for use, after dicing of the wafer, as one of a plurality of layers stacked vertically to form a three dimensional integrated circuit. Within the metal layer in the circuit portion, the metal is removably distributed such that the ratio of metal to nonmetal area, within the via region, varies by less than a predetermined amount from the ratio of metal to nonmetal area outside the via region. | 2008-11-06 |
20080272500 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device according to the present invention has a semiconductor chip provided with an insulating layer formed so as to be thinner in a first secondary-wire-free area than in a first secondary-wire-containing area. Further, the semiconductor chip has an edge extending further outward than a side wall, which severs as an edge of an upper insulating layer, in an extending direction of a circuit-forming surface of the semiconductor chip on which electrode pads are provided. This makes it possible to provide a semiconductor device capable of suppressing electromagnetic interference between a secondary wire and an electronic circuit of a semiconductor chip and the curvature of a wafer even in the case of overlap between the secondary wire and the electronic circuit, and of reducing the risk of occurrence of chipping in a dicing step. | 2008-11-06 |
20080272501 | SEMICONDUCTOR PACKAGE SUBSTRATE STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor package substrate structure and a manufacturing method thereof are disclosed. The structure includes a substrate having a plurality of electrical connecting pads formed on at least one surface thereof; a plurality of electroplated conductive posts each covering a corresponding one of the electrical connecting pads and an insulating protective layer formed on the surface of the substrate and having a revealing portion for exposing the electroplated conductive posts therefrom. The invention allows the interval between the electroplated conductive posts to be minimized, the generation of concentrated stresses and the overflow of underfill to be avoided, as well as the reduction of the overall height of the fabricated package. | 2008-11-06 |
20080272502 | PACKAGING BOARD AND MANUFACTURING METHOD THEREFOR, SEMICONDUCTOR MODULE AND MANUFACTURING METHOD THEREFOR, AND PORTABLE DEVICE - A method for manufacturing a semiconductor module includes: a first process of forming a conductor on one face of an insulating layer; a second process of exposing the conductor from the other face of the insulating layer; a third process of providing a first wiring layer on an exposed area of the conductor and on the other face of the insulating layer; a fourth process of preparing a substrate on which a circuit element is formed, the second wiring being formed on the substrate; and a fifth process of embedding the conductor in the insulating layer by press-bonding the insulating layer and the substrate in a state where the conductor on which the first wiring layer is provided by the third process is disposed counter to the second wiring layer. Wiring is formed without causing damaging to the circuit element. | 2008-11-06 |
20080272503 | Semiconductor Device and Method for Making Same - A transfer mold process for encapsulation of a matrix array package of dice on a substrate is proposed wherein the flow of the mold compound between dice is at least partly obstructed. In other words, the flow velocity of the mold compound between dice is constrained with the goal of approximating it to the flow velocity above the dice. It is to be understood that every limitation of the flow velocity between the dice, even if it does not result in equal or uniform velocity throughout the cross-sectional area, will bring about a positive effect in terms of reducing the clustering of filler particles in certain areas of the mold compound. The semiconductor device thus produced is part of the present disclosure. | 2008-11-06 |
20080272504 | Package-in-Package Using Through-Hole via Die on Saw Streets - A semiconductor device includes a first die having top, bottom, and peripheral surfaces. A bond pad is formed over the top surface. An organic material is connected to the first die and disposed around the peripheral surface. A via hole is formed in the organic material. A metal trace connects the via hole to the bond pad. A conductive material is deposited in the via hole. A redistribution layer (RDL) has an interconnection pad disposed over the top surface of the first die. | 2008-11-06 |
20080272505 | CARBURETOR - A carburetor includes a base, a Venturi cone assembly, a cam assembly, a horsepower adjustment assembly, and a vacuum horsepower adjustment valve. The Venturi cone assembly is mounted in the base. A supporting portion of a cone collides with a cam of the cam assembly. An oil line rotation wheel of the horsepower adjustment assembly is drawn by an oiling line to drive the fan blade. The amount of displacement of the cone of the Venturi cone assembly under vacuum suction from the engine is controlled by a cam of the cam assembly. The vacuum horsepower adjustment valve automatically supplies enough fuel to the engine. Accordingly, the present invention can make the fuel burn sufficiently, effectively improving efficiency and reducing air pollution. | 2008-11-06 |
20080272506 | SUBMERGED GAS EVAPORATORS AND REACTORS - A submerged gas processor in the form of an evaporator or a submerged gas reactor includes a vessel, a gas delivery tube partially disposed within the vessel to deliver a gas into the vessel and a process fluid inlet that provides a process fluid to the vessel at a rate sufficient to maintain a controlled constant level of fluid within the vessel. A weir is disposed within the vessel adjacent the gas delivery tube to form a first fluid circulation path between a first weir end and a wall of the vessel and a second fluid circulation path between a second weir end and an upper end of the vessel. During operation, gas introduced through the tube mixes with the process fluid and the combined gas and fluid flow at a high rate with a high degree of turbulence along the first and second circulation paths defined around the weir, thereby promoting vigorous mixing and intimate contact between the gas and the process fluid. This turbulent flow develops a significant amount of interfacial surface area between the gas and the process fluid resulting in a reduction of the required residence time of the gas within the process fluid to achieve thermal equilibrium and/or to drive chemical reactions to completion, all of which leads to a more efficient and complete evaporation, chemical reaction, or combined evaporation and chemical reaction process. | 2008-11-06 |
20080272507 | Stably preserved microspheres - In accordance with the present invention, active carboxylic acid ester groups are coupled on the surfaces of microspheres so as to reduce protocols for microsphere processing, control side reactions, and stably preserve beads containing active carboxylic acid ester groups. | 2008-11-06 |
20080272508 | MANUFACTURE OF SPHERICAL PARTICLES OUT OF A PLASTIC MELT - The invention relates to a method and a device for producing spherical particles from a melted mass of plastic. According to the invention, said melted mass is transformed into droplets by means of a droplet-forming nozzle ( | 2008-11-06 |
20080272509 | Insert Molding Machine With an Automatic Hoop Feeder System - An insert molding machine for manufacturing electronic parts, is equipped with an automatic hoop feeder system for intermittently feeding the metal components of a molded product by way of a hoop formed of a thin carrier strip on which a plurality of metal components are carried at regular intervals in a row. A pair of hoop conveying means are installed adjacently to one of the opposed inlet and outlet sides of the mold of an injection molding machine, and a pair of carriages supported by the respective hoop conveying means are interconnected mechanically to each other through a coupling connector so that the both carriages are moved forward and backward in complete synchronism with each other when one of the carriages is driven to slide. | 2008-11-06 |
20080272510 | Method and Apparatus for Directly Injecting Steam in an Expanded Plastic Material Mold - A traditional steam chest molding apparatus for the manufacture of products from expanded plastic materials requires excessive amounts of steam to properly expand and fuse pellets of plastic together A molding apparatus is provided wherein a pair of complementary molds ( | 2008-11-06 |
20080272511 | METHOD OF MOLDING LOAD-BEARING ARTICLES FROM COMPRESSIBLE CORES AND HEAT MALLEABLE COVERINGS - Load-bearing articles are manufactured from shape defining compressible cores and thermoplastic shells. The manufacture of these articles requires specific methods and tools. Articles that can be manufactured using these methods include relatively lightweight pallets with high load-bearing capacity. | 2008-11-06 |
20080272512 | Transferring Resin for Forming Fastener Products - Method and apparatus for making fastener products ( | 2008-11-06 |
20080272513 | Process for the Coextrusion of Melt Streams of Different Composition - The invention relates to a method for coextrusion of at least two molten material flows having different composition by separating the molten material into at least two molten material flows, admixing additives in at least one of the molten material flows and bringing together the molten material flows by coextrusion in one or more extrusion tools. The method is particularly suitable for the production of PVB films with a color strip for composite glazings. | 2008-11-06 |
20080272514 | Closure Cap With Injection Molded Annular Gasket and Method of Making Same - A closure cap and method of making the same wherein an annular or ring-shaped gasket is injection molded onto the inner surface of a cap shell formed of plastic or metal. The annular or ring-shaped gasket includes radially extending tabs integrally formed therewith, one of said tabs being formed at a location wherein the plastic melt is fed to an annular gasket-forming channel in a mold core and another of said tabs being formed at the location wherein plastic melt is discharged from said channel. Preferably, said other tab includes a cold well formation which communicates with the annular gasket through a connecting portion of reduced cross-sectional area with respect to the cross-sectional areas of both the gasket and the cold well formation. | 2008-11-06 |
20080272515 | METHOD AND APPARATUS FOR FORMING A CLOSURE DEVICE AND A CONTAINER - A method for forming a closure device for a container is disclosed including providing a first mold component having a first annular groove. The first annular groove is configured to form a skirt of the closure device. A plurality of ejector blades are provided and are positioned within the mold component. The blades include a notch for forming a lug on an inner surface of the skirt. The lug is back-locked relative to the mold component. A moldable material is introduced into a mold cavity to form the closure device. The device is removed from the mold component by moving the blades along a path defined by tracks formed in the mold component that is generally along a vertical axis of the mold component, wherein the path includes a radially outward component, and the moving of the blades relieves the back-lock of the lug formed on the closure device. | 2008-11-06 |
20080272516 | Successive Shrinking of Elastomers - a Simple Miniaturization Protocol to Produce Micro- and Nano-Structures - A stepwise contraction and adsorption nanolithography (SCAN) patterning process can shrink complex microstructures (produced by current microfabrication technology) into the nanometer region. The basis of SCAN is to transfer a pre-engineered microstructure onto a extended elastomer. This extended elastomer is then allowed to relax, reducing the microstructure accordingly. The new miniaturized structure is then used as a stamp to transfer the structure onto another stretched elastomer. Through iterations of this procedure, patterns of materials with pre-designed geometry are miniaturized to the desired dimensions, including sub-100 ran. The simplicity and high throughput capability of SCAN make the platform a competitive alternative to other micro- and nanolithography techniques for potential applications in multiplexed sensors, non-binary optical displays, biochips, nanoelectronics devices, and microfluidic devices. | 2008-11-06 |
20080272517 | Method of making elastomeric pad for a compressible elastomeric spring - A method of making a compressible elastomeric pad from a preselected polymer material includes the steps of providing a preform including a substantially solid body having a predetermined cross-section disposed normal to a central axis of the preform and a pair of axial ends, each having a substantially flat surface disposed normal to the central axis and a central socket formed within at least one substantially flat surface. Next, providing a pair of forming plates, at least one of the pair of forming plates having a raised annular ring and an axially aligned cavity provided on one surface thereof. Then, positioning the preform between the pair of forming plates and axially aligning the exterior peripheral edge of the annular ring with a peripheral edge of a respective central socket. Finally, forming the pad and removing the pad from engagement with the pair of forming plates. | 2008-11-06 |
20080272518 | METHOD OF COMPRESSION MOLDING MOTOR VEHICLE COMPONENTS AND PARTS MADE THEREFROM - The invention is a method to make compression molded motor vehicle parts from a charge of composite material with resin and fibers, such as sheet molded compound. The parts have voids, such as holes and gaps, that form in the compression mold under heat and pressure and not in secondary processing steps. The resin in the charge is melts in a reservoir in the mold to form resinous material from the charge. A flow front of resinous material is allowed to flow into a flow path around a restriction corresponding to the shape of the void from the reservoir. The flow front carries sufficient reinforcing fibers into the flow path. At least part of a border for the void forms in the flow path. The configuration is allowed to at least partially set. | 2008-11-06 |
20080272519 | Method for Producing a Microcircuit Card - The invention relates to a method for producing a microcircuit card, comprising the following steps: a step for positioning a microcircuit in an open-cavity mould, and a step for depositing a material in the open cavity of the mould, the material being sufficiently poorly viscous for coating at least indirectly at least part of the microcircuit. | 2008-11-06 |
20080272520 | NONWOVEN FABRIC AND PROCESS FOR PRODUCING THE SAME - A process for production of a nonwoven fabric, which comprises a step wherein a thermoplastic polymer is dissolved in a mixed solvent composed of a volatile good solvent and a volatile poor solvent, a step wherein the resulting solution is spun by an electrospinning method and a step wherein a nonwoven fabric accumulated on a collecting sheet is obtained, is employed to provide a nonwoven fabric having a surface area sufficiently large as a matrix for cell culturing in the field of regenerative medicine, with large gaps between filaments and a low apparent density suitable for cell culturing. | 2008-11-06 |