45th week of 2014 patent applcation highlights part 14 |
Patent application number | Title | Published |
20140327028 | LIGHT-EMITTING DIODE, METHOD FOR MANUFACTURING LIGHT-EMITTING DIODE, LIGHT-EMITTING DIODE LAMP AND ILLUMINATION DEVICE - A light-emitting diode, a method of manufacturing the same, a lamp and an illumination device. A light-emitting diode ( | 2014-11-06 |
20140327029 | SEMICONDUCTOR LIGHT EMITTING DEVICE WITH THICK METAL LAYERS - A device according to embodiments of the invention includes a semiconductor structure including a light emitting layer sandwiched between an n-type region and a p-type region and first and second metal contacts, wherein the first metal contact is in direct contact with the n-type region and the second metal contact is in direct contact with the p-type region. First and second metal layers are disposed on the first and second metal contacts, respectively. The first and second metal layers are sufficiently thick to mechanically support the semiconductor structure. A portion of a sidewall the device adjacent to one of the first and second metal layers is reflective. | 2014-11-06 |
20140327030 | CONTROLLED LED LIGHT OUTPUT BY SELECTIVE AREA ROUGHENING - The surface of a light emitting device is roughened to enhance the light extraction efficiency of the surface, but the amount of roughened area is selected to achieve a desired level of light extraction efficiency. Photo-lithographic techniques may be used to create a mask that limits the roughening to select areas of the light emitting surface. Because the amount of roughened area can be precisely controlled, the light extraction efficiency can be precisely controlled, substantially independent of the particular process used to roughen the surface. Additionally, the selective roughening of the surface may be used to achieve a desired light emission output pattern. | 2014-11-06 |
20140327031 | CURRENT CONDUCTING ELEMENT - A current conducting element including a substrate, a through hole, an electrode layer and a conductor structure is provided. The through hole is disposed through the substrate and has a first opening. The electrode layer is disposed on the substrate. A portion of the first opening is exposed from the electrode layer. The conductor structure is disposed in the through hole and contacted with the electrode layer. The electrode layer and the conductor structure form a current conducting path. | 2014-11-06 |
20140327032 | LIGHT EMITTING DIODE AND METHOD OF MANUFACTURING THE SAME, AND LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE LIGHT EMITTING DEVICE - Disclosed are a light emitting device, a conductive substrate; a second electrode layer on the conductive substrate and including a center portion and a peripheral portion surrounding the center portion; a protective layer on the peripheral portion of the second electrode layer; and a light emitting structure including a second conductive semiconductor layer on the second electrode layer, an active layer on the second conductive semiconductor layer and a first conductive semiconductor layer on the active layer; and a first electrode layer on the first conductive semiconductor layer, wherein the second conductive semiconductor layer includes edge portions extending outside of the light emitting structure. | 2014-11-06 |
20140327033 | FLIP-CHIP LIGHT EMITTING DIODE - A flip-chip light emitting diode comprises a transparent base-plate, at least a first electrical semi-conductive layer, a light emitting layer, a second electrical semi-conductive layer, at least a first ohmic contact, a second ohmic contact and a third ohmic contact are installed above the transparent base-plate. The at least first ohmic contact is electrically connected to the third ohmic contact through a connection passage. A first electrode area is formed above the second electrical semi-conductive layer. The second ohmic contact is disposed above the transparent base-plate and adjacent to a side of the first ohmic contact. A second electrode area is formed on the second ohmic contact. | 2014-11-06 |
20140327034 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor light emitting device of the present invention includes a semiconductor laminate including a first conductivity type semiconductor layer, a light emitting layer, and a second conductivity-type semiconductor layer in his order; a contact portion including a stack including a contact layer and an ohmic electrode layer on the first conductivity type semiconductor layer; a first electrode which is in contact with the ohmic electrode layer and is electrically connected to the first conductivity-type semiconductor layer; a second electrode electrically connected to the second conductivity type semiconductor layer. The contact portion has a plurality of island-like openings in which the first conductivity-type semiconductor layer is exposed. | 2014-11-06 |
20140327035 | ACTIVE MATRIX TYPE DISPLAY DEVICE - An active matrix substrate includes a plurality of first lines extending parallel to each other, and a plurality of second lines extending parallel to each other, and crossing the plurality of first lines with an insulation film therebetween. The active matrix substrate also includes a plurality of lead-out lines connecting an end of at least one of the plurality of first lines and the plurality of second lines with a driver, and extending spaced apart from each other in a non-display region, and a plurality of redundant wirings extending along the plurality of lead-out lines with an insulation film therebetween. Each of the plurality of lead-out lines overlaps, in plan view, with an overlapping region of any of the plurality of redundant wirings. Each of the plurality of redundant wirings has a length shorter than an arbitrary one of the plurality of lead-out lines overlapping at the overlapping region. | 2014-11-06 |
20140327036 | LIGHT EMITTING DIODE CHIP AND MANUFACTURING METHOD THEREOF - A light emitting diode (LED) chip includes an N-type semiconductor layer, a compensation layer arranged on the N-type semiconductor layer, an active layer arranged on the compensation layer; and a P-type semiconductor layer arranged on the active layer. During growth of the compensation layer, atoms of an element (i.e., Al) of the compensation layer move to fill epitaxial defects in the N-type semiconductor layer, wherein the epitaxial defects are formed due to lattice mismatch when growing the N-type semiconductor. A method for manufacturing the chip is also disclosed. The compensation layer is made of a compound having a composition of Al | 2014-11-06 |
20140327037 | METHOD FOR MANUFACTURING A SEMICONDUCTOR MICRO- OR NANO-WIRE, SEMICONDUCTOR STRUCTURE COMPRISING SUCH A MICRO- OR NANO-WIRE, AND METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE - A method of manufacturing at least one semiconducting micro- or nano-wire used for formation of an optoelectric structure, optoelectronic structures including the micro- or nano-wires, and a method enabling manufacture of the photoelectronic structures. The method includes providing a semiconducting substrate, forming a crystalline buffer layer on the substrate, the buffer layer having a first zone over at least part of its thickness composed mainly of magnesium nitride in a form Mg | 2014-11-06 |
20140327038 | POWER SEMICONDUCTOR AND MANUFACTURING METHOD THEREOF - A power semiconductor includes a semiconductor substrate, a metal oxide semiconductor layer, a N-type buffer layer and a P-type injection layer. The semiconductor substrate has a first surface and a second surface. The metal oxide semiconductor layer is formed on the first surface for defining a N-type drift layer of the semiconductor substrate. The N-type buffer layer is formed on the second surface through ion implanting, and the P-type injection layer is formed on the N-type buffer layer through ion implanting. By utilizing the semiconductor substrate having drift layer and forming the N-type buffer layer and the P-type injection layer on the second surface of the semiconductor substrate through ion implanting, the ion concentration is adjustable. As a result, the electron hole injection efficiency and the width of depletion region are easily adjusted, the fabricating processes are simplified, and the fabricating time and cost are reduced. | 2014-11-06 |
20140327039 | TRENCH TYPE POWER TRANSISTOR DEVICE - The present invention provides a trench type power transistor device including a substrate, an epitaxial layer, a doped diffusion region, a doped source region, and a gate structure. The substrate, the doped diffusion region, and the doped source region have a first conductivity type, and the substrate has an active region and a termination region. The epitaxial layer is disposed on the substrate, and has a second conductivity type. The epitaxial layer has a through hole disposed in the active region. The doped diffusion region is disposed in the epitaxial layer at a side of the through hole, and is in contact with the substrate. The doped source region is disposed in the epitaxial layer disposed right on the doped diffusion region, and the gate structure is disposed in the through hole between the doped diffusion region and the doped source region. | 2014-11-06 |
20140327040 | POWER SEMICONDUCTOR DEVICE - Provided is a power semiconductor device including a semiconductor substrate, in which a current flows in a thickness direction of the semiconductor substrate. The semiconductor substrate includes a resistance control structure configured so that a resistance to the current becomes higher in a central portion of the semiconductor substrate than a peripheral portion of the semiconductor substrate. | 2014-11-06 |
20140327041 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A thin semiconductor wafer, on which a top surface structure and a bottom surface structure that form a semiconductor chip are formed, is affixed to a supporting substrate by a double-sided adhesive tape. Then, on the thin semiconductor wafer, a trench to become a scribing line is formed by wet anisotropic etching with a crystal face exposed so as to form a side wall of the trench. On the side wall of the trench with the crystal face thus exposed, an isolation layer for holding a reverse breakdown voltage is formed by ion implantation and low temperature annealing or laser annealing so as to be extended to the top surface side while being in contact with a p collector region as a bottom surface diffused layer. Then, laser dicing is carried out to neatly dice a collector electrode, formed on the p collector region, together with the p collector region, without presenting any excessive portions and any insufficient portions under the isolation layer. Thereafter, the double-sided adhesive tape is removed from the collector electrode to produce semiconductor chips. A highly reliable reverse-blocking semiconductor device can thus be formed at a low cost. | 2014-11-06 |
20140327042 | SEMICONDUCTOR ELECTROSTATIC PROTECTION CIRCUIT DEVICE - An electrostatic protection circuit in a semiconductor device includes a first first-conductivity type well extending in a first direction over a semiconductor substrate, a second first-conductivity type well extending in a second direction over the semiconductor substrate and perpendicular to the first direction with one end coupled to a first long side of the first first-conductivity type well, and a second-conductivity type well formed around the first first-conductivity type well and the second first-conductivity type well. It also includes a first high-concentration second-conductivity type region extending in the second direction on a surface of the second first-conductivity type well and a first high-concentration first-conductivity type region extending in the second direction on a surface of the second-conductivity type well while facing the first high-concentration second-conductivity type region. | 2014-11-06 |
20140327043 | HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - Provided are a high electron mobility transistor (HEMT) and a method of manufacturing the HEMT. The HEMT includes: a channel layer comprising a first semiconductor material; a channel supply layer comprising a second semiconductor material and generating two-dimensional electron gas (2DEG) in the channel layer; a source electrode and a drain electrode separated from each other in the channel supply layer; at least one depletion forming unit that is formed on the channel supply layer and forms a depletion region in the 2DEG; at least one gate electrode that is formed on the at least one depletion forming unit; at least one bridge that connects the at least one depletion forming unit and the source electrode; and a contact portion that extends from the at least one bridge under the source electrode. | 2014-11-06 |
20140327044 | METHOD TO MAKE DUAL MATERIAL FINFET ON SAME SUBSTRATE - A method of fabricating a semiconductor device including proving a substrate having a germanium containing layer that is present on a dielectric layer, and etching the germanium containing layer of the substrate to provide a first region including a germanium containing fin structure and a second region including a mandrel structure. A first gate structure may be formed on the germanium containing fin structures. A III-V fin structure may then be formed on the sidewalls of the mandrel structure. The mandrel structure may be removed. A second gate structure may be formed on the III-V fin structure. | 2014-11-06 |
20140327045 | METHOD TO MAKE DUAL MATERIAL FINFET ON SAME SUBSTRATE - A method of fabricating a semiconductor device including proving a substrate having a germanium containing layer that is present on a dielectric layer, and etching the germanium containing layer of the substrate to provide a first region including a germanium containing fin structure and a second region including a mandrel structure. A first gate structure may be formed on the germanium containing fin structures. A III-V fin structure may then be formed on the sidewalls of the mandrel structure. The mandrel structure may be removed. A second gate structure may be formed on the III-V fin structure. | 2014-11-06 |
20140327046 | Fin-Last FinFET and Methods of Forming Same - Embodiments of the present disclosure are a FinFET device, and methods of forming a FinFET device. An embodiment is a method for forming a FinFET device, the method comprising forming a semiconductor strip over a semiconductor substrate, wherein the semiconductor strip is disposed in a dielectric layer, forming a gate over the semiconductor strip and the dielectric layer, and forming a first recess and a second recess in the semiconductor strip, wherein the first recess is on an opposite side of the gate from the second recess. The method further comprises forming a source region in the first recess and a drain region in the second recess, and recessing the dielectric layer, wherein a first portion of the semiconductor strip extends above a top surface of the dielectric layer forming a semiconductor fin. | 2014-11-06 |
20140327047 | FET DIELECTRIC RELIABILITY ENHANCEMENT - A semiconductor device may be formed by forming a silicon-containing gate dielectric layer over a semiconductor layer. A gate metal layer is formed over the gate dielectric layer; the gate metal layer includes 2 atomic percent to 10 atomic percent silicon during formation. The gate metal layer is patterned to form a metal gate. Source and drain contact holes are subsequently formed, and contact metal is formed and patterned in the contact holes. A subsequent contact anneal heats the contact metal and gate for at least 30 seconds at a temperature of at least 750° C. | 2014-11-06 |
20140327048 | Compact Electrostatic Discharge (ESD) Protection Structure - A multi-gate Schottky depletion-mode field effect transistor (FET), at least one diode and two resistors comprise a compact electrostatic discharge (ESD) protection structure. This ESD protection structure can be laid out in a smaller area than typical multiple diode ESD devices. The multi-gate FET may comprise various types of high-electron-mobility transistor (HEMT) devices, e.g., (pseudomorphic) pHEMT, (metamorphic) mHEMT, induced HEMT. The multiple gates of the Schottky field effect device are used to form an ESD trigger and charge draining paths for protection of circuits following the ESD protection device. Both single and dual polarity ESD protection devices may be provided on an integrated circuit die for protection of input-output circuits thereof. | 2014-11-06 |
20140327049 | METHODS OF MANUFACTURING THE GALLIUM NITRIDE BASED SEMICONDUCTOR DEVICES - Gallium nitride (GaN) based semiconductor devices and methods of manufacturing the same. The GaN-based semiconductor device may include a heterostructure field effect transistor (HFET) or a Schottky diode, arranged on a heat dissipation substrate. The HFET device may include a GaN-based multi-layer having a recess region; a gate arranged in the recess region; and a source and a drain that are arranged on portions of the GaN-based multi-layer at two opposite sides of the gate (or the recess region). The gate, the source, and the drain may be attached to the heat dissipation substrate. The recess region may have a double recess structure. While such a GaN-based semiconductor device is being manufactured, a wafer bonding process and a laser lift-off process may be used. | 2014-11-06 |
20140327050 | STANDARD CELL HAVING CELL HEIGHT BEING NON-INTEGRAL MULTIPLE OF NOMINAL MINIMUM PITCH - An integrated circuit, manufactured by a process having a nominal minimum pitch of metal lines, includes a plurality of metal lines and a plurality of standard cells under the plurality of metal lines. The plurality of metal lines extends along a first direction, and the plurality of metal lines are separated, in a second direction perpendicular to the first direction, by integral multiples of the nominal minimum pitch. At least one of the plurality of standard cells has a cell height along the second direction, and the cell height is a non-integral multiple of the nominal minimum pitch. | 2014-11-06 |
20140327051 | IMAGE SENSOR AND METHOD OF MANUFACTURING THE SAME - An image sensor and a method of manufacturing the image sensor are provided. The image sensor may include a photo detecting device and a charge storage device. The image sensor may further include a trench and a shield which blocks light from being absorbed by the charge storage device. The charge storage device may temporarily store accumulated charges by the photo detecting device. | 2014-11-06 |
20140327052 | SOLID-STATE IMAGING DEVICE, PRODUCTION METHOD THEREOF, AND ELECTRONIC DEVICE - Disclosed is a solid-state imaging device which includes a pixel section, a peripheral circuit section, a first isolation region formed with a STI structure on a semiconductor substrate in the peripheral circuit section, and a second isolation region formed with the STI structure on the semiconductor substrate in the pixel section. The portion of the second isolation region buried into the semiconductor substrate is shallower than the portion buried into the semiconductor substrate of the first isolation region, and the height of the upper face of the second isolation region is equal to that of the first isolation region. A method of producing the solid-state imaging device and an electronic device provided with the solid-state imaging devices are also disclosed. | 2014-11-06 |
20140327053 | Semiconductor Device Including Trench Transistor Cell Array and Manufacturing Method - A semiconductor device includes a trench transistor cell array in a silicon semiconductor body with a first main surface and a second main surface opposite to the first main surface. A main lateral face of the semiconductor body between the first main surface and the second main surface has a first length along a first lateral direction parallel to the first and second main surfaces. The first length is equal or greater than lengths of other lateral faces of the semiconductor body. The trench transistor cell array includes predominantly linear gate trench portions. At least 50% of the linear gate trench portions extend along a second lateral direction or perpendicular to the second lateral direction. An angle between the first and second lateral directions is in a range of 45°±15°. | 2014-11-06 |
20140327054 | Raised Source/Drain and Gate Portion with Dielectric Spacer or Air Gap Spacer - A semiconductor structure and method of manufacturing the same are provided. The semiconductor device includes epitaxial raised source/drain (RSD) regions formed on the surface of a semiconductor substrate through selective epitaxial growth. In one embodiment, the faceted side portions of the RSD regions are utilized to form cavity regions which may be filled with a dielectric material to form dielectric spacer regions. Spacers may be formed over the dielectric spacer regions. In another embodiment, the faceted side portions may be selectively grown to form air gap spacer regions in the cavity regions. A conformal spacer layer with interior and exterior surfaces may be formed in the cavity region, creating an air gap spacer defined by the interior surfaces of the conformal spacer layer. | 2014-11-06 |
20140327055 | REPLACEMENT GATE PROCESS AND DEVICE MANUFACTURED USING THE SAME - A replacement gate process is disclosed. A substrate and a dummy gate structure formed on the substrate is provided, wherein the dummy gate structure comprises a dummy layer on the substrate, a hard mask layer on the dummy layer, spacers at two sides of the dummy layer and the hard mask layer, and a contact etch stop layer (CESL) covering the substrate, the spacers and the hard mask layer. The spacers and the CESL are made of the same material. Then, a top portion of the CESL is removed to expose the hard mask layer. Next, the hard mask layer is removed. Afterward, the dummy layer is removed to form a trench. | 2014-11-06 |
20140327056 | SEMICONDUCTOR DEVICE HAVING CONTACT PLUG AND METHOD OF MANUFACTURING THE SAME - A semiconductor device having a contact plug is manufactured. The semiconductor device includes a substrate having a cell array region and a peripheral circuit region, a gate electrode on the substrate, and an interlayer dielectric layer on the substrate. The interlayer dielectric layer has an upper surface having a first height. | 2014-11-06 |
20140327057 | Power Semiconductor Device with a Double Metal Contact - A power semiconductor device that includes a stack of a thin metal layer and a thick metal layer over the active region thereof, and a method for the fabrication thereof. | 2014-11-06 |
20140327058 | SELF-ALIGNED CONTACTS FOR REPLACEMENT METAL GATE TRANSISTORS - Embodiments of the invention include methods of forming gate caps. Embodiments may include providing a semiconductor device including a gate on a semiconductor substrate and a source/drain region on the semiconductor substrate adjacent to the gate, forming a blocking region, a top surface of which extends above a top surface of the gate, depositing an insulating layer above the semiconductor device, and planarizing the insulating layer using the blocking region as a planarization stop. Embodiments further include semiconductor devices having a semiconductor substrate, a gate above the semiconductor substrate, a source/drain region adjacent to the gate, a gate cap above the gate that cover the full width of the gate, and a contact adjacent to the source/drain region having a portion of its sidewall defined by the gate cap. | 2014-11-06 |
20140327059 | SOLID-STATE IMAGING DEVICE, METHOD OF MANUFACTURING SOLID-STATE IMAGING DEVICE, AND ELECTRONIC APPARATUS - The present technique relates to a solid-state imaging device, a solid-state imaging device manufacturing method, and an electronic apparatus that are capable of providing a solid-state imaging device that can prevent generation of RTS noise due to miniaturization of amplifying transistors, and can achieve a smaller size and a higher degree of integration accordingly. | 2014-11-06 |
20140327060 | Semiconductor Sensor Structures with Reduced Dislocation Defect Densities and Related Methods for the Same - Non-silicon based semiconductor devices are integrated into silicon fabrication processes by using aspect-ratio-trapping materials. Non-silicon light-sensing devices in a least a portion of a crystalline material can output electrons generated by light absorption therein. Exemplary light-sensing devices can have relatively large micron dimensions. As an exemplary application, complementary-metal-oxide-semiconductor photodetectors are formed on a silicon substrate by incorporating an aspect-ratio-trapping technique. | 2014-11-06 |
20140327061 | SUBSTRATE STACKED IMAGE SENSOR HAVING A DUAL DETECTION FUNCTION - The present invention relates to a substrate stacked image sensor having a dual detection function, in which when first to fourth photodiodes are formed in a first substrate, a fifth photodiode is formed in a second substrate, and the substrates are stacked and combined with each other, the first to fourth photodiodes and the fifth photodiode are combined with each other to obtain a complete photodiode as an element of one pixel, and signals individually detected in each photodiode are selectively read or added to be read according to necessity. To this end, the first to fourth photodiodes are formed in the first substrate, the fifth photodiode is formed in the second substrate, the first to fourth photodiodes and the fifth photodiode make electrical contact with each other, and pixel array sizes of the first substrate and the second substrate are allowed to be different from each other, so that sensor resolution of the first substrate and sensor resolution of the second substrate are different from each other. | 2014-11-06 |
20140327062 | ELECTRONIC DEVICES INCLUDING OXIDE DIELECTRIC AND INTERFACE LAYERS - An electronic device may include a substrate, an oxide dielectric layer on the substrate, an interface layer on the oxide dielectric layer, and an electrode on the interface layer. The oxide dielectric layer may include an aluminum oxide layer between first and second zirconium oxide layers. The interface layer may have a first formation enthalpy, and the oxide dielectric layer may be between the substrate and the interface layer. The electrode may have a second formation enthalpy higher than the first formation enthalpy, and the interface layer may be between the oxide dielectric layer and the electrode. | 2014-11-06 |
20140327063 | SEMICONDUCTOR DEVICE HAVING LANDING PADS - A semiconductor device including a substrate, the substrate including active regions; a pair of conductive lines spaced apart from the substrate such that an insulating layer is between the substrate and the pair of conductive lines; insulating spacers covering side walls of each of the pair of conductive lines such that contact holes having first widths in a first direction are defined between the pair of conductive lines; upper insulating patterns on the pair of conductive lines, the upper insulating patterns defining landing pad holes connected to the contact holes such that the landing pad holes have second widths in the first direction that are greater than the first widths; contact structures including contact plugs connected to the active regions by passing through the insulating layer, and first landing pads connected to the contact plugs, the first landing pads being in the landing pads holes such that the first landing pads vertically overlap with one of the pair of conductive lines; and capacitor lower electrodes connected to the contact structures. | 2014-11-06 |
20140327064 | METHOD FOR FABRICATING A METAL-INSULATOR-METAL (MIM) CAPACITOR HAVING CAPACITOR DIELECTRIC LAYER FORMED BY ATOMIC LAYER DEPOSITION (ALD) - In a thin film transistor, each of an upper electrode and a lower electrode is formed of at least one material selected from the group consisting of a metal and a metal nitride, represented by TiN, Ti, W, WN, Pt, Ir, Ru. A capacitor dielectric film is formed of at least one material selected from the group consisting of ZrO | 2014-11-06 |
20140327065 | CONDUCTIVE LAYERS FOR HAFNIUM SILICON OXYNITRIDE FILMS - Electronic apparatus and methods of forming the electronic apparatus include HfSiON for use in a variety of electronic systems. In various embodiments, conductive material is coupled to a dielectric containing HfSiON, where such conductive material may include one or more monolayers of titanium nitride, tantalum, or combinations of titanium nitride and tantalum. | 2014-11-06 |
20140327066 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - In a non-volatile memory in which writing/erasing is performed by changing a total charge amount by injecting electrons and holes into a silicon nitride film serving as a charge accumulation layer, in order to realize a high efficiency of a hole injection from a gate electrode, the gate electrode of a memory cell comprises a laminated structure made of a plurality of polysilicon films with different impurity concentrations, for example, a two-layered structure comprising a p-type polysilicon film with a low impurity concentration and a p | 2014-11-06 |
20140327067 | Three-Dimensional Nonvolatile Memory Device - A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, and a plurality of gate electrodes. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicular to the semiconductor substrate. The gate electrodes include a first gate electrode and a second gate electrode. The first gate electrode is disposed on the memory cell region to intersect the active pillars. The second gate electrode is disposed on the contact region, connected to the first gate electrode and comprising metal material. | 2014-11-06 |
20140327068 | Semiconductor Device with a Super Junction Structure with One, Two or More Pairs of Compensation Layers - A super junction semiconductor device comprises a semiconductor portion with mesa regions protruding from a base section. The mesa regions are spatially separated in a lateral direction parallel to a first surface of the semiconductor portion. A compensation structure with at least two first compensation layers of a first conductivity type and at least two second compensation layers of a complementary second conductivity type may cover sidewalls of the mesa regions and portions of the base section between the mesa regions. Buried lateral faces of segments of the compensation structure may cut the first and second compensation layers between the mesa regions. A drain connection structure of the first conductivity type may extend along the buried lateral faces and may structurally connect the first compensation layers in an economic way keeping the thermal budget low. | 2014-11-06 |
20140327069 | Semiconductor Device with a Super Junction Structure Based On a Compensation Structure with Compensation Layers and Having a Compensation Rate Gradient - A super junction structure is formed in a semiconductor portion of a super junction semiconductor device. The super junction structure includes a compensation structure with a first compensation layer of a first conductivity type and a second compensation layer of a complementary second conductivity type. The compensation structure lines at least sidewall portions of compensation trenches that extend between semiconductor mesas along a vertical direction perpendicular to a first surface of the semiconductor portion. Within the super junction structure and a pedestal layer that may adjoin the super junction structure, a sign of a lateral compensation rate changes along the vertical direction resulting in a local peak of a vertical electric field gradient and to improved avalanche ruggedness. | 2014-11-06 |
20140327070 | Super Junction Structure Semiconductor Device Based on a Compensation Structure Including Compensation Layers and a Fill Structure - A super junction semiconductor device includes strip structures between mesa regions that protrude from a base section in a cell area. Each strip structure includes a compensation structure with a first and a second section inversely provided on opposing sides of a fill structure. Each section includes a first compensation layer of a first conductivity type and a second compensation layer of a complementary second conductivity type. The strip structures extend into an edge area surrounding the cell area. In the edge area the strip structures include end sections. The end sections may be modified to enhance break down voltage characteristics, avalanche ruggedness and commutation behavior. | 2014-11-06 |
20140327071 | Method of Manufacturing a Semiconductor Device - The method includes providing a semiconductor chip having a first main face and a second main face opposite the first main face. The semiconductor chip includes an electrical device adjacent to the first main face. Material of the semiconductor chip is removed at the second main face except for a pre-defined portion so that a non-planar surface remains at the second main face. | 2014-11-06 |
20140327072 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: an N-type drift layer; a P-type anode layer on the N-type drift layer; a trench penetrating the P-type anode layer; a conductive substance embedded in the trench via an insulating film; and an N-type buffer layer between the N-type drift layer and the P-type anode layer and having impurity concentration which is higher than that of the N-type drift layer. | 2014-11-06 |
20140327073 | SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD THEREOF - The semiconductor apparatus according to the present invention includes: a second-conductivity-type first diffusion region formed on the semiconductor layer; a first-conductivity-type second diffusion region formed in the first diffusion region; a second-conductivity-type first high concentration diffusion region and a first-conductivity-type second high concentration diffusion region formed in the second diffusion region; a second-conductivity-type third high concentration diffusion region, separated by a given distance from the second diffusion region, in the first diffusion region; and a gate electrode formed above and between the first high concentration diffusion region and third high concentration diffusion region, with a gate insulation film interposed therebetween, where the gate electrode is formed overlapping the first high concentration diffusion region, and the gate electrode is electrically connected with the first high concentration diffusion region and second high concentration diffusion region, at the same potential. | 2014-11-06 |
20140327074 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a substrate, a multi-gate transistor device formed on the substrate, and an n-well resistor formed in the substrate. The substrate includes a plurality of first isolation structures and at least a second isolation structure formed therein. A depth of the first isolation structures is smaller than a depth of the second isolation structure. The multi-gate transistor device includes a plurality of fin structures, and the fin structures are parallel with each other and spaced apart from each other by the first isolation structures. The n-well resistor includes at least one first isolation structure. The n-well resistor and the multi-gate transistor device are electrically isolated from each other by the second isolation structure. | 2014-11-06 |
20140327075 | HIGH VOLTAGE AND ULTRA-HIGH VOLTAGE SEMICONDUCTOR DEVICES WITH INCREASED BREAKDOWN VOLTAGES - A lateral DMOS transistor is provided with a source region, a drain region, and a conductive gate. The drain region is laterally separated from the conductive gate by a field oxide that encroaches beneath the conductive gate. The lateral DMOS transistor may be formed in a racetrack-like configuration with the conductive gate including a rectilinear portion and a curved portion and surrounded by the source region. Disposed between the conductive gate and the trapped drain is one or more levels of interlevel dielectric material. One or more groups of isolated conductor leads are formed in or on the dielectric layers and may be disposed at multiple device levels. The isolated conductive leads increase the breakdown voltage of the lateral DMOS transistor particularly in the curved regions where electric field crowding can otherwise degrade breakdown voltages. | 2014-11-06 |
20140327076 | ROBUST REPLACEMENT GATE INTEGRATION - A method including forming a dummy gate on a substrate, wherein the dummy gate includes an oxide, forming a pair of dielectric spacers on opposite sides of the dummy gate, and forming an inter-gate region above the substrate and in contact with at least one of the pair of dielectric spacers, the inter-gate region comprising a protective layer on top of a first oxide layer, wherein the protective layer comprises a material resistant to etching techniques designed to remove oxide. The method may further include removing the dummy gate to leave an opening, and forming a gate within the opening. | 2014-11-06 |
20140327077 | Semiconductor-on-Insulator Integrated Circuit with Reduced Off-State Capacitance - An integrated circuit assembly comprises an insulating layer, a semiconductor layer, a handle layer, a metal interconnect layer, and transistors. The insulating layer has a first surface, a second surface, and a hole extending from the first surface to the second surface. The semiconductor layer has a first surface and a second surface, the first surface of the semiconductor layer contacting the first surface of the insulating layer. The handle layer is coupled to the second surface of the semiconductor layer. The metal interconnect layer is coupled to the second surface of the insulating layer, the metal interconnect layer being disposed within the hole in the insulating layer. The transistors are located in the semiconductor layer. The hole in the insulating layer extends to at least the first surface of the semiconductor layer. The metal interconnect layer electrically couples a plurality of the transistors to each other. | 2014-11-06 |
20140327078 | Semiconductor Device - It is an object of the present invention to connect a wiring, an electrode, or the like formed with two incompatible films (an ITO film and an aluminum film) without increasing the cross-sectional area of the wiring and to achieve lower power consumption even when the screen size becomes larger. The present invention provides a two-layer structure including an upper layer and a lower layer having a larger width than the upper layer. A first conductive layer is formed with Ti or Mo, and a second conductive layer is formed with aluminum (pure aluminum) having low electric resistance over the first conductive layer. A part of the lower layer projected from the end section of the upper layer is bonded with ITO. | 2014-11-06 |
20140327079 | Electrostatic Discharge (ESD) Clamp Circuit with High Effective Holding Voltage - Boosted Electrostatic Discharge (ESD) clamp circuit with high effective holding voltage. In some embodiments, an integrated circuit may include a trigger circuit operably coupled to a first voltage bus and to a reference bus; a diode including an anode terminal operably coupled to a second voltage bus, the second voltage bus distinct from the first voltage bus; a transistor including a gate operably coupled to an output terminal of the trigger circuit, a drain operably coupled to a cathode terminal of the diode, and a source operably coupled to the reference bus; and an input/output (I/O) cell operably coupled to the first voltage bus, the second voltage bus, and the reference bus. | 2014-11-06 |
20140327080 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - The present invention provides a manufacturing method of a semiconductor structure, comprising the following steps. First, a substrate is provided, a first dielectric layer is formed on the substrate, a metal gate is disposed in the first dielectric layer and at least one source/drain region (S/D region) is disposed on two sides of the metal gate, a second dielectric layer is then formed on the first dielectric layer, a first etching process is then performed to form a plurality of first trenches in the first dielectric layer and the second dielectric layer, wherein the first trenches expose each S/D region. Afterwards, a salicide process is performed to form a salicide layer in each first trench, a second etching process is then performed to form a plurality of second trenches in the first dielectric layer and the second dielectric layer, and the second trenches expose the metal gate. | 2014-11-06 |
20140327081 | STANDARD CELL METAL STRUCTURE DIRECTLY OVER POLYSILICON STRUCTURE - A semiconductor structure includes a first active area structure, an isolation structure surrounding the first active area structure, a first polysilicon structure, a first metal structure, and a second metal structure. The first polysilicon structure is over the first active area structure. The first metal structure is directly over a first portion of the first active area structure. The second metal structure is directly over and in contact with a portion of the first polysilicon structure and in contact with the first metal structure. | 2014-11-06 |
20140327082 | SRAM WELL-TIE WITH AN UNINTERRUPTED GRATED FIRST POLY AND FIRST CONTACT PATTERNS IN A BIT CELL ARRAY - An integrated circuit containing an SRAM may be formed using one or more periodic photolithographic patterns for elements of the integrated circuit such as gates and contacts, which have alternating line and space configurations in SRAM cells. Strap rows of the SRAM containing well ties and/or substrate taps which have SRAM cells on two opposite sides are configured so that the alternating line and space configurations are continuous across the regions containing the well ties and substrate taps. | 2014-11-06 |
20140327083 | COMBINATION-TYPE TRANSISTOR AND METHOD FOR MANUFACTURING SAME - Disclosed is a combination-type transistor including a first MOSFET that includes a gate, a first source formed on one side of the gate, and a first drain formed on the other side of the gate; a second MOSFET that includes the gate, a second drain formed on the one side of the gate, and a second source formed on the other side of the gate; a first BJT that is formed such that the first source of the first MOSFET is used as an emitter, the second drain of the second MOSFET is used as a collector, and the substrate is used as a base; and a second BJT that is formed such that the second source of the second MOSFET is used as an emitter, the first drain of the first MOSFET is used as a collector, and the substrate is used as a base. | 2014-11-06 |
20140327084 | DUAL SHALLOW TRENCH ISOLATION (STI) FIELD EFFECT TRANSISTOR (FET) AND METHODS OF FORMING - Various embodiments include field effect transistor (FET) structures and methods of forming such structures. In various embodiments, an FET structure includes: a deep n-type well; an shallow n-type well and a p-type well each within the deep n-type well; and a shallow trench isolation (STI) region within the shallow n-type well, the STI region including: a first section having a first depth within the shallow n-type well as measured from an upper surface of the shallow n-type well; and a second section contacting and overlying the first section, the second section having a second depth within the shallow n-type well as measured from the upper surface of the shallow n-type well. | 2014-11-06 |
20140327085 | VARIABLE RESISTANCE DEVICE HAVING PARALLEL STRUCTURE - A variable resistance device includes a parallel structure. The variable resistance device is formed using a silicon (Si) substrate. In the variable resistance device, a conductive line arranged in a current direction is formed over an impurity region, and a resistance value of the resistance device is precisely adjusted by adjusting a level of a voltage applied to the conductive line. The variable resistance device includes a first impurity region formed in a substrate, a second impurity region formed in the substrate and arranged parallel to the first impurity region, a conductive line formed over the first impurity region, and electrode terminals formed at both longitudinal ends of the second impurity region to be coupled to the second impurity region. | 2014-11-06 |
20140327086 | Semiconductor Device and Method for Forming Same - A system and method for forming a resistor system is provided. An embodiment comprises a resistor formed in a U-shape. The resistor may comprise multiple layers of conductive materials, with a dielectric layer filling the remainder of the U-shape. The resistor may be integrated with a dual metal gate manufacturing process or may be integrated with multiple types of resistors. | 2014-11-06 |
20140327087 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device may include a substrate having a first region and a second region on a surface thereof, and a first semiconductor fin on the first region of the substrate with the first semiconductor fin including a first trench therethrough. A first gate electrode may be provided in the first trench, and first and second source/drain regions may be provided in the first semiconductor fin, with the first gate electrode between the first and second source/drain regions. A second semiconductor fin may be provided on the second region of the substrate with the second semiconductor fin including a second trench therethrough, a second gate electrode may be provided in the second trench, and third and fourth source/drain regions may be provided in the second semiconductor fin with the second gate electrode being between the third and fourth source/drain regions. | 2014-11-06 |
20140327088 | FINFET SEMICONDUCTOR DEVICE WITH A RECESSED LINER THAT DEFINES A FIN HEIGHT OF THE FINFET DEVICE - One method disclosed herein includes forming a conformal liner layer in a plurality of trenches that define a fin, forming a layer of insulating material above the liner layer, exposing portions of the liner layer, removing portions of the liner layer so as to result in a generally U-shaped liner positioned at a bottom of each of the trenches, performing at least one third etching process on the layer of insulating material, wherein at least a portion of the layer of insulating material is positioned within a cavity of the U-shaped liner layer, and forming a gate structure around the fin. A FinFET device disclosed herein includes a plurality of trenches that define a fin, a local isolation that includes a generally U-shaped liner that defines, in part, a cavity and a layer of insulating material positioned within the cavity, and a gate structure positioned around the fin. | 2014-11-06 |
20140327089 | FINFET DEVICES HAVING RECESSED LINER MATERIALS TO DEFINE DIFFERENT FIN HEIGHTS - One method includes performing an etching process through a patterned mask layer to form trenches in a substrate that defines first and second fins, forming liner material adjacent the first fin to a first thickness, forming liner material adjacent the second fin to a second thickness different from the first thickness, forming insulating material in the trenches adjacent the liner materials and above the mask layer, performing a process operation to remove portions of the layer of insulating material and to expose portions of the liner materials, performing another etching process to remove portions of the liner materials and the mask layer to expose the first fin to a first height and the second fin to a second height different from the first height, performing another etching process to define a reduced-thickness layer of insulating material, and forming a gate structure around a portion of the first and second fin. | 2014-11-06 |
20140327090 | FINFET DEVICE WITH AN ETCH STOP LAYER POSITIONED BETWEEN A GATE STRUCTURE AND A LOCAL ISOLATION MATERIAL - One illustrative method disclosed herein includes forming a sacrificial gate structure above a fin, wherein the sacrificial gate structure is comprised of a sacrificial gate insulation layer, a layer of insulating material, a sacrificial gate electrode layer and a gate cap layer, forming a sidewall spacer adjacent opposite sides of the sacrificial gate structure, removing the sacrificial gate structure to thereby define a gate cavity that exposes a portion of the fin, and forming a replacement gate structure in the gate cavity. One illustrative device disclosed herein includes a plurality of fin structures that are separated by a trench formed in a substrate, a local isolation material positioned within the trench, a gate structure positioned around portions of the fin structures and above the local isolation material and an etch stop layer positioned between the gate structure and the local isolation material within the trench. | 2014-11-06 |
20140327091 | FIN FIELD EFFECT TRANSISTOR - A fin field effect transistor including a first insulation region and a second insulation region over a top surface of a substrate. The first insulation region includes tapered top surfaces, and the second insulation region includes tapered top surfaces. The fin field effect transistor further includes a fin extending above the top surface between the first insulation region and the second insulation region. The fin includes a first portion having a top surface below the tapered top surfaces of the first insulation region. The fin includes a second portion having a top surface above the tapered top surfaces of the first insulation region. | 2014-11-06 |
20140327092 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - The present invention provides a semiconductor device which suppresses a short circuit and a leakage current between a semiconductor film and a gate electrode generated by a break or thin thickness of a gate insulating film in an end portion of a channel region of the semiconductor film, and the manufacturing method of the semiconductor device. Plural thin film transistors which each have semiconductor film provided over a substrate continuously, conductive films provided over the semiconductor film through a gate insulating film, source and drain regions provided in the semiconductor film which are not overlapped with the conductive films, and channel regions provided in the semiconductor film existing under the conductive films and between the source and drain regions. And impurity regions provided in the semiconductor film which is not overlapped with the conductive film and provided adjacent to the source and drain regions. Further, the conductive films are provided over the channel regions and regions of the semiconductor film which are provided adjacent to the channel regions. | 2014-11-06 |
20140327093 | FIELD-EFFECT TRANSISTOR AND FABRICATING METHOD THEREOF - A field-effect transistor comprises a substrate, a gate dielectric layer, a barrier layer, a metal gate electrode and a source/drain structure. The gate dielectric layer is disposed on the substrate. The barrier layer having a titanium-rich surface is disposed on the gate dielectric layer. The metal gate electrode is disposed on the titanium-diffused surface. The source/drain structure is formed in the substrate and adjacent to the metal gate electrode. | 2014-11-06 |
20140327094 | SEMICONDUCTOR STRUCTURE FOR ELECTROMAGNETIC INDUCTION SENSING AND A METHOD OF MANUFACTURING THE SAME - A semiconductor structure for electromagnetic induction sensing and a method for manufacturing the same are provided: forming the Hall sensor in a first semiconductor fabrication; forming the passivation layer above the Hall sensor to cover the Hall sensor according to the first semiconductor fabrication; and forming the current-carrying layer above the passivation layer in a second semiconductor fabrication to form the semiconductor structure for electromagnetic induction sensing. The current-carrying layer carries the current to be sensed; and the Hall sensor senses the magnetic field generated. The Hall sensor generates a voltage or a current signal proportional to the strength of the current to be sensed. | 2014-11-06 |
20140327095 | MAGNETIC DEVICE - A magnetic device can include a tunnel bather and a hybrid magnetization layer disposed adjacent the tunnel barrier. The hybrid magnetization layer can include a first perpendicular magnetic anisotropy (PMA) layer, a second PMA layer, and an amorphous blocking layer disposed between the first and second PMA layers. The first PMA layer can include a multi-layer film in which a first layer formed of Co and a second layer formed of Pt or Pd are alternately stacked. A first dopant formed of an element different from those of the first and second layers can also be included in the first PMA layer. The second PMA layer can be disposed between the first PMA layer and the tunnel barrier, and can include at least one element selected from a group consisting of Co, Fe, and Ni. | 2014-11-06 |
20140327096 | PERPENDICULAR STT-MRAM HAVING LOGICAL MAGNETIC SHIELDING - A perpendicular STT-MRAM comprises apparatus and a method of manufacturing a plurality of magnetoresistive memory element having local magnetic shielding. As an external perpendicular magnetic field exists, the permeable dielectric layers, the permeable bit line and the permeable bottom electrode are surrounding and have capability to absorb and channel most magnetic flux surrounding the MTJ element instead of penetrate through the MTJ element. Thus, magnetization of a recording layer can be less affected by the stray field during either writing or reading, standby operation. | 2014-11-06 |
20140327097 | STORAGE ELEMENT AND STORAGE DEVICE - Provided is an information storage element comprising a first layer, an insulation layer coupled to the first layer, and a second layer coupled to the insulation layer opposite the first layer. The first layer has a transverse length that is approximately 45 nm or less, or an area that is approximately 1,600 nm | 2014-11-06 |
20140327098 | METHOD OF PRODUCING A RADIATION IMAGER EXHIBITING IMPROVED DETECTION EFFICIENCY - A radiation imager including: a reading block; a first substrate; a plurality of portions made from a first material with a first optical index between the first substrate and the reading block; a second material at a periphery of at least one of the portions, the second material having a second optical index lower than the first optical index; and areas made from a third material surrounding at least ends of the portions oriented on a same side as the reading block, the areas made from a third material obtained by applying a layer made from a third material to the reading block and penetration of the end of the at least one portion made from a first material in the layer made from a third material. | 2014-11-06 |
20140327099 | NANOMETER-SCALE LEVEL STRUCTURES AND FABRICATION METHOD FOR DIGITAL ETCHING OF NANOMETER-SCALE LEVEL STRUCTURES - A ramped etalon cavity structure and a method of fabricating same. A bi-layer stack is deposited on a substrate. The bi-layer stack includes a plurality of bi-layers. Each bi-layer of the plurality of bi-layers includes an etch stop layer and a bulk layer. A three dimensional photoresist structure is formed by using gray-tone lithography. The three dimensional photoresist is plasma etched into the bi-layer stack, thereby generating an etched bi-layer stack. The etched bi-layer stack is chemically etched with a first chemical etchant to generate a multiple-step structure on the substrate, wherein the first chemical etchant stops at the etch stop layer. | 2014-11-06 |
20140327100 | LIGHT DETECTION DEVICE - A semiconductor light detection element has a plurality of channels, each of which consists of a photodiode array including a plurality of avalanche photodiodes operating in Geiger mode, quenching resistors connected in series to the respective avalanche photodiodes, and signal lines to which the quenching resistors are connected in parallel. A mounting substrate is configured so that a plurality of electrodes corresponding to the respective channels are arranged on a third principal surface side and so that a signal processing unit for processing output signals from the respective channels is arranged on a fourth principal surface side. In a semiconductor substrate, through-hole electrodes electrically connected to the signal lines are formed for the respective channels. The through-hole electrodes and the electrodes are electrically connected through bump electrodes. | 2014-11-06 |
20140327101 | IMAGE PICKUP DEVICE AND MANUFACTURING METHOD FOR PRODUCING SAME - An image pickup device includes a light-receiving device unit, a processing portion, a first connection body, and a second connection body. The first connection body electrically connects a first electrode of the light-receiving device unit to a corresponding second electrode of the processing portion. The first connection body includes an indium-containing solder portion disposed between the first electrode and the second electrode, and a barrier layer for suppressing alloying of the solder portion with the first electrode and the second electrode. The second connection body includes an alloy portion formed by alloying with a solder containing a material having a melting point equal to or higher than a melting point of the first connection body and a hardness higher than that of the first connection body. | 2014-11-06 |
20140327102 | NEGATIVELY CHARGED LAYER TO REDUCE IMAGE MEMORY EFFECT - An image sensor pixel includes a photodiode region having a first polarity doping type disposed in a semiconductor layer. A pinning surface layer having a second polarity doping type is disposed over the photodiode region in the semiconductor layer. A first polarity charge layer is disposed proximate to the pinning surface layer over the photodiode region. A contact etch stop layer is disposed over the photodiode region proximate to the first polarity charge layer. The first polarity charge layer is disposed between the pinning surface layer and the contact etch stop layer such that first polarity charge layer cancels out charge having a second polarity that is induced in the contact etch stop layer. The first polarity charge layer is disposed between a first one of a plurality of passivation layers and a second one of the plurality of passivation layers disposed over the photodiode region. | 2014-11-06 |
20140327103 | Semiconductor Device with an Electrode Buried in a Cavity - A semiconductor device with a buried electrode is manufactured by forming a cavity within a semiconductor substrate, forming an active device region in an epitaxial layer disposed on the semiconductor substrate and forming the buried electrode below the active device region in the cavity. The buried electrode is formed from an electrically conductive material different than the material of the semiconductor substrate. | 2014-11-06 |
20140327104 | Semiconductor Device with a Super Junction Structure with Compensation Layers and a Dielectric Layer - A super junction semiconductor device includes a layered compensation structure with an n-type compensation layer and a p-type compensation layer, a dielectric layer facing the p-type layer, and an intermediate layer interposed between the dielectric layer and the p-type compensation layer. The layered compensation structure and the intermediate layer are provided such that when a reverse blocking voltage is applied between the n-type and p-type compensation layers, holes accelerated in the direction of the dielectric layer have insufficient energy to be absorbed and incorporated into the dielectric material. Since the dielectric layer absorbs and incorporates significantly less holes than without the intermediate layer, the breakdown voltage remains stable over a long operation time. | 2014-11-06 |
20140327105 | ELECTROSTATIC DISCHARGE DIODE - A method includes thinning a back-side of a substrate to expose a portion of a first via that is formed in the substrate. The method also includes forming a first diode at the back-side of the substrate. The first diode is coupled to the first via. | 2014-11-06 |
20140327106 | BIPOLAR JUNCTION TRANSISTORS WITH SELF-ALIGNED TERMINALS - Device structures, fabrication methods, and design structures for a bipolar junction transistor. A semiconductor material layer is formed on a substrate and a mask layer is formed on the semiconductor material layer. The mask layer is patterned to form a plurality of openings to the semiconductor material layer. After the mask layer is formed and patterned, the semiconductor material layer is etched at respective locations of the openings to define a first trench, a second trench separated from the first trench by a first section of the semiconductor material layer defining a terminal of the bipolar junction transistor, and a third trench separated from the first trench by a second section of the semiconductor material layer defining an isolation pedestal. A trench isolation region is formed at a location in the substrate that is determined at least in part using the isolation pedestal as a positional reference. | 2014-11-06 |
20140327107 | Semiconductor Device and Method of Forming Inductor Over Insulating Material Filled Trench in Substrate - A semiconductor device has a trench formed in a substrate. The trench has tapered sidewalls and depth of 10-120 micrometers. A first insulating layer is conformally applied over the substrate and into the trench. An insulating material, such as polymer, is deposited over the first insulating layer in the trench. A first conductive layer is formed over the insulating material. A second insulating layer is formed over the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and electrically contacts the first conductive layer. The first and second conductive layers are isolated from the substrate by the insulating material in the trench. A third insulating layer is formed over the second insulating layer and second conductive layer. The first and second conductive layers are coiled over the substrate to exhibit inductive properties. | 2014-11-06 |
20140327108 | NOISE CANCELLATION FOR A MAGNETICALLY COUPLED COMMUNICATION LINK UTILIZING A LEAD FRAME - An integrated circuit package includes an encapsulation and a lead frame with a portion of the lead frame disposed within the encapsulation. The lead frame includes a first conductor having a first conductive loop and a third conductive loop disposed within the encapsulation. The third conductive loop is wound in a direction relative to the first conductive loop such that the first conductive loop is coupled out of phase with the third conductive loop. The lead frame also includes a second conductor galvanically isolated from the first conductor. The second conductor includes a second conductive loop disposed within the encapsulation proximate to the first conductive loop to provide a communication link between the first and second conductors. | 2014-11-06 |
20140327109 | DEEP TRENCH CAPACITOR MANUFACTURED BY STREAMLINED PROCESS - The present disclosure provides a deep trench capacitor device. A first capacitor electrode is made up of a doped region of semiconductor substrate in which two or more trenches are arranged. A second capacitor electrode is made up of a continuous body of conductive material. The continuous body of conductive material includes a lower body portion filling the two or more trenches and an upper body portion extending continuously over the lower body portion. The upper body portion extends upwardly out of the trenches by a non-zero distance. A capacitor dielectric liner is arranged in the two or more trenches to separate the first and second capacitor electrodes. The capacitor dielectric liner extends continuously out of the two or more trenches along outer sidewalls of the upper body portion. | 2014-11-06 |
20140327110 | METHOD OF MANUFACTURING A BIPOLAR TRANSISTOR, BIPOLAR TRANSISTOR AND INTEGRATED CIRCUIT - Consistent with an example embodiment, a bipolar transistor comprises an emitter region vertically separated from a collector region in a substrate by a base region. The bipolar transistor further comprises a field plate electrically connected to the emitter region; the field plate extends from the emitter region along the base region into the collector region and the field plate is laterally electrically insulated from the base region and the collector region by a spacer. The spacer comprises an electrically isolating material that includes a silicon nitride layer and is vertically electrically isolated from the substrate by a further electrically isolating material. | 2014-11-06 |
20140327111 | TRENCH ISOLATION STRUCTURES AND METHODS FOR BIPOLAR JUNCTION TRANSISTORS - Device structures, fabrication methods, and design structures for a bipolar junction transistor. A first isolation region is formed in a substrate to define a lateral boundary for an active device region and an intrinsic base layer is formed on the substrate. The intrinsic base layer has a section overlying the active device region. After the intrinsic base layer is formed, the first isolation region is partially removed adjacent to the active device region to define a trench that is coextensive with the substrate in the active device region and that is coextensive with the first isolation region. The trench is at least partially filled with a dielectric material to define a second isolation region. | 2014-11-06 |
20140327112 | METHOD TO DELINEATE CRYSTAL RELATED DEFECTS - Process for detecting grown-in-defects in a semiconductor silicon substrate. The process includes contacting a surface of the semiconductor silicon substrate with a gaseous acid in a reducing atmosphere at a temperature and duration sufficient to grow grown-in -defects disposed in the semiconductor silicon substrate to a size capable of being detected by an optical detection device. | 2014-11-06 |
20140327113 | 3D INTEGRATED HETEROSTRUCTURES HAVING LOW-TEMPERATURE BONDED INTERFACES WITH HIGH BONDING ENERGY - The invention relates to a process for assembling a first element that includes at least one first wafer, substrate or at least one chip, and a second element of at least one second wafer or substrate, involving the formation of a surface layer, known as a bonding layer, on each substrate, at least one of the bonding layers being formed at a temperature less than or equal to 300° C.; conducting a first annealing, known as degassing annealing, of the bonding layers, before assembly, at least partly at a temperature at least equal to the subsequent bonding interface strengthening temperature but below 450° C.; forming an assembling of the substrates by bringing into contact the exposed surfaces of the bonding layers, and conducting an annealing of the assembled structure at a bonding interface strengthening temperature below 450° C. | 2014-11-06 |
20140327114 | SEMICONDUCTOR COMPONENT WITH OPTIMIZED EDGE TERMINATION - A semiconductor component includes a two-sided semiconductor body, an inner zone with a basic doping of a first conduction type, and two semiconductor zones. The first zone, disposed between the first side and inner zone, is of the first conduction type with a doping concentration higher than that of the inner zone. The second zone, disposed between the second side and inner zone, is of a second conduction type complementary to the first type with a doping concentration higher than that of the inner zone. | 2014-11-06 |
20140327115 | MULTIPLE SEAL-RING STRUCTURE FOR THE DESIGN, FABRICATION, AND PACKAGING OF INTEGRATED CIRCUITS - A semiconductor circuit design includes an outer seal-ring and an inner seal-ring for each sub-section of the design that may potentially be cut into separate die. The use of multiple seal-rings permits a single circuit design and fabrication run to be used to support flexibly packaging different product releases having different numbers of integrated circuit blocks per packaged unit. | 2014-11-06 |
20140327116 | COMPOSITE SUBSTRATE - Disclosed is a composite substrate, which is provided with an inorganic insulating sintered substrate, which has a heat conductivity of 5 W/m·K or more, and a volume resistivity of 1×10 | 2014-11-06 |
20140327117 | OPTICALLY TUNED HARDMASK FOR MULTI-PATTERNING APPLICATIONS - The embodiments herein provides methods for forming a PVD silicon oxide or silicon rich oxide, or PVD SiN or silicon rich SiN, or SiC or silicon rich SiC, or combination of the preceding including a variation which includes controlled doping of hydrogen into the compounds heretofore referred to as SiO | 2014-11-06 |
20140327118 | POWER SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A method of fabricating a power semiconductor device includes the following steps. Firstly, a substrate is provided. A first epitaxial layer is formed over the substrate. A first trench is formed in the first epitaxial layer. A second epitaxial layer is refilled into the first trench. The first epitaxial layer and the second epitaxial layer are collaboratively defined as a first semiconductor layer. A third epitaxial layer is formed over the substrate, and a second trench is formed in the third epitaxial layer. A first doping region is formed in a sidewall of the second trench. An insulation layer is refilled into the second trench. The insulation layer, the first doping region and the third epitaxial layer are collaboratively defined as a second semiconductor layer. The power semiconductor device fabricated by the fabricating method can withstand high voltage and has low on-resistance. | 2014-11-06 |
20140327119 | INTEGRATED CIRCUIT HAVING SHIELDING STRUCTURE - An integrated circuit includes a signal line and a plurality of shielding structures. The signal line is routed along a first direction and is in a first metallization layer. Each shielding structure includes a plurality of non-contiguous shielding patterns aligned along the first direction. The plurality of shielding structures includes a first and a second shielding structures in a second metallization layer that adjoins the first metallization layer and a third and a fourth shielding structures in a third metallization layer that adjoins the first metallization layer. The first metallization layer is between the second and the third metallization layers. The first and the second shielding structures are separated from each other along a second direction perpendicular to the first direction. The third and the fourth shielding structures are separated from each other along the second direction. | 2014-11-06 |
20140327120 | DIFFERENTIAL EXCITATION OF PORTS TO CONTROL CHIP-MODE MEDIATED CROSSTALK - A differential port and a method of arranging the differential port are described. The method includes arranging a first electrode to receive a drive signal, and arranging a second electrode to receive a guard signal, the guard signal having a different phase than the drive signal and the first electrode and the second electrode having a gap therebetween. The method also includes disposing a signal line from the first electrode to drive a radio frequency (RF) device. | 2014-11-06 |
20140327121 | Semiconductor Device and Method for Manufacturing Same - The purpose of the present invention is to increase the reliability of a semiconductor device in which a semiconductor element and a substrate are connected by solder and which is molded by resin. | 2014-11-06 |
20140327122 | MICRO LEAD FRAME STRUCTURE HAVING REINFORCING PORTIONS AND METHOD - In one embodiment, a micro lead frame structure includes one or more stiffness reinforcing structures formed on leads and/or connecting structures. The stiffness reinforcing structures can be formed by leaving predetermined portions of the micro lead frame at full thickness including, for example, portions of an inner lead, portions of an outer lead, and portions of a connecting bar, combinations thereof, and other structures. The stiffness reinforcing structures are configured to reduce deformation defects and electrical short defects caused by assembly processes. | 2014-11-06 |
20140327123 | PACKAGED IC HAVING PRINTED DIELECTRIC ADHESIVE ON DIE PAD - A packaged integrated circuit (IC) includes a leadframe having metal terminals positioned outside the die pad. An IC die having a top side including a plurality of bond pads is placed with its bottom side onto attached by a dielectric polymer material to the die pad. Bond wires are between the plurality of bond pads and the metal terminals of the leadframe. A mold material different from said dielectric polymer material provides encapsulation for the packaged IC. An area of the dielectric polymer material exceeds an area of the IC die. The dielectric polymer material forms a dielectric polymer/mold material interface with the mold material. | 2014-11-06 |
20140327124 | POWER TRANSISTOR WITH HEAT DISSIPATION AND METHOD THEREFORE - A device comprising a substrate, an integrated circuit (IC) die attached to the substrate on one side, a plurality of contact pads on an active side of the IC die, a plurality of thermally and electrically conductive legs, each of the legs attached to a respective one of the contact pads, and an encapsulating material formed around the substrate, the IC die, and a portion of the legs. A contact end of each of the legs is exposed, and one of the contact ends conducts a signal from a transistor in the IC die. | 2014-11-06 |
20140327125 | SEMICONDUCTOR PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF - A semiconductor package structure and a fabrication method thereof are provided. The fabrication method comprises: providing a substrate strip, the substrate strip comprising a plurality of substrate units; disposing a plurality of chips on the plurality of substrate units; disposing a packaging encapsulant on the substrate strip to encapsulate the chips; forming a warp-resistant layer on a top surface of the packaging encapsulant; and dividing the substrate strip to separate the plurality of substrate units to further fabricate a plurality of semiconductor package structures, wherein the warp-resistant layer is formed of a selected material with a selected thickness to make a variation of warpage of the semiconductor package structure at a temperature between 25° C. and 260° C. to be smaller than 560 μm. | 2014-11-06 |
20140327126 | COOLING INTEGRATED CIRCUIT PACKAGES FROM BELOW - The subject disclosure is directed towards cooling an integrated circuit package such as a flip chip ball gate array from beneath the package. The integrated circuit package comprises a silicon die, and a substrate below the silicon die. The substrate includes microvias configured to transfer heat away from the silicon die in a direction towards the circuit board for cooling the silicon die from beneath. The circuit board may likewise contain vias or share common vias with the package to facilitate cooling from beneath the circuit board. | 2014-11-06 |
20140327127 | Power module with cooling structure on bonding substrate for cooling an attached semiconductor chip - According to an exemplary embodiment, a power module is provided which comprises a semiconductor chip, a bonding substrate comprising an electrically conductive sheet and an electric insulator sheet which is directly attached to the electrically conductive sheet and which is thermally coupled to the semiconductor chip, and an array of cooling structures directly attached to the electrically conductive sheet and configured for removing heat from the semiconductor chip when interacting with cooling fluid. | 2014-11-06 |