45th week of 2014 patent applcation highlights part 37 |
Patent application number | Title | Published |
20140329331 | NOVEL CYANINE DERIVATIVES HAVING MESO-REACTIVE FUNCTIONAL GROUP AT POLYMETHINE CHAIN AND PREPARATION METHOD THEREOF - The present invention relates to a novel cyanne derivative having a meso-reaction functional group in a polymethine chain, and a preparation method thereof, and the cyanine derivative having the reaction functional group substituted at the meso site may be suitable for mass production thanks to a very simple synthesis method, have a very fast reaction rate because while a related art reagent for detection of nerve agents undergoes two steps of reactions, the cyanine derivative of the present invention undergoes only one step of reaction, have very excellent sensitivity, and be useful as an acid pH-activated ratiometric NIR probe because it is able to be activated in an acidic pH and is usable in an aqueous environment. | 2014-11-06 |
20140329332 | DEVICE AND METHOD FOR RAPID ASSAY OF MULTIPLE BIOLOGICAL SAMPLES FOR OXYGEN CONSUMPTION | 2014-11-06 |
20140329333 | MICRO-SAMPLING-SYSTEM FOR SMALL AMOUNTS OF FLUID SAMPLES FOR ANALYSIS IN THE VAPOUR PHASE - Microsampling system for small amounts of fluid samples for analysis in the vapour phase, which comprises a plurality of integrated functional units and is suitable for small sample quantities with fast reaction times. | 2014-11-06 |
20140329334 | METHOD FOR MONITORING, DIAGNOSIS AND/OR PROGNOSIS OF ACUTE KIDNEY INJURY IN EARLY STAGE - The present invention relates to a method and a kit for monitoring, diagnosis, prognosis of acute kidney injury in early stage and determination of treatment in subjects suffering thereof. The method comprises the steps of a) providing a urine sample; b) enriching the urine sample in exosomes present in the urine sample using at least one step of immunopurification; c) detecting an acute kidney injury (AKI) marker in the exosome. The invention also relates to a kit for determining the presence and/or level of a specific kidney injury marker, for simple and early determination of the onset of AKI in a subject, the kit comprising means for enriching the urine sample in exosomes using at least one step of immunopurification, and means for detecting a predetermined kidney injury marker of a condition. | 2014-11-06 |
20140329335 | MAGNETIC PARTICLE DETECTION WITH INCUBATION PERIOD - The invention relates to a method and a device for the detection of magnetic particles ( | 2014-11-06 |
20140329336 | CHEMICAL SENSOR, CHEMICAL SENSOR MODULE, CHEMICAL SUBSTANCE DETECTION APPARATUS, AND CHEMICAL SUBSTANCE DETECTION METHOD - [Object] To provide a chemical sensor provided with a spectral filter excellent in spectral characteristic, a chemical sensor module, a chemical substance detection apparatus, and a chemical substance detection method. | 2014-11-06 |
20140329337 | PERPENDICULAR SPIN TRANSFER TORQUE MEMORY (STTM) DEVICE HAVING OFFSET CELLS AND METHOD TO FORM SAME - Perpendicular spin transfer torque memory (STTM) devices having offset cells and methods of fabricating perpendicular STTM devices having offset cells are described. For example, a spin torque transfer memory (STTM) array includes a first load line disposed above a substrate and having only a first STTM device. The STTM array also includes a second load line disposed above the substrate, adjacent the first load line, and having only a second STTM device, the second STTM device non-co-planar with the first STTM device. | 2014-11-06 |
20140329338 | METHOD FOR PREPARING NANO-SHEET ARRAY STRUCTURE OF GROUP V-VI SEMICONDUCTOR - The object of the present invention is to provide a method for preparing a nano-sheet array structure of a Group V-VI semiconductor, comprising: (A) providing an electrolyte containing a hydrogen ion and disposing an auxiliary electrode and a working electrode in the electrolyte, wherein the working electrode comprises a Group V-VI semiconductor bulk; and (B) applying a redox reaction bias to the auxiliary electrode and the working electrode to form a nano-sheet array structure on the bulk. | 2014-11-06 |
20140329339 | DEFECT DETECTION AND CORRECTION OF PIXEL CIRCUITS FOR AMOLED DISPLAYS - A method of testing an array-based semiconductor device for defects during fabrication of the semiconductor device detects defects in said entities forming the semiconductor device at an intermediate stage in the fabrication of multiple types of entities forming the semiconductor device; determines whether the detected defects exceed preselected thresholds for the types of entities in which said detects are detected; if the detected defects do not exceed said preselected thresholds, continues the fabrication of the semiconductor device; and if the detected defects exceed said preselected thresholds, identifies the types of defects detected, repairs the identified defects, and continues the fabrication of the semiconductor device. | 2014-11-06 |
20140329340 | HEAT TREATMENT METHOD AND HEAT TREATMENT APPARATUS - After a substrate implanted with impurities is heated to a preheating temperature, the front surface of the substrate is heated to a target temperature by irradiating the front surface of the substrate with a flash of light. Further, the flash irradiation is continued to maintain the temperature of the front surface near the target temperature for a predetermined time period. At this time, a flash irradiation time period in the flash heating step is made longer than a heat conduction time period required for heat conduction from the front surface of the substrate to the back surface thereof, and a difference in temperature between the front and back surfaces of the substrate is controlled to be always not more than one-half of an increased temperature from the preheating temperature to the target temperature during the flash irradiation. This alleviates the concentration of stresses resulting from a difference in thermal expansion between the front and back surfaces of the substrate to thereby prevent the cracking of the substrate. | 2014-11-06 |
20140329341 | BONDING METHOD, BONDING APPARATUS AND BONDING SYSTEM - A bonding method according to an exemplary embodiment of the present disclosure includes a first holding processing, a second holding processing, a temporary bonding processing, a temperature increasing processing and a main bonding processing. In the first holding processing, a target substrate is held. In the second holding processing, a glass substrate held by electrostatic adsorption. In the temporary bonding processing, the target substrate and the glass substrate are temporarily bonded with a pressing force lower than a predetermined pressing force at a temperature lower than a predetermined temperature. In the temperature increasing processing, while releasing the electrostatic adsorption of the glass substrate at the same time as or after the temporary bonding, the temperature is increased to the predetermined temperature. In the main bonding processing, a main bonding of the target substrate and the glass substrate is performed with the predetermined pressing force. | 2014-11-06 |
20140329342 | METHOD FOR INSPECTING PACKAGING EFFECTIVENESS OF OLED PANEL - The present invention provides a method for inspecting packaging effectiveness of an OLED panel, including: (1) in a manufacture process of an OLED component, forming a test block on a substrate, wherein the test block is made of an active metal, and then forming a plurality of test electrodes, wherein each of the test electrodes has an end connected to the test block and an opposite end extending to the outside for connection with a measurement device; (2) packaging an OLED panel so that said opposite ends of the test electrodes extend out of an enclosing frame; (3) electrically connecting the measurement device to the test electrodes to measure an actual conductivity of the test block; and (4) determining packaging effectiveness according to the actual conductivity. The method of the present invention makes use of conductivity differential of a test block made of an active metal in environments having different water/oxygen content to detect, in a more precise manner, the water/oxygen content in a packaged OLED panel so as to correctly determine the effectiveness of packaging. | 2014-11-06 |
20140329343 | METHOD AND SYSTEM FOR MONITORING CRYSTALLIZATION OF AMORPHOUS SILICON THIN FILM, AND METHOD OF MANUFACTURING THIN FILM TRANSISTOR BY USING THE METHOD AND SYSTEM - A method and system for monitoring crystallization of an amorphous silicon (a-Si) thin film, and a method of manufacturing a thin film transistor (TFT) by using the method and system are disclosed. The method of monitoring the crystallization of the a-Si thin film includes: irradiating light from a light source onto a monitoring a-Si thin film to anneal the monitoring a-Si thin film; annealing the monitoring a-Si thin film and concurrently measuring a Raman scattering spectrum of light scattered by the monitoring a-Si thin film at set time intervals; and calculating a crystallization characteristic value of the monitoring a-Si thin film based on the Raman scattering spectrum. | 2014-11-06 |
20140329344 | TESTING AN ELECTRICAL CONNECTION OF A DEVICE CAP - A method of testing a device includes setting a potential of a cap terminal of the device to a first voltage, setting a potential of a self test plate of the device to a testing voltage, and detecting a first displacement of a proof mass of the device when the cap terminal is set to the first voltage and the self test plate is set to the testing voltage. The method includes setting a potential of the cap terminal of the device to a second voltage, detecting a second displacement of the proof mass of the device when the cap terminal is set to the second voltage and the self test plate is set to the testing voltage, and comparing the first displacement and the second displacement to evaluate an electrical connection between the cap terminal and a cap of the device. | 2014-11-06 |
20140329345 | MANUFACTURING METHOD OF ORGANIC LIGHT EMITTING DIODE DISPLAY - A manufacturing method of an organic light emitting diode (OLED) display includes manufacturing a mother substrate including a plurality of panels formed with a plurality of anodes for each pixel and a test pad connected to each anode of the panel. The method further includes loading the mother substrate into a plasma chamber and applying a plasma voltage to the test pad of the mother substrate to perform a plasma surface treatment process. The test pad is applied with a different plasma voltage for each pixel. | 2014-11-06 |
20140329346 | ELEMENT CONNECTING BOARD, PRODUCING METHOD THEREOF, AND LIGHT EMITTING DIODE DEVICE - An element-connecting board is a lead frame for allowing a light emitting diode element to be connected to one side thereof in a thickness direction. The element-connecting board includes the lead frame which is provided with a plurality of leads disposed with spaces from each other and a first insulating resin portion which is light reflective and fills the spaces. | 2014-11-06 |
20140329347 | METHOD FOR MANUFACTURING LIGHT EMITTING DIODES - An exemplary method for manufacturing a light emitting diode includes following steps: providing a substrate; growing an undoped GaN layer on the substrate, the undoped GaN layer comprising an upper surface away from the substrate and a lower surface contacting the substrate; etching the upper surface of the undoped GaN layer to form a plurality of cavities; growing an Distributed Bragg Reflector layer on the upper surface of the undoped GaN layer; and forming sequentially an N-type GaN layer, an active layer and a P-type GaN layer on the Distributed Bragg Reflector layer. | 2014-11-06 |
20140329348 | METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device includes a semiconductor layer including a first surface, a second surface opposite to the first surface, and a light emitting layer; a p-side electrode provided on the second surface of the semiconductor layer in a region including the light emitting layer; an n-side electrode provided on the second surface of the semiconductor layer in a region not including the light emitting layer; an insulating film being more flexible than the semiconductor layer, the insulating film provided on the second surface and a side surface of the semiconductor layer, and the insulating film having a first opening reaching the p-side electrode and a second opening reaching the n-side electrode; a p-side interconnection layer provided on the insulating film and connected to the p-side electrode; and an n-side interconnection layer provided on the insulating film and connected to the n-side electrode. | 2014-11-06 |
20140329349 | ORGANIC LAYER DEPOSITION APPARATUS, AND METHOD OF MANUFACTURING ORGANIC LIGHT-EMITTING DISPLAY APPARATUS BY USING THE SAME - An organic layer deposition apparatus includes a conveyer unit including a transfer unit, a first conveyer unit, and a second conveyer unit; and a deposition unit including one or more organic layer deposition assemblies for depositing an organic layer on a substrate attached to the transfer unit. Each of the one or more organic layer deposition assemblies includes: a plurality of deposition sources for discharging a deposition material; a deposition source nozzle unit including a plurality of deposition source nozzles; a patterning slit sheet including a plurality of patterning slits; and a plurality of source shutters separated from the plurality of deposition sources, respectively, and blocking a deposition material that is vaporized in each of the plurality of deposition sources. The plurality of source shutters move in different directions, thereby blocking or allowing to pass the deposition material. | 2014-11-06 |
20140329350 | Method for Producing a Light-Emitting Diode - A method is provided for producing a light-emitting diode. In one embodiment, a series of layers is deposited on the silicon surface of a carrier in a direction of growth and a light-emitting diode structure is deposited on the series of layers. The series of layers includes a GaN layer, which is formed with gallium nitride. The series of layers includes a masking layer, which is formed with silicon nitride. The masking layer follows at least part of the GaN layer in the direction of growth. | 2014-11-06 |
20140329351 | FABRICATING A SMALL-SCALE RADIATION DETECTOR - A method for a constructing radiation detector includes fabricating a multi-layer structure upon a wafer, the multi-layer structure comprising a plurality of metal layers, a plurality of sacrificial layers, and a plurality of insulating layers, forming a cavity within the multi-layer structure, filling the cavity with a gas that ionizes in response to nuclear radiation, and sealing the gas within the cavity. | 2014-11-06 |
20140329352 | Photovoltaic Cell and Fabrication Method Thereof - The present structure and method for fabrication thereof provides a photovoltaic cell structure for converting light energy into electrical energy. According to one embodiment, a pillared photovoltaic cell structure comprises an array of pillars that are situated closely to each other to take advantage of both the wave-like properties and the particle-like properties of light to enhance the energy conversion efficiency of the photovoltaic cell. According to one embodiment, a pillared photovoltaic cell structure incorporating self-aligned P/P+ junctions enable holes generated near the top surface of the cell structure to be captured by the self-aligned P/P+ junctions. | 2014-11-06 |
20140329353 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS - A manufacturing method of a semiconductor device includes exposing a wiring layer which is formed of an alloy including two or more types of metals having different standard electrode potentials, on one surface side of a semiconductor substrate and performing a plasma process of allowing plasma generated by a mixture gas of a gas including nitrogen and an inert gas or plasma generated by a gas including nitrogen to irradiate a range which includes an exposed surface of the wiring layer. | 2014-11-06 |
20140329354 | PROCESS FOR IMPRINT PATTERNING MATERIALS IN THIN-FILM DEVICES - The present disclosure provides a method for patterning materials that are or are on top of chemically sensitive organic semiconductors. The method employs imprint lithography and a bilayer resist structure that simultaneously protects lower layers from harmful solvents and allows for cleaner liftoff by producing an undercut geometry to the resist pattern. | 2014-11-06 |
20140329355 | Techniques for Enhancing Performance of Photovoltaic Devices - Techniques for improving energy conversion efficiency in photovoltaic devices are provided. In one aspect, an antimony (Sb)-doped film represented by the formula, Cu | 2014-11-06 |
20140329356 | Curable Acrylate Based Printing Medium - An acrylate-based curable printing medium is disclosed. Acrylates, in the form of monomers, dimers, trimers and oligomers, as well as resins, form an interpenetrating polymer network by crosslinking, which is effected by heat, and optionally peroxide curing agents. Formulations can be tailored to achieve desired properties of the cured polymer including film hardness, burnout properties, and adhesion to glass. Such properties are adjusted by manipulating the relative proportions of the acrylic monomers, oligomers and resins that are used as a ceramic medium or vehicle. | 2014-11-06 |
20140329357 | TELLURIUM COMPOUNDS USEFUL FOR DEPOSITION OF TELLURIUM CONTAINING MATERIALS - Precursors for use in depositing tellurium-containing films on substrates such as wafers or other microelectronic device substrates, as well as associated processes of making and using such precursors, and source packages of such precursors. The precursors are useful for deposition of Ge | 2014-11-06 |
20140329358 | ELECTRONIC DEVICES AND COMPONENTS FOR HIGH EFFICIENCY POWER CIRCUITS - An electronic component includes a III-N transistor and a III-N rectifying device both encased in a single package. A gate electrode of the III-N transistor is electrically connected to a first lead of the single package or to a conductive structural portion of the single package, a drain electrode of the III-N transistor is electrically connected to a second lead of the single package and to a first electrode of the III-N rectifying device, and a second electrode of the III-N rectifying device is electrically connected to a third lead of the single package. | 2014-11-06 |
20140329359 | PROCESS FOR MAKING A SEMICONDUCTOR SYSTEM - Multiple devices, including a first device and a second device, have operational circuitry and opposing first and second surfaces. First and second electrical contacts are formed at the first surface, while a third electrical contact is formed at the second surface opposite the first electrical contact. The first electrical contact is electrically connected to the operational circuitry, and the second electrical contact is electrically connected to the third electrical contact. The first device and the second device are subsequently stacked such that the first surface of the second device is located adjacent the second surface of the first device such that the first electrical contact of the second device is aligned with the third electrical contact of the first device. The first electrical contact of the second device is electrically connected to the third electrical contact of the first device. | 2014-11-06 |
20140329360 | METHOD OF MANUFACTURING LEAD FRAME - There is provided a method of manufacturing a lead frame, the method including: preparing a lead frame raw material; forming openings in the lead frame raw material so that the lead frame material includes: a die pad; a die pad supporting portion supporting the die pad; a rail portion supporting the die pad supporting portion; a lead supporting portion having both ends fixed to the die pad supporting portion; and a plurality of leads having a first end connected to the rail portion and a second end connected to the lead supporting portion; plating the lead frame raw material having the openings with a plating layer; and removing the lead supporting portion. | 2014-11-06 |
20140329361 | Method for Mounting a Semiconductor Chip on a Carrier - A method includes providing a semiconductor chip having a first main surface and a layer of solder material deposited on the first main surface, wherein the layer of solder material has a roughness of at least 1 μm. The semiconductor chip is placed on a carrier with the first main surface of the semiconductor chip facing the carrier. The semiconductor chip is pressed on the carrier with a pressure of at least 1 Newton per mm | 2014-11-06 |
20140329362 | QFN/SON-Compatible Package - A leadless package and method for manufacturing silicon based leadless QFN/SON compatible packages are described. In addition the package allows for hermetic sealing of devices while maintaining electrical and optical access. Micro-vias with feed-through metallization through a silicon structure facilitates a surface mount technology compatible silicon package with bottom SMT pads and top surface device integration. Sloped edges on the SMT side enable solder filleting for post solder inspection. Hermetic seal can be attained for example using anodic bonding of a glass lid or using metal soldering. Metal soldering enables the use of solder bumps to provide electrical connections for the package to the lid with integrated device functionality used for sealing. Hermetically sealed silicon packages eliminates the need for an extra packaging layer required in plastic packages and provides a standard interface for enclosing one or more discrete devices. | 2014-11-06 |
20140329363 | FIBER-CONTAINING RESIN SUBSTRATE, SEALED SUBSTRATE HAVING SEMICONDUCTOR DEVICE MOUNTED THEREON, SEALED WAFER HAVING SEMICONDUCTOR DEVICE FORMED THEREON, A SEMICONDUCTOR APPARATUS, AND METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS - A fiber-containing resin substrate for collectively sealing a semiconductor devices mounting surface of a substrate having the semiconductor devices mounted thereon or a semiconductor devices forming surface of a wafer having semiconductor devices formed thereon, includes: a resin-impregnated fiber base material obtained by impregnating a fiber base material with a thermosetting resin and semi-curing or curing the thermosetting resin; and an uncured resin layer containing an uncured thermosetting resin and formed on one side of the resin-impregnated fiber base material. There can be a fiber-containing resin substrate that enables suppressing warp of a wafer and delamination of semiconductor devices even though a large-diameter wafer or a large-diameter substrate made of a metal and the like is sealed, enables collectively sealing a semiconductor devices mounting surface of the substrate or a semiconductor devices forming surface of the wafer, and has excellent heat resistance or moisture resistance after sealing. | 2014-11-06 |
20140329364 | MANUFACTURING METHOD OF POWER SEMICONDUCTOR - A manufacturing method of a power semiconductor includes steps of providing a first semiconductor substrate and a second semiconductor substrate, forming a metal oxide semiconductor layer on a first surface of the first semiconductor substrate, grinding a second surface of the first semiconductor substrate, forming a N-type buffer layer and a P-type injection layer on a third surface of the second semiconductor substrate through ion implanting, grinding a fourth surface of the second semiconductor substrate, and combining the second surface of the first semiconductor substrate with the third surface of the second semiconductor substrate for forming a third semiconductor substrate. As a result, the present invention achieves the advantages of enhancing the process flexibility and un-limiting the characteristics of the power semiconductor. | 2014-11-06 |
20140329365 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An embodiment is to include a staggered (top gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. The buffer layer having higher carrier concentration than the semiconductor layer is provided intentionally between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed. | 2014-11-06 |
20140329366 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device including: forming a silicon layer on an upper face of a nitride semiconductor layer including a channel layer of a FET; thermally treating the nitride semiconductor layer in the process of forming the silicon layer or after the process of forming the silicon layer; and forming an insulating layer on an upper face of the silicon layer after the process of forming the silicon layer. | 2014-11-06 |
20140329367 | METHODS OF FABRICATING SEMICONDUCTOR DEVICES INCLUDING IMPLANTED REGIONS FOR PROVIDING LOW-RESISTANCE CONTACT TO BURIED LAYERS AND RELATED DEVICES - Methods of fabricating a semiconductor device include forming a first semiconductor layer of a first conductivity type and having a first dopant concentration, and forming a second semiconductor layer on the first semiconductor layer. The second semiconductor layer has a second dopant concentration that is less than the first dopant concentration. Ions are implanted into the second semiconductor layer to form an implanted region of the first conductivity type extending through the second semiconductor layer to contact the first semiconductor layer. A first electrode is formed on the implanted region of the second semiconductor layer, and a second electrode is formed on a non-implanted region of the second semiconductor layer. Related devices are also discussed. | 2014-11-06 |
20140329368 | BIPOLAR TRANSISTOR WITH EMBEDDED EPITAXIAL EXTERNAL BASE REGION AND METHOD OF FORMING THE SAME - The present invention discloses a bipolar transistor with an embedded epitaxial external base region, which is designed to solve the problem of the TED effect with the prior art structures. The bipolar transistor with an embedded epitaxial external base region of the present invention comprises at least a collector region, a base region and an external base region on the collector region, an emitter on the base region, and sidewalls at both sides of the emitter. The external base region is grown through an in-situ doping selective epitaxy process and is embedded in the collector region. A portion of the external base region is located beneath the sidewalls. The present invention discloses a method of forming a bipolar transistor with an embedded epitaxial external base region. The bipolar transistor with an embedded epitaxial external base region of the present invention avoids the TED effect and reduces the resistance of the external base region of the device so that the performance of the device is improved. The method of forming a bipolar transistor with an embedded epitaxial external base region of the present invention achieves the aforesaid bipolar transistor with an embedded epitaxial external base region, and features concise steps, a low cost and simple operations, and the structure obtained has good performance. | 2014-11-06 |
20140329369 | PINCHED CENTER RESISTIVE CHANGE MEMORY CELL - The present invention is a method for forming a vertically oriented element having a narrower area near its center away from either end. The present invention will find applicability in other memory cell structures. The element will have a narrow portion towards its center such that current density will be higher away from the ends of the element. In this way, the heating will occur away from the ends of the storage element. Heating in a phase-change or resistive change element leads to end of life conditions, including the condition whereby contaminants from the end point contacts are enabled to migrate away from the end point and into the storage element thereby contaminating the storage element material and reducing its ability to be programmed, erased and/or read back. By keeping the greatest heating towards the center of the element where it is surrounded by more of the same material and away from the ends of the element where end point contact material can be heated and potentially activated, the lifetime of the element will be increased. | 2014-11-06 |
20140329370 | LAYER TRANSFER OF SILICON ONTO III-NITRIDE MATERIAL FOR HETEROGENOUS INTEGRATION - An integrated silicon and III-N semiconductor device may be formed by growing III-N semiconductor material on a first silicon substrate having a first orientation. A second silicon substrate with a second, different, orientation has a release layer between a silicon device film and a carrier wafer. The silicon device film is attached to the III-N semiconductor material while the silicon device film is connected to the carrier wafer through the release layer. The carrier wafer is subsequently removed from the silicon device film. A first plurality of components is formed in and/or on the silicon device film. A second plurality of components is formed in and/or on III-N semiconductor material in the exposed region. In an alternate process, a dielectric interlayer may be disposed between the silicon device film and the III-N semiconductor material in the integrated silicon and III-N semiconductor device. | 2014-11-06 |
20140329371 | SOI SUBSTRATE, METHOD FOR MANUFACTURING THE SAME, AND SEMICONDUCTOR DEVICE - An SOI substrate having an SOI layer that can be used in practical applications even when a substrate with low upper temperature limit, such as a glass substrate, is used, is provided. A semiconductor device using such an SOI substrate, is provided. In bonding a single-crystal semiconductor layer to a substrate having an insulating surface or an insulating substrate, a silicon oxide film formed using organic silane as a material on one or both surfaces that are to form a bond is used. According to the present invention, a substrate with an upper temperature limit of 700° C. or lower, such as a glass substrate, can be used, and an SOI layer that is strongly bonded to the substrate can be obtained. In other words, a single-crystal semiconductor layer can be formed over a large-area substrate that is longer than one meter on each side. | 2014-11-06 |
20140329372 | METHOD FOR MANUFACTURING SOI WAFER - A method for manufacturing a SOI wafer, including a step of performing a thickness reducing adjustment to a SOI layer of the SOI wafer by carrying out a sacrificial oxidation to the SOI wafer for effecting thermal oxidation to a surface of the SOI layer and removing a formed thermal oxide film, wherein, when the thermal oxidation in the sacrificial oxidation treatment is carried out with the use of a batch processing heat treatment furnace during the rising of a temperature and/or the falling of a temperature, a substantially concentric oxide film thickness distribution is formed on the surface of the SOI layer. The result is a method for manufacturing a SOI wafer that enables manufacturing a SOI wafer that has improved radial film thickness distribution with good productivity by performing the sacrificial oxidation treatment for forming a substantially concentric oxide film and removing the formed thermal oxide film. | 2014-11-06 |
20140329373 | Method of Dicing a Wafer - A method of dicing a semiconductor wafer includes forming a layer stack on a first main surface of a substrate. The layer stack and a portion of the substrate are etched according to a pattern defining an intended dicing location to obtain a trench structure. The substrate is irradiated with a laser beam to locally modify the substrate between a bottom of the trench structure and a second main surface of the substrate opposite to the first main surface. | 2014-11-06 |
20140329374 | METHODS OF FABRICATING QUANTUM WELL FIELD EFFECT TRANSISTORS HAVING MULTIPLE DELTA DOPED LAYERS - Methods of fabricating quantum well field effect transistors are provided. The methods may include forming a first barrier layer including a first delta doped layer on a quantum well layer and forming a second barrier layer including a second delta doped layer selectively on a portion of the first barrier layer in a first region of the substrate. The methods may also include patterning the first and second barrier layers and the quantum well layer to form a first quantum well channel structure in the first region and patterning the first barrier layer and the quantum well layer to form a second quantum well channel structure in a second region. The methods may further include forming a gate insulating layer on the first and second quantum well channel structures of the substrate and forming a gate electrode layer on the gate insulating layer. | 2014-11-06 |
20140329375 | Methods for Depositing Amorphous Silicon - Methods for depositing an amorphous silicon layer on wafers are disclosed. A process wafer, a control wafer, and a dummy wafer may be loaded into a chamber where an amorphous silicon layer may be deposited on the process wafer. Afterwards, the process wafer and the control wafer may be removed from the chamber. The chamber and the dummy wafers are dry cleaned together. The dry cleaned dummy wafers are used in the next run for depositing amorphous silicon layer. The process may be controlled by a computer system issuing a control job comprising a first process job and a second process job, wherein the first process job is to deposit an amorphous silicon layer on the process wafer, and the second process job is to dry clean the chamber and the dummy wafer. | 2014-11-06 |
20140329376 | STRUCTURE AND METHOD OF FORMING METAMORPHIC HETEROEPI MATERIALS AND III-V CHANNEL STRUCTURES ON SI - Embodiments described herein generally relate to a method of fabrication of a device structure comprising Group III-V elements on a substrate. A <111> surface may be formed on a substrate and a Group III-V material may be grown from the <111> surface to form a Group III-V device structure in a trench isolated between a dielectric layer. A final critical dimension of the device structure may be trimmed to achieve a suitably sized node structure. | 2014-11-06 |
20140329377 | SUPPLY SOURCE AND METHOD FOR ENRICHED SELENIUM ION IMPLANTATION - A novel method for ion implanting isotopically enriched selenium containing source material is provided. The source material is selected and enriched in a specific mass isotope of selenium, whereby the enrichment is above natural abundance levels. The inventive method allows reduced gas consumption and reduced waste. The source material is preferably stored and delivered from a sub-atmospheric storage and delivery device to enhance safety and reliability during the selenium ion implantation process. | 2014-11-06 |
20140329378 | GATE ELECTRODE WITH DEPLETION SUPPRESSION AND TUNABLE WORKFUNCTION - Semiconductor device performance is improved via a gate structure having a tunable effective workfunction and reduced gate depletion effects. According to an example embodiment, the design threshold voltage of a semiconductor device is adjusted in a manner that includes providing a gate having a workfunction that enables operation of the semiconductor device at a selected voltage. The gate is formed having two different conductive materials with different electric workfunctions that both significantly contribute to the overall workfunction of the gate. The relative composition, thickness, and arrangement of each of the two conductive materials is selected to attain a gate electrode workfunction that is different than the workfunctions of each of the two layers and that sets the threshold voltage of the semiconductor device. The adjustability of the effective workfunction of the gate electrode can be applied to a variety of semiconductor devices. The ability to reduce gate depletion effects also provides enhanced device current drive. | 2014-11-06 |
20140329379 | PATTERNING METHOD FOR FORMING STAIRCASE STRUCTURE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING THE SAME - A patterning method includes forming a photoresist layer on a processing layer and exposing the photoresist layer using a standing wave/defocusing exposure to produce a photoresist layer having a staircase pattern. | 2014-11-06 |
20140329380 | FORMATION OF SEMICONDUCTOR STRUCTURES WITH VARIABLE GATE LENGTHS - A plurality of doped sacrificial semiconductor material portions of a first width and a plurality of doped sacrificial semiconductor material portions of a second width, which is different from the first width, are provided on a sacrificial gate dielectric material. Exposed portions of the sacrificial dielectric material are removed. A dielectric material is formed adjacent each doped sacrificial semiconductor material portion such that an upper surface of each doped sacrificial semiconductor material portion is exposed. Each doped sacrificial semiconductor material portion is removed providing a first set of gate cavities having the first width and a second set of gate cavities having the second width. Each gate cavity is filled with a gate structure. The gate structures formed in the first set of gate cavities have the first width, while the gate structure formed in the second set of gate cavities have the second width. | 2014-11-06 |
20140329381 | TSV Backside Reveal Structure and Exposing Process - A TSV exposing process is provided, including: performing a mechanical grinding process on the substrate back surface of a substrate with a TSV conductive column, a liner between the substrate and the TSV conductive column; performing a first and a second chemical mechanical polishing process on the grinded substrate back surface; then performing an etching on the substrate back surface, and making the TSV backside reveal more than 10 μm. | 2014-11-06 |
20140329382 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING BUMP - Provided is a method of fabricating a semiconductor device. The method includes forming a photoresist pattern having a side recess on a seed metal layer and forming a plating layer having a hem using a plating process to fill the side recess. | 2014-11-06 |
20140329383 | SEMICONDUCTOR DEVICE WITH EMBEDDED HEAT SPREADING - A semiconductor device includes a semiconductor substrate and a plurality of clock drivers, wherein the plurality of clock drivers comprises substantially all clock drivers of the semiconductor device, and an interconnect region over the semiconductor substrate, wherein the interconnect region comprises a plurality of heat spreaders, wherein at least 25% of the plurality of clock drivers have a corresponding heat spreader of the plurality of heat spreaders. Each corresponding heat spreader of the plurality of heat spreaders covers at least 50% of a transistor within a corresponding clock driver of the plurality of clock drivers and extends across at least 70% of a perimeter of the transistor within the corresponding clock driver. | 2014-11-06 |
20140329384 | INTEGRATED CIRCUIT DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, an integrated circuit device includes a plurality of interconnects and a contact via. The plurality of interconnects are arranged parallel to each other. The contact via is connected to each of the interconnects. A protrusion is formed at a portion of the each of the interconnects connected to the contact via to protrude in a direction of the arrangement. A recess is formed at a portion of the each of the interconnects separated from the portion having the protrusion to recede in the direction of the arrangement. The protrusion formed on one interconnect of two mutually-adjacent interconnects among the plurality of interconnects is opposed to the recess formed in one other interconnect of the two mutually-adjacent interconnects. In the each of the interconnects, the portion having the recess is separated from portions on two sides of the portion having the recess and is separated also from the portion having the protrusion. | 2014-11-06 |
20140329385 | METHOD FOR MANUFACTURING SEMICONDUCTOR THICK METAL STRUCTURE - A method for manufacturing a semiconductor thick metal structure includes a thick metal deposition step, a metal patterning step, and a passivation step. In the thick metal deposition step, a Ti—TiN laminated structure is used as an anti-reflection layer to implement 4 μm metal etching without residue. In the metal patterning step, N | 2014-11-06 |
20140329386 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package includes a semiconductor chip having a front surface and a back surface facing away from the front surface; a through electrode formed in the semiconductor chip and passing through the front surface and the back surface; and a contamination preventing layer formed in the semiconductor chip, the through electrode passing through the contamination preventing layer. | 2014-11-06 |
20140329387 | Sonos Device and Method for Fabricating the Same - An improved semiconductor device is provided whereby the semiconductor device is defined by a layered structure comprising a first dielectric layer, a data storage material disposed on the first dielectric layer, and a second dielectric layer disposed on the data storage material, the layered structured substantially forming the outer layer of the semiconductor device. For example, the semiconductor device may be a SONOS structure having an oxide-nitride-oxide (ONO) film that substantially surrounds the SONOS structure. The invention also provides methods for fabricating the semiconductor device and the SONOS structure of the invention. | 2014-11-06 |
20140329388 | METHODS OF PATTERNING FEATURES HAVING DIFFERING WIDTHS - Disclosed herein are methods of patterning features that have differing widths. In one example, the method includes forming a layer of material above a semiconductor substrate, forming a masking layer above the layer of material, wherein the masking layer is comprised of a first plurality features positioned above a first region of the semiconductor substrate and a second plurality of features positioned above a second region of the semiconductor substrate, wherein the first and second plurality of features have the same pitch spacing and wherein the first and second plurality of features have different widths, and performing at least one etching process on the layer of material through the masking layer. | 2014-11-06 |
20140329389 | BULK NANO-RIBBON AND/OR NANO-POROUS STRUCTURES FOR THERMOELECTRIC DEVICES AND METHODS FOR MAKING THE SAME - Structure including nano-ribbons and method thereof. The structure include multiple nano-ribbons. Each of the multiple nano-ribbons corresponds to a first end and a second end, and the first end and the second end are separated by a first distance of at least 100 μm. Each of the multiple nano-ribbons corresponds to a cross-sectional area associated with a ribbon thickness, and the ribbon thickness ranges from 5 nm to 500 nm. Each of the multiple nano-ribbons is separated from at least another nano-ribbon selected from the multiple nano-ribbons by a second distance ranging from 5 nm to 500 nm. | 2014-11-06 |
20140329390 | PLASMA TREATMENT METHOD AND PLASMA TREATMENT DEVICE - A plasma treatment device includes a dielectric window containing SiO | 2014-11-06 |
20140329391 | CONTINUOUS PLASMA ETCH PROCESS - A method for etching features with a continuous plasma is provided. A first plasma process is provided, comprising providing a flow of a first process gas into a process chamber, maintaining the continuous plasma, and stopping the flow of the first process gas into the process chamber. A transition process is provided, comprising providing a flow of a transition gas into the process chamber, maintaining the continuous plasma, and stopping the flow of the transition gas into the process chamber. A second plasma process is provided, comprising providing a flow of a second process gas into the process chamber, maintaining the continuous plasma, and stopping the second process gas into the process chamber. | 2014-11-06 |
20140329392 | COATINGS FOR RELATIVELY MOVABLE SURFACES - A device has a microelectromechanical system (MEMS) component with at least one surface and a coating disposed on at least a portion of the surface. The coating has a compound of the formula M(CnF2n+1Or), wherein M is a polar head group and wherein n≧2r. The value of n may range from 2 to about 20, and the value of r may range from 1 to about 10. The value of n plus r may range from 3 to about 30, and a ratio of n:r may have a value of about 2:1 to about 20:1. | 2014-11-06 |
20140329393 | Stack connector component in which high-speed signal pins are routed to different side than low-speed signal pins, and circuit board therefor - A stacked connector component includes a housing, connectors at a front opening of the housing and arranged in a stacked formation within one or more columns, and a for and exposed at the connectors. The pins include high-speed pins routed within the housing to a bottom side thereof and low-speed pins routed within the housing to a back side or a top side thereof. A circuit board includes pin pads connectable to the pins and disposed on a substrate. The pin pads include high-speed signal pin pads for the high-speed signal pins. The substrate includes contiguous high-speed areas in which the high-speed signal pin pads for the high-speed pins are located, between which no pin pads are located. | 2014-11-06 |
20140329394 | Connecting Structure and Connecting Method of Flat Circuit Body and Terminal - A portion of a flat conductor of a flat circuit board is exposed from an insulating layer covering at least one of surfaces of the flat conductor. A terminal includes a bottom plate on which the exposed portion of the flat conductor is provided, and crimp claws which are raised at two side edges of the bottom plate so that the exposed portion of the flat conductor is disposed therebetween. A spacer member is provided on the exposed portion of the flat conductor, and is configured to be plastically deformed so as to contact with inner surfaces of the crimp claws when the crimp claws are crimped onto the spacer member, thereby the terminal is crimped to the flat conductor in a state where the exposed portion of the flat conductor is in surface contact with the bottom plate. | 2014-11-06 |
20140329395 | CONNECTORS FOR ELECTRICALLY ACTIVE GRID - A connector for electrical connection to an electrified grid element having first and second conductors disposed on a top portion of the grid element. In one embodiment, the connector comprises a single-piece insulator housing; a fastening means on the insulator housing for attaching the connector to a device; and first and second contacts within the insulator housing, the insulator housing configured to align the first and second contacts with the first and second conductors of the electrified grid element; wherein a base of the insulator housing comprises a recess that corresponds to the shape of the top portion of the grid element such that the housing can be mounted over the top portion of the grid member. | 2014-11-06 |
20140329396 | PIN TERMINAL - A pin terminal (PT) is such that a cap ( | 2014-11-06 |
20140329397 | ELECTRICAL MODULAR TERMINAL AND MODULAR TERMINAL BLOCK - An electrical series terminal having a terminal housing, conductor connector elements, and current bars, the current bars each having a connector section and a first contact section, the connector sections being assigned to a conductor connector element and the first contact sections together forming a resilient contact region to receive the plug of the test or power plug. A switchable transverse bridge is producible by each current bar having a second contact section, two further current bar pieces being arranged in the terminal housing, and a recess being formed in a current bar piece for insertion of a branch of a jumper. A current bar piece is assigned to a respective current bar so that the second contact section of a current bar is connected to the assigned current bar piece when no plug is inserted and is spaced from the assigned current bar piece when a plug is inserted. | 2014-11-06 |
20140329398 | CONTACT, CONNECTOR, AND CONNECTING DEVICE - A distance between first contact portions is set smaller than a thickness of a first connection object in the state where neither of the first connection object and a second connection object is inserted into a contact. A distance between second contact portions is set greater than a thickness of the second connection object in the state where neither of the first connection object and the second connection object is inserted into the contact. When the first connection object is inserted between the first contact portions, a pair of conductive portions are relatively moved to shorten the distance between the second contact portions so that the second connection object is held between the second contact portions. | 2014-11-06 |
20140329399 | CONNECTOR AND METHOD OF FILLING POTTING MATERIAL OF CONNECTOR - A connector ( | 2014-11-06 |
20140329400 | LOCK DEVICE - A lock device that restricts removal of an engaging member from an engaged member includes a cover attachable to the engaging member. The cover is moved between a position covering an operation portion and a position exposing the operation portion when external force is applied to the cover. A holding unit holds the cover at the position covering the operation portion. An authentication portion releases the cover from the holding unit when authentication is accomplished. | 2014-11-06 |
20140329401 | ELECTRICAL CONNECTOR ASSEMBLY FOR AN ELECTRONIC MODULE - An electrical connector assembly for an electronic module includes a plug element having a body including at least one terminal receiving section. The at least one terminal receiving section includes at least one locking tab element. At least one rigid bus bar terminal is mounted in the at least one terminal receiving section. The at least one bus bar terminal extends from a first end to a second end through a substantially rigid intermediate portion. The first end includes a locking tab member inter-engaging with the locking tab element and the second end includes a module connector member. | 2014-11-06 |
20140329402 | SECURING MEMBER FOR A CONNECTOR - A securing member adapted for securely connecting a male connector member and a female connector member of a connector of IEC60320 standard. The securing member includes a main body including an inner wall, an outer wall and an end wall interconnecting the inner and outer walls. The inner, outer and end walls cooperatively define a receiving space adapted for receiving fittingly and separably at least part of an open end portion of a surrounding wall of the male connector member, and abutting respectively and separably against inner, outer and distal surfaces of the open end portion. The main body is adapted to engage an insertion groove of the female connector member fittingly and removably. | 2014-11-06 |
20140329403 | ELECTRICAL SOCKET HAVING IMPROVED CAM - An electrical socket used for an electronic package with a plurality of pins, includes a base defining a number of passageways in a vertical direction. A number of contacts are received in the passageways. A cover is slidably mounted upon the base and defines a plurality of holes corresponding to the passageways. A cam is used for driving the cover horizontally moved along the base between an open position and a closed position. Wherein, the pins moves with regard to the contact in a linear return path when the electrical socket moved from the open position to the closed position or from the closed position to the open position. | 2014-11-06 |
20140329404 | HOLDING DEVICE USED FOR ELECTRICAL CONNECTOR - A holding device for an electrical connector, includes a frame with an opening defined on a center thereof A first locking portion is disposed on the frame and extends into the opening. A second locking portion has a main body with an elastic arm. The main body defines a fixed end fixed to the frame and an active end rotating around the fixed end. The second locking portion has an open position that the active end can move freely and a closed position that the active end locks to the frame while the elastic arm extends into the opening | 2014-11-06 |
20140329405 | THERMAL MANAGEMENT STRUCTURES FOR OPTOELECTRONIC SYSTEMS - An example embodiment includes a thermal management system for an active cable connector. The system includes a shell and a back plate. The shell defines a cavity and includes multiple heat-transfer areas on an internal shell surface. A first heat-transfer area is positioned with respect to a first heat-generating component to absorb a first portion of thermal energy generated by the first heat-generating component. The back plate is positioned with respect to the first heat-generating component to absorb a second portion of the thermal energy generated by the first heat-generating component. The back plate is further positioned proximate to a second heat-transfer area to transfer the second portion of the thermal energy to the shell. | 2014-11-06 |
20140329406 | COVER FOR CABLE CONNECTORS - A cover for a cable connector includes, in one embodiment, a unitary cover body extending along an axis. The cover defines a cavity and has a plurality of regions. The regions have different diameters for receiving a cable connector and establishing one or more seals. | 2014-11-06 |
20140329407 | WALL MOUNTING APPARATUS - A wall mounting apparatus includes a container defining a mounting hole therein, a lock device received in the container, and a connector engaging with the container and the lock device to assemble the container on a determined position stably. The lock device includes a driver, an electrical connector electrically connecting the driver, and an engaging plate driven by the driver. A recess is defined in the engaging plate. One end of the connector is mounted on the determined position, and the other end thereof extends through the mounting hole and supports the container. The electrical connector is turned off to make the driver drive the engaging plate moving towards the connector to make the connector insert in the recess of the engaging plate and be clasped by the engaging plate. | 2014-11-06 |
20140329408 | LOW CROSSTALK ELECTRICAL CONNECTOR - An electrical connector includes contact units and housing units for retaining the contact units. The contact unit includes an insulating body and a plurality of contacts retained therein. The housing unit includes a shielding member defining an upper end and a lower end opposite to each other, an insulating cover seated on the upper end of the shielding member, and an insulating base seated on the lower end of the shielding member. A cavity is defined between the insulating cover and the insulating base for decreasing the plastic content so as to reduce the crosstalk. | 2014-11-06 |
20140329409 | ELECTRONIC DEVICE AND SOCKET CONNECTOR USED IN ELECTRONIC DEVICE - An electronic device and a socket connector used in the electronic device are presented. The socket connector comprises a housing and a flexible sheet-shaped conductor. The housing comprises a housing body. The flexible sheet-shaped conductor is fixed on the housing body and electrically connected to the housing body, wherein at least a portion of the flexible sheet-shaped conductor protrudes forward from a front end of the housing body so that the flexible sheet-shaped conductor is electrically connected to a casing of an electronic device when the socket connector is mounted in the electronic device. | 2014-11-06 |
20140329410 | SHIELD CONNECTOR DEVICE - A shield connector is provided capable of reducing the number of components and assembly processes while ensuring shielding characteristics and movability. First and second connectors | 2014-11-06 |
20140329411 | INTERFACE TERMINATING DEVICE - An interface terminating device for an interface port includes, in one embodiment, a resistor having first and second conductive leads and a resistive element between the first and second leads. The interface terminating device includes a resistor holder and resistor engager which cooperate together to establish electrical contact with an interface port. | 2014-11-06 |
20140329412 | ELECTRICAL CONNECTOR - An electrical connector includes a casing, touch unit, processing module, light source unit, and connection unit. The casing has a receiving portion for receiving the processing module and the light source unit. The touch unit is disposed above the casing and adapted to be touched by a user to thereby generate a triggering signal. The processing module receives the triggering signal and outputs a current. The light source unit and the processing module are connected. The current drives the light source unit, such that the light source unit emits a light beam to be conveyed to the electronic device by the casing and the touch unit. The connection unit is connected to an electronic device for receiving a current and data from the electronic device. The electrical connector enables the electronic device to be illuminated, such that a user can connect the electrical connector to the electronic device easily. | 2014-11-06 |
20140329413 | TERMINAL FIXATION STRUCTURE AND POWER SUPPLY DEVICE USING THE SAME - A terminal fixation structure includes a terminal fixing portion including a terminal housing chamber, a terminal including a positioning recessed portion and housed in the terminal housing chamber, and a positioning rib provided in a center of the terminal fixing portion to protrude into the terminal housing chamber and fitted into the positioning recessed portion. | 2014-11-06 |
20140329414 | MATING CONTACTS FOR HIGH SPEED ELECTRICAL CONNECTORS - An electrical interconnection system with high speed, high density electrical connectors. One of the connectors includes a mating contact portion that has multiple contact surface. The mating contact portion has multiple segments, each with a contact surface, such that multiple points of contact to a complementary mating contact portion in a mating connector are provided for mechanical robustness. Such a mating contact may have parallel elongated members on which the mating surface are positioned, providing for the possibility of more than two contact surface per mating contact portion. The mating contact surfaces may be positioned on the elongated members such that the points of contact are at different distances from the distal end of the mating contact portion. | 2014-11-06 |
20140329415 | ELECTRICAL CONNECTOR AND ASSEMBLY THEREOF - An electrical connector for connecting a plurality of cables with a PCB comprises an insulating housing and a plurality of first and second contacts received therein. The insulating housing comprises a first mounting surface and a second mounting surface parallel to each other and a tongue portion extending downwardly in an up-to-down direction. The first mounting surface is lower than the second mounting surface in the up-to-down direction forming a stepped surface. The tongue portion extends far away from the stepped surface and comprises opposite periphery surfaces. The first contact comprises a first connecting portion on the first mounting surface and a first contacting portion extending along one periphery surface of the tongue portion while the second contact comprises a second connecting portion on the second mounting surface and a second contacting portion extending along the other periphery surface of the tongue portion. | 2014-11-06 |
20140329416 | CONNECTORS FOR ELECTRONIC DEVICES - A dual orientation connector having a connector tab with first and second major opposing sides and a plurality of electrical contacts carried by the connector tab. The plurality of contacts includes a first set of external contacts formed at the first major side and a second set of external contacts formed at the second major side. The first plurality of contacts are symmetrically spaced with the second plurality of contacts and the connector tab is shaped to have 180 degree symmetry so that it can be inserted and operatively coupled to a corresponding receptacle connector in either of two insertion orientations. | 2014-11-06 |
20140329417 | TERMINAL BLOCK - A terminal block for electrically connecting a plurality of first wires connected to an electric motor and a plurality of second wires connected to a power conversion device for supplying drive power of the electric motor includes a case, a plurality of terminals housed in the case and configured to connect the plurality of first wires and the plurality of second wires to each other, a partition wall provided between the plurality of terminals to electrically isolate the plurality of terminals from each other, and plate-like members provided between the partition wall and the terminals and made of a material with a higher elasticity than the case and the partition wall. | 2014-11-06 |
20140329418 | COMPOSITION FOR PRODUCTION OF CONTACT, CONTACT USING SAME, AND PROCESS FOR PRODUCTION OF CONTACT - A composition for making a contact includes a nickel-cobalt alloy containing 1% by weight or more to less than 20% by weight of cobalt, and 0.002 part by weight or more to 0.1 part by weight or less of sulfur with respect to 100 parts by weight of the nickel-cobalt alloy. The composition has an average particle size of 0.07 μm or larger to 0.35 μm or smaller. | 2014-11-06 |
20140329419 | Sleeve Contact for an Electrical Zero-Force Plug-Type Connector - A sleeve contact includes a base body, a clamping sleeve, and a spring. The base body includes a receiving region. The clamping sleeve displaceable against the base body. The spring has first and second S-curve sections and is mounted at one end to the base body to thereby form a lever having a short lever arm from the end to the first S-curve section and a long lever arm from the end to the second S-curve section. The clamping sleeve acts on the spring as the contact sleeve displaces to produce a contact force towards the receiving region such that the long lever arm is pressed by the clamping sleeve towards the receiving region to thereby cause the short lever arm to bear against a plug contact inserted into the receiving region. | 2014-11-06 |
20140329420 | GROUNDING AND BONDING BRACKET - An improved grounding and bonding bracket-type electrical connector is described with improved properties for directionally orienting grounding conductors. The electrical connector has a body with a first and a second clamp area. The second clamp area may be partially formed by a second body member. A frame substrate is connected in the first clamp area, while a grounding conductor is connected in the second clamp area. The grounding conductor may be connected such that the path of the conductor runs parallel, at 45 degrees, or perpendicular as compared to the mounting line of the frame substrate. | 2014-11-06 |
20140329421 | CONNECTING MEMBER - A connecting member for the electrically conductive connection of two components, having a (first) conductor which comprises a tubular shell which has at least one opening to reduce axial stiffness. | 2014-11-06 |
20140329422 | OUTBOARD MOTOR CONTROL SYSTEM - A plurality of outboard motors are mounted to a stern of a watercraft, and configured to be steered independently. A target steering angle setting section is configured to set a target steering angle for each of the outboard motors. Actuators are configured to steer the outboard motors such that the steering angle of each of the outboard motors is equal or substantially equal to a target steering angle. An actual steering angle detecting section is configured to detect an actual steering angle of each of the outboard motors. A control section is programmed and configured to control the steering operation of the outboard motors such that, when a steering angle difference defining a difference between the actual steering angles of adjacently arranged outboard motors becomes equal to or larger than a prescribed value, an increase of the steering angle difference is prevented. | 2014-11-06 |
20140329423 | BUOYANT ICE TRANSPORT VEHICLE - A collapsible, inexpensive and lightweight vehicle powered by an engine for movement over frozen bodies of water. In one embodiment, an internal combustion engine, a kayak and a drive system assembly comprising detachable studded wheels is detachably connected to a collapsible chassis. The vehicle provides transport across frozen bodies of water and the kayak provides buoyancy sufficient to support the vehicle and a passenger should the ice collapse underneath the vehicle. The vehicle thus provides fast, convenient and safe transport across frozen bodies of water. | 2014-11-06 |
20140329424 | WATER SLED APPARATUS - A towed water sled apparatus is disclosed. The towed water sled apparatus is designed to provide lift to an overturned water sled apparatus thereby preventing the overturned water sled apparatus from diving below the water surface. The towing line may be above the water surface while pulling the overturned water sled apparatus along the water surface. The nose radius may transition to the lift section to provide lift to the overturned water sled apparatus and prevent the overturned water sled apparatus from sinking into the water surface. | 2014-11-06 |
20140329425 | COLLAPSIBLE FLOTATION DEVICE - A collapsible flotation device is provided that uses a coilable spring coupled to a panel to collapse the device when the spring is coiled, and to expand the device when the spring is uncoiled configuration. The spring can be contained within a sleeve along the outer portion of the panel. A support member that traverses the panel is provided. An inflatable bladder disposed about a part of the outer portion of the panel and coupled to the support member buoyantly supports a body weight of a user. The combination of the inflatable bladder and the support member provide support for a user in a seated position on the panel. Many configurations are disclosed, including a multi-user collapsible flotation device, multiple connected single-user flotation devices, and so forth. A back support member and a headrest, both of which can be inflatable, provide additional support for a user to maintain a seated position on the panel. A foot support member is provided for the comfort of the user. | 2014-11-06 |
20140329426 | GLITTER FILM BACKING FOR ADHESIVE TAPES AND METHODS OF MAKING THE SAME - Film-based articles useful, for example, as the backing of an adhesive tape. The film-based article includes a film layer and a plurality of glitter particles. The glitter particles are disposed within the film layer and each has a melting point of not less than 135° C. In some embodiments, the top and bottom film layers are additionally provided along opposing major surfaces of the film layer, with the film layers each comprising a polyolefin-based resin. The articles are formed by a blown film extrusion process, and some or all of the glitter particles can have an elevated particle size, for example not less than 130 μm, alternatively not less than 240 μm. | 2014-11-06 |
20140329427 | INFRARED WELDING PROCESS FOR BONDING PORTIONS OF A VEHICLE INTERIOR ASSEMBLY - A method of manufacturing a vehicle interior assembly. The method includes attaching a scrim to a polyurethane substrate. The method also includes disposing a polypropylene material directly on the scrim. The method includes applying infrared energy to the polypropylene material to bond the polypropylene material to the scrim. | 2014-11-06 |
20140329428 | DISSOLVABLE FIBROUS WEB STRUCTURE ARTICLE COMPRISING ACTIVE AGENTS - The personal care compositions of the present invention are in the form of an Article comprising a dissolvable fibrous web structure. The fibers of the dissolvable fibrous web structure comprise a surfactant; a water soluble polymeric structurant; and a plasticizer. Additionally the ratio of the water soluble water soluble polymeric structurant to the active agent in the fiber is 3.5 or less. | 2014-11-06 |
20140329429 | FIBER REINFORCED STRUCTURAL ELEMENT - A fiber reinforced structural element comprising a thermoplastic fiber reinforced member, a non-thermoplastic fiber reinforced member, and a multi-layer woven tie layer. The thermoplastic fiber reinforced member contains at least one layer of thermoplastic fibers and the non-thermoplastic fiber reinforced member contains at least one layer of non-thermoplastic fibers. The multi-layer woven tie layer contains at least a first woven ply and a second woven ply, where the woven plies are integrated through combined portions formed by interlacing warps or wefts of adjacent woven plies. The multi-layer woven tie layer is oriented such that the upper surface of the multi-layer woven tie layer which is predominately thermoplastic fibers is adjacent the thermoplastic fiber reinforced member and the lower surface of the multi-layer woven tie layer which is predominately non-thermoplastic fibers is adjacent the non-thermoplastic fiber reinforced member. | 2014-11-06 |
20140329430 | Low Defect Nanotube Application Solutions and Fabrics and Methods for Making Same - The present disclosure provides methods for removing defects nanotube application solutions and providing low defect, highly uniform nanotube fabrics. In one aspect, a degassing process is performed on a suspension of nanotubes to remove air bubbles present in the solution. In another aspect, a continuous flow centrifugation (CFC) process is used to remove small scale defects from the solution. In another aspect, a depth filter is used to remove large scale defects from the solution. According to the present disclosure, these three methods can be used alone or combined to realize a low defect nanotube application solutions and fabrics. | 2014-11-06 |