45th week of 2019 patent applcation highlights part 57 |
Patent application number | Title | Published |
20190341259 | SUBSTRATE TREATING APPARATUS AND SUBSTRATE TREATING METHOD - Disclosed are a substrate treating apparatus and a substrate treating method. The substrate treating apparatus includes a chamber providing an interior space for treating a substrate, a support unit provided in the chamber and configured to support the substrate, a first ejection unit having a first nozzle configured to supply a first cleaning medium in an aerosol state to the substrate supported by the support unit, and a second ejection unit having a second nozzle configured to supply a second cleaning medium to the substrate supported by the support unit. | 2019-11-07 |
20190341260 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - To restrain a side portion of a trench from being damaged by ion implantation. A method for manufacturing a semiconductor device comprises a stacking process, an ion implantation process, a heat treatment process, a groove forming process, and a first electrode forming process. In the stacking process, a p-type semiconductor layer is stacked on a first n-type semiconductor layer. In the ion implantation process, an n-type impurity or a p-type impurity is ion-implanted into a position on a surface of the p-type semiconductor layer. The position is away from a position where a groove is to be formed. In the heat treatment process, heat treatment is performed to activate the ion-implanted impurity so as to form an implanted region and to diffuse a p-type impurity in the p-type semiconductor layer into the first n-type semiconductor layer located below the implanted region so as to form a p-type impurity diffused region. In the groove forming process, the groove that penetrates the p-type semiconductor layer and has a bottom portion located in the first n-type semiconductor layer is formed. In the first electrode forming process, the first electrode is formed on an insulation film on a surface of the groove. | 2019-11-07 |
20190341261 | Implanted Dopant Activation for Wide Bandgap Semiconductor Electronics - An enhanced symmetric multicycle rapid thermal annealing process for removing defects and activating implanted dopant impurities in a III-nitride semiconductor sample. A sample is placed in an enclosure and heated to a temperature T | 2019-11-07 |
20190341262 | METHOD FOR ELIMINATING DISLOCATIONS IN ACTIVE AREA AS WELL AS SEMICONDUCTOR DEVICE - A method for eliminating dislocations in an active area and a semiconductor device are disclosed. The method includes: providing a substrate containing the active area; forming source and drain regions in the active area through implanting arsenic therein by a low-energy implantation process under conditions including an implantation energy of 3 kV-30 kV; and performing an annealing process. In the method and semiconductor device of the present invention, the source and drain regions are formed in the active area by low-energy implantation of arsenic. In this way, by optimizing implantation condition of the source and drain, less lattice mismatch in the active area will occurred. Such effective inhibition of lattice dislocations can reduce the occurrence of leakage current. Further, with the recovery by the annealing process, dislocations in the active area can be further reduced, allowing improved performance of the final product. | 2019-11-07 |
20190341263 | Self-Aligned Insulated Film for High-K Metal Gate Device - A method forming a gate dielectric over a substrate, and forming a metal gate structure over the semiconductor substrate and the gate dielectric. The metal gate structure includes a first metal material. The method further includes forming a seal on sidewalls of the metal gate structure. The method further includes forming a dielectric film on the metal gate structure, the dielectric film including a first metal oxynitride comprising the first metal material and directly on the metal gate structure without extending over the seal formed on sidewalls of the metal gate structure. | 2019-11-07 |
20190341264 | METHODS, APPARATUSES AND SYSTEMS FOR SUBSTRATE PROCESSING FOR LOWERING CONTACT RESISTANCE - Methods, apparatuses, and systems for substrate processing for lowering contact resistance in at least contact pads of a semiconductor device are provided herein. In some embodiments, a method of substrate processing for lowering contact resistance of contact pads includes: circulating a cooling fluid in at least one channel of a pedestal; and exposing a backside of the substrate located on the pedestal to a cooling gas to cool a substrate located on the pedestal to a temperature of less than 70 degrees Celsius. In some embodiments in accordance with the present principles, the method can further include distributing a hydrogen gas or hydrogen gas combination over the substrate. | 2019-11-07 |
20190341265 | MASK AND FABRICATION METHOD THEREOF - A mask and a fabrication method for the mask are provided. An exemplary mask includes a substrate, including a first surface, a second surface opposite to the first surface, and a plurality of openings passing through the substrate. A mask pattern layer is disposed on the first surface of the substrate and includes a pattern region and a shield region adjacent to the pattern region. The pattern region contains at least one through-hole passing through the mask pattern layer, and the pattern region is exposed by and corresponds to one opening of the plurality of openings. A protection layer is disposed on the shield region of the mask pattern layer facing away from the substrate. A first sacrificial layer is disposed between the mask pattern layer and the protection layer. | 2019-11-07 |
20190341266 | Integrated Structures, Capacitors and Methods of Forming Capacitors - Some embodiments include an integrated structure having a semiconductor base and an insulative frame over the semiconductor base. The insulative frame has vertically-spaced sheets of first insulative material, and pillars of second insulative material between the vertically-spaced sheets. The first and second insulative materials are different from one another. Conductive plates are between the vertically-spaced sheets and are directly against the insulative pillars. Some embodiments include capacitors, and some embodiments include methods of forming capacitors. | 2019-11-07 |
20190341267 | METHOD FOR REDUCING DEFECTS OF ELECTRONIC COMPONENTS BY A SUPERCRITICAL FLUID - A method for reducing defects of an electronic component using a supercritical fluid includes recrystallizing and rearranging grains in the electronic component by introducing the supercritical fluid doped with H | 2019-11-07 |
20190341268 | Methods Of Increasing Selectivity For Selective Etch Processes - Processing methods comprising etching a metal nitride layer with an etchant. The etchant can be, for example, WCl | 2019-11-07 |
20190341269 | STIFFENER PACKAGE AND METHOD OF FABRICATING STIFFENER PACKAGE - A wafer level fan out package includes a semiconductor die having a first surface, a second surface, and a third surface. A stiffener is disposed on the third surface of the semiconductor die. A conductive via passes through the stiffener. First and second electrically conductive patterns electrically connected to the conductive via are disposed on the first and second surfaces of the semiconductor die and stiffener. Solder balls are electrically connected to the first or second electrically conductive patterns. | 2019-11-07 |
20190341270 | Semiconductor Device Assembly with Pillar Array - A semiconductor device assembly and method of forming a semiconductor device assembly that includes a first substrate, a second substrate disposed over the first substrate, at least one interconnect between the substrates, and at least one pillar extending from the bottom surface of the first substrate. The pillar is electrically connected to the interconnect and is located adjacent to a side of the first substrate. The pillar is formed by filling a via through the substrate with a conductive material. The first substrate may include an array of pillars extending from the bottom surface adjacent to a side of the substrate that are formed from a plurality of filled vias. The substrate may include a test pad located on the bottom surface or located on the top surface. The pillars may include a removable coating enabling the pillars to be probed without damaging the inner conductive portion of the pillar. | 2019-11-07 |
20190341271 | LOW COST PACKAGE WARPAGE SOLUTION - Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer. | 2019-11-07 |
20190341272 | SUBSTRATE PROCESSING APPARATUS, SUBSTRATE PROCESSING SYSTEM, AND SUBSTRATE PROCESSING METHOD - A substrate processing apparatus according to the present disclosure includes: a substrate processing unit; a partition wall; and a liquid supply source. The substrate processing unit includes a substrate holder and performs a liquid processing on a substrate. The partition wall serves as a partition wall between a first space from a carry-in/out port through which the substrate is carried in/out to the substrate processing unit, and a second space other than the first space. The liquid supply source is provided in the second space and supplies a processing liquid to the substrate. | 2019-11-07 |
20190341273 | CIRCULATING EFEM - A circulating EFEM includes an introduction port for introducing a gas, a housing for circulating the introduced gas, and a discharge port for discharging the gas from the housing into a discharge pipe. The discharge port includes a box and a damper. The box is disposed to surround a discharge opening formed on the housing and connected to the discharge pipe. The damper is disposed inside the box to close and open the discharge port and adjusts a discharge amount of the gas via the discharge opening by at least partially moving in response to a differential pressure between the housing and the box. | 2019-11-07 |
20190341274 | APPARATUS AND METHOD FOR PROCESSING SUBSTRATE - The inventive concept relates to an apparatus and method for forming a film on a substrate by spin coating. The apparatus includes liquid dispensing units that dispense processing liquids to form liquid films on the first and second substrates, respectively, air-flow supply units that form downward air flows in the first and second spaces, respectively, and a controller that controls the liquid dispensing units and the air-flow supply units. Each of the liquid dispensing units includes a pre-treatment nozzle that dispenses a pre-treatment liquid and a coating solution nozzle that dispenses a coating solution onto a corresponding one of the first and second substrates. The controller controls the liquid dispensing units to dispense the pre-treatment liquids and thereafter the coating solutions onto the first and second substrates and adjusts supply states of the downward air flows according to amounts of the pre-treatment liquids dispensed. | 2019-11-07 |
20190341275 | EDGE RING FOCUSED DEPOSITION DURING A CLEANING PROCESS OF A PROCESSING CHAMBER - A method for performing a cleaning process in a processing chamber includes, without a substrate arranged on a substrate support of the processing chamber, supplying reactant gases in a side gas flow via side tuning holes of a gas distribution device to effect deposition of a coating on an edge ring of the substrate support. The side gas flow targets an outer region of the processing chamber above the edge ring, and the reactant gases are supplied at a first flow rate. The method further includes, while supplying the reactant gases via the side tuning holes, supplying inert gases in a center gas flow via center holes of the gas distribution device. The inert gases are supplied at a second flow rate that is greater than the first flow rate. | 2019-11-07 |
20190341276 | INTEGRATED SEMICONDUCTOR PART CLEANING SYSTEM - Embodiments described herein relate to chamber component cleaning systems and methods for cleaning a chamber component. The chamber component cleaning system includes a spray station, at least a first cleaning station, a dry station, a component transfer mechanism, and one or more enclosures that enclose the spray station, at least the first cleaning station, the dry station, and the component transfer mechanism. The spray station has a holder to position a chamber component in a path of a flow of a cleaning spray and a movable nozzle to provide the flow of the cleaning spray at a first pressure in a path of portions of the chamber component. The first cleaning station has a push mechanism to force a cleaning fluid through features and/or holes of the chamber component and at least one movable transducer to provide ultrasonic energy to the portions of the chamber component. | 2019-11-07 |
20190341277 | DISPLAY DEVICE MANUFACTURING APPARATUS AND METHOD - Provided is a display device manufacturing apparatus and a manufacturing method of a display device. The display device manufacturing apparatus includes: a chamber; a supporter arranged in the chamber and supporting a substrate; an electrode arranged in the chamber so as to face the supporter; a gas supply arranged in the chamber and configured to supply process gas into the chamber; a first baffle arranged at a rim of the supporter and having at least one first through hole; and a second baffle arranged between the first baffle and the chamber and covering the at least one first through hole in a plan view to alter a path of by-products discharged from the chamber. | 2019-11-07 |
20190341278 | SUBSTRATE PROCESSING SYSTEM - A substrate processing system includes: first and second process tubes spaced apart from each other in a first axial direction to provide process spaces independent from each other; a substrate boat on which a plurality of substrates are multiply stacked and which is provided to each of process spaces of the first and second process tubes; and first and second boat elevation units provided to the first and second process tubes, respectively, to elevate the substrate boat, wherein each of the first and second boat elevation units includes an elevation shaft member disposed in a space between the first and second process tubes. | 2019-11-07 |
20190341279 | CERAMIC HEATER - Disclosed is a ceramic heater, which includes: a disc-shaped ceramic substrate with top and bottom surfaces; and a planar electrode and first and second heating resistors embedded in the ceramic substrate in this order from top to bottom. In top view, the first heating resistor has: a planer first resistive portion arranged inside a first imaginary circle defined by an outermost circumferential contour of the planer electrode; a linear or strip-shaped second resistive portion arranged outward of the first resistive portion in a radial direction of the ceramic substrate and extending along a circumferential direction of the ceramic substrate; and a connecting portion connecting the first and second resistive portions to each other; and the second heating resistor is arranged inside a second imaginary circle defined by an innermost circumferential contour of the second resistive portion. | 2019-11-07 |
20190341280 | WAFFER PEDESTAL WITH HEATING MECHANISM AND REACTION CHAMBER INCLUDING THE SAME - The present invention discloses a wafer pedestal including a plate, a heating assembly and a heat insulation assembly embedded in the plate at a radial position that divides the plate into a first heating zone and a second heating zone. | 2019-11-07 |
20190341281 | HEAT TREATMENT APPARATUS - A heat treatment apparatus includes: a processing container extended in a vertical direction; and a heater provided to surround the processing container. The heater includes: a first insulator of a cylindrical shape that has a ceiling surface and an opening at a lower end; a heat generator provided along a circumferential direction on an inner circumferential side of the first insulating member; and a second insulator arranged along the circumferential direction of the first insulating member at a position adjacent to the heat generating elements. | 2019-11-07 |
20190341282 | BUFFER CHAMBER UNIT FOR WAFER PROCESSING EQUIPMENT - The present invention relates to a buffer chamber unit for wafer processing equipment. | 2019-11-07 |
20190341283 | SUBSTRATE PROCESSING APPARATUS - Provided is a substrate processing apparatus including a load-lock chamber; a transfer chamber connected to the load-lock chamber; and one or more processing chambers connected to the transfer chamber. The transfer chamber includes a transfer arm that transfers a substrate between the load-lock chamber and the one or more processing chambers, the load-lock chamber includes a plurality of load-lock stations for accommodating a plurality of substrates as a matrix of m×n. According to the substrate processing apparatus, a time taken to transfer substrates may be reduced greatly, and productivity may be improved. | 2019-11-07 |
20190341284 | TEMPERATURE MONITORING APPARATUS, HEAT TREATMENT APPARATUS, AND TEMPERATURE MONITORING METHOD - A temperature monitoring apparatus includes: a calculator configured to calculate a temperature monitoring waveform by a first-order lag function based on an elapsed time from a start of a temperature change from a first temperature to a second temperature, and a time constant calculated based on a locus of the temperature change; and a monitor configured to monitor a temperature changing from the first temperature to the second temperature based on the temperature monitoring waveform calculated by the calculator. | 2019-11-07 |
20190341285 | SUBSTRATE DEFORMATION DETECTION AND CORRECTION - A method and apparatus for detecting and correcting incoming substrate deformation is disclosed. Substrates are positioned in a first process chamber, where the presence and type of substrate bow is detected. Based upon the detection of substrate bow, and a determination of whether the substrate has a compressive bow or a tensile bow, a substrate processing program is selected for execution. The substrate processing program can be executed in the first process chamber or in a second process chamber to correct or alleviate the bow prior to or during further processing of the substrate. | 2019-11-07 |
20190341286 | BATCH SUBSTRATE SUPPORT WITH WARPED SUBSTRATE CAPABILITY - Methods and apparatus for supporting substrates are provided herein. In some embodiments, a substrate support for supporting a plurality of substrates includes: a plurality of substrate support elements having a ring shape configured to support a plurality of substrates in a vertically spaced apart relation; and a plurality of substrate lift elements interfacing with the plurality of substrate support elements and configured to simultaneously selectively raise or lower substrates off of or onto respective substrate support elements. | 2019-11-07 |
20190341287 | WAFER-LIKE SUBSTRATE PROCESSING METHOD AND APPARATUS - The present invention refers to a method for processing a wafer like substrate using a touching gripper and a touchless gripper. Furthermore, the present invention refers to an apparatus for processing a wafer-like substrate containing a touching gripper and a touchless gripper. Additionally, the present invention refers to the use of an inventive apparatus to process a wafer-like substrate. | 2019-11-07 |
20190341288 | LOWER ELECTRODE WAFER CHUCK OF AN ETCHING MACHINE - A lower electrode wafer chuck of an etching machine comprises an upper stage, configured for placing a wafer, coupled to a lower stage. The upper stage includes a lower surface that includes a cooling liquid circulation groove, and an upper surface that includes a cooling gas distribution groove and a cooling gas outlet hole. The lower stage includes a cooling liquid inlet, a cooling liquid outlet and a cooling gas inlet hole, the cooling liquid inlet and the cooling liquid outlet both being communicated with the cooling liquid circulation groove. To cool a lower electrode, cooling liquid enters the cooling liquid circulation groove from the cooling liquid inlet, and then flows out the cooling liquid outlet. To cool a wafer on the upper stage, cooling gas enters from the cooling gas inlet hole, passes through the cooling gas outlet hole, and diffuses into the cooling gas distribution groove. | 2019-11-07 |
20190341289 | MULTI-ZONE GASKET FOR SUBSTRATE SUPPORT ASSEMBLY - A gasket for a substrate support assembly may have a top surface having a surface area and a plurality of zones that together define the surface area of the top surface. The plurality of zones may comprise at least a) a first zone comprising a first stack of gasket layers, the first zone having a first average thermal conductivity in a first direction, and b) a second zone comprising one or more gasket layers, the second zone having a second average thermal conductivity in the first direction. | 2019-11-07 |
20190341290 | WAFER CHUCK ASSEMBLY - The present disclosure generally relates to chuck technology for supporting semiconductor wafers during processing. In one example, a wafer chuck assembly comprises a chuck hub and a centering hub disposed within the chuck hub. An engagement device is operable between an engaged position and a disengaged position respectively to engage the chuck hub with the centering hub to prevent relative movement therebetween in at least a first direction, or to allow relative movement therebetween. A chuck motor is provided for selectively rotating the chuck hub and/or the centering hub during a wafer processing operation and a wafer centering operation based on an engaged or disengaged position of the engagement device. A plurality of chuck arms is mounted to the chuck hub, each chuck arm extending radially between a proximal end adjacent the chuck hub, and a distal end remote therefrom. Each of a plurality of centering cams is mounted at or towards a distal end of a chuck arm, and movable to engage or release a wafer edge in response to rotational movement of the centering hub relative to the chuck hub. | 2019-11-07 |
20190341291 | CHUCK FOR EDGE BEVEL REMOVAL AND METHOD FOR CENTERING A WAFER PRIOR TO EDGE BEVEL REMOVAL - A chuck useful for supporting a wafer during an edge bevel removal (EBR) process comprises a rotatable center hub having a plurality of support arms extending outwardly from the rotatable center hub, support pins on ends of the support arms, gas passages extending through upper surfaces of the support pins, and gas conduits in the support arms, the gas conduits configured to supply gas to the gas passages or apply a vacuum to the gas passages. The support arms can include alignment cams which are rotatable from an outer non-alignment position away from a periphery of the wafer to an inner alignment position at which the wafer is centered. To supply gas or apply a vacuum force to the gas outlets in the support pins, the rotatable center hub can have a gas inlet and a plurality of gas delivery ports in fluid communication with the gas delivery conduits in the support arms. Gas can be supplied to the gas outlets by a source of pressurized gas connected to the gas inlet and suction can be applied to the gas outlets by a vacuum source connected to the gas inlet. During centering, the wafer is floated on a gas cushion which reduces wear of the support pins. | 2019-11-07 |
20190341292 | WAFER POSITIONING PEDESTAL FOR SEMICONDUCTOR PROCESSING - An assembly used in a process chamber for depositing a film on a wafer and including a pedestal extending from a central axis. An actuator is configured for controlling movement of the pedestal. A central shaft extends between the actuator and pedestal, the central shaft configured to move the pedestal along the central axis. A lift pad is configured to rest upon the pedestal and having a pad top surface configured to support a wafer placed thereon. A pad shaft extends between the actuator and the lift pad and controls movement of the lift pad. The pad shaft is positioned within the central shaft and is configured to separate the lift pad from the pedestal top surface by a process rotation displacement when the pedestal is in an upwards position. The pad shaft is configured to rotate relative to the pedestal top surface between first and second angular orientations. | 2019-11-07 |
20190341293 | Gold Plating On Metal Layer For Backside Connection Access - A backside connection access structure and method for manufacturing are described. The method including forming a gold layer over at least a portion of a substrate. The method also including forming a metal layer over the gold layer. And, the method includes forming an opening in the substrate to expose at least a portion of the gold layer. | 2019-11-07 |
20190341294 | FORMATION AND IN-SITU TREATMENT PROCESSES FOR GAP FILL LAYERS - The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device having an enhanced gap fill layer in trenches. The present disclosure provides a novel gap fill layer formed using a multi-step deposition and in-situ treatment process. The deposition process can be a flowable chemical vapor deposition (FCVD) utilizing one or more assist gases and molecules of low reactive sticking coefficient (RSC). The treatment process can be an in-situ process after the deposition process and includes exposing the deposited gap fill layer to plasma activated assist gas. The assist gas can be formed of ammonia. The low RSC molecule can be formed of trisilylamin (TSA) or perhydropolysilazane (PHPS). | 2019-11-07 |
20190341295 | METHOD AND DEVICE ISOLATION STRUCTURE IN FINFET - A method of forming a semiconductor device. The method may include providing a semiconductor device structure. The semiconductor device structure may include a semiconductor fin; and a mask, disposed over the semiconductor fin, the mask defining a plurality of openings, wherein the semiconductor fin is exposed in the plurality of openings. The method may further include directing angled ions into the plurality of openings, wherein a plurality of trenches are formed in the semiconductor fin, wherein a given trench of the plurality of trenches comprises a reentrant profile. | 2019-11-07 |
20190341296 | HIGH RESISTIVITY SILICON-ON-INSULATOR SUBSTRATE COMPRISING A CHARGE TRAPPING LAYER FORMED BY He-N2 CO-IMPLANTATION - A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and comprises a region of nitrogen-reacted nanovoids in the front surface region; a silicon dioxide layer on the surface of the semiconductor handle substrate; a dielectric layer in contact with the silicon dioxide layer; and a semiconductor device layer in contact with the dielectric layer. | 2019-11-07 |
20190341297 | BACK SIDE PROCESSING OF INTEGRATED CIRCUIT STRUCTURES TO FORM INSULATION STRUCTURE BETWEEN ADJACENT TRANSISTOR STRUCTURES - Techniques are disclosed for forming integrated circuit structures having a plurality of non-planar transistors. An insulation structure is provided between channel, source, and drain regions of neighboring fins. The insulation structure is formed during back side processing, wherein at least a first portion of the isolation material between adjacent fins is recessed to expose a sub-channel portion of the semiconductor fins. A spacer material is then deposited at least on the exposed opposing sidewalls of the exposed sub-channel portion of each fin. The isolation material is then further recessed to form an air gap between gate, source, and drain regions of neighboring fins. The air gap electrically isolates the source/drain regions of one fin from the source/drain regions of an adjacent fin, and likewise isolates the gate region of the one fin from the gate region of the adjacent fin. The air gap can be filled with a dielectric material. | 2019-11-07 |
20190341298 | VIA CONTACT RESISTANCE CONTROL - A first dielectric layer on a substrate is provided. The first dielectric layer has a first level metal line embedded in the dielectric. An opposite gouging feature is in a top surface of the first level metal line. The opposite gouging feature has a protuberant shape relative to the first level metal line. A second dielectric layer is over the first dielectric layer. A compound recess is in the second dielectric layer. A first portion of the recess is for a via connector positioned over the opposite gouging feature. | 2019-11-07 |
20190341299 | Structure and Method for Interconnection - Various self-aligned interconnect structures are disclosed herein. An exemplary interconnect structure includes a first dielectric layer disposed over a substrate; a first conductive feature disposed in the first dielectric layer; an etch stop layer disposed over a top surface of the first dielectric layer and a top surface of the first conductive feature; a second dielectric layer disposed over the first dielectric layer; and a second conductive feature disposed in the second dielectric layer. The top surface of the first conductive feature is lower than the top surface of the first dielectric layer. The etch stop layer includes a portion that extends between the top surface of the first conductive feature and the top surface of the first dielectric layer, on which the second conductive feature may or may not be disposed. In some implementations, the second conductive feature may be a via feature. | 2019-11-07 |
20190341300 | TRANSISTORS EMPLOYING CARBON-BASED ETCH STOP LAYER FOR PRESERVING SOURCE/DRAIN MATERIAL DURING CONTACT TRENCH ETCH - Techniques are disclosed for forming transistors employing a carbon-based etch stop layer (ESL) for preserving source and drain (S/D) material during contact trench etch processing. As can be understood based on this disclosure, carbon-based layers can provide increased resistance for etch processing, such that employing a carbon-based ESL on S/D material can preserve that S/D material during contact trench etch processing. This is due to carbon-based layers being able to provide more robust (e.g., more selective) etch selectivity during contact trench etch processing than the S/D material it is preserving (e.g., Si, SiGe, Ge, group III-V semiconductor material) and other etch stop layers (e.g., insulator material-based etch stop layers). Employing a carbon-based ESL enables a given S/D region to protrude from shallow trench isolation (STI) material prior to contact metal deposition, thereby providing more surface area for making contact to the given S/D region, which improves transistor performance. | 2019-11-07 |
20190341301 | Method of Forming Trenches - A method of forming a semiconductor device includes forming a material layer over a substrate and forming a first trench in the material layer, forming a conformal capping layer along sidewalls of the first trench, forming a second trench in the material layer while the capping layer is disposed along sidewalls of the first trench and forming a conductive feature within the first trench and the second trench. | 2019-11-07 |
20190341302 | Deposition Of Metal Films - Apparatuses and methods to provide electronic devices having metal films are provided. Some embodiments of the disclosure utilize a metallic tungsten layer as a liner that is filled with a metal film comprising cobalt. The metallic tungsten layer has good adhesion to the cobalt leading to enhanced cobalt gap-fill performance. | 2019-11-07 |
20190341303 | GLOBAL DIELECTRIC AND BARRIER LAYER - A semiconductor device including a substrate having a dielectric layer over the substrate and a first conductive feature disposed within the dielectric layer. A metal nitride material is disposed directly on a top surface of the first conductive feature. A metal oxynitride material is disposed directly on a top surface of the dielectric layer, wherein the metal nitride and the metal oxynitride are coplanar. A second conductive feature is disposed over and interfacing the metal nitride material. | 2019-11-07 |
20190341304 | Barrier for Copper Metallization and Methods of Forming - Electronic devices and methods with a barrier layer and methods of forming the barrier layer are described. A substrate can be exposed to a metal precursor (e.g., a tantalum precursor), a reactant (e.g., ammonia) and an optional plasma to form a first thickness of the barrier layer. An optional aluminum film can be formed on the first barrier layer and a second barrier layer is formed on the first barrier layer to form barrier layer with an aluminum inter-layer. | 2019-11-07 |
20190341305 | SELECTIVELY CONTROLLING APPLICATION OF A SELF-ASSEMBLED MONOLAYER COATING ON A SUBSTRATE OF A DEVICE FOR FACILITATING A REDUCTION OF ADVERSE EFFECTS OF SUCH COATING ON THE DEVICE - Selectively controlling application of a self-assembled monolayer (SAM) coating on a substrate of a device is presented herein. A method comprises: forming a material on a first substrate; removing a selected portion of the material from a defined contact area of the first substrate; forming a SAM coating on the material and the defined contact area—the SAM coating comprising a first adhesion force with respect to the material and a second adhesion force with respect to the defined contact area, and the first adhesion force being less than the second adhesion force; removing the SAM coating that has been formed on the material; and attaching the first substrate to the second substrate—the first substrate being positioned across from the second substrate, and the SAM coating that has been formed on the defined contact area being positioned across from a bump stop of the second substrate. | 2019-11-07 |
20190341306 | VIA FOR COMPONENT ELECTRODE CONNECTION - Embodiments provide a high aspect ratio via for coupling a top electrode of a vertically oriented component to the substrate, where the top electrode of the component is coupled to the via by a conductive bridge, and where the bottom electrode of the component is coupled to substrate. Some embodiments provide for mounting the component by a component wafer and separating the components while mounted to the substrate. Some embodiments provide for mounting individual components to the substrate. | 2019-11-07 |
20190341307 | METAL INSULATOR METAL CAPACITOR WITH EXTENDED CAPACITOR PLATES - A capacitor structure is described. A metal insulator metal capacitor in an integrated circuit device includes a first dielectric layer on a substrate. The first dielectric layer has a linear trench feature in which the capacitor is disposed. A bottom capacitor plate is in a lower portion of the trench. The bottom capacitor plate has an extended top face so that the extended top face extends upwards in a central region of the bottom capacitor plate metal relative to side regions. A high-k dielectric layer is disposed over the extended top face of the bottom capacitor plate. A top capacitor plate is disposed in a top, remainder portion of the trench on top of the high-k dielectric layer. | 2019-11-07 |
20190341308 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - In a semiconductor device, a semiconductor element is formed in a semiconductor, an interlayer insulating film having a contact hole and containing at least one of phosphorus and boron is disposed above the semiconductor, a metal electrode is disposed above the interlayer insulating film and is connected to the semiconductor element through the contact hole, and the interlayer insulating film is filled with hydrogen. | 2019-11-07 |
20190341309 | FABRICATION OF SELF-ALIGNED GATE CONTACTS AND SOURCE/DRAIN CONTACTS DIRECTLY ABOVE GATE ELECTRODES AND SOURCE/DRAINS - A method of forming an active device having self-aligned source/drain contacts and gate contacts, including, forming an active area on a substrate, where the active area includes a device channel; forming two or more gate structures on the device channel; forming a plurality of source/drains on the active area adjacent to the two or more gate structures and device channel; forming a protective layer on the surfaces of the two or more gate structures, plurality of source/drains, and active layer; forming an interlayer dielectric layer on the protective layer; removing a portion of the interlayer dielectric and protective layer to form openings, where each opening exposes a portion of one of the plurality of source/drains; forming a source/drain contact liner in at least one of the plurality of openings; and forming a source/drain contact fill on the source/drain contact liner. | 2019-11-07 |
20190341310 | Methods and Apparatus for MOS Capacitors in Replacement Gate Process - Methods and apparatus for polysilicon MOS capacitors in a replacement gate process. A method includes disposing a gate dielectric layer over a semiconductor substrate; disposing a polysilicon gate layer over the dielectric layer; patterning the gate dielectric layer and the polysilicon gate layer to form a plurality of polysilicon gates spaced by at least a minimum polysilicon to polysilicon pitch; defining a polysilicon resistor region containing at least one of the polysilicon gates and not containing at least one other of the polysilicon gates, which form dummy gates; depositing a mask layer over an inter-level dielectric layer; patterning the mask layer to expose the dummy gates; removing the dummy gates and the gate dielectric layer underneath the dummy gates to leave trenches in the inter-level dielectric layer; and forming high-k metal gate devices in the trenches in the inter-level dielectric layer. An apparatus produced by the method is disclosed. | 2019-11-07 |
20190341311 | METHOD FOR FORMING NANO SENSING CHIP BY SELECTIVE DEPOSITION OF SENSING MATERIALS THROUGH DEVICE-LOCALIZED JOULE HEATING AND NANO SENSING CHIP THEREOF - A method for forming a nanodevice sensing chip includes forming nanodevices having a sensing region capable of producing localized Joule heating. Individual nanodevice is electrical-biased in a chemical vapor deposition (CVD) system or an atomic layer deposition (ALD) system enabling the sensing region of the nanodevice produce localized Joule heating and depositing sensing material only on this sensing region. A sensing chip is formed via nanodevices with sensing region of each nanodevice deposited various materials separately. The sensing chip is also functioned under device Joule self-heating to interact and detect the specific molecules. | 2019-11-07 |
20190341312 | Semiconductor Device and Method for Atomic Layer Deposition of a Dielectric over a Substrate - A method includes performing an atomic layer deposition (ALD) process to deposit a dielectric material over a substrate, curing the deposited dielectric material using an ultra violet (UV) light, and annealing the deposited dielectric material after the curing. | 2019-11-07 |
20190341313 | SEMICONDUCTOR DEVICE AND TRANSISTOR THEREOF - Semiconductor device and transistor are provided. The semiconductor device includes a plurality of first fin structures formed on a substrate, each first fin structure having a first width along a first direction perpendicular to a length direction of the first fin structure; a plurality of second fin structures, each formed on a first fin structure and including a first region located on the first fin structure and a second region located on the first region, the first region having a second width along the first direction, and the second region having a third width along the first direction; a first isolation layer, formed on the substrate and between adjacent first fin structures and adjacent second fin structures; and a second isolation layer formed on the first region and between a bottom portion of sidewall surfaces of each second region and the first isolation layer. | 2019-11-07 |
20190341314 | MULTIVALENT OXIDE CAP FOR MULTIPLE WORK FUNCTION GATE STACKS ON HIGH MOBILITY CHANNEL MATERIALS - A method of fabricating a semiconductor device includes providing a high-k dielectric layer arranged on a channel region including a first transistor area and a second transistor area. The method further includes depositing a multivalent oxide layer directly on the high-k dielectric layer of the first transistor area. The method includes depositing a first work function metal on the multivalent oxide layer of the first transistor area and directly on the high-k dielectric layer of the second transistor area. | 2019-11-07 |
20190341315 | REPLACEMENT GATE FORMATION WITH ANGLED ETCH AND DEPOSITION - Methods herein may include forming a gate dielectric within a set of trenches in a stack of layers. A first work function (WF) metal may be formed atop the gate dielectric, and a capping layer may be formed over the first WF metal using an angled ion implant deposition, the capping layer extending across the trenches. | 2019-11-07 |
20190341316 | NANOSHEET SUBSTRATE ISOLATED SOURCE/DRAIN EPITAXY BY NITROGEN IMPLANTATION - Parasitic transistor formation under a semiconductor containing nanosheet device is eliminated by implantation of nitrogen into physically exposed surfaces of a semiconductor substrate after formation of a nanosheet stack of alternating nanosheets of a sacrificial semiconductor material nanosheet and a semiconductor channel material nanosheet on a portion of the semiconductor substrate. The nitrogen doped semiconductor region that is created by the nitrogen implantation is subsequently converted into a semiconductor nitride region (i.e., an isolation region) prior to the epitaxial growth of a semiconductor material that provides S/D regions from physically exposed sidewalls of each semiconductor channel material stack. The presence of the semiconductor nitride region prevents bottom up growth of the semiconductor material that provides the S/D regions. | 2019-11-07 |
20190341317 | High-K Metal Gate and Method for Fabricating the Same - Embodiments of the present disclosure provide wet process based methods for modifying threshold value (Vt) of high-k metal gate using self-assembled monolayer (SAM) on dedicated transistor. In one embodiment, the method includes forming a gate structure over a substrate, the gate structure comprising a gate dielectric layer, a barrier layer formed over the gate dielectric layer, and an oxide layer formed over the barrier layer, and forming a self-assembled monolayer on the oxide layer by exposing the oxide layer to an aqueous solution containing metal oxides in a metal dissolving acid. | 2019-11-07 |
20190341318 | SACRIFICIAL CAP FOR FORMING SEMICONDUCTOR CONTACT - A method for forming a semiconductor device includes forming a fins on a substrate, forming a sacrificial gate stack over a channel region of the fins, a source/drain region with a first material on the fins, a first cap layer with a second material over the source/drain region, and a second cap layer with a third material on the first cap layer. A dielectric layer is deposited over the second cap layer. The sacrificial gate stack is removed to expose a channel region of the fins. A gate stack is formed over the channel region of the fins. A portion of the dielectric layer is removed to expose the second cap layer. The second cap layer and the first cap layer are removed to expose the source/drain region. A conductive material is deposited on the source/drain region. | 2019-11-07 |
20190341319 | Packaging Mechanisms for Dies with Different Sizes of Connectors - Embodiments of mechanisms for testing a die package with multiple packaged dies on a package substrate use an interconnect substrate to provide electrical connections between dies and the package substrate and to provide probing structures (or pads). Testing structures, including daisy-chain structures, with metal lines to connect bonding structures connected to signals, power source, and/or grounding structures are connected to probing structures on the interconnect substrate. The testing structures enable determining the quality of bonding and/or functionalities of packaged dies bonded. After electrical testing is completed, the metal lines connecting the probing structures and the bonding structures are severed to allow proper function of devices in the die package. The mechanisms for forming test structures with probing pads on interconnect substrate and severing connecting metal lines after testing could reduce manufacturing cost. | 2019-11-07 |
20190341320 | GLASS BASED ELECTRONICS PACKAGES AND METHODS OF FORMING THEREOF - Electronics packages that incorporate components such as glass-based interposer assemblies are disclosed, as well as methods of forming thereof. A method includes bonding a glass-based substrate to a carrier, applying a metallization layer and/or a dielectric layer over the glass-based substrate to obtain a layered structure bonded to the carrier, removing sections of the layered structure such that portions of the layered structure remain on the carrier with a space between each thereof, attaching one or more dies to the portions, dispensing an underfill material between the glass-based substrate and the dies to obtain assemblies bonded to the carrier, encapsulating the assemblies with a polymeric material to obtain encapsulated assemblies, removing the carrier from the encapsulated assemblies to expose a back side of the encapsulated assemblies, and applying second metallization layers and second dielectric layers over the back side of the encapsulated assemblies to form the glass-based structures. | 2019-11-07 |
20190341321 | EXTERNAL GETTERING METHOD AND DEVICE - Disclosed embodiments include external gettering provided by electronic packaging. An external gettering element for a semiconductor substrate, which may be incorporated as part of an electronic packaging for the structure, is disclosed. Semiconductor structures and stacked semiconductor structures including an external gettering element are also disclosed. An encapsulation mold compound providing external gettering is also disclosed. Methods of fabricating such devices are also disclosed. | 2019-11-07 |
20190341322 | SEMICONDCUTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package includes an encapsulated semiconductor device, a redistribution structure, and a protection layer. The encapsulated semiconductor device includes a semiconductor device and an encapsulating material encapsulating the semiconductor device. The redistribution structure is disposed on the encapsulated semiconductor device and includes a dielectric layer and a redistribution circuit layer electrically connected to the semiconductor device. The protection layer at least covers the dielectric layer, wherein an oxygen permeability or a water vapor permeability of the protection layer is substantially lower than an oxygen permeability or a vapor permeability of the dielectric layer. | 2019-11-07 |
20190341323 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor element, a first substrate, a first electrode, a second electrode and a sealing resin. The first substrate has a first front surface and a first back surface that are spaced apart from each other in a thickness direction. The semiconductor element is mounted on the first main surface. The first electrode includes a first conductive portion and a second conductive portion. The first conductive portion is formed on a portion of the first front surface. The second conductive portion is connected to the first conductive portion and overlaps with the first substrate as viewed in a first direction perpendicular to the thickness direction. The sealing resin covers the semiconductor element. The second electrode is exposed from the sealing resin and electrically connected to the first electrode. The second electrode is in contact with the second conductive portion. | 2019-11-07 |
20190341324 | Manufacturing a package using plateable encapsulant - A method of manufacturing a package, comprising embedding the semiconductor chip with an encapsulant comprising a transition metal in a concentration in a range between 10 ppm and 10,000 ppm; selectively converting of a part of the transition metal, such that the electrical conductivity of the encapsulant increases; and plating the converted part of the encapsulant with an electrically conductive material. | 2019-11-07 |
20190341325 | Carrier Removal By Use of Multilayer Foil - A semiconductor device assembly having a semiconductor device attached to a substrate with a foil layer on a surface of the substrate. A layer of adhesive connects the substrate to a first surface of the semiconductor device. The semiconductor device assembly enables processing on the second surface of the semiconductor device. An energy pulse may be applied to the foil layer causing an exothermic reaction to the foil layer that releases the substrate from the semiconductor device. The semiconductor device assembly may include a release layer positioned between the foil layer and the layer of adhesive that connects the substrate to the semiconductor device. The heat generated by the exothermic reaction breaks down the release layer to release the substrate from the semiconductor device. The energy pulse may be an electric charge, a heat pulse, or may be applied from a laser. | 2019-11-07 |
20190341326 | Lighting Device Using Short Thermal Path Cooling Technology and other Device Cooling By Placing Selected Openings on Heat Sinks - A novel heat sinking technology, uniquely adaptive to LED lighting devices in a generally LED array format containing multiple openings on said heat sink's base portions and optionally fin portions providing “short path cooling” technology. The “short path cooling” technology is thoroughly taught with multiple examples. Also taught, are methods of heat sink area maintenance when said openings are placed on said heat sinks. Indeed, even surface area increases are shown to be possible when multiple openings are placed on said heat sinks. Lastly, other non-LED semiconductor cooling is discussed and illustrated in various figures using said “short path cooling” technology. | 2019-11-07 |
20190341327 | HEAT TRANSFER FOR POWER MODULES - In one general aspect, an apparatus can include a module including a semiconductor die. The apparatus can include a heatsink coupled to the module and including a substrate, and a plurality of protrusions. The apparatus can include a cover including a channel where the plurality of protrusions of the heatsink are disposed within the channel, and can include a sealing mechanism disposed between the cover and the module. | 2019-11-07 |
20190341328 | MECHANICALLY IMPROVED MICROELECTRONIC THERMAL INTERFACE STRUCTURE FOR LOW DIE STRESS - A heat dissipation structure for a semiconductor integrated circuit die having a plurality of connection areas may include a thermal mount comprising a plurality of pillars each having an aspect ratio preferable greater than 2:1 and each positioned to connect to one of the connection areas on a peripheral portion of the semiconductor integrated circuit die with one of a plurality of interface layers. A thermal conductivity of materials for the connection areas, the thermal mount, the pillars, each of which is preferably copper, and the interface layers, which are preferably copper nanoparticle layers, has a thermal conductivity greater than 100 Watts per meter degree Kelvin (W/m·K). Flexure of the pillars accommodates mechanical strain arising from temperature changes and differences in coefficients of thermal expansion for materials of the semiconductor integrated circuit die and the thermal mount. | 2019-11-07 |
20190341329 | MODULE - A module improves a heat-releasing effect and that can be stably mounted on a mother substrate or the like. The module includes: a first component mounted on one main surface of a wiring substrate and generates heat; second components mounted on the one main surface of the wiring substrate; a sealing resin layer that seals the first component and the second components so as not to cover a top surface of the first component; and heat-dissipating parts arranged on the top surface of the first component. The height of the highest positions of the heat-dissipating parts relative to the one main surface is less than or equal to the position of a highest surface out of a surface of the sealing resin layer that is on the opposite side from the surface of the sealing resin layer that faces the one main surface. | 2019-11-07 |
20190341330 | HEAT DISSIPATION COMPONENT FOR SEMICONDUCTOR ELEMENT - A sheet-shaped aluminum-diamond composite containing a prescribed amount of a diamond powder wherein a first and second peak in a volumetric distribution of particle sizes occurs at 5-25 μm and 55-195 μm, and a ratio between an area of a volumetric distribution of particle sizes of 1-35 μm and 45-205 μm is from 1:9 to 4:6, the composite including an aluminum-containing metal as the balance, wherein the composite is covered, on both main surfaces, with a surface layer having prescribed film thicknesses and containing 80 vol % or more of an aluminum-containing metal, two or more Ni-containing layers are formed on at least the surface layer, the Ni-containing layers being such that a first and second layer from the surface layer side are amorphous Ni alloy layers having prescribed thicknesses, and an Au layer having a prescribed thickness is formed as an outermost layer. | 2019-11-07 |
20190341331 | SUBSTRATE FOR POWER MODULE, CIRCUIT BOARD FOR POWER MODULE, AND POWER MODULE - A substrate for a power module ( | 2019-11-07 |
20190341332 | HIGH POWER MODULE PACKAGE STRUCTURES - A dual-side cooling package includes a first semiconductor die and a second semiconductor die disposed between a first direct bonded metal (DBM) substrate and a second DBM substrate. A metal surface of the first DBM substrate defines a first outer surface of a package and a metal surface of the second DBM substrate defines a second outer surface of the package. The first semiconductor die is thermally coupled to the first DBM substrate. A first conductive spacer thermally couples the first semiconductor die to the second DBM substrate. The second semiconductor die is thermally coupled to a second conductive spacer. Further, one of the second semiconductor die and the second conductive spacer is thermally coupled to the first DMB substrate and the other of the second semiconductor die and the second conductive spacer is thermally coupled to the second DBM substrate. | 2019-11-07 |
20190341333 | DEVICE FOR REMOVING HEAT - Removing device including: a heat exchanger that is mounted on a platen so that the exchanger lies above and a distance away from an electronic component; a chassis that lies between the electronic component and the platen, and device for fastening the chassis to the platen or to the electronic board; a rigid heat sink that is mounted on the chassis in order to slide perpendicularly to the electronic board and that has a first end making contact with the component and a second end in abutment against a thermally conductive layer that is fastened to the platen in order to elastically return the rigid heat sink into abutment against the electronic component whatever the thickness of the electronic component. Electronic equipment having such a removing device. | 2019-11-07 |
20190341334 | TRANSAXLE WITH SEMICONDUCTOR DEVICE COOLING ARRANGEMENT - This disclosure relates to a motor vehicle including a transaxle with a cooling arrangement for semiconductor devices such as IGBTs or MOSFETs, and a corresponding method. In particular, this disclosure relates to a motor vehicle, such as an electrified vehicle, including a transaxle, a plurality of semiconductor devices mounted adjacent the transaxle, and a source of cooling fluid. The semiconductor devices are exposed to fluid from the source that flows into the transaxle. | 2019-11-07 |
20190341335 | COOLING APPARATUS, SEMICONDUCTOR MODULE, AND VEHICLE - The flow speed distribution of a refrigerant in a cooling apparatus is made uniform. A cooling apparatus provided includes: a top plate; a casing portion having a base plate facing the top plate, and a refrigerant delivery portion arranged between the top plate and the base plate, the casing portion provided with two opening portions to function as an inlet port through which a refrigerant is let into the refrigerant delivery portion and an outlet port through which the refrigerant is let out; a cooling fin portion arranged in the refrigerant delivery portion of the casing portion and between the two opening portions; and a loss adding portion arranged in the refrigerant delivery portion of the casing portion and between the cooling fin portion and at least one of the two opening portions, the loss adding portion generating pressure loss in the refrigerant passing therethrough. | 2019-11-07 |
20190341336 | POWER MODULE APPARATUS, COOLING STRUCTURE, AND ELECTRIC VEHICLE OR HYBRID ELECTRIC VEHICLE - A power module apparatus ( | 2019-11-07 |
20190341337 | WATER COOLING MODULE - A water cooling module includes a flow-guiding main body and a pump set. The flow-guiding main body includes a first inlet, a first outlet and a flow-guiding passage set. The flow-guiding passage set includes a plurality of flow-guiding passages, and the first inlet and the first outlet are respectively communicable with one of the flow-guiding passages. The pump set includes a first pump having a first water inlet and a first water outlet, and a second pump having a second water inlet and a second water outlet. The first water inlet and the first water outlet are respectively communicable with one of the flow-guiding passages; the second water inlet and the second water outlet are also respectively communicable with one of the flow-guiding passages. The flow-guiding main body replaces rubber pipes to guide working fluid without the problem of oxidized and leaked pipes while providing prolonged service life. | 2019-11-07 |
20190341338 | PREFORMED LEAD FRAME AND LEAD FRAME PACKAGE MADE FROM THE SAME - A preformed lead frame includes multiple lead frame units, a connection bar connecting the lead frame units and extending along a singulation line, and a molding layer molded over the lead frame units and the connection bar. The molding layer has a lower surface and a plurality of spaced apart elongate grooves indented upwardly from the lower surface. Each of the lead frame units includes a row of spaced-apart leads, each of which has a grooved surface exposed from the lower surface of the molding layer and a grooved soldering surface indented upwardly from the grooved surface and exposed in one of the elongate groove. A lead frame package formed from the preformed lead frame is also disclosed. | 2019-11-07 |
20190341339 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Reliability of a semiconductor device is improved. In the semiconductor device SA | 2019-11-07 |
20190341340 | MOUNTING RACK WITH CIRCUIT - A mounting rack with circuit includes a leadframe, a molding seat and a circuit layer. The leadframe comprises a plurality of electrodes. The molding seat is arranged on the leadframe and has a cup body to expose backsides of the electrodes and a cup opening to expose front sides of the electrodes. The circuit layer is arranged on the cup body and at least comprises two conductive parts, two electrical-connection parts and two soldering pads, wherein the two electrical-connection parts are arranged on the cup opening, one end of each of the two electrical-connection parts is electrically connected to one end of a respective one of the two conductive parts, the two soldering pads are arranged on bottom of the cup body, each of the two soldering pads is electrically connected to the other end of a respective one of the two conductive parts. | 2019-11-07 |
20190341341 | POWER MODULE - A power module ( | 2019-11-07 |
20190341342 | METHOD TO ACHIEVE VARIABLE DIELECTRIC THICKNESS IN PACKAGES FOR BETTER ELECTRICAL PERFORMANCE - Embodiments include packages substrates and a method of forming the package substrate. A package substrate includes a first dielectric comprising a first conductive layer, and a second dielectric comprising a second conductive layer and a third conductive layer. The second and third conductive layers are embedded in the second dielectric, where a top surface of the third conductive layer is above a top surface of the second conductive layer. The package substrate has a fourth conductive layer on the second dielectric. The first dielectric has a first dielectric thickness between the first and third conductive layers. The first dielectric also has a second dielectric thickness between the first and second conductive layers. The package substrate includes the second dielectric thickness that is greater than the first dielectric thickness. The second dielectric may have a z-height of a first bottom surface greater than a z-height of a second bottom surface. | 2019-11-07 |
20190341343 | MODULE ASSEMBLY - A module assembly includes an adapter substrate with at least one cavity and a surface mounted die mounted on a top surface of the adapter substrate. The first cavity extends through the adapter substrate and has at least one first side wall. A first metallization layer is provided within the cavity. A first recessed die is attached to the first metallization layer and mounted within the cavity such that the first recessed die is at least partially recessed into the first cavity and surrounded by a gap filler that resides between side portions of the first recessed die and the at least one first side wall. The top surface of the gap filler is flush with the top surface of the adapter substrate and a top surface of the first recessed die. | 2019-11-07 |
20190341344 | POWER MANAGEMENT APPLICATION OF INTERCONNECT SUBSTRATES - Various applications of interconnect substrates in power management systems are described. | 2019-11-07 |
20190341345 | SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING SEMICONDUCTOR MODULE - A semiconductor module includes a metal plate; a solder applied on the metal plate; a component-to-be-bonded mounted on the solder; and a linear guide portion delineated along a circumference of the component-to-be-bonded on a top surface of the metal plate, and including a metal surface having greater surface roughness than a peripheral region. | 2019-11-07 |
20190341346 | MEMORY CELL HAVING MULTI-LEVEL WORD LINE - A method of designing a memory circuit is provided that includes generating a layout of a first memory cell using an integrated circuit design system. The layout of the first memory cell is generated by routing a first word line in a first layer on a first level, and routing a second word line in the first layer. Also, the method includes generating a layout of a second memory cell using the integrated circuit design system. The layout of the second memory cell is generated by routing a third word line in the first layer, the second word line being between the first word line and the third word line, and routing a fourth word line in the first layer, the third word line being between the second word line and the fourth word line. Moreover, the method includes assigning a first color scheme to the first word line and to the third word line, and assigning a second color scheme to the second word line and to the fourth word line. The first color scheme is associated with a first manufacturing process using a first mask and the second color scheme is associated with a second manufacturing process using a second mask. | 2019-11-07 |
20190341347 | MIM CAPACITOR FOR IMPROVED PROCESS DEFECT TOLERANCE - A method and structure to isolate BEOL MIM capacitors shorted or rendered highly leaky due to in process, or service induced defects, in a semiconductor chip are provided such that the rejection and loss of yield of otherwise good chips is minimized. In one embodiment, the method incorporates an isolation element such as, for example, a fuse, or a phase change material such as, a metal/insulation transition metal material, in series between the MIM capacitor and the active circuit. When a high current passes through the element due to the MIM capacitor being defective, the isolation element is rendered highly resistive or electrically open thereby disconnecting the defective capacitor or electrode plate from the active circuitry. | 2019-11-07 |
20190341348 | ELECTRICAL FUSE AND/OR RESISTOR STRUCTURES - Electrical fuse (eFuse) and resistor structures and methods of manufacture are provided. The method includes forming metal gates having a capping material on a top surface thereof. The method further includes protecting the metal gates and the capping material during an etching process which forms a recess in a dielectric material. The method further includes forming an insulator material and metal material within the recess. The method further includes forming a contact in direct electrical contact with the metal material. | 2019-11-07 |
20190341349 | SIDE MOUNTED INTERCONNECT BRIDGES - A device and method of utilizing an interconnect bridge to electrically couple two semiconductor dies located on different surfaces. Integrated circuit packages using an interconnect bridge to electrically couple a semiconductor die on a substrate to a semiconductor die on a motherboard are shown. Integrated circuit packages using an interconnect bridge to electrically couple a semiconductor die on a top surface of a substrate to a semiconductor die on a bottom surface of a substrate are shown. Methods of electrically coupling semiconductor dies on different surfaces using interconnect bridges are shown. | 2019-11-07 |
20190341350 | DIELETS ON FLEXIBLE AND STRETCHABLE PACKAGING FOR MICROELECTRONICS - Dielets on flexible and stretchable packaging for microelectronics are provided. Configurations of flexible, stretchable, and twistable microelectronic packages are achieved by rendering chip layouts, including processors and memories, in distributed collections of dielets implemented on flexible and/or stretchable media. High-density communication between the dielets is achieved with various direct-bonding or hybrid bonding techniques that achieve high conductor count and very fine pitch on flexible substrates. An example process uses high-density interconnects direct-bonded or hybrid bonded between standard interfaces of dielets to create a flexible microelectronics package. In another example, a process uses high-density interconnections direct-bonded between native interconnects of the dielets to create the flexible microelectronics packages, without the standard interfaces. | 2019-11-07 |
20190341351 | MICROELECTRONIC DEVICE WITH EMBEDDED DIE SUBSTRATE ON INTERPOSER - A microelectronic device is formed to include an embedded die substrate on an interposer; where the embedded die substrate is formed with no more than a single layer of transverse routing traces. In the device, all additional routing may be allocated to the interposer to which the embedded die substrate is attached. The embedded die substrate may be formed with a planarized dielectric formed over an initial metallization layer supporting the embedded die. | 2019-11-07 |
20190341352 | TAPERED CORNER PACKAGE FOR EMI SHIELD - A semiconductor package comprises a substrate, a die mounted on the substrate, and a mold formed over the die and on the substrate, the mold having a top surface and a plurality of tapered side surfaces, wherein the tapered side surfaces provide uniform thickness of an electromagnetic interference (EMI) shielding film. | 2019-11-07 |
20190341353 | FAN-OUT SEMICONDUCTOR PACKAGE - A fan-out semiconductor package includes a connection member including an insulating layer and a redistribution layer, a semiconductor chip disposed on the connection member, an encapsulant encapsulating the semiconductor chip, and an electromagnetic wave shielding layer disposed on the semiconductor chip and including a plurality of degassing holes. The electromagnetic wave shielding layer includes a first region and a second region in which densities of the degassing holes are different from each other, the first region having a density of the degassing holes higher than a density of the degassing holes in the second region. | 2019-11-07 |
20190341354 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a support member having a first surface and a second surface, and having a through-hole, a first metal layer for shielding disposed on an internal sidewall of the through-hole and the first surface and the second surface of the support member, a connection member disposed on the first surface of the support member, and having a redistribution layer, a semiconductor chip disposed in the through-hole, an encapsulant sealing the semiconductor chip located in the through-hole, and covering the second surface of the support member, a second metal layer for shielding disposed on the encapsulant, and connected to the first metal layer for shielding by a connecting trench via passing through the encapsulant, and a reinforcing via disposed in a region, overlapping the trench via for connection, of the support member, and connected to the first metal layer for shielding. | 2019-11-07 |
20190341355 | FAN-OUT SEMICONDUCTOR PACKAGE - A fan-out semiconductor package includes a connection member including an insulating layer and a redistribution layer, a semiconductor chip disposed on the connection member, an encapsulant encapsulating the semiconductor chip, and an electromagnetic radiation blocking layer disposed above the semiconductor chip and including a base layer in which a plurality of degassing holes are formed and a porous blocking portion filled in the plurality of degassing holes. | 2019-11-07 |
20190341356 | INNOVATIVE FAN-OUT PANEL LEVEL PACKAGE (FOPLP) WARPAGE CONTROL - Fan-out panel level packages (FOPLPs) comprising warpage control structures and techniques of formation are described. An FOPLP may comprise one or more redistribution layers; a semiconductor die on the one or more redistribution layers; one or more warpage control structures adjacently located next to the semiconductor die; and a mold compound encapsulating the semiconductor die and the one or more warpage control structures on the one or more redistribution layers. The FOPLP can be coupled a board (e.g., a printed circuit board, etc.). The warpage control structures can assist with minimizing or eliminating unwanted warpage, which can occur during or after formation of an FOPLP or a packaged system. In this way, the warpage control structures can assist with reducing costs associated with semiconductor packaging and/or manufacturing of an FOPLP or a packaged system. | 2019-11-07 |
20190341357 | FLIP-CHIP PACKAGE SUBSTRATE - A flip-chip package substrate is provided. A strengthening structure is provided on one side of a circuit structure to increase the rigidity of the flip-chip package substrate. When the flip-chip package substrate is used in large-scale packaging, the flip-chip package substrate can have good rigidity, so that the electronic package can be prevented from warping. | 2019-11-07 |
20190341358 | METHOD OF FORMING SEMICONDUCTOR DEVICE USING POLISHING RESISTANCE PATTERN - A method of forming a semiconductor device, includes: forming a design pattern on a substrate, wherein the design pattern protrudes from the substrate; forming a filling layer on the substrate, wherein the filling layer at least partially covers the design pattern; forming a polishing resistance pattern adjacent to the design pattern in the filling layer using a laser irradiation process and/or an ion implantation process; and removing the filling layer using a chemical mechanical polishing (CMP) process to expose the design pattern. | 2019-11-07 |