45th week of 2017 patent applcation highlights part 57 |
Patent application number | Title | Published |
20170324353 | METHOD FOR MONITORING CHANGE IN CAPACITANCE IN ELECTRIC SYSTEM AND ELECTRIC SYTEM - A method for monitoring a change in a capacitance in an electric system, and an electric system comprising a multilevel inverter and at least two capacitances connected in series between a negative DC pole and a positive DC pole of the inverter, wherein the connection point between the capacitances is connected to one of the at least one middle DC pole of the inverter, and a controller configured to provide by the inverter an AC current component to one of the at least one middle DC pole of the inverter, which AC current component is distributed between the two capacitances connected to the middle DC pole, and monitor resulting AC voltage components in the two capacitances, and determine on the basis of a difference between the monitored AC voltage components a change in at least one of the two capacitances. | 2017-11-09 |
20170324354 | Thermal Energy Harvesting Optimization with Bistable Elements and Collaborative Behavior - A system includes a hot source, a cold source, and a device thermally coupled between the hot source and the cold source. The device includes a thermal-mechanical transducer and a mechanical-electrical transducer. The thermal-mechanical transducer includes a band of bimetallic strips linked mechanically together by their longitudinal ends. The band partially suspended over a portion of a substrate. Each bimetallic strip has a first stable state having a first curvature and a second stable state having a second curvature opposite the first curvature, and adjacent bimetallic strips have opposite curvature. | 2017-11-09 |
20170324355 | MAIN DRIVE CONTROL METHOD FOR GLASS FACTORIES - A main drive control method for glass factories, comprising the following steps: (a) providing a first circuit breaker and a second circuit breaker on a power supply loop of an electrical motor, wherein one end thereof is respectively connected to two main drive electrical motors; (b) enabling the first circuit breaker to be connected to a municipal power supply and the second circuit breaker to be connected to a UPS power supply; and (c) enabling the first circuit breaker and the second circuit breaker to be interlocked via a mechanical interlocking mechanism, so that only one of the circuit breakers can be switched on during a normal operation. The main drive control method for glass factories solves the problem that the rotation speed of a main drive electrical motor is incorrect due to the interference on a signal. | 2017-11-09 |
20170324356 | METHOD AND DEVICE FOR CONTROLLING AN OPERATION OF AN ELECTRIC MOTOR - In a method for controlling an operation of an electric motor, electric voltages applied to electric phases of the electric motor are generated and output in a modulation in a controlled manner dependent on a rotor position of the electric motor and a target/actual comparison of at least one first variable which characterizes a load on the electric motor or an actual rotational speed of the electric motor. A rotor position angle, which characterizes the rotor position, is complemented with a specified preliminary control angle and another regulated preliminary control angle component upon reaching a field weakening range of the electric motor so as to form a sum angle. The sum angle is used to characterize the rotor position in the modulation upon reaching the field weakening range. The disclosure also relates to a device for controlling an operation of an electric motor. | 2017-11-09 |
20170324357 | BRUSHLESS MOTOR AND WIPER APPARATUS - A brushless motor comprises: a stator | 2017-11-09 |
20170324358 | FAULT-TOLERANT CONTROL METHOD FOR POSITION SENSOR OF SWITCHED RELUCTANCE MOTOR - A fault-tolerant control method for a position sensor of a switched reluctance motor, if the position sensor of the switched reluctance motor runs without a fault, detecting, in real time, four equal-interval or equal-angle continuous edge pulses of an output signal of the position sensor, the fourth edge pulse being the current edge pulse, and detecting time intervals (T | 2017-11-09 |
20170324359 | Method and Apparatus for Adjusting Motor Commutation Phase and Period - A method and apparatus for controlling commutation of a motor. A voltage is measured at each of a plurality of windings of a motor using an electric circuit. A controller computes an overall back electromotive force for the motor using the voltage measured at each winding in the plurality of windings. The controller generates a result having either a first value or a second value based on the overall back electromotive force. The controller adjusts the commutation phase and the commutation period of the motor using the result. | 2017-11-09 |
20170324360 | MULTIPLE ENGINE CONDITION MATCHING VIA ELECTRICAL POWER EXTRACTION CONTROL - A multi-engine power system is described that includes a load requiring a total amount of electrical power, a first engine configured to provide a first portion of the total amount of electrical power to be provided to the load, and a second engine configured to provide a second portion of the total amount of electrical power to be provided to the load. The system further includes a controller configured to determine the total amount of electrical power to be provided to the load, estimate a respective service time associated with each of the first and second engines, and control each of the first and second engines to provide the total amount of electrical power to the load and to coordinate the respective service times associated with the first and second engines. | 2017-11-09 |
20170324361 | INTELLIGENT COOPERATIVE CONTROL SYSTEM AND METHOD FOR MULTI-UNIT PERMANENT MAGNET SYNCHRONOUS MOTOR - An intelligent cooperative control system and method thereof. A parallel structure for low-voltage multi-module permanent magnet synchronous motor cooperative control units is adopted to realize control of low-voltage high power, control of low-speed large torque and system redundancy control; a double-parallel PWM rectifier circuit structure is used, when the system is in unbalanced power supply network environments; a resonant pole-type three-phase soft-switching inverter circuit is used as an inverter unit to improve utilization of DC bus voltage and to greatly reduce device switch losses at high frequencies; a current control and speed estimation unit is used, so that rotor speed and phase angle information is accurately estimated with low cost and high reliability; a controlled object is the multi-module permanent magnet synchronous motor, so that the problems of difficulties in motor installation, transportation and maintenance of a high-power electric drive system and the like are solved. | 2017-11-09 |
20170324362 | Management of Motor Regeneration - A method and apparatus for controlling regeneration for a motor. An instantaneous voltage provided by a power supply to the motor is identified using a voltage signal received from a voltage sensor. A new average voltage is computed for the motor using the instantaneous voltage, a previously computed average voltage, and a weight factor for the instantaneous voltage. A difference between the new average voltage and the instantaneous voltage is compared to a selected threshold to determine whether a regeneration condition exists. Operation of the motor is controlled such that a duty cycle of the motor does not decrease in response to a determination that the regeneration condition exists. | 2017-11-09 |
20170324363 | CONTROLLER FOR AC ROTATING MACHINE AND CONTROLLER FOR ELECTRIC POWER STEERING - This invention is concerning a controller for an AC rotating machine, this controller having an estimated sum current computing unit configured to output, as estimated sum current, a sum of current of a first winding and current of a second winding when it is determined that the current of the first winding can be detected, and maintain the estimated sum current which has been outputted as a previous value when it is determined that the current of the first winding cannot be detected. When it is determined that the current of the first winding cannot be detected, a first voltage command for the first winding is computed based on an estimated current value of the first winding, which has been calculated by subtracting the current of the second winding detected by the second current detector, from the estimated sum current output from the estimated sum current computing unit. | 2017-11-09 |
20170324364 | Motor Control Using Phase Current and Phase Voltage - Methods and apparatus to control a three-phase BLDC motor using phase current and phase voltage at zero current detection and a driving current derived from a bus current, for example. The driving current can be combined with a difference angle with an output provided to a controller to control a speed of the motor/ | 2017-11-09 |
20170324365 | MOTOR APPARATUS AND MOTOR CONTROL METHOD - A motor apparatus and a motor control method are provided. The method includes the following steps. An actual speed and an actual current of a motor module are sensed by a sensor module. An adjusted speed is kept at a set speed or a speed curve by a speed adjusting circuit. A control signal is provided by a feedback control circuit according to a difference between the adjusted speed and the actual speed. The control signal is converted to a current to drive the motor module, such that the actual speed is kept at the adjusted speed. When the actual speed is decreased and the actual current is increased to a limited current value, a setting parameter of the feedback controller is changed according to the limited current value, such that the control signal enters a saturation state and the actual current is kept at the limited current value. | 2017-11-09 |
20170324366 | INPUT STAGE FOR A MOTOR CONTROLLER, AND MOTOR CONTROLLER, ESPECIALLY FOR AN ELECTRIC MOTOR - The invention relates to an input stage ( | 2017-11-09 |
20170324367 | SOLAR PANEL MOUNTING APPARATUS AND SYSTEM - An aspect of the present disclosure provides solar panel mounting and charging system comprising a hub and a girder assembly. The hub may comprise a plurality of attachment points on its exterior. The girder assembly may comprise a plurality of top girders configured to be mechanically fastened to each other at their proximal ends, and having a distance between their distal ends that is greater than a distance between the proximal ends of the top girders. The girder assembly may also comprise a plurality of bottom girders configured to be mechanically fastened to each other at their proximal ends and the plurality of top girders at their distal ends. The system may further comprise an electric vehicle charging system affixed to the pole, wherein the electric vehicle charging system is configured to receive electrical power from at least one solar panel affixed to the girder assembly. | 2017-11-09 |
20170324368 | SOLAR CELL MODULE - A solar cell module includes a solar cell panel, a frame member, and an adhesive. The solar cell panel has a front surface, a back surface and a lateral surface. The frame member is located along an outer peripheral part of the solar cell panel, and includes a fitting section with the outer peripheral part fitted therein. The adhesive is located in a space in the fitting section, and bonded to the outer peripheral part. The adhesive includes a pressure-sensitive first adhesive and a curable second adhesive. The curable second adhesive exists at a position different from a position at which the first adhesive exists, in a direction along the longitudinal direction of the frame member. | 2017-11-09 |
20170324369 | PROCESS FOR MANUFACTURING A PHOTOVOLTAIC CONCENTRATOR COMPRISING AN OPTICAL STRUCTURE EQUIPPED WITH TWO OPTICAL-LENS STAGES - The process for manufacturing a photovoltaic concentrator comprising a photovoltaic substrate ( | 2017-11-09 |
20170324370 | HIGH-PERFORMANCE PLANAR SOLAR CONCENTRATORS BASED ON NANOPARTICLE DOPING - A light scattering-based solar concentrator (LSSC) uses high refractive index nanoparticles (NPs) as dopants to selectively scatter photons across the solar spectrum without spectroscopic conversion by different sized nanoparticles. The LSSCs are limited by a single parameter: the surface photon losses, which can be addressed by nanofabrication to implement anti-reflective and light trapping structures into LSSC designs. The LSSC design provides solar concentrator techniques for photovoltaic (PV) applications. | 2017-11-09 |
20170324371 | FAIL-SAFE DISCONNECT JUNCTION BOX AND SOLAR POWER SYSTEM - The invention discloses a fail-safe disconnect junction box for a solar photovoltaic module and a power station system, wherein the junction box comprises a box body, the box body is provided with a printed circuit board, the printed circuit board is printed with N bus bar connecting ends and two cable connecting ends, each bus bar connecting end is connected with a solar battery pack strand via bus bars, two adjacent bus bar connecting ends are further connected via a diode; wherein an electronic switch is connected between the first bus bar connecting end and the first cable connecting end in series, the electronic switch is controlled to turn on or off via a received control signal; the Nth bus bar connecting end is connected with the second cable connecting end; and two cable connecting ends are connected to the outside via a cable respectively. The power station system controls the junction box via the control signal. According to the invention, the voltage in the power station system will be reduced within a safety range manually or automatically when an accident happens, thus facilitating carrying out site disposal in time. | 2017-11-09 |
20170324372 | Shading Object, Intelligent Umbrella and Intelligent Shading Charging Security System and Method of Operation - An intelligent umbrella includes an array of solar panels/cells for capturing sunlight and converting into electrical energy, a solar panel charging assembly to receive power from one or more solar assemblies, a rechargeable battery to receive power generated from the solar panel charging assembly, and a processor and a memory, the processor and the memory to receive power from the rechargeable battery; and a wireless transceiver to receive power from the rechargeable battery, the wireless transceiver to communicate messages and/or signals when no external power source is connected to and/or available for the intelligent umbrella. The intelligent umbrella may further comprise a cellular transceiver to receive power from the rechargeable battery, the cellular transceiver to communicate messages and/or signals when no external power source is connected to and/or available to supply power for the intelligent umbrella. | 2017-11-09 |
20170324373 | PHOTOVOLTAIC COLLECTOR - Disclosed is an inflatable solar photovoltaic collector system that uses a flexible tubular plastic enclosure that is inflated to support a solar photovoltaic collector. Both the flexible tubular plastic enclosure and the solar photovoltaic collector can be flexible and lightweight and can be used as a portable generator of electricity. In addition to providing support for the solar photovoltaic collector, the flexible tubular plastic enclosure can also be inflated with a blower, which cools the solar photovoltaic collector to prevent thermal radiation damage to the solar photovoltaic collector and simultaneously provides a source of warm air. Further, the flexible tubular plastic enclosure can be inflated with a lighter-than-air gas so that the inflatable photovoltaic collector system floats in air. Also, the flexible tubular plastic enclosure can be tightly sealed so that the inflatable photovoltaic collector system floats in water. The system can also be used to create a source of potable water. | 2017-11-09 |
20170324374 | SYSTEM AND METHOD FOR OPTIMIZING ENERGY GENERATION - A system and method for optimizing energy generation. The method includes remotely connecting to an energy storage apparatus that is connected to a tested solar panel; receiving, from the energy storage apparatus, at least one test power measurement, wherein each test power measurement is an amount of power generated by the tested solar panel; obtaining at least one benchmarking power measurement, wherein each benchmarking power measurement is an amount of power generated by one of at least one benchmarking solar panel; determining, based on the at least one benchmarking power measurement, at least one optimization threshold; comparing each test power measurement to each optimization threshold; determining, based on the comparison, whether placement of the tested solar panel is at least an optimal placement; and generating a notification indicating whether placement of the tested solar panel is optimal. | 2017-11-09 |
20170324375 | Method to Remove the Effects of LO Drift from Vector Network Analyzer Measurements - Certain exemplary embodiments can provide a method, which can comprise automatically removing effects of local oscillator phase drift occurring in between two measurements of reciprocal networks as made with a vector network analyzer. The method can further comprise determining that the vector network analyzer substantially simultaneously samples all incident and reflected waves from the reciprocal networks. | 2017-11-09 |
20170324376 | System and Method for Multifunction Segmented Array Compensation for Oscillators - The present disclosure provides for a system and method for compensating an electronic oscillator for one or more environmental parameters. A method may comprise segmenting test data received from an output signal of the oscillator and generating at least one correction voltage to thereby compensate the oscillator for one or more environmental parameters. A system may comprise at least one multi-function segmented array compensation module configured to receive one or more output signals from an oscillator and generate one or more correction voltages to thereby compensate the oscillator for environmental parameters. The system may also comprise one or more sensors and a user EFC. | 2017-11-09 |
20170324377 | AMPLITUDE DETECTION WITH COMPENSATION - A circuit including an amplitude detector. The amplitude detector includes an input to receive a signal having an amplitude voltage and a first pair of transistors configured in parallel. The input is coupled to the control terminal of at least one transistor of the first pair. The amplitude detector includes a first node providing a voltage indicative of the amplitude voltage. The first node is in series with each of the first pair of transistors. The circuit includes a compensation circuit. The compensation circuit includes a second pair of transistors configured in parallel and a second node. The second node is coupled in series with each transistor of the second pair. The circuit includes an amplifier including a first amplifier input coupled to the first node and a second amplifier input coupled to the second node. | 2017-11-09 |
20170324378 | RADIO FREQUENCY OSCILLATOR - The embodiments of the invention relate to a radio frequency oscillator, the radio frequency oscillator comprising a resonator circuit resonant at an excitation of the resonator circuit in a differential mode and at an excitation of the resonator circuit in a common mode, wherein the resonator circuit has a differential mode resonance frequency at the excitation in the differential mode, and wherein the resonator circuit has a common mode resonance frequency at the excitation in the common mode, a first excitation circuit configured to excite the resonator circuit in the differential mode to obtain a differential mode oscillator signal oscillating at the differential mode resonance frequency, and a second excitation circuit configured to excite the resonator circuit in the common mode to obtain a common mode oscillator signal oscillating at the common mode resonance frequency. | 2017-11-09 |
20170324379 | SPIKE TRAIN GENERATING CIRCUIT - An oscillator circuit that includes a voltage source, a resistor, a capacitor, and a nonlinear device. The capacitor and the nonlinear device may be coupled in parallel with one another. The resistor may be coupled in series with the capacitor and the nonlinear device. The voltage source may be coupled in series with the resistor. The voltage source may supply the oscillator circuit with a direct current input signal. The nonlinear device may include an active layer coupled to a first electrode and a second electrode. In response to the direct current input signal, the oscillator circuit may output a spike train including a spike bunch. | 2017-11-09 |
20170324380 | POWER CONTROL METHOD, DEVICE AND COMMUNICATION TERMINAL FOR IMPROVING POWER AMPLIFIER SWITCH SPECTRUM - A power control method and device for improving radio-frequency power amplifier (RF PA) switch spectrum, the method comprising the following steps: (a) detecting the gate voltage and drain voltage, or the gate voltage and supply voltage (vdd) of a pass element ( | 2017-11-09 |
20170324381 | TRANSFORMER, POWER MATCHING NETWORK AND DIGITAL POWER AMPLIFIER - A transformer includes: a primary winding comprising a first port, a second port and a metal layer connected between the first port and the second port, the metal layer comprising a plurality of sections of different electrical lengths and/or characteristic impedances; and a secondary winding electromagnetically coupled with the primary winding, the secondary winding comprising a first port, a second port and a metal layer connected between the first port and the second port, the metal layer comprising a plurality of sections of different electrical lengths and/or characteristic impedances. | 2017-11-09 |
20170324382 | SELF-OSCILLATING AMPLIFIER WITH HIGH ORDER LOOP FILTER - A self-oscillating amplifier system is disclosed. The system comprises a pulse modulator, a switching power amplification stage and a demodulation filter. Moreover, the system comprises a compensator including a forward filter which is a high order filter including a second order pole pair and a second order zero pair. Hereby it is possible to decrease the phase turn at low frequencies for better stability and increasing the gain of the control loop within the desired bandwidth. | 2017-11-09 |
20170324383 | CALIBRATION OF PUSH-PULL AMPLIFIER TO A LOW SECOND ORDER DISTORTION - An integrated circuit comprises a first amplifier circuit with a push-pull amplifier configured to be calibrated to a low second order distortion. The integrated circuit further comprises a second amplifier circuit with at least one push-pull amplifier, wherein a size ratio between sizes of the transistors is adjustable by adjusting the size of at least one transistor device. The size ratio can be consecutively adjusted to a plurality of values, and for each value, a first output signal of a push-pull amplifier with an applied test signal and a second output signal of a push-pull amplifier without applied test signal, are determined. The size ratio for which a difference between the push-pull amplifier output signals is closest to zero is determined, and the push-pull amplifier of the first amplifier circuit is calibrated in dependence of the determined size ratio. | 2017-11-09 |
20170324384 | Systems and Methods Using Digital Predistortion to Linearize Radio Transmitter Operation - A method of linearizing a relationship between a signal to an amplifier and an output signal from the amplifier includes applying an inverse of a transfer function of the amplifier to the signal prior to presenting the signal as the amplifier input. The inverse transfer function is represented by a polynomial defined by a set of coefficients. The transmitter output signal is measured by the idle receiver in a time division duplex system. The output signal is filtered to isolate intermodulation products of a selected order and the peak power of the isolated intermodulation products is thenestimated. An adaptive algorithm is applied in response to the estimate of the peak power to update the set of coefficients of the polynomial representing the inverse of the transfer function of the amplifier. | 2017-11-09 |
20170324385 | METHOD, APPARATUS AND SYSTEM FOR BACK GATE BIASING FOR FD-SOI DEVICES - At least one method, apparatus and system disclosed involves providing semiconductor device having transistors comprising back gates and front gates. The semiconductor device comprises a signal processing unit for processing an input signal to provide an output signal. The signal processing unit includes a first transistor and a second transistor. The first transistor includes a first back gate electrically coupled to a first front gate. The signal processing unit also includes a second transistor operatively coupled to the first transistor. The second transistor includes a second back gate electrically coupled to a second front gate. The semiconductor device also includes a gain circuit for providing a gain upon the output signal. The semiconductor device also includes a bias circuit to provide a first bias signal to the first back gate and a second bias signal to the second back gate. | 2017-11-09 |
20170324386 | RF CLASS AB CASCODE AMPLIFIER WITH LINEARIZATION AND STEERING DIODES - Systems and methods for amplifying signals. In some embodiments, the signals may be amplified using a diode steering network with an amplifier operated in class AB mode. In some embodiments, distortion in the amplified signal may be corrected using a feed forward cancellation circuit operated in class A mode. | 2017-11-09 |
20170324387 | INPUT FEED-FORWARD TECHNIQUE FOR CLASS AB AMPLIFIER - An amplifier includes an amplifying stage, a cascoded circuit, an input feed-forward circuit and an output stage. The amplifying stage is arranged receiving a differential input pair to generate an amplified differential input pair. The input feed-forward circuit is coupled to the cascoded circuit, and is arranged for feeding the differential input pair forward to the cascoded circuit. The output stage is coupled to the amplifying stage and the cascoded circuit, and is arranged for generating a differential output pair according to the amplified differential input pair and an output of the cascoded circuit. | 2017-11-09 |
20170324388 | APPARATUS AND METHODS FOR POWER AMPLIFIERS WITH AN INJECTION-LOCKED OSCILLATOR DRIVER STAGE - Apparatus and methods for power amplifiers with an injection-locked oscillator driver stage are provided herein. In certain configurations, a multi-mode power amplifier includes a driver stage implemented using an injection-locked oscillator and an output stage having an adjustable supply voltage that changes based on a mode of the multi-mode power amplifier. By implementing the multi-mode power amplifier in this manner, the multi-mode power amplifier exhibits excellent efficiency, including when the voltage level of the adjustable supply voltage is relatively low. | 2017-11-09 |
20170324389 | HARMONIC FILTER FOR MAGNETIC AMPLIFIER - A magnetic amplifier includes a permeable core having multiple legs. Control windings wound around separate legs are spaced apart from each other and connected in series in an anti-symmetric relation. Harmonic filters are positioned adjacent to the control windings to attenuate even-ordered harmonics generated by an alternating load current passing through a portion of the legs. The control windings are configured to bias magnetic flux arising from a control current flowing through one of the control windings which is substantially equal to the biasing magnetic flux flowing into a second control winding. The flow of the control current through each of the control windings changes the reactance of the permeable core reactor by driving those portions of the permeable core that convey the biasing magnetic flux in the permeable core into saturation. The phasing of the control winding limits a voltage induced in the plurality of control windings caused by a magnetic flux passing around a portion of the permeable core. | 2017-11-09 |
20170324390 | PORTABLE PROGRAMMABLE DEVICE, SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT - There is disclosed a portable programmable device including a battery, a memory and a terminal connectable to earpieces, the device including in the memory a calibration file, parameter or parameters relating to audio sensitivity of the earpieces, the device being configured to play media data including audio, and to provide audio output to the earpieces, the device being further configured to, using the calibration file, parameter or parameters, calculate a noise dose relating to a sound exposure of a user resulting from audio output provided to the earpieces, and to record the noise dose on the device, wherein the device is configured to adjust audio output level in response to: (a) audio content included in played media data; (b) the calibration file, parameter or parameters, and (c) noise dose data of the user recorded on the device. A related method and computer program product are also disclosed. | 2017-11-09 |
20170324391 | IMPEDANCE MATCHING STRUCTURE OF TRANSMISSION LINE - An impedance matching structure is disposed on a circuit board for matching an impedance of a transmission line for transmitting an electronic signal. The structure includes: at least two redundant conducting sections coupled to different points between an input terminal and an output terminal of the transmission line, wherein the redundant conducting sections are apart from one another, and a first terminal of each of the redundant conducting sections is coupled to the transmission line, while a second terminal of each of the redundant conducting sections is apart from the transmission line; and at least one grounded conducting section, each of which corresponds to one of the redundant conducting sections, and surrounds in separation from the corresponding redundant conducting section, wherein each of the at least two redundant conducting sections is disposed in a corresponding plating hole. | 2017-11-09 |
20170324392 | SELF-ADJUSTING ELECTROMAGNETIC COUPLER WITH AUTOMATIC FREQUENCY DETECTION - Electromagnetic coupler systems including built-in frequency detection, and modules and devices including such. One example of an electromagnetic coupler system include an electromagnetic coupler having an input port, an output port, a coupled port, and an isolation port, the electromagnetic coupler including a main line extending between the input port and the output port, and a coupled line extending between the coupled port and the isolation port, the electromagnetic coupler being configured to produce a coupled signal at the coupled port responsive to receiving an input signal at the input port. An adjustable termination impedance is connected to the isolation port. A frequency detector is connected to the adjustable termination impedance and to the coupled port, and configured to detect a frequency of the coupled signal and provide an impedance control signal to tune the adjustable termination impedance based on the frequency of the coupled signal. | 2017-11-09 |
20170324393 | Radio Frequency Duplexer - A radio frequency duplexer with a first directional coupler configured to divide an input reception signal into a first auxiliary reception signal and a second auxiliary reception signal, where the first auxiliary reception signal and the second auxiliary reception signal comprise signal components at a reception frequency, a first filter configured to filter the first auxiliary reception signal to obtain a third auxiliary reception signal, a second filter configured to filter the second auxiliary reception signal to obtain a fourth auxiliary reception signal, where pass bands of the first and the second filters comprise the reception frequency, a second directional coupler configured to combine the third auxiliary reception signal with the fourth auxiliary reception signal to obtain an output reception signal. | 2017-11-09 |
20170324394 | SAW TRANSDUCER WITH SUPPRESSED MODE CONVERSION - A transducer for SAW-type or PSAW-type acoustic waves is proposed in which the dielectric (DK) is applied onto the substrate so that the gap (GP) between the ends of the electrode fingers and the opposite bus electrode is completely filled with said dielectric (DK), but the active area of the transducer, thus transversal overlap area (UB) of the electrode fingers, is not covered by said dielectric. | 2017-11-09 |
20170324395 | STACKED WAFER-LEVEL PACKAGING DEVICES - Stacked wafer-level packaging devices. In some embodiments, a wireless device includes a transceiver configured to generate a radio-frequency (RF) signal. The wireless device also includes a front-end module (FEM) in communication with the transceiver, the front-end module including a packaging substrate configured to receive a plurality of components, the front-end module further including a stacked assembly implemented on the packaging substrate, the stacked assembly including a first wafer-level packaging (WLP) device having a radio-frequency (RF) shield, the stacked assembly further including a second wafer-level packaging device having an RF shield, the second wafer-level packaging device positioned over the first wafer-level packaging device such that the RF shield of the second wafer-level packaging device is electrically connected to the RF shield of the first wafer-level packaging device. The wireless devices further includes an antenna in communication with the front-end module, the antenna configured to transmit the amplified radio-frequency signal. | 2017-11-09 |
20170324396 | PIEZOELECTRIC COMPONENT - A piezoelectric component includes a support substrate; a piezoelectric element having both ends fixed to the support substrate, so as to be oscillatable; a pair of terminal electrodes located below the ends of the piezoelectric element, respectively; a pair of capacitance-forming electrodes each having a greater width than the piezoelectric element, extending from the pair of terminal electrodes, respectively, toward a center of the piezoelectric element; and excitation electrodes disposed on a first principal surface and a second principal surface of the piezoelectric element, respectively, the excitation electrodes facing each other so that a facing region in which the excitation electrodes overlap with each other as seen in a transparent plan view is defined therebetween, at least part of a region of the pair of capacitance-forming electrodes which protrudes outside the facing region in a width direction thereof as seen in a plan view, being covered with an insulating film. | 2017-11-09 |
20170324397 | ACOUSTIC WAVE DEVICE - An acoustic wave device includes: a substrate; a piezoelectric film located on the substrate; a lower electrode and an upper electrode facing each other across at least a part of the piezoelectric film; a silicon oxide film located at an opposite side of at least one of the lower electrode and the upper electrode from the piezoelectric film; a first insulating film that is located between the at least one of the lower electrode and the upper electrode and the silicon oxide film and includes a non-oxygen-containing material; and an additional film located at an opposite side of the silicon oxide film from the first insulating film and made of a material different from a material of the silicon oxide film and a material of the first insulating film. | 2017-11-09 |
20170324398 | SAW DEVICE AND METHOD FOR MANUFACTURING SAW DEVICE - A SAW device includes a SAW element, a conductor connected to the SAW element, an LT substrate including the SAW element, and a case for housing the LT substrate including the SAW element. The case includes a cover part, a lateral part, and a bottom part. The bottom part is including a sapphire substrate, the LT substrate is positioned on a first surface of the sapphire substrate, the first surface serving as an inner surface of the case, and a second surface opposite to the first surface serves as an outer surface of the case. The conductor includes a via conductor provided in a through-hole continuously penetrating through the sapphire substrate and the LT substrate. | 2017-11-09 |
20170324399 | SEMICONDUCTOR INTEGRATED CIRCUIT - An object of the present invention is to reduce burden on a program for changing an operation mode of an internal circuit in accordance with an internal clock frequency without mounting a large-scale circuit in an LSI in which setting of the frequency of an internal clock can be dynamically changed. In an LSI including an internal clock generation circuit generating an internal clock from a clock source in accordance with a parameter supplied, a register storing frequency information of the clock source, a register storing the parameter, and an internal circuit having a plurality of operation modes, a table circuit controlling the operation mode of the internal circuit in association with the frequency information and the parameter supplied from the registers is provided. | 2017-11-09 |
20170324400 | FLEXIBLE RIPPLE MODE DEVICE IMPLEMENTATION FOR PROGRAMMABLE LOGIC DEVICES - Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and a plurality of logic cells within at least one of the PLBs, where each logic cell includes a four input lookup table (4-LUT) configured to provide a 4-LUT output signal to associated carry logic. Each logic cell is configurable according to at least two selectable operational modes including a logic function output mode and a ripple arithmetic output mode, and at least three of the 4-LUT inputs are interchangeable when a selected operational mode comprises the ripple arithmetic output mode. | 2017-11-09 |
20170324401 | MULTIPLE MODE DEVICE IMPLEMENTATION FOR PROGRAMMABLE LOGIC DEVICES - Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and at least first and second logic cells within at least one of the PLBs, where each logic cell includes a lookup table (LUT) and associated mode logic configured to receive a LUT output signal from the LUT. The associated mode logic is configured to use a single physical signal output to provide a logic cell output signal corresponding to a selected logic function operational mode, ripple arithmetic operational mode, or extended logic function operational mode for each logic cell. | 2017-11-09 |
20170324402 | POWER EFFICIENT HIGH SPEED LATCH CIRCUITS AND SYSTEMS - The present invention relates to a combiner latch circuit for generation of one phase differential signal pair or two phase differential signal pairs. The combiner latch circuit comprises an input circuit configured to select a state of the output circuit from a group of: a fourth state comprising the differential output X=1, Y=0, a fifth state comprising the differential output X=0, Y=1. The input circuit is further configured to select the fourth state if the input A=0 and the input B=1 and the clock input encounter a leading edge from 0 to 1 and the output circuit is in the fifth state, and select the fifth state if the input A=1 and the input B=0 and the clock input encounter a leading edge from 0 to 1 and the output circuit is in the fourth state. | 2017-11-09 |
20170324403 | PULSE COUNTING CIRCUIT - A pulse counting circuit receives pulses supplied by a source circuit having at least two inverted pulse signal supply terminals. The circuit includes a first counter to count pulses of a first pulse signal and supply a first count and a second counter to count pulses of a second pulse signal and supply a second count. A selection circuit selects one of the first and second counts. | 2017-11-09 |
20170324404 | SIGNAL CALCULATOR - Examples of a signal calculator include a voltage multiplier and a time divider. The voltage multiplier copies time information corresponding to a first voltage and generates a third voltage using a second current corresponding to a second voltage during a first period corresponding to the copied time information. The time divider generates an output according to a result of comparing a voltage generated by a first current on the basis of a voltage corresponding to a first time with a second voltage corresponding to a second time. | 2017-11-09 |
20170324405 | MULTIPLEXER STRUCTURE - A logic two-to-one multiplexer includes: two input terminals; one output terminal; a control terminal. Four series-connected two-to-one multiplexers are connected such that a first multiplexer has its inputs connected to the input terminals, a last multiplexer has its output connected to the output terminal, and the other multiplexers have their respective inputs interconnected to the output of the previous multiplexer in the series association. Half of the multiplexers are controlled in reverse with respect to the other half of the multiplexers. | 2017-11-09 |
20170324406 | BRIDGE LEG CIRCUIT ASSEMBLY AND FULL-BRIDGE CIRCUIT ASSEMBLY - A bridge leg circuit assembly comprising: a circuit board, a first active switch die, and a second active switch die. The circuit board having an insulating plate with a first and second side and a first and second conducting layer on the first and second sides of the insulating plate, respectively. The second conducting layer having a first and second conducting region that are insulated from each other. The first active switch die having an opposing first side, facing and coupled with the first conducting region, and an opposing second side, coupled with the second conducting region, which are embedded into the circuit board. The second active switch die having an opposing first side, coupled with the second conducting region, and an opposing second side, coupled with the first conducting layer, which are embedded into the circuit board. | 2017-11-09 |
20170324407 | Radio Frequency Switching Circuit with Distributed Switches - An RF switching device having distributed shunt switches distributed along transmission lines to improve RF bandwidth as well as the signal isolation of the device. The shunt switches may be physically positioned on both sides of the transmission lines to keep an integrated circuit (IC) design essentially symmetrical so as to provide predictable and reliable operational characteristics. Some embodiments include stacked FET shunt switches and series switches to tolerate high voltages. In some embodiments, the gate resistor for each FET shunt switch is divided into two or more portions. | 2017-11-09 |
20170324408 | MIXING MODULE AND CAPACITIVE TOUCH PANEL - A mixing module ( | 2017-11-09 |
20170324409 | GENERATOR OF NUMBERS OF OSCILLATIONS - A circuit generates a number of oscillations. The circuit includes a first branch with at least one delay line introducing symmetrical delays on rising edges and on falling edges and at least one asymmetrical delay element introducing different delays on rising edges and on falling edges. The circuit further includes a second branch looped back on the first branch and including at least one delay line introducing symmetrical delays on rising edges and on falling edges. | 2017-11-09 |
20170324410 | CLOCK GATING CIRCUIT OPERATES AT HIGH SPEED - A clock gating circuit includes a first precharge unit charging a first node based on a clock signal, a second precharge unit charging a second node based on the clock signal, a first discharge unit discharging the first node based on the clock signal, a second discharge unit discharging the second node based on the clock signal, a first cross-coupled maintain unit maintaining the first node at a charge state according to a voltage level of the second node, a second cross-coupled maintain unit maintaining the second node at a charge state according to a voltage level of the first node, and a control unit controlling the first and second discharge units to discharge the first node or the second node on the basis of a clock enable signal. | 2017-11-09 |
20170324411 | VOLTAGE CONVERTER INTEGRATED CIRCUIT WITH AN INTEGRATED BOOTSTRAP CAPACITOR - A bootstrap circuit integrated to a voltage converter integrated circuit (IC) and a voltage converter IC for a switch mode voltage regulator. The bootstrap circuit is used to provide a bootstrap voltage signal for driving a high side switch of the voltage converter IC. The bootstrap circuit has a pre-charger and a bootstrap capacitor. The pre-charger provides a first bootstrap signal to pre-charge a control terminal of the high side switch, and the bootstrap capacitor provides a second bootstrap signal to enhance the charge of the control terminal of the high side switch. | 2017-11-09 |
20170324412 | Electronic Device and Associated Signal Processing Method - An electronic device includes a transmission interface, a driving circuit, a receiving circuit, a sampling circuit, a detecting circuit, a timing control circuit and a processing circuit. The transmission interface is for connecting to another electronic device via a connecting cable. The driving circuit outputs a backward signal via the transmission interface to the another electronic device. The receiving circuit receives a received signal including the backward signal and a forward signal from the transmission interface. The sampling circuit samples the received signal to obtain a plurality of sample results. The detecting circuit detects transitions of the sample results to obtain a plurality of detection results. The processing circuit generates a control signal according to the detection results, and adjusts a time point at which the driving circuit outputs the backward signal through the timing control circuit. | 2017-11-09 |
20170324413 | SEMICONDUCTOR CIRCUITS - A semiconductor circuit includes a first circuit and a second circuit. The first circuit is configured to generate a voltage level at a first node based on a voltage level of input data, an inverted value of the voltage level at the first node, a voltage level of a clock signal, and a voltage level at a second node; and the second circuit is configured to generate the voltage level at the second node based on the voltage level of input data, an inverted value of the voltage level at the second node, the voltage level of the clock signal, and the inverted value of the voltage level at the first node. When the clock signal is at a first level, the first and second nodes have different logical levels. When the clock signal is at a second level, the first and second nodes have the same logical level. | 2017-11-09 |
20170324414 | MULTI-STAGE FREQUENCY DIVIDERS AND POLY-PHASE SIGNAL GENERATORS - An electronic latch circuit, a 4-phase signal generator, a multi-stage frequency divider and a poly-phase signal generator are disclosed. The electronic latch circuit comprises an output circuit comprising a first output and a second output. The electronic latch circuit further comprises an input circuit comprising a first input, a second input and a clock signal input. The electronic latch circuit is configured to change state based on the input signals' level at the inputs of the input circuit and a present state of the output circuit. The 4-phase signal generator is built with two electronic latch circuits. The multi-stage frequency dividers and poly-phase signal generators comprise a plurality of the electronic latch circuits and 4-phase signal generators. | 2017-11-09 |
20170324415 | BIDIRECTIONAL GRAY CODE COUNTER - Apparatuses, systems and methods associated with bidirectional Gray code counter design are disclosed herein. In embodiments, a bidirectional Gray code counter may include a sequential logic element to store a Gray code value and logic circuitry. The logic circuitry may be to determine, based on a bidirectional indicator signal, whether to increment or decrement the Gray code value update, through performance of an increment or a decrement of the Gray code value based on the determination of whether to increment or decrement the Gray code value, the Gray code value to be a sequential Gray code value and replace the Gray code value stored in the sequential logic element with the updated Gray code value. Other embodiments may be described and/or claimed. | 2017-11-09 |
20170324416 | SUB-SAMPLING PHASE-LOCKED LOOP - A sub-sampling phase-locked loop is described, which comprises a digital-to-time converter, a sampler module, an interpolator, and a voltage controlled oscillator. The digital-to-time converter is configured to provide a first delay signal (S | 2017-11-09 |
20170324417 | Downshift Techniques for Oscillator with Feedback Loop - Techniques are disclosed relating to rapidly downshifting the output frequency of an oscillator. In some embodiments, the oscillator is configured to operate in a closed-loop mode in which negative feedback is used to maintain a particular output frequency (e.g., in a phase-locked loop (PLL)). In some embodiments, the negative feedback loop is configured to maintain the output of the oscillator at a particular frequency based on a reference clock signal and the output of the oscillator. The nature of a negative feedback loop may render rapid frequency changes difficult, e.g., because of corrections by the loop. Therefore, in some embodiments, the loop is configured to switch to an open-loop mode in which a control input to the oscillator is fixed. In some embodiments, the loop switches to open-loop mode in response to a trigger signal and control circuitry forces the oscillator to a new target frequency. | 2017-11-09 |
20170324418 | Frequency Synthesizing Device and Automatic Calibration Method Thereof - A frequency synthesizing device includes a voltage-controlled oscillator receiving an adjusting signal and generating an output signal according to the adjusting signal. A feedback frequency divider having a plurality of divisor values receives the output signal and generates a feedback signal after performing frequency dividing. An automatic frequency calibration circuit of the frequency synthesizing device includes a first frequency divider receiving a reference frequency, and a second frequency divider receiving the feedback signal. A comparator of the automatic frequency calibration circuit receives and compares outputs from the first frequency divider and the second frequency divider in a predetermined period to generate a comparing result. A state machine outputs the adjusting signal according to the comparing result in a calibration mode. | 2017-11-09 |
20170324419 | APPARATUS AND METHODS FOR PHASE SYNCHRONIZATION OF PHASE-LOCKED LOOPS - Apparatus and methods for phase synchronization of phase-locked loops (PLLs) are provided. In certain configurations, an RF communication system includes a PLL that generates one or more output clock signals and a phase synchronization circuit that synchronizes a phase of the PLL. The phase synchronization circuit includes a sampling circuit that generates samples by sampling the one or more output clock signals based on timing of a reference clock signal. Additionally, the phase synchronization circuit includes a phase difference calculation circuit that generates a phase difference signal based on the samples and a tracking digital phase signal representing the phase of the PLL. The phase synchronization circuit further includes a phase adjustment control circuit that provides a phase adjustment to the PLL based on the phase difference signal so as to synchronize the PLL. | 2017-11-09 |
20170324420 | WIDEBAND POLAR RECEIVER ARCHITECTURE AND SIGNAL PROCESSING METHODS - Wideband polar receivers and method of operation are described. A phase-modulated input signal is received at a polar receiver that includes an injection-locked oscillator. The injection-locked oscillator includes a plurality of injection points. Based on the frequency of the input signal, a particular Nth harmonic is selected, and the input signal is injected at the set of injection points corresponding to the selected Nth harmonic. The injection-locked oscillator generates an oscillator output signal, and the phase of the input signal is determined from the phase of the oscillator output signal. In some embodiments, the oscillator output signal is frequency-multiplied by N, mixed with the input signal, and filtered for use in amplitude detection. The input signal is decoded based on the phase and amplitude information. | 2017-11-09 |
20170324421 | METHODS AND APPARATUS TO REDUCE NON-LINEARITY IN ANALOG TO DIGITAL CONVERTERS - Methods and apparatus for reducing non-linearity in analog to digital converters are disclosed. An example apparatus includes an analog-to-digital converter to convert an analog signal into a digital signal; and a non-linearity corrector coupled to the analog-to-digital converter to determine a derivative of the digital signal; determine cross terms including a combination of the digital signal and the derivative of the digital signal; and determine a non-linearity term corresponding to a combination of the cross terms. | 2017-11-09 |
20170324422 | BUILT IN SELF-TEST - A method for testing a DAC comprising controlling the DAC digitally to cause it to produce a known desired analogue output, for example a fixed amplitude sine wave; determining the duration of fixed voltage segments of the actual output of the DAC and using the duration of the fixed voltage segments to assess or determine performance of the DAC. | 2017-11-09 |
20170324423 | DIGITAL DOWN CONVERTER - A digital down converter includes a low resolution mixer, a decimation filter, and a high resolution mixer. The low resolution mixer is configured to receive a digitized radio frequency signal, and apply a first down conversion to the radio frequency signal to produce an intermediate frequency signal. The decimation filter is coupled to the low resolution mixer. The decimation filter is configured to receive the intermediate frequency signal, and reduce a sampling rate of the intermediate frequency signal to produce a decimated intermediate frequency signal. The high resolution mixer is coupled to the decimation filter. The high resolution mixer is configured to receive the decimated intermediate frequency signal, and apply a second down conversion to the decimated intermediate frequency signal to produce a down converted signal. | 2017-11-09 |
20170324424 | TRANSMITTING APPARATUS AND INTERLEAVING METHOD THEREOF - A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to perform a low-density parity check (LDPC) encoding on input bits using a parity check matrix to generate an LDPC codeword comprising information word bits and parity bits; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol. | 2017-11-09 |
20170324425 | EMBEDDED PARITY MATRIX GENERATOR - A circuit, including an embedded parity matrix generator configured to generate a parity matrix for a data word of any data width; an encoder configured to add a redundancy word to the data word based on the parity matrix; a sub-circuit coupled to the encoder, and configured to receive the data word and the redundancy word from the encoder; and a decoder coupled to the sub-circuit, and configured to receive the data word and the redundancy word from the sub-circuit, and to detect any errors in the data word based on the parity matrix. | 2017-11-09 |
20170324426 | LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 64800 AND CODE RATE OF 2/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME - A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 2/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM). | 2017-11-09 |
20170324427 | TRANSMITTING APPARATUS AND INTERLEAVING METHOD THEREOF - A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol. | 2017-11-09 |
20170324428 | Data Packet Processing Method and Device - A packet processing method and device are disclosed. The method includes: performing code block segmentation on a source packet to obtain a sub-packets; performing error correction encoding on each sub-packet respectively, or performing error correction encoding after respectively adding a CRC sequence to each sub-packet to obtain a error correction encoding sub-packets; performing network encoding on the a error correction encoding sub-packet to obtain b check sub-packets; and performing bit selection operation on the a error correction encoding sub-packets and the b check sub-packets respectively to collectively form an encoded packet; herein a and b are integers greater than 0. | 2017-11-09 |
20170324429 | ENCODER, DECODER AND ENCODING METHOD WITH LOW ERROR FLOOR - Disclosed herein is an encoder for encoding digital data, said encoder comprising one or more component encoders, one or more interconnections between component encoders, one or more inputs and one or more outputs. The encoder is configured to carry out the following steps:—combining internal input bits received via an interconnection and external input bits received via a corresponding input, to assemble a local information word,—encoding the local information word such as to generate a local code word,—outputting a reduced local code word and handing the same reduced local code word over to said interconnect for forwarding said same reduced local code word via said interconnect to another component encoder or to itself, wherein said encoder is configured to forward on each interconnect the bits of the reduced local code in parallel but with delays that are mutually different for at least a subset of the reduced local code word bits. | 2017-11-09 |
20170324430 | Systems and Methods for Data Processing With Folded Parity Sector - An apparatus for processing data includes a decoder configured to iteratively decode codewords in a data block representing a number of user data sectors, the codewords including user data, folded parity sector data and error correction code parity bits. The folded parity sector data includes a number of parity checks, each with multiple user data bits from each of the data sectors, and with an offset between each of the user data bits from the data sectors determined at least in part by a number of folds in the data sectors. The apparatus also includes a scheduler configured to control decoding of the codewords based at least in part on the folded parity sector data. | 2017-11-09 |
20170324431 | Circuit arrangement and method for attenuation compensation in an antenna signal link - A circuit arrangement for compensating for an attenuation occurring in an antenna signal link between a mobile radio terminal and an antenna has at least one antenna signal amplifier in the antenna signal link and a control unit for adjusting a gain factor. The antenna signal conducted through an associated antenna signal amplifier is amplified or attenuated. The circuit arrangement has a detection unit for detecting an antenna signal power (P | 2017-11-09 |
20170324432 | Multiple Band Multiple Mode Transceiver Front End Flip-Chip Architecture and Circuitry with Integrated Power Amplifiers - An integrated circuit architecture and circuitry is defined by a die structure with a plurality of exposed conductive pads arranged in a grid of rows and columns. The die structure has a first operating frequency region with a first transmit and receive chain, and a second operating frequency region with a second transmit chain and a second receive chain. There is a shared region of the die structure defined by an overlapping segment of the first operating frequency region and the second operating frequency region with a shared power supply input conductive pad connected to the first transmit chain, the second transmit chain, the first receive chain, and the second receive chain, and a shared power detection output conductive pad connected to the first transmit chain and the second transmit chain. | 2017-11-09 |
20170324433 | METHOD AND DEVICE FOR TRANSMITTING AND RECEIVING INTER-CELL INFORMATION FOR CANCELLING INTER-CELL INTERFERENCE - Provided are a method and a device for transmitting and receiving inter-cell information for cancelling inter-cell interference in a wireless communication system. The method for transmitting and receiving inter-cell information may comprise the steps of: taking a PMI set which is a set of PMIs of a signal generating interference to an area partitioned in a predetermined direction and transmitting same to the base station of an adjacent cell transmitting the signal generating interference; and receiving, from the base station of the adjacent cell, PMI information on at least one of the PMIs included in the PMI set. | 2017-11-09 |
20170324434 | AMPLITUDE DOMAIN CIRCUITS AND METHODS FOR REDUCING AN INTERFERENCE SIGNAL THAT SPECTRALLY OVERLAPS A DESIRED SIGNAL - Under one aspect, a method for reducing interference in a received signal can include splitting a received signal into a first portion and a second portion, the received signal comprising a desired signal and an interference signal that spectrally overlaps the desired signal. The method also can include estimating an amplitude A(t) of the first portion as a function of time. The method also can include suppressing at least a portion of the interference signal in the estimated amplitude A(t) to generate an interference suppressed amplitude A′(t). The method also can include delaying the second portion by an amount of time corresponding to the estimation and suppression. The method also can include multiplying the interference suppressed amplitude A′(t) by the delayed second portion to obtain an output having reduced contribution from the interference signal. | 2017-11-09 |
20170324435 | DC offset cancellation method and device - Disclosed is a DC offset cancellation (DCOC) method, comprising: after a receiver is electrified, acquiring a digital signal of an offset voltage at a circuit output port in the receiver, obtaining a digital control signal for controlling a DCOC output stage from the digital signal, and outputting, by the DCOC output stage, a current to a corresponding circuit of the receiver according to the digital control signal. Also disclosed is a DC offset cancellation device. | 2017-11-09 |
20170324436 | METHOD AND APPARATUS FOR RECEIVING DIGITAL RADIO FREQUENCY (RF) SIGNAL - Disclosed is a digital radio frequency (RF) signal receiving apparatus including an RF filter configured to convert multichannel wireless signals received through an antenna into signals available for digital sampling, an analog-to-digital converter configured to perform digital sampling on the multichannel wireless signals converted by the RF filter, a digital processor configured to perform filtering on each of the digital-sampled multichannel wireless signals into a plurality of bandwidth signals within a maximum bandwidth range simultaneously, and down-convert the filtered multichannel wireless signals to be signals in a baseband, a data formatter configured to format the down-converted signals based on an input/output data form of transmission interfaces, and a data transmitter configured to simultaneously transmit each of formatted signals to a corresponding processing platform. | 2017-11-09 |
20170324437 | SMART AVIATION COMMUNICATION HEADSET AND PERIPHERAL COMPONENTS - In one embodiment, an aviation communication headset includes, but is not limited to, at least one microphone; one or more speakers; one or more docks configured to interface with one or more eyepieces; and at least one control unit operable to perform operations including at least: detecting a presence of one or more eyepieces at the one or more docks; and outputting aviation flight information via the one or more docks for display on the one or more eyepieces. | 2017-11-09 |
20170324438 | LIGHTING DEVICE WITH LIGHTS ON ROTATABLE PANELS FOR MOBILE ELECTRONIC DEVICES - A photography lighting device that provides a lighting source to a mobile electronic device. The mobile electronic device includes a front facing camera and a rearward facing camera. The lighting device includes a first light source movable from a first position to a second position. The first light source is rearward facing in the first position to provide illumination for the rearward facing camera. The first light source is forward facing in the second position to provide illumination for the forward facing camera. The lighting device further includes a second light source movable from a first position to a second position. The second light source is rearward facing in the first position to provide illumination for the rearward facing camera. The second light source is forward facing in the second position to provide illumination for the forward facing camera. | 2017-11-09 |
20170324439 | FLEXIBLE RADIO ASSIGNMENT - A flexible radio assignment algorithm that reduces co-channel interference in Wi-Fi networks is disclosed. The flexible radio assignment algorithm calculates a density value for each of the APs controlled by a network controller. The flexible radio assignment algorithm selects an AP with the highest density value and determines that a radio in the selected AP is redundant. The flexible radio assignment algorithm manages the redundant radio in the selected AP to mitigate co-channel interference in a frequency band. | 2017-11-09 |
20170324440 | SYSTEMS AND METHODS FOR SIGNAL DETECTION AND DIGITAL BANDWIDTH REDUCTION IN DIGITAL PHASED ARRAYS - Methods and systems are provided including a system for signal detection and digital bandwidth reduction in a phased array comprising a digital phased array receiving system, digital beamforming network, and central system-level processing system. In at least one embodiment, a system for signal detection and digital bandwidth reduction in a phased array is provided that includes a digital phased array receiving and transmitting system, a plurality of digital processing nodes, transceivers, and a core processing node, and a plurality of digital beamforming nodes. The exemplary the digital processing nodes including control sections that each perform preprocessing to identify signals with predetermined signal characteristics. The exemplary said preprocessing further includes selecting reflected signals received by the digital phased array receiving and transmitting system having one or more of the predetermined signal characteristics. The selected reflected signals reduced in size and passed to the core processing node with radar data sets. | 2017-11-09 |
20170324441 | COMMUNICATION DEVICE AND METHOD IN THE CELLULAR BAND - A wireless communication method in a network comprising a plurality of nodes including ranging masters, broadcasting a chirp-modulated ranging requests, and ranging slaves slave, replying with thereto with chirp-modulated ranging responses, whereby mobile nodes can locate themselves passively by listening to the request/reply exchanges, based on the respective time differences of arrival. | 2017-11-09 |
20170324442 | COMMUNICATION PROCESS AND SYSTEM FOR HIGH-SENSITIVITY AND SYNCHRONOUS DEMODULATION SIGNALS - The communication process for high-sensitivity and synchronous demodulation signals between a transmitter ( | 2017-11-09 |
20170324443 | SCHEDULED COMMUNICATION WITH RESOURCE PROVIDERS AND A HOME AREA NETWORK - Systems and methods are disclosed for providing scheduled communication between a primary network, such as a time synchronized channel hopping (“TSCH”) network, and a secondary network, such as a carrier sense multiple access (“CSMA”) network. During a first selected slot-offset in a TSCH hopping pattern, a gateway node communicates with a primary network node. During a second selected slot-offset in the TSCH hopping pattern, the gateway node communicates with a secondary network node. A communication schedule identifies the source and destination nodes and channel frequency for each slot-offset. The communication schedule is set such that the CSMA wake-up period for the secondary network is synchronized with the second slot-offset in the TSCH hopping pattern. | 2017-11-09 |
20170324444 | COMMUNICATIONS NETWORK - An optical network is disclosed which includes an optical fiber shared by a plurality of transmitters using code division multiple access techniques. The transmitters are connected by tributary optical fibers to the shared optical fiber. In code division multiple access techniques, each communication is encoded with a distinctive code which enables a receiver to extract the communication intended for it from amongst communications intended for other receivers. It is found that synchronizing the communications on the optical fiber improves the ability of a receiver to extract the communication intended for it. Injecting an optical pulse signal into the optical network, and using the tributary optical fibers to carry the clock signal to the transmitters provides an inexpensive method of synchronizing the transmitters which feed signals onto the optical fiber. The technology is of use in optical networks, and other transmission line networks, and is well-suited to use in local area networks. | 2017-11-09 |
20170324445 | DRIVE CONTROL DEVICE AND DRIVE CONTROL SYSTEM COMPRISING SAME - According to an aspect of the present invention, a drive control system is provided that includes a transmitting apparatus and a plurality of drive control apparatuses and drives and controls a plurality of devices to be controlled, wherein the transmitting apparatus includes: a control information addition apparatus that frequency-multiplexes a plurality of control signals, and an electric wire that supplies power and the plurality of control signals to the plurality of drive control apparatuses. | 2017-11-09 |
20170324446 | Contactless Interface for mm-wave Near Field Communication - A system is provided in which a first waveguide has a first resonator coupled to an end of the first waveguide. A second waveguide has a second resonator coupled to the second waveguide. The first resonator is spaced apart from the second resonator by a gap distance. Transmission of a signal propagated by the first waveguide across the gap to the second waveguide is enhanced by a confined near field mode magnetic field produced by the first resonator in response to the propagating wave that is coupled to the second resonator. | 2017-11-09 |
20170324447 | WIRELESS POWER TRANSMITTING DEVICE AND METHOD - The present invention relates to a wireless power transmitting device and method which are configured to: transmit a first state confirmation signal through a first transmitting method; transmit power through the first transmitting method when a first state response signal corresponding to the first state confirmation signal is received; and transmit a second state confirmation signal through a second transmitting method when the first state response signal is not received. According to the present invention, the wireless power transmitting device alternatingly uses the first transmitting method and the second transmitting method, and the existence of a wireless power receiving device and a receiving method thereof can be detected. | 2017-11-09 |
20170324448 | System for Wireless Charging of a Plurality of Devices - A master unit for wirelessly charging a slave device includes a plurality of radio frequency integrated circuit (RFIC) modules, each of the plurality of RFIC modules having an antenna array. The master unit is configured to select one of a single beam mode by using all or substantially all antenna arrays in the plurality of RFIC modules, a multi-beam mode by using each respective antenna array in each of the RFIC modules to form a separate beam from each RFIC module, and a customized beam pattern mode by using a customized combination of antennas in selected ones of the plurality of RFIC modules. The master unit is configured to dynamically select from one of the single beam mode, the multi-beam mode, and the customized beam pattern mode based on a location of the slave device relative to the master unit. | 2017-11-09 |
20170324449 | Methods and Apparatus for Determining Nearfield Localization Using Phase and RSSI Delivery - Methods and apparatus to determine nearfield localization using phase and received signal strength indication (RSSI) diversity are disclosed. An example method includes determining a first strength of an electric field and a second strength of a magnetic field, the electric field and the magnetic field associated with an electromagnetic signal sent from a transmitter; determining a difference between the first strength and the second strength; and determining a transmitter distance based on the difference between the first strength and the second strength. | 2017-11-09 |
20170324450 | WIRELESS POWER TRANSMISSION APPARATUS, WIRELESS POWER RECEPTION APPARATUS, AND WIRELESS CHARGING SYSTEM - The present disclosure relates to a wireless power transmitter, a wireless power receiver, and a wireless charging system, in the field of wireless power transmission. A wireless power transmitter configured to transmit wireless power to a wireless power receiver, according to the present invention, comprises: first and second coils which are arranged so that any one of the first and second coils winds around the other one of the first and second coils; a shielding unit having a plurality of shielding members which are sequentially arranged to be spaced apart from one another along the circumference of at least one of the first and second coils so as to form a radial shape; and a control unit adapted to control the first and second coils so that the wireless power is supplied to the wireless power receiver through at least one of the first and second coils. | 2017-11-09 |
20170324451 | COMPENSATING AMPLIFIER PHASE IN A DIVERSITY RECEIVER FRONT END - Diversity receiver front end system with amplifier phase compensation. A receiving system can include a first amplifier disposed along a first path, corresponding to a first frequency band, between an input of the receiving system and an output of the receiving system. The receiving system can include a second amplifier disposed along a second path, corresponding to a second frequency band, between the input of the receiving system and the output of the receiving system. The receiving system can include a first phase-shift component disposed along the first path and configured to phase-shift the second frequency band of a signal passing through the first phase-shift component based on a phase-shift caused by the first amplifier at the second frequency band. | 2017-11-09 |
20170324452 | USER TERMINAL, RADIO BASE STATION, RADIO COMMUNICATION SYSTEM, AND RADIO COMMUNICATION METHOD - An object is to enable proper operation of extended carrier aggregation that can allocate at least six component carriers to each user terminal. Provided is a user terminal that communicates with a radio base station that configures a plurality of cell groups each of which including one or more cells. The user terminal includes: a control unit that controls six or more component carriers configured by the radio base station; and a transmitting/receiving unit that receives information on a plurality of component carriers configured by the radio base station and feedbacks ACK/NACK information to one of the component carriers in each cell group. | 2017-11-09 |