45th week of 2021 patent applcation highlights part 57 |
Patent application number | Title | Published |
20210351148 | BONDED BODY AND MANUFACTURING METHOD OF BONDED BODY - A bonded body includes: a first base body including a first wiring, a first electrode made of an electroplating film and including a first surface having a first region covering a periphery of an end portion of the first wiring and a second region covering the end portion of the first wiring, and a first passivation layer made of an insulating material and covering a periphery of the first electrode; a second base body including a second electrode; and solder disposed between the first region of the first electrode and the second electrode. | 2021-11-11 |
20210351149 | Semiconductor Package and Method of Forming the Same - A method of forming a semiconductor package includes receiving a carrier, coating the carrier with a bonding layer, forming a first insulator layer over the bonding layer, forming a backside redistribution layer over the first insulator layer, forming a second insulator layer over the backside redistribution layer, patterning the second insulator layer to form a recess that extends through the second insulator layer and to the backside redistribution layer, filling the recess with a solder, and coupling a surface-mount device (SMD) to the solder. | 2021-11-11 |
20210351150 | Semiconductor Package and Method for Fabricating the Semiconductor Package - Provided are a semiconductor package and a method for fabricating the semiconductor package. The method includes followings steps: a first workpiece is provided, where the first workpiece includes a first substrate and multiple first rewiring structures arranged on the first substrate at intervals, and each first rewiring structure includes at least two first rewiring layers; an encapsulation layer is formed on the first rewiring structures, where the encapsulation layer is provided with multiple first through holes, and the first through holes exposes one first rewiring layer; at least two second rewiring layers are disposed on a side of the encapsulation layer facing away from the first rewiring layer; multiple semiconductor elements are provided, where the semiconductor elements are arranged on a side of the first rewiring structures facing away from the encapsulation layer, where the first rewiring layers are electrically connected to pins of the semiconductor elements. | 2021-11-11 |
20210351151 | Circuit Carrier Having an Installation Place for Electronic Components, Electronic Circuit and Production Method - Various embodiments include a circuit carrier comprising: an installation place for an electronic component; and a deposit of a joining adjuvant applied to the installation place. The installation place has at an edge, a recess forming a depression in a surface of the circuit carrier. The deposit comprises a sintered material with a protuberance at an edge of the deposit. | 2021-11-11 |
20210351152 | CAPACITOR DIE FOR STACKED INTEGRATED CIRCUITS - An apparatus is provided that includes a die stack having a first die and a second die disposed above a substrate, and a capacitor die disposed in the die stack between the first die and the second die. The capacitor die includes a plurality of integrated circuit capacitors that are configured to be selectively coupled together to form a desired capacitor value coupled to at least one of the first die and the second die. | 2021-11-11 |
20210351153 | BONDING WIRE, SEMICONDUCTOR PACKAGE INCLUDING THE SAME, AND WIRE BONDING METHOD - A bonding wire for connecting a first pad to a second pad is provided. The bonding wire includes a ball part bonded to the first pad, a neck part formed on the ball part, and a wire part extending from the neck part to the second pad. Less than an entire portion of a top surface of the neck part is covered by the wire part, and the wire part is in contact with the neck part, the ball part, and the first pad. | 2021-11-11 |
20210351154 | Mass transfer device and mass transfer method - Provided are a mass transfer device and a mass transfer method. The mass transfer device is provided with multiple channels, a first opening of each channel is arranged on a first surface of the mass transfer device, a second opening of each channel is arranged on a second surface of the mass transfer device, and the distances between the channels are gradually increased along a direction from the first surface to the second surface. In the provided mass transfer method, through a laser irradiation mode, the Micro-LEDs are separated from the first substrate and enter the channels of the mass transfer device through the first openings, and falling into Micro-LED to-be-installed positions on a second substrate through the second openings of the channels, thereby transferring the Micro-LEDs from the first substrate to the second substrate. | 2021-11-11 |
20210351155 | WIRE BONDING METHOD AND WIRE BONDING APPARATUS - A wire bonding method for connecting a wire to two different surfaces by bonding with a single wire bonding step. The wire bonding method includes: bonding one end of a wire fed from a distal end of a capillary to a first bonding surface; moving the capillary in the Z direction; moving the capillary the X and/or Y direction; moving the capillary in the X, Y, and/or Z direction, a plurality of times; moving the capillary to a highest position; and bonding another end of the wire to the second bonding surface. The wire bonding method includes, at any timing, rotating the first bonding surface about a rotation axis to move the second bonding surface to a position capable of bonding. An angle formed by the first bonding surface and the second bonding surface on a side where the wire is stretched is 200° or more. | 2021-11-11 |
20210351156 | Method for Producing an Electronic Component, Wherein a Semiconductor Chip is Positioned and Placed on a Connection Carrier, Corresponding Electronic Component, and Corresponding Semiconductor Chip and Method for Producing a Semiconductor Chip - In an embodiment a method includes providing a semiconductor chip having a plurality of contact pins, at least one positioning pin and an underside, wherein the contact pins and the positioning pin protrude from the underside, respectively, wherein the contact pins are configured for making electrical contact with the semiconductor chip, wherein the positioning pin narrows in a direction away from the underside, and wherein the positioning pin protrudes further from the underside than the contact pins, providing a connection carrier having a plurality of contact recesses, at least one positioning recess and an upper side, wherein each contact recess is at least partially filled with a solder material, heating the solder material in the contact recesses to a joining temperature at which the solder material at least partially melts and placing the semiconductor chip on the connection carrier, wherein each contact pin is inserted into a contact recess and the positioning pin is inserted into the positioning recess. | 2021-11-11 |
20210351157 | MEMBER CONNECTION METHOD - This member connection method includes a printing step. In the printing step, a coating film-formed region in which the coating film is formed, and a coating film non-formed region in which the coating film is not formed are formed in the print pattern, and the coating film-formed region is divided into a plurality of concentric regions and a plurality of radial regions by means of a plurality of line-shaped regions provided so as to connect various points, which are separated apart from one another in the marginal part of the connection region. | 2021-11-11 |
20210351158 | APPARATUS AND METHOD FOR SELF-ASSEMBLING SEMICONDUCTOR LIGHT-EMITTING DEVICE - Discussed is an apparatus for self-assembling semiconductor light-emitting devices, the apparatus including a fluid chamber to accommodate the semiconductor light-emitting devices, each semiconductor light-emitting device having a magnetic body; a magnet to apply a magnetic force to the semiconductor light-emitting devices while an assembly substrate is disposed at an assembly position of the self-assembly apparatus; a power supply to induce formation of an electric field on the assembly substrate to allow the semiconductor light-emitting devices to be seated at a preset positions on the assembly substrate in a process of moving the semiconductor light-emitting devices due to a change in a position of the magnet; and a fluid injector to shoot a fluid to some of the semiconductor light-emitting devices to allow the some of the semiconductor light-emitting devices seated on the assembly substrate to be separated from the assembly substrate. | 2021-11-11 |
20210351159 | ACTIVE BRIDGING APPARATUS - Techniques and mechanisms for coupling chiplets to microchips utilizing active bridges. The active bridges include circuits that provide various functions and capabilities that previously may have been located on the microchips and/or the chiplets. Furthermore, the active bridges may be coupled to the microchips and the chiplets via “native interconnects” utilizing direct bonding techniques. Utilizing the active bridges and the direct bonding techniques of the active bridges to the microchips and the chiplets, the pitch for the interconnects can be greatly reduced going from a pitch in the millimeters to a fine pitch that may be in a range of less than one micron to approximately five microns. | 2021-11-11 |
20210351160 | MITIGATING THERMAL IMPACTS ON ADJACENT STACKED SEMICONDUCTOR DEVICES - A semiconductor device assembly and associated methods are disclosed herein. The semiconductor device assembly includes (1) a substrate having a first side and a second side opposite the first side; (2) a first set of stacked semiconductor devices at the first side of the substrate; ( | 2021-11-11 |
20210351161 | SEMICONDUCTOR DEVICE - According to an embodiment, provided is a semiconductor device includes an insulating substrate; a first main terminal; a second main terminal; an output terminal; a first metal layer connected to the first main terminal; a second metal layer connected to the second main terminal; a third metal layer disposed between the first metal layer and the second metal layer and connected to the output terminal; a first semiconductor chip and a second semiconductor chip provided on the first metal layer; and a third semiconductor chip and a fourth semiconductor chip provided on the third metal layer. The second metal layer includes a first slit. Alternatively, the third metal layer includes a second slit. | 2021-11-11 |
20210351162 | SEMICONDUCTOR PACKAGE HAVING MULTIPLE VOLTAGE SUPPLY SOURCES AND MANUFACTURING METHOD THEREOF - The present application provides a semiconductor package and a manufacturing method thereof. The semiconductor package includes a package substrate, a bottom device die, a top device die and an additional package substrate. The bottom device die is attached on the package substrate. The top device die is attached on the bottom device die with its active side facing away from the bottom device die. A first portion of die I/Os at the active side of the top device die are electrically connected to the package substrate. The additional package substrate is attached on the active side of the top device die, and electrically connected to the package substrate and a second portion of the die I/Os of the top device die. | 2021-11-11 |
20210351163 | HIGH DENSITY PILLAR INTERCONNECT CONVERSION WITH STACK TO SUBSTRATE CONNECTION - A semiconductor device assembly can include a first semiconductor device and an interposer. The interposer can include a substrate and through vias in which individual vias include an exposed portion and an embedded portion, the exposed portions projecting from one or both of the first surface and the second surface of the substrate, and the embedded portions extending through at least a portion of the substrate. The interposer can include one or more test pads, a first electrical contact, and a second electrical contact. The semiconductor device assembly can include a controller positioned on an opposite side of the interposer from the first semiconductor device and operably coupled to the interposer via connection to the second electrical contact. | 2021-11-11 |
20210351164 | SEMICONDUCTOR DEVICES WITH DUPLICATED DIE BOND PADS AND ASSOCIATED DEVICE PACKAGES AND METHODS OF MANUFACTURE - Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture are disclosed herein. In one embodiment, a semiconductor device package includes a plurality of package contacts and a semiconductor die having a plurality of first die bond pads, a plurality of second die bond pads, and a plurality of duplicate die bond pads having the same pin assignments as the first die bond pads. The semiconductor die further includes an integrated circuit operably coupled to the package contacts via the plurality of first die bond pads and either the second die bond pads or the duplicate die bond pads, but not both. The integrated circuit is configured to be programmed into one of (1) a first pad state in which the first and second die bond pads are enabled for use with the package contacts and (2) a second pad state in which the first and duplicate die bond pads are enabled for use with the package contacts. | 2021-11-11 |
20210351165 | LIGHT EMITTING DEVICE - A light emitting device includes a printed circuit board (PCB) substrate, a first ink layer covering the PCB substrate, the first ink layer having a first refractive index, light emitters on the first ink layer, and a second ink layer on the first ink layer and spaced apart from the light emitters, the second ink layer having a second refractive index different from the first refractive index. | 2021-11-11 |
20210351166 | Method And System For Transferring Alignment Marks Between Substrate Systems - A method for transferring alignment marks between substrate systems includes providing a substrate having semiconductor devices and alignment marks in precise alignment with the semiconductor devices; and physically transferring and bonding the semiconductor devices and the alignment marks to a temporary substrate of a first substrate system. The method can also include physically transferring and bonding the semiconductor devices and the alignment marks to a mass transfer substrate of a second substrate system; and physically transferring and bonding the semiconductor devices and the alignment marks to a circuitry substrate of a third substrate system. A system for transferring alignment marks between substrate systems includes the substrate having the semiconductor devices and the alignment marks in precise alignment with the semiconductor devices. The system also includes the first substrate system, and can include the second substrate system and the third substrate system. | 2021-11-11 |
20210351167 | LIGHT EMITTING DEVICE AND LIGHT EMITTING MODULE INCLUDING THE SAME - A light emitting module including a mounting substrate, light emitting chips mounted on the mounting substrate, and pads, in which the light emitting chips include a first substrate, a first light emitting unit on a first surface of the first substrate, a second substrate spaced apart from the first substrate, and a second light emitting unit on a second surface of the second substrate, the first substrate includes a first side surface including a first modified surface, and the second substrate includes a second side surface facing the first side surface and including a second modified surface, the first modified surface includes first modified regions extended in a thickness direction and first ruptured regions disposed therebetween, the second modified surface includes second modified regions extended in the thickness direction and second ruptured regions disposed therebetween, and the first ruptured regions have the same width as the second ruptured regions. | 2021-11-11 |
20210351168 | SEMICONDUCTOR MODULE - In an embodiment, a semiconductor module includes a low side switch and a high side switch. The low side switch and the high side switch are arranged laterally adjacent one another and coupled in series between a ground package pad and a voltage input (VIN) package pad of the semiconductor module and form a half bridge configuration having an output node. The semiconductor module further includes a first capacitor pad coupled to ground potential and a second capacitor pad coupled to a VIN potential. The first capacitor pad is arranged vertically above the low side switch and the second capacitor pad is arranged vertically above the high side switch. | 2021-11-11 |
20210351169 | Dense Hybrid Package Integration Of Optically Programmable Chip - An interconnect for a semiconductor device includes: a carrier; a UV programmable chip mounted on the carrier using a first array of solder connections; a UV light source mounted on the carrier using a second array of solder connections, the UV light source being in optical communication with the UV programmable chip; and a plurality of transmission lines extending on or through the carrier and providing electrical communication between the UV programmable chip and the UV light source. | 2021-11-11 |
20210351170 | BACKLIGHT MODULE, DISPLAY PANEL AND ELECTRONIC DEVICE - The present application provides a backlight module, a display panel and an electronic device, including a substrate; a plurality of driving units, formed on the glass substrate; and a plurality of mini-LEDs, each of which includes a first electrode and a second electrode, wherein the driving unit includes a switching module, a driving module and a storing module, one end of the switching module is connected to the driving module and the storing module, the driving module is connected to the mini-LED. | 2021-11-11 |
20210351171 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING SAME - A display device may include: a substrate including a display area and a non-display area; and pixels disposed on the display area, and each including sub-pixels, each sub-pixel including a pixel circuit layer, and a display element layer including a light emitting element. The display element layer includes first and second electrodes spaced apart from each other; a first insulating layer disposed between the pixel circuit layer and the light emitting element; and a second insulating layer disposed on the light emitting element and filling spaces between the first insulating layer and ends of the light emitting element. The light emitting element includes a first conductive semiconductor layer, an active layer enclosing at least one side of the first conductive semiconductor layer, a second conductive semiconductor layer enclosing the active layer, an electrode layer enclosing the second conductive semiconductor layer, and an insulating film covering the electrode layer. | 2021-11-11 |
20210351172 | Semiconductor Package and Method - In an embodiment, a method includes: aligning a first package component with a second package component, the first package component having a first region and a second region, the first region including a first conductive connector, the second region including a second conductive connector; performing a first laser shot on a first portion of a top surface of the first package component, the first laser shot reflowing the first conductive connector of the first region, the first portion of the top surface of the first package component completely overlapping the first region; and after performing the first laser shot, performing a second laser shot on a second portion of the top surface of the first package component, the second laser shot reflowing the second conductive connector of the second region, the second portion of the top surface of the first package component completely overlapping the second region. | 2021-11-11 |
20210351173 | Integrated Circuit Structure and Method for Reducing Polymer Layer Delamination - An embodiment integrated circuit structure includes a substrate, a metal pad over the substrate, a post-passivation interconnect (PPI) structure over the substrate and electronically connected to the metal pad, a first polymer layer over the PPI structure, an under bump metallurgy (UBM) extending into an opening in the first polymer layer and electronically connected to the PPI structure, and a barrier layer on a top surface of the first polymer layer adjacent to the UBM. | 2021-11-11 |
20210351174 | GATE STRUCTURE FOR SEMICONDUCTOR DEVICES - A semiconductor structure is disclosed, including a first gate and a second gate aligned with the first gate, a first gate via, a second gate via, multiple conductive segments, and a first conductive line. The first gate via is disposed on the first gate and the second gate via is disposed on the second gate. The first and second gates are configured to be a terminal of a first logic circuit, which is coupled to a terminal of a second logic circuit. The first conductive line is coupled to the first gate through a first connection via and the first gate via and is electrically coupled to the second gate through a second connection via and the second gate via. | 2021-11-11 |
20210351175 | Integrated Hybrid Standard Cell Structure with Gate-All-Around Device - The disclosed circuit includes a first and a second active region (AR) spaced a spacing S along a direction in a first standard cell (SC) that spans D | 2021-11-11 |
20210351176 | ELECTROSTATIC PROTECTION CIRCUIT - An electrostatic protection circuit connected with an internal circuit is provided. The electrostatic protection circuit includes: a first circuit, a first diode connected in parallel with the first circuit, a second circuit, and a second diode connected in parallel with the second circuit. The first circuit is connected between a power supply pad and an internal circuit input terminal. The second circuit is connected between the internal circuit input terminal and a ground pad. The first circuit and the second circuit are diode-triggered silicon controlled rectifier circuits. The technical solution of the disclosure can improve electrostatic protection capability of a charged device model of a chip. | 2021-11-11 |
20210351177 | SEMICONDUCTOR DEVICE - A semiconductor device including a first line configured to receive a power supply voltage, a second line configured to be coupled to a load of the semiconductor device, first and second metal-oxide-semiconductor (MOS) transistors coupled in series between the first line and the second line, each of the first and second MOS transistors having a drain electrode and a gate electrode, the drain electrode of the first MOS transistor being coupled to the drain electrode of the second MOS transistor, a third line coupled to the gate electrode of the first MOS transistor, and a fourth line coupled to the gate electrode of the second MOS transistor, the third and fourth lines being electrically separated from each other. | 2021-11-11 |
20210351178 | DOUBLE-SIDED VERTICAL POWER TRANSISTOR STRUCTURE - A multi-transistor configuration including a first transistor having a first terminal that is configured to control the flow of current between, a second terminal of the first transistor and a third terminal of the first transistor; a second transistor, that is a bipolar junction transistor comprising a base terminal, an emitter terminal, and a collector terminal, wherein the third terminal of the first transistor and the collector terminal of the second transistor are electrically connected; and a first voltage source having a first terminal at a first voltage and a second terminal at a second voltage. | 2021-11-11 |
20210351179 | INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING SAME - An integrated circuit including a substrate, a first semiconductor element, and a second semiconductor element is provided. The substrate has a high voltage region and a low voltage region separated from each other. The first semiconductor element is located in the high voltage region. The first semiconductor element includes a first oxide layer and a first gate. The first oxide layer is embedded in the substrate. The first gate is located on the first oxide layer. The first gate is a polycrystalline gate. The second semiconductor element is located in the low voltage region. The second semiconductor element includes a second oxide layer and a second gate. The second oxide layer is embedded in the substrate. The second gate is located on the second oxide layer. The second gate is a metal gate. A manufacturing method of an integrated circuit is also provided. | 2021-11-11 |
20210351180 | METHOD OF MAKING MULTIPLE NANO LAYER TRANSISTORS TO ENHANCE A MULTIPLE STACK CFET PERFORMANCE - In a method of forming a semiconductor device, an epitaxial layer stack is formed over a substrate. The epitaxial layer stack includes intermediate layers, one or more first nano layers and one or more second nano layers positioned below the one or more first nano layers. Trenches are formed in the epitaxial layer stack to separate the epitaxial layer stack into sub-stacks, the one of more first nano layers into first nano-channels, and the one or more second nano layers into second nano-channels. The intermediate layers are recessed so that one or more first nano-channels of the first nano-channels and one or more second nano-channels of the second nano-channels in each of the sub-stacks protrude from sidewalls of the intermediate layers. Bottom source/drain (S/D) regions are formed in the trenches to connect the second nano-channels. Top S/D regions are formed in the trenches to connect the first nano-channels. | 2021-11-11 |
20210351181 | SEMICONDUCTOR STRUCTURE - Semiconductor structures are provided. A first logic cell includes a plurality of first transistors over a substrate. The first transistor includes a first gate electrode across a first channel region. The first gate electrode is electrically connected to a first conductive line in a first dielectric layer through a first contact in a second dielectric layer and a first via in the first dielectric layer. A second logic cell includes a plurality of second transistors over the substrate. The second transistor includes a second gate electrode across a second channel region, wherein the second gate electrode is electrically connected to a second conductive line in the first dielectric layer through a second via. The first dielectric layer is formed over the second dielectric layer, and the second via extends from the second conductive line to the second gate electrode and penetrates the first and second dielectric layers. | 2021-11-11 |
20210351182 | APPARATUSES INCLUDING TRANSISTORS, AND RELATED METHODS, MEMORY DEVICES, AND ELECTRONIC SYSTEMS - An apparatus comprises a first conductive structure and at least one transistor in electrical communication with the first conductive structure. The at least one transistor comprises a lower conductive contact coupled to the first conductive structure and a split-body channel on the lower conductive contact. The split-body channel comprises a first semiconductive pillar and a second semiconductive pillar horizontally neighboring the first semiconductive pillar. The at least one transistor also comprises a gate structure horizontally interposed between the first semiconductive pillar and the second semiconductive pillar of the split-body channel and an upper conductive contact vertically overlying the gate structure and coupled to the split-body channel. Portions of the gate structure surround three sides of each of the first semiconductive pillar and the second semiconductive pillar. Memory devices, electronic systems, and methods of forming the apparatus are also disclosed. | 2021-11-11 |
20210351183 | 3D PITCH MULTIPLICATION - Memory devices and methods of manufacturing memory devices are provided. Described are devices and methods where 3D pitch multiplication decouples high aspect ratio etch width from cell width, creating small cell active area pitch to allow for small DRAM die size. | 2021-11-11 |
20210351184 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device includes: an active region defined by a device isolation layer formed in a substrate; a word line configured to cross the active region, the word line extending in a first direction and being formed in the substrate; a bit line extending in a second direction perpendicular to the first direction on the word line; a first contact connecting the bit line to the active region; a first mask for forming the active region, the first mask being formed on the active region; and a second mask of which a height of a top surface thereof is greater than a height of a top surface of the active region, the second mask covering the word line, wherein the active region has a bar shape that extends to form an acute angle with respect to the first direction. | 2021-11-11 |
20210351185 | SEMICONDUCTOR DEVICE WITH TAPERING IMPURITY REGION AND METHOD FOR FABRICATING THE SAME - The present application discloses a semiconductor device with a tapering impurity region and the method for fabricating the semiconductor device with the tapering impurity region. The semiconductor device includes a substrate, a word line structure positioned in the substrate, an impurity region including an upper portion positioned adjacent to the word line structure and a lower portion positioned below the upper portion. The upper portion has a tapering cross-sectional profile. | 2021-11-11 |
20210351186 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate comprising a plurality of active regions extending in a first direction and a device isolation region electrically isolating the plurality of active regions, a gate trench extending across the plurality of active regions and the device isolation region, a gate structure extending in the gate trench of each of and along opposite sidewalls of the plurality of active regions, a gate dielectric film formed between the gate trench and the gate structure in each of the plurality of active regions, and an insulating barrier film provided in each of the plurality of active regions under the gate trench spaced apart from a lower surface of the gate trench and extending in an extension direction of the gate trench. | 2021-11-11 |
20210351187 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH SELF-ALIGNED LANDING PAD - The present application discloses a method for fabricating a semiconductor device with a self-aligned landing pad. The method includes: providing a substrate; forming a dielectric layer with a plug over the substrate; performing an etching process to remove a portion of the dielectric layer to expose a protruding portion of the plug; forming a liner layer covering the dielectric layer and the protruding portion; and performing a thermal process to form a landing pad over the dielectric layer. The landing pad comprises a protruding portion of the plug, a first silicide layer disposed over the protruding portion, and a second silicide layer disposed on a sidewall of the protruding portion. | 2021-11-11 |
20210351188 | STRUCTURES AND METHODS FOR FORMING DYNAMIC RANDOM-ACCESS DEVICES - Disclosed are DRAM devices and methods of forming DRAM devices. One non-limiting method may include providing a device, the device including a plurality of angled structures formed from a substrate, a bitline and a dielectric between each of the plurality of angled structures, and a drain disposed along each of the plurality of angled structures. The method may further include providing a plurality of mask structures of a patterned masking layer over the plurality of angled structures, the plurality of mask structures being oriented perpendicular to the plurality of angled structures. The method may further include etching the device at a non-zero angle to form a plurality of pillar structures. | 2021-11-11 |
20210351189 | MEMORY AND METHOD FOR FORMING SAME - A memory and a method for forming the same are provided. In the method, a word line trench is formed in active regions and an isolation layer. The formed word line trench includes a first partial word line trench located in the active regions and a second partial word line trench located in the isolation layer. The width and depth of the second partial word line trench are greater than the width and depth of the first partial word line trench respectively. Therefore, when a word line structure is formed in the word line trench, the formed word line structure also includes a first partial word line structure located in the first partial word line trench and a second partial word line structure located in the second partial word line trench. | 2021-11-11 |
20210351190 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - The present application discloses a method for fabricating a semiconductor device. The method includes: providing a substrate including a plurality of first regions and second regions; forming a plurality of bit line contacts over the first regions of the substrate; forming a plurality of bit lines respectively over the plurality of bit line contacts; forming a plurality of capacitor contacts respectively over the second regions of the substrate; forming a plurality of capacitor plugs respectively over the plurality of capacitor contacts; forming a plurality of first spacers respectively over a plurality of protruding portions of the plurality of capacitor plugs, wherein a width of the first spacer is larger than a width of the capacitor plug; and forming a plurality of capacitor structures over the plurality of first spacers; wherein at least one of the plurality of bit lines is an undulating stripe extending between two adjacent capacitor contacts. | 2021-11-11 |
20210351191 | METHOD FOR FORMING A MFMIS MEMORY DEVICE - Various embodiments of the present application are directed towards a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) memory device, as well as a method for forming the MFMIS memory device. According to some embodiments of the MFMIS memory device, a first source/drain region and a second source/drain region are vertically stacked. An internal gate electrode and a semiconductor channel overlie the first source/drain region and underlie the second source/drain region. The semiconductor channel extends from the first source/drain region to the second source/drain region, and the internal gate electrode is electrically floating. A gate dielectric layer is between and borders the internal gate electrode and the semiconductor channel. A control gate electrode is on an opposite side of the internal gate electrode as the semiconductor channel and is uncovered by the second source/drain region. A ferroelectric layer is between and borders the control gate electrode and the internal gate electrode. | 2021-11-11 |
20210351192 | ONE-TIME PROGRAMMABLE DEVICE WITH ANTIFUSE - Certain aspects of the present disclosure generally relate to a one-time programmable (OTP) device including an antifuse device. The antifuse device generally includes a first active region, a second active region, a channel region disposed between the first active region and the second active region, a gate region disposed above the channel region, and a first set of lightly doped drain (LDD) extension regions extending partially across the channel region from the first active region and the second active region and extending into a portion of the channel region underneath the gate region. The first set of LDD extension regions have a same dopant type as the gate region and at least one of the first active region or the second active region. | 2021-11-11 |
20210351193 | LAYOUT STRUCTURE OF STORAGE CELL AND MANUFACTURING METHOD THEREOF - A method of forming a storage cell includes: forming a transistor on a semiconductor substrate; forming a plurality of fuses in at least one conductive layer on the semiconductor substrate to couple a connecting terminal of the transistor; forming a bit line to couple the plurality of fuses; and forming a word line to couple a control terminal of the transistor. | 2021-11-11 |
20210351194 | MANUFACTURING METHOD FOR MEMORY STRUCTURE - A method of manufacturing a memory structure including the following steps is provided. A spacer layer is formed on sidewalls of gate stack structures. A protective material layer covering the spacer layer and the gate stack structures is formed. A mask material layer is formed on the protective material layer. There is a void located in the mask material layer between two adjacent gate stack structures. A first distance is between a top of the protective material layer and a top of the mask material layer. A second distance is between a top of the void and a top of the mask material layer above the void. A third distance is between a bottom of the void and a bottom of the mask material layer below the void. The first distance is greater than a sum of the second and third distances. | 2021-11-11 |
20210351195 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING - The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first gate structure over a substrate and laterally surrounded by a first sidewall spacer. The first gate structure protrudes outward from a top of the first sidewall spacer. A second gate structure is over the substrate and is laterally surrounded by a second sidewall spacer. The first gate structure has a first height that is larger than a second height of the second gate structure. The first sidewall spacer has a first cross-sectional profile that is a different shape and a different size than a second cross-sectional profile of the second sidewall spacer. | 2021-11-11 |
20210351196 | SEMICONDUCTOR MEMORY STRUCTURE AND MANUFACTURING METHOD THEREOF - Methods and apparatus for fabricating memory devices are provided. In one aspect, an intermediate stack of dielectric layers are formed on a first stack of dielectric layers in a first tier. The intermediate stack of dielectric layers is then partially or fully etched and have a landing pad layer deposited thereon. In response to planarizing the landing pad layer to expose a top surface of the intermediate stack of dielectric layers, a second stack of dielectric layers are deposited above the planarized landing pad layer. A staircase is formed by etching through the second stack, the intermediate stack, and the first stack of dielectric layers in the staircase region of the memory device. The staircase is located adjacent to one end of the center landing pad, where steps of the staircase are formed within the thickness of the center landing pad. | 2021-11-11 |
20210351197 | Methods Of Forming An Array Of Elevationally-Extending Strings Of Memory Cells, Methods Of Forming Polysilicon, Elevationally-Extending Strings Of Memory Cells Individually Comprising A Programmable Charge Storage Transistor, And Electronic Components Comprising Polysilicon - A method of forming polysilicon comprises forming a first polysilicon-comprising material over a substrate, with the first polysilicon-comprising material comprising at least one of elemental carbon and elemental nitrogen at a total of 0.1 to 20 atomic percent. A second polysilicon-comprising material is formed over the first polysilicon-comprising material. The second polysilicon-comprising material comprises less, if any, total elemental carbon and elemental nitrogen than the first polysilicon-comprising material. Other aspects and embodiments, including structure independent of method of manufacture, are disclosed. | 2021-11-11 |
20210351198 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device includes a stacked structure including a first region in which conductive layers and the insulating layers are stacked alternately with each other, and a second region in which sacrificial layers and the insulating layers are stacked alternately with each other, a first slit structure located at a boundary between the first region and the second region and including a first through portion passing through the stacked structure and first protrusions extending from a sidewall of the first through portion, a second slit structure located at the boundary and including a second through portion passing through the stacked structure and second protrusions extending from a sidewall of the second through portion and coupled to the first protrusions, a circuit located under the stacked structure, and a contact plug passing through the second region of the stacked structure and electrically connected to the circuit. | 2021-11-11 |
20210351199 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DETECTING ELECTRICAL FAILURE THEREOF - Disclosed are three-dimensional semiconductor memory devices and methods of detecting electrical failure thereof. The three-dimensional semiconductor memory device includes a substrate with a first conductivity including a cell array region and an extension region having different threshold voltages from each other, a stack structure on the substrate and including stacked electrodes, an electrical vertical channel penetrating the stack structure on the cell array region, and a dummy vertical channel penetrating the stack structure on the extension region. The substrate comprises a pocket well having the first conductivity and provided with the stack structure thereon, and a deep well surrounding the pocket well and having a second conductivity opposite to the first conductivity. | 2021-11-11 |
20210351200 | MULTI-DIVISION STAIRCASE STRUCTURE OF THREE-DIMENSIONAL MEMORY DEVICE AND METHOD FOR FORMING THE SAME - A method for forming a staircase structure of a memory device includes the following operations. A first number of divisions are formed at different depths along a first direction in a stack structure and a trench structure between adjacent divisions, the stack structure comprising interleaved sacrificial material layers and dielectric material layers. A plurality of stairs are formed along a second direction. Each of the plurality of stairs includes the first number of divisions, and each of the divisions includes a first number of sacrificial portions. The second direction is perpendicular to the first direction. An insulating portion is formed in the trench structure. A top sacrificial portion is formed on a top surface of each of the first number of divisions and in contact with the insulating portion. The top sacrificial portion is replaced with a conductor portion through a slit structure in the insulating portion and in contact with the top sacrificial portion. | 2021-11-11 |
20210351201 | Integrated Assemblies Having Thicker Semiconductor Material Along One Region of a Conductive Structure than Along Another Region, and Methods of Forming Integrated Assemblies - Some embodiments include an integrated assembly having a conductive structure which includes a semiconductor material over a metal-containing material. A stack of alternating conductive levels and insulative levels is over the conductive structure. A partition extends through the stack. The partition has wall regions, and has corner regions where two or more wall regions meet. The conductive structure includes a first portion which extends directly under the corner regions, and includes a second portion which is directly under the wall regions and is not directly under the corner regions. The first portion has a first thickness of the semiconductor material and the second portion has a second thickness of the semiconductor material. The first thickness is greater than the second thickness. Some embodiments include methods of forming integrated assemblies. | 2021-11-11 |
20210351202 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device including a plurality of rows of IO cells has a configuration capable of avoiding a latchup error without causing an increase in area. The device includes a first IO cell row placed closest to an edge of a chip and a second IO cell row placed adjacent to a core region side of the first IO cell row. Each of the IO cells of the first and second IO cell rows has a high power supply voltage region and a low power supply voltage region provided separately in a direction perpendicular to a direction in which the IO cells are lined up. The IO cell rows are placed so that the high power supply voltage regions of these rows are mutually opposed. | 2021-11-11 |
20210351203 | Array Substrate and Manufacturing Method Thereof, and Display Device - An array substrate and a manufacturing method thereof, and a display device. The array substrate includes: a base substrate, including a first surface and a second surface opposite to each other, and a through-hole penetrating the base substrate from the first surface to the second surface; a data line on the first surface of the base substrate, the data line being at least partially filled in the through-hole; a thin film transistor on the second surface of the base substrate, the thin film transistor including a source electrode and a drain electrode, and the source electrode being electrically connected to the data line | 2021-11-11 |
20210351204 | DISPLAY PANEL AND DISPLAY DEVICE - The present application provides a display panel, comprising a display area and a border area disposed at a periphery of the display area, the border area comprising: an array substrate comprising a first substrate and a gate driver on array (GOA) circuit disposed on the first substrate; a color filter substrate comprising a second substrate and a signal trace disposed on the second substrate; wherein the GOA circuit is overlapped with the signal trace. The present application also relates to a display device. | 2021-11-11 |
20210351205 | DISPLAY PANEL AND LARGE FORMAT DISPLAY APPARATUS USING THE SAME - A display panel is provided. The display panel according to an embodiment includes a thin film transistor glass substrate, a plurality of micro light emitting diodes (LEDs) arranged on one surface of the thin film transistor glass substrate, and a plurality of side wirings formed at an edge of the thin film transistor glass substrate to electrically connect the one surface of the thin film transistor glass substrate to an opposite surface to the one surface. | 2021-11-11 |
20210351206 | THIN FILM TRANSISTOR, METHOD FOR MANUFACTURING THE SAME, AND SEMICONDUCTOR DEVICE - In a thin film transistor, an increase in off current or negative shift of the threshold voltage is prevented. In the thin film transistor, a buffer layer is provided between an oxide semiconductor layer and each of a source electrode layer and a drain electrode layer. The buffer layer includes a metal oxide layer which is an insulator or a semiconductor over a middle portion of the oxide semiconductor layer. The metal oxide layer functions as a protective layer for suppressing incorporation of impurities into the oxide semiconductor layer. Therefore, in the thin film transistor, an increase in off current or negative shift of the threshold voltage can be prevented. | 2021-11-11 |
20210351207 | THIN FILM TRANSISTOR, ARRAY SUBSTRATE, FABRICATING METHODS THEREOF, AND DISPLAY APPARATUS - The present disclosure is related to a thin film transistor. The thin film transistor may include a gate pattern; an active layer pattern; a gate insulating layer between the gate pattern and the active layer pattern; a first conductive pattern including a first pattern part and a first connecting part; a second conductive pattern a second pattern part and a second connecting part; and a first intermediate insulating layer between the first pattern part and the second pattern part. The first conductive pattern and the second conductive pattern may be a source pattern and a drain pattern, respectively. A first through hole may be provided on the first intermediate insulating layer. The second conductive pattern may be connected to the active layer pattern through the second connecting part in the first through hole. | 2021-11-11 |
20210351208 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF - A method for manufacturing an array substrate is provided. The method includes providing a substrate comprising a base layer and a poly-silicon layer, then sequentially deposing a first metal layer and a second metal layer on the poly-silicon layer, implementing a first patterning process so that the second metal layer comprises a first area to be etched that protrudes from the third metal, implementing a second patterning process to remove first area to be etched of the third metal layer, and repeating the above steps. | 2021-11-11 |
20210351209 | IMAGE SENSOR DEVICE - An image sensor device which can reduce a chip size and power consumption, is disclosed. The image sensor device includes a substrate provided with a first surface and a second surface that are arranged to face each other, a pad disposed at the first surface of the substrate, a line layer disposed below the second surface of the substrate, a first through silicon via (TSV) formed to penetrate the substrate and the line layer, and disposed at one side of the pad, a second TSV formed to penetrate the substrate and the line layer, and disposed at the other side of the pad, and a power-supply switch disposed between the first TSV and the second TSV. | 2021-11-11 |
20210351210 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A low noise device includes an isolation feature in a substrate. The low noise device further includes a gate stack over a channel in the substrate, wherein the isolation feature is adjacent to the channel. The low noise device further includes a spacer surrounding a portion of the gate stack, wherein an edge of the gate stack is spaced from an edge of the isolation feature adjacent to the spacer by a distance ranging from a minimum spacing distance to about 0.3 microns (μm). | 2021-11-11 |
20210351211 | SINGLE PHOTON AVALANCHE DIODE - A single photon avalanche diode includes a silicon-on-insulator (SOI) substrate having a base substrate, a buried oxide layer over the base substrate, and a silicon layer over the buried oxide layer. At least one photodiode region is disposed in the base substrate. The photodiode region comprises an epitaxial layer embedded in the base substrate. | 2021-11-11 |
20210351212 | IMAGING DEVICE - An imaging device includes a photoelectric conversion layer, a counter electrode provided above the photoelectric conversion layer, a pixel electrode that faces the counter electrode with the photoelectric conversion layer disposed between the counter electrode and the pixel electrode, and a contact plug covered with the pixel electrode and connected to the pixel electrode. The pixel electrode includes a first layer and a second layer provided on the first layer in contact with the first layer. A surface of the first layer that is in contact with the second layer has a protrusion that protrudes upward. | 2021-11-11 |
20210351213 | SOLID-STATE IMAGING DEVICE AND METHOD FOR MANUFACTURING SOLID-STATE IMAGING DEVICE, AND ELECTRONIC DEVICE - A solid-state imaging device includes a first-conductivity-type semiconductor well region, a plurality of pixels each of which is formed on the semiconductor well region and is composed of a photoelectric conversion portion and a pixel transistor, an element isolation region provided between the pixels and in the pixels, and an element isolation region being free from an insulation film and being provided between desired pixel transistors. | 2021-11-11 |
20210351214 | IMAGE SENSOR AND SIGNAL PROCESSING METHOD THEREOF - An image sensor comprising a unique color filtration layer and a light conversion layer is described. The color filtration layer includes an array of color filtration regions, that at least one of the color filtration regions contains a color filter occupying 20% to 80% area of the color filtration region. The image sensor increases light sensitivity in low light condition while maintains enough chromatic information in image details. | 2021-11-11 |
20210351215 | METHOD AND APPARATUS FOR REDUCING LIGHT LEAKAGE AT MEMORY NODES IN CMOS IMAGE SENSORS - Disclosed is a CMOS image sensor with global shutters and a method for fabricating the CMOS image sensor. In one embodiment, a semiconductor device, includes: a light-sensing region; a charge-storage region; a light-shielding structure; and at least one via contact; wherein the charge-storage region is spatially configured adjacent to the light-sensing region in a lateral direction, wherein the light-shielding structure is configured over the charge-storage region in a vertical direction so as to prevent incident light leaking from the light-sensing region to the signal-processing region, wherein the light-shielding structure is configured in an interlayer dielectric (ILD) layer, and wherein the light-shielding structure is simultaneously formed with the at least one via contact. | 2021-11-11 |
20210351216 | OPTICAL IMAGING DEVICE - An aspect of the present invention provides an optical imaging device including a first detecting unit. The first detecting unit includes a plurality of first pixels, a first opaque layer and at least one first micro-lens. The plurality of first pixels respectively has a plurality of first optoelectronic elements. The first opaque layer has at least one opening and is disposed over the plurality of first optoelectronic elements. The at least one first micro-lens is disposed over the first opaque layer, and overlaps at least one of the plurality of first pixels. | 2021-11-11 |
20210351217 | PHOTOELECTRIC CONVERSION ELEMENT AND LIGHT RECEIVING DEVICE - A light receiving device includes plural photoelectric conversion element units | 2021-11-11 |
20210351218 | SEMICONDUCTOR DEVICES FOR IMAGE SENSING - The present disclosure relates to a semiconductor device including a semiconductor substrate. A grid structure extends from a first side of the semiconductor substrate to within the semiconductor substrate. An image sensing element is disposed within the semiconductor substrate and is laterally surrounded by the grid structure. A plurality of protrusions are arranged along the first side of the semiconductor substrate. The plurality of protrusions are disposed over the image sensing element and are laterally surrounded by the grid structure. The plurality of protrusions are substantially identical to one another and have a characteristic dimension. An inner surface of the grid structure facing the image sensing element is spaced apart from a point of one of the plurality of protrusions by a predetermined reflective length that is based on the characteristic dimension of the plurality of protrusions. | 2021-11-11 |
20210351219 | SEMICONDUCTOR DEVICE - Effective use is achieved of a region in a proximity of a joining plane of semiconductor substrates in a semiconductor device including a stacked semiconductor substrate in which multilayer wiring layers of a plurality of semiconductor substrates are electrically connected to each other. The stacked semiconductor substrate includes plural semiconductor substrates on each of which a multilayer wiring layer is formed. In this stacked semiconductor substrate, the multilayer wiring layers are joined together and electrically connected to each other. In the proximity of a joining plane of the plurality of semiconductor substrates, a conductor is formed. This conductor is formed such that it is electrified in a direction of the joining plane. | 2021-11-11 |
20210351220 | IMAGE SENSOR CHIP - An image sensor chip includes a lower chip, an upper chip stacked on the lower chip and including a photoelectric element, a via hole penetrating through the upper chip and penetrating through at least a portion of the lower chip, and a conductive connection layer electrically connecting the lower chip and the upper chip to each other in the via hole. The upper chip includes an upper substrate, an upper isolation layer and an upper element on the upper substrate, a connection contact plug, and a multilayer interconnection line electrically connected to the connection contact plug. A distance between an upper surface of the connection contact plug and an upper surface of the upper isolation layer is greater than a distance between an upper surface of an upper gate electrode of the upper element and an upper surface of the upper isolation layer. | 2021-11-11 |
20210351221 | PHOTONIC DEVICE AND METHOD HAVING INCREASED QUANTUM EFFECT LENGTH - Photonic devices and methods having an increased quantum effect length are provided. In some embodiments, a photonic device includes a substrate having a first surface. A cavity extends into the substrate from the first surface to a second surface. A semiconductor layer is disposed on the second surface in the cavity of the substrate, and a cover layer is disposed on the semiconductor layer. The semiconductor layer is configured to receive incident radiation through the substrate and to totally internally reflect the radiation at an interface between the semiconductor layer and the cover layer. | 2021-11-11 |
20210351222 | SEMICONDUCTOR DEVICES WITH SINGLE-PHOTON AVALANCHE DIODES AND LIGHT SPREADING LENSES - An imaging device may include single-photon avalanche diodes (SPADs). The single-photon avalanche diodes may be arranged in a one-dimensional or two-dimensional array in a SPAD-based semiconductor device. The SPAD-based semiconductor device may also include a transparent cover glass that is formed over the array of SPADs. Each line of SPADs within the SPAD-based semiconductor device may be covered by a respective light spreading lens. The light spreading lens may be formed as a groove in an upper surface of the transparent cover glass. The light spreading lens may have a uniform cross-section along its length. The light spreading lens may be formed as a convex lens on an upper or lower surface of the transparent cover glass. | 2021-11-11 |
20210351223 | SOLID-STATE IMAGE SENSOR - It is an object of the present technology to provide a solid-state image sensor capable of reducing display unevenness of a captured image. A solid-state image sensor includes: a first substrate that includes a photoelectric conversion unit, a transfer gate unit that is connected to the photoelectric conversion unit, an FD unit that is connected to the transfer gate unit, and an interlayer insulating film that covers the photoelectric conversion unit, the transfer gate unit, and the FD unit; and a second substrate that includes an amplifier transistor and is disposed to be adjacent to the interlayer insulating film, the amplifier transistor constituting a part of a pixel transistor connected to the FD unit via the interlayer insulating film and including a back gate unit. | 2021-11-11 |
20210351224 | Imaging Device and Electronic Device - A thin imaging device including a light source is provided. The imaging device includes a light-emitting device which emits infrared light. Infrared light emitted by the light-emitting device and reflected by a subject is received by a photoelectric conversion device included in a pixel circuit. Since an EL element is used as the light-emitting device, a thin imaging device with a light source can be formed. A pixel circuit utilizing an oxide semiconductor transistor having a property of low off-state current is used, whereby image capturing by a global shutter method is possible and a distortion-free image can be obtained even when the subject is moving. | 2021-11-11 |
20210351225 | IMAGE SENSOR GRID AND METHOD OF MANUFACTURING SAME - In a method for forming a semiconductor device photo-sensing regions are formed over a frontside of a substrate. A first layer is formed over a backside of the substrate and is patterned to form a plurality of grid lines. The grid lines can define a plurality of first areas and a plurality of second areas. A second layer maybe formed over exposed portions of the backside, the gridlines, the first areas, and the second areas and a third layer may be formed over the second layer. The second and third layer may have different etch rates and the third layer is pattern so as to remove the third layer from over the plurality of first areas. | 2021-11-11 |
20210351226 | FULL COLOR LIGHT EMITTING DIODE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A LED structure includes a substrate, a first semiconductor layer, a second semiconductor layer, and a color conversion layer. The first semiconductor layer is formed on the substrate, and the first semiconductor layer includes a first LED unit and a second LED unit formed therein. The first LED unit and the second LED unit emit light of a first color. The second semiconductor layer is formed above the first semiconductor layer, and the second semiconductor layer includes a third LED unit formed therein. The third LED unit emits light of a second color different from the first color. The color conversion layer is formed on the first LED unit to convert light of the first color to light of a third color different from the first color and the second color. | 2021-11-11 |
20210351227 | DISPLAY DEVICE - A display panel and a display device are provided by the present disclosure, wherein the display panel includes a pixel region having a plurality of pixels. The pixel region includes a first area and a second area, wherein the transmittance of the second area is greater than the transmittance of the first area. The second area has a coverage, and a width of the coverage is not less than 0.43 millimeters. | 2021-11-11 |
20210351228 | LIGHT-EMITTING DEVICE, AND METHOD FOR PRODUCING SAME - A light-emitting device includes a multiplicity of light-emitting modules arranged on a first substrate. Each light-emitting module of the multiplicity of light-emitting modules includes a multiplicity of light-emitting components arranged on a second substrate. The second substrate is electrically connected to the first substrate, and includes a common primary lens for the multiplicity of light-emitting components. | 2021-11-11 |
20210351229 | LIGHT EMITTING DEVICE FOR DISPLAY AND DISPLAY APPARATUS HAVING THE SAME - A light emitting device for a display according to an exemplary embodiment includes a first LED stack, a second LED stack located under the first LED stack, and a third LED stack located under the second LED stack. The light emitting device further includes a first bonding layer, a second bonding layer, a first planarization layer, a second planarization layer, lower buried vias, and upper buried vias. The first planarization layer is recessed inwardly to expose an edge of the second LED stack. | 2021-11-11 |
20210351230 | LIGHT EMITTING DIODE (LED) STACK FOR A DISPLAY - A light emitting diode (LED) stack for a display including a substrate, a first LED stack disposed on the substrate, a second LED stack disposed on the first LED stack, a third LED stack disposed on the second LED stack, a first color filter interposed between the first LED stack and the second LED stack, and a second color filter interposed between the second LED stack and the third LED stack, in which the second LED stack and the third LED stack are configured to transmit light generated from the first LED stack to the outside, and the third LED stack is configured to transmit light generated from the second LED stack to the outside. | 2021-11-11 |
20210351231 | LED DISPLAY APPARATUS, MASS TRANSFER METHOD, AND STORAGE MEDIUM - The present application relates to the field of display manufacturing, and more particularly, to a light emitting diode (LED) display apparatus. The LED display apparatus includes a display backplane, first LED chips, second LED chips, and third LED chips. The display backplane is provided with first bosses and second bosses. The first LED chips are disposed on the first bosses, the second LED chips are disposed on the second bosses. The first bosses each have a height of H11 greater than a height H22 of the second bosses. The present application also relates to a mass transfer method and a storage medium. | 2021-11-11 |
20210351232 | RESERVOIR ELEMENT AND NEUROMORPHIC ELEMENT - A reservoir element according to an aspect of the present invention includes a plurality of ferromagnetic layers laminated in a first direction and separated from each other, at least one spin-orbit torque wiring that faces at least one of the plurality of ferromagnetic layers, and a spin transport layer that faces the plurality of ferromagnetic layers, connects at least the two ferromagnetic layers closest to each other among the plurality of ferromagnetic layers and transports spins. | 2021-11-11 |
20210351233 | SEMICONDUCTOR DEVICE - A semiconductor device including a substrate that has a first region and a second region, a plurality of lower conductive patterns on the substrate, the plurality of lower conductive patterns including a first conductive pattern in the first region of the substrate and a second conductive pattern in the second region of the substrate, a magnetic tunnel junction on the first conductive pattern, a contact between the magnetic tunnel junction and the first conductive pattern, a through electrode on the second conductive pattern, and a plurality of upper conductive patterns on the magnetic tunnel junction and the through electrode. The contact includes a first contact on the lower conductive patterns, a second contact on the first contact, and a first barrier layer that covers a bottom surface and a lateral surface of the second contact. | 2021-11-11 |
20210351234 | THREE-DIMENSIONAL MEMORY ARRAYS, AND METHODS OF FORMING THE SAME - An example apparatus includes a three-dimensional (3D) memory array including a sense line and a plurality of vertical stacks. Each respective on of the vertical stacks includes a different respective portion of the sense line, a first memory cell coupled to that portion of the sense line, a second memory cell coupled to that portion of the sense line, a first access line coupled to the first memory cell and a second access line coupled to the second memory cell. The first and second access lines are perpendicular to the sense line. | 2021-11-11 |
20210351235 | SEMICONDUCTOR MEMORY AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode. | 2021-11-11 |
20210351236 | ELECTRONIC DEVICE INCLUDING DISPLAY AND CAMERA - Various embodiments of the disclosure relate to an electronic device including a display and a camera. The electronic device may include a camera overlapping the display and configured to photograph external light passing through the display, wherein the display may include: a colorless and transparent substrate, a pixel layer disposed in a first direction from the substrate and comprising organic light-emitting diode (OLED) type pixels, an organic encapsulation layer (e.g., thin film encapsulation (TFE)) disposed in the first direction from the pixel layer, and a color filter layer disposed in the first direction from the organic encapsulation layer, wherein the display may include: a first area overlapping at least a portion of the camera and a second area not overlapping the camera, wherein an arrangement density of a first group of pixels in the first area may be lower than an arrangement density of a second group of pixels in the second area, and wherein the color filter layer may include first color filters overlapping the pixels of the first group, second color filters overlapping the pixels of the second group, a black matrix disposed between the second color filters in the second area, and a transmission area disposed between the first color filters in the first area. | 2021-11-11 |
20210351237 | DISPLAY DEVICE - The disclosure provides a display device including red, green and blue pixel units. In the red pixel unit, a light emitting element emits a blue light that then passes through a light conversion element and a color filter and the blue light is converted into a red light while passing through the light conversion element. In the green pixel unit, a light emitting element emits a blue light that then passes through a light conversion element and a color filter and the blue light is converted into a green light while passing through the light conversion element. In the blue pixel, a light emitting element emits a blue light that then passes through a color filter. The red pixel unit has a lighting area greater than a lighting area of the blue pixel unit and less than a lighting area of the green pixel unit. | 2021-11-11 |
20210351238 | COLOR FILTER AND DISPLAY DEVICE COMPRISING SAME - Provided is a color filter having improved light efficiency and color reproducibility. The color filter includes: a substrate having a plurality of pixel areas and a light blocking area surrounding the plurality of pixel areas; a light blocking layer on the light blocking area; a first color conversion layer on a first pixel area among the plurality of pixel areas and configured to convert incident light into light of a first color; a first color filter layer between the substrate and the first color conversion layer and configured to selectively transmit the light of the first color emitted from the first color conversion layer; and a light reflection layer between the first color conversion layer and the first color filter layer and including a reflective material. | 2021-11-11 |
20210351239 | ELECTRONIC DEVICE, METHOD FOR MANUFACTURING SAME, AND DISPLAY DEVICE INCLUDING THE SAME - An electronic device includes a first substrate, a plurality of light emitting elements each having a horizontal length and a vertical length which are less than or equal to about 10 micrometers (μm), each of the plurality of light emitting elements being disposed on the first substrate, a quantum dot color filter layer disposed on the plurality of light emitting elements, and a first overcoat layer between a plurality of light emitting elements and the quantum dot color filter layer. The quantum dot color filter layer includes a plurality of quantum dot color filters partitioned by a plurality of first partition walls so as to be overlapped with the plurality of light emitting elements, respectively. | 2021-11-11 |
20210351240 | ORGANIC LIGHT-EMITTING DISPLAY DEVICE HAVING TOUCH SENSOR - An organic light-emitting display device can include a light-emitting element on a substrate; an encapsulation unit on the light-emitting element and including first and second inorganic encapsulation films, and an organic encapsulation film; a touch insulating film on the second inorganic encapsulation film; a touch sensor including first and second touch electrodes; a routing line; a touch pad; and a plurality of connection electrodes electrically connecting the routing line with the touch pad, in which the first touch electrodes are connected via first bridges, the second touch electrodes are connected via second bridges, and the first and second bridges and the first and second touch electrodes are formed of a same material as each other in a same plane. | 2021-11-11 |
20210351241 | DISPLAY DEVICE - A display device includes a display panel including a first display area having first pixels, and a second display area having second pixels. The display device includes a lower member below the display panel, a supporting member extended to the display panel, and a first slide module disposed between the lower member and the supporting member, the first slide module enabling the lower member and the supporting member to move relative to each other in a direction. The second display area protrudes beyond the lower member in the direction due to a movement by the first slide module. A number of first pixels per a unit area of the first display area is greater than a number of second pixels per the unit area of the second display area. | 2021-11-11 |
20210351242 | Electronic Device and Display - An electronic device and a display may be disclosed. The electronic device may include a display and a camera. The display may include a display face and a bottom face. The bottom face may be disposed opposite to the display face. The bottom face may be a curved face. The camera may be located at a side of the bottom face away from the display face. The camera may be configured to acquire optical signals through the display. | 2021-11-11 |
20210351243 | DISPLAY DEVICES, DISPLAY PANELS AND TRANSPARENT DISPLAY PANELS THEREOF - A display device, a display panel and a transparent display panel thereof. The transparent display panel includes a light-transmitting substrate, and a plurality of first sub-pixels. The first sub-pixels are located on the light-transmitting substrate. Each of the first sub-pixels includes a light-transmitting region and a non-light-transmitting region. Each of the first sub-pixels includes a first light-reflecting anode, a first light-emitting structure layer, and a first cathode stacked in the non-light-transmitting region. The light-transmitting region completely encloses the non-light-transmitting region, or the non-light-transmitting region completely encloses the light-transmitting region. | 2021-11-11 |
20210351244 | LIGHT EMITTING ELEMENT, LIGHT EMITTING DEVICE, AND METHOD FOR MANUFACTURING LIGHT EMITTING ELEMENT - A light-emitting element includes: pixel electrodes provided for individual subpixels of at least three colors; a common electrode provided facing each of the pixel electrodes; and light-emitting layers of each color provided between the common electrode and, respectively, each of the pixel electrodes, wherein one of each of the pixel electrodes and the common electrode is a cathode electrode and the other is an anode electrode and among the light-emitting layers of the at least three colors, a light-emitting layer of a color having a largest electron affinity extends in a state of being layered between the cathode electrode and each light-emitting layer of the other colors as well. | 2021-11-11 |
20210351245 | DISPLAY DEVICE - A display device may include a display panel including a substrate that includes a display area and a pad area adjacent to the display area, and a first pad and a second pad on the pad area of the substrate, and a chip-on-film package over the pad area of the substrate with the first pad and the second pad in between, the chip-on-film package including an insulation layer, a first wiring on an upper surface of the insulation layer and electrically connected to the first pad, and a second wiring on a lower surface of the insulation layer and electrically connected to the second pad. A first signal having alternating voltage levels may be applied to the first wiring, and a second signal having a constant voltage level may be applied to the second wiring. | 2021-11-11 |
20210351246 | PIXEL LAYOUT STRUCTURE OF OLED, OLED DISPLAY PANEL, AND MANUFACTURING METHOD THEREOF - The present disclosure provides a pixel layout structure of an organic light emitting diode (OLED), an OLED display panel, and a manufacturing method of the OLED display panel. The OLED display panel includes the pixel layout structure. The pixel layout structure includes pixel unit odd rows and pixel unit even rows arranged in mutual misalignment. | 2021-11-11 |
20210351247 | Novel Hybrid Display Architecture - Embodiments of the disclosed subject matter provide a full-color pixel arrangement for a full-color display is provided, the arrangement having a plurality of pixels, with each pixel including a first sub-pixel comprising a Group III-V inorganic emissive thin film configured to emit light of a first color, where there is at least one first sub-pixel per pixel of the full-color pixel arrangement. Each pixel may include an organic second sub-pixel and an organic third sub-pixel that are configured to emit light of a different color than the first color. | 2021-11-11 |