46th week of 2009 patent applcation highlights part 25 |
Patent application number | Title | Published |
20090279332 | Flyback constant voltage converter having both a PWFM mode and a PWM mode - A flyback AC/DC switching converter has a constant voltage (CV) mode. The CV mode has sub-modes. In one sub-mode (“mid output power sub-mode”), the output voltage (VOUT) of the converter is regulated using both pulse width modulation and pulse frequency modulation. Both types of modulation are used simultaneously. In a second sub-mode (“low output power sub-mode”), VOUT is regulated using pulse width modulation, but the converter switching frequency is fixed at a first frequency. By setting the first frequency at a frequency above the frequency limit of human hearing, an undesirable audible transformer humming that might otherwise occur is avoided. In some embodiments, the converter has a third sub-mode (“high output power sub-mode”), in which pulse width modulation is used but the switching frequency is fixed at a second frequency. By proper setting of the second frequency, undesirable EMI radiation and other problems that might otherwise occur are avoided. | 2009-11-12 |
20090279333 | METHOD AND APPARATUS FOR REDUCING STANDBY POWER OF SWITCHING MODE POWER SUPPLIES - An apparatus for coupling a switching mode power supply (SMPS) controller to a rectified line voltage. The apparatus includes a high-voltage startup transistor configured to provide a charging current during a startup phase of the SMPS controller and to provide substantially no current during a normal operation phase of the SMPS controller. A switch coupled to the high-voltage startup transistor. The switch receives a control signal from the SMPS controller, for turning off the switch during the startup phase and turning on the switch during the normal operation phase. A biasing device is connected in series with the switch and maintains the startup transistor in an off state when the SMPS controller is in the normal operation phase. A standby current in the apparatus is substantially lower when the SMPS controller is in the normal operation phase than the charging current in the apparatus when the SMPS is in the startup phase. | 2009-11-12 |
20090279334 | ELECTRONIC DEVICE AND SWITCHING POWER SUPPLY THEREOF - A switching power supply includes a rectifier circuit, a converter, a detecting unit, a control unit, a switching unit, and a protection unit. The rectifier circuit is used for rectifying an input voltage into a first direct current voltage. The converter is configured for generating a first current according to the first direct current voltage. The detecting unit is used for generating a detected voltage according to the first current. The control unit is configured for generating a control signal. The switching unit is used for enabling the converter, and conducting the first current to the detecting unit when receiving the control signal. The protection unit is configured for shunting the first current with the detecting unit when the first current becomes a large current surge. The control unit stops generating the control signal when determining that the detected voltage is equal to or higher than a predetermined value. | 2009-11-12 |
20090279335 | POWER CONVERTER - To provide a power converter, comprising: a pair of main circuit switching elements to which diodes are connected; a means for generating a first PWM basic signal for driving a main circuit switching element; and a reverse voltage application circuit to be operated, triggered by a second PWM basic signal which differs from the first PWM basic signal only in phase. | 2009-11-12 |
20090279336 | Inverter modulator with variable switching frequency - An inverter control is used to control the output of a distributed power generating station, such as a photovoltaic (PV) solar power station, connected to a power grid. The power station is connected to an inverter output. Pulse width modulation is used to shape the output in order to maximize power output within power quality parameters and provides control of a switching frequency of the inverter responsive to a sensed parameter. The technique allows an increase in output efficiency and provides for adjustment of power output to meet power quality parameters to an extent required in order to connect to the power grid. | 2009-11-12 |
20090279337 | LOAD DRIVE DEVICE AND VEHICLE EQUIPPED WITH THE SAME - A surge voltage generated by the switching operation of an IGBT element and voltage variation generated in an equivalent series resistance of a capacitor are superimposed on an input voltage of an inverter. The equivalent series resistance has a temperature dependence that a resistance value increases with a decrease in a capacitor temperature. The IGBT element has a temperature dependence that an element withstand voltage decreases with a decrease in an inverter temperature. When capacitor temperature is lower than a predetermined threshold value, a control device reduces an upper limit value of the input voltage by an amount corresponding to the voltage variation from its upper limit value at a high temperature, and controls a target voltage of a boost converter such that an output voltage does not exceed the upper limit value. Consequently, the allowable range of the surge voltage can be ensured. | 2009-11-12 |
20090279338 | CYCLOCONVERTER GENERATOR - In a cycloconverter generator, there are provided, q number of power circuits that supply rectified DC power of a DC power supply unit as operating power to the p (p>q) number of thyristors, and r (p>r) number of thyristor drive circuits that are connected to the q number of the power circuits and drive the p number of the thyristors, wherein the r number of the thyristors drive circuits are individually used to drive in common ones among the p number of the thyristors whose operation is unaffected even if driven at the same timing such that the number r of the drive circuits is made smaller than the number p of the thyristors, thereby enabling to simplify circuit configuration. | 2009-11-12 |
20090279339 | CYCLOCONVERTER GENERATOR - In a cycloconverter generator equipped with an AC power generator that generates single-phase AC power to be supplied to a load by turning on positive and negative switching elements at variable timing every half-period of a desired AC power frequency based on a phase signal and a DC power generator that generates DC power by turning on the positive switching elements in accordance with a timing determined by desired DC voltage, there is installed with a selection switch that is installed to be operable by an user and produces an output indicative of a result of the user's selection between the AC power and DC power thereby enabling to the user to easily select either one of alternating current and direct current. | 2009-11-12 |
20090279340 | N-way mode content addressable memory array - A disclosed embodiment is an N-way mode CAM (content addressable memory) array comprising M rows that each contain N subwords. Each of the N subwords has a respective mode cell. Additionally, a mode input bus is coupled to each mode cell of each of the N subwords, and a data input bus is coupled to each of the M rows. The mode input bus and the data input bus can uniquely identify as a match a single subword or a plurality of subwords in one of the M rows during a search operation. The disclosed embodiment further comprises a row address encoder/generator coupled to each of the M rows, and an address output bus coupled to each of the row address encoder/generators. The mode input bus is also coupled to each of the row address encoder/generators. A uniquely identified single subword address may be outputted on the address output bus. | 2009-11-12 |
20090279341 | PROXIMITY OPTICAL MEMORY MODULE - A memory module is formed of multiple memory chips and an optical interface chip fixed on a substrate. The chips are interconnected by proximity communication (PxC) in which each chip includes transmitting and receiving elements, such as electrical pads which form capacitively coupled links when the chips are placed together with their pads facing each other. The PxC links may be directly between the chips or through an intermediate passive bridge chip. The interface chip is coupled to an external optical channel and includes converters between optical and electrical signals, control circuitry, buffers, and PxC elements for communicating with the memory chips. The array of memories may be a linear or two-dimensional array around the interface chip forming a redundant PxC network, optionally with redundant PxC connections. Multiple rectangular memory chips may present their narrow sides to the interface chip to maximize bandwidth. | 2009-11-12 |
20090279342 | Method to Improve Ferroelectric Memory Performance and Reliability - One embodiment of the present invention relates to a method by which the imprint of a ferroelectric random access memory (FRAM) array is reduced. The method begins when an event that will cause imprint to the memory array is anticipated by an external agent to the device comprising the chip. The external agent sends a command to the control circuitry that the data states are to be written to a particular data state. Upon receiving a signal the control circuitry writes all of the ferroelectric memory cells in the FRAM array to a preferred memory data state. The memory data states are held in the preferred data state for the entire duration of the event to minimize imprint of the FRAM memory cells. When the event ends the external agent sends a command to the control circuitry to resume normal memory operation. Other methods and circuits are also disclosed. | 2009-11-12 |
20090279343 | OPERATING METHOD OF ELECTRICAL PULSE VOLTAGE FOR RRAM APPLICATION - Metal-oxide based memory devices and methods for operating and manufacturing such devices are described herein. A method for manufacturing a memory device as described herein comprises forming a metal-oxide memory element, and applying an activating energy to the metal-oxide memory element. In embodiments the activating energy can be applied by applying electrical and/or thermal energy to the metal-oxide material. | 2009-11-12 |
20090279344 | RESISTANCE CHANGE MEMORY DEVICE - A resistance change memory device includes: a memory cell formed of a variable resistance element and a diode connected in series, the state of the variable resistance element being reversibly changed in accordance with applied voltage or current; and a stabilizing circuit so coupled in series to the current path of the memory cell as to serve for stabilizing the state change of the memory cell passively. | 2009-11-12 |
20090279345 | RESISTIVE MEMORY ELEMENT SENSING USING AVERAGING - A system for determining the logic state of a resistive memory cell element, for example an MRAM resistive cell element. The system includes a controlled voltage supply, an electronic charge reservoir, a current source, and a pulse counter. The controlled voltage supply is connected to the resistive memory cell element to maintain a constant voltage across the resistive element. The charge reservoir is connected to the voltage supply to provide a current through the resistive element. The current source is connected to the charge reservoir to repeatedly supply a pulse of current to recharge the reservoir upon depletion of electronic charge from the reservoir, and the pulse counter provides a count of the number of pulses supplied by the current source over a predetermined time. The count represents a logic state of the memory cell element. | 2009-11-12 |
20090279346 | FAULT TOLERANT ASYNCHRONOUS CIRCUITS - New and improved methods and circuit designs for asynchronous circuits that are tolerant to transient faults, for example of the type introduced through radiation or, more broadly, single-event effects. SEE-tolerant configurations are shown and described for combinational logic circuits, state-holding logic circuits and SRAM memory circuits. | 2009-11-12 |
20090279347 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device having a memory cell including a flip-flop; and a memory cell power supply circuit for supplying a low voltage cell power supply voltage to the memory cell. The memory cell power supply circuit supplies a cell power supply voltage in a first period and a different cell power supply voltage in a second period, a predetermined first power supply voltage in case where the cell power supply voltage in supplied in a data read cycle and in a case where data is not written to a memory cell to which the cell power supply voltage is supplied in a write cycle, and a second power supply voltage higher than the first power supply voltage in a case where data is written to a memory cell to which the cell power supply voltage is supplied in a write cycle. | 2009-11-12 |
20090279348 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a memory cell array, which includes a plurality of read word lines, a plurality of first and second read bit lines, and a plurality of memory cells arranged in array. The memory cell includes a first and a second cell node in complementary pair, a first drive transistor controlled by the second cell node, and a second drive transistor controlled by the first cell node. The read word line and the first read bit line are connected with each other via the first drive transistor. The read word line and the second read bit line are connected with each other via the second drive transistor. | 2009-11-12 |
20090279349 | PHASE CHANGE DEVICE HAVING TWO OR MORE SUBSTANTIAL AMORPHOUS REGIONS IN HIGH RESISTANCE STATE - Memory devices are described herein along with method for operating the memory device. A memory cell as described herein includes a first electrode and a second electrode. The memory cell also comprises phase change material having first and second active regions arranged in series along an inter-electrode current path between the first and second electrode. | 2009-11-12 |
20090279350 | BIPOLAR SWITCHING OF PHASE CHANGE DEVICE - Memory devices and methods for operating such devices are described herein. A method as described herein includes applying a reset bias arrangement to a memory cell to change the resistance state from the lower resistance state to the higher resistance state. The reset bias arrangement comprises a first voltage pulse. The method further includes applying a set bias arrangement to the memory cell to change the resistance state from the higher resistance state to the lower resistance state. The set bias arrangement comprises a second voltage pulse, the second voltage pulse having a voltage polarity different from that of the first voltage pulse. | 2009-11-12 |
20090279351 | SEMICONDUCTOR MEMORY DEVICES AND METHODS HAVING CORE STRUCTURES FOR MULTI-WRITING - A semiconductor memory device having an efficient core structure for multi-writing includes a data input/output line, a plurality of memory banks each comprising a plurality of memory cells, a first global bit line and a second global bit line which are shared by the plurality of memory banks, and a first write driver and a second write driver which are connected with the data input/output line and provide a program current to the plurality of memory banks through the first and second global bit lines, respectively. Each memory bank includes a first cell area connected with the first global bit line and a second cell area connected with the second global bit line. In a multi-write mode, the first cell area in a first memory bank among the plurality of memory banks and the second cell area in a second memory bank among the plurality of memory banks are simultaneously selected and data is written to memory cells in the selected first and second cell areas, so that data writing time is reduced under the same conditions as a normal write mode. | 2009-11-12 |
20090279352 | Storage nodes, phase change memories including a doped phase change layer, and methods of operating and fabricating the same - Example embodiments may provide a doped phase change layer and a method of operating and fabricating a phase change memory with the example embodiment doped phase change layer. The phase change memory may include a storage node having a phase change layer and a switching device, wherein the phase change layer includes indium with a concentration ranging from about 5 at % to about 15 at %. The phase change layer may be a GST layer that includes indium. The phase change layer may be a GST layer that includes gallium. | 2009-11-12 |
20090279353 | MAGNETIC TUNNEL JUNCTION TRANSISTOR - A magnetic tunnel junction transistor and method of operating the same. In a particular embodiment, the magnetic tunnel junction transistor includes electrically conductive source, drain and gate electrodes. An electrically insulating material having a non-magnetoelectric region and a magnetoelectric region is positioned such that the non-magnetoelectric region is, at least partially, between the source electrode and the drain electrode. The magnetoelectric region of the insulating material, when energized, is configured to change magnetic state of the insulating material. The gate electrode is positioned proximate the magnetoelectric region of the insulating material. | 2009-11-12 |
20090279354 | Stacked Magnetic Devices - Techniques for improving magnetic device performance are provided. In one aspect, a magnetic device, e.g., a magnetic random access memory device, is provided which comprises a plurality of current carrying lines; and two or more adjacent stacked magnetic toggling devices sharing at least one of the plurality of current carrying lines in common and positioned therebetween. The magnetic device is configured such that at least one of the adjacent magnetic toggling devices toggles mutually exclusively of another of the adjacent magnetic toggling devices. In an exemplary embodiment, the magnetic device comprises a plurality of levels with each of the adjacent stacked magnetic toggling devices residing in a different level. | 2009-11-12 |
20090279355 | LOW POWER FLOATING BODY MEMORY CELL BASED ON LOW BANDGAP MATERIAL QUANTUM WELL - Embodiments of the invention relate to apparatus, system and method for use of a memory cell having improved power consumption characteristics, using a low-bandgap material quantum well structure together with a floating body cell. | 2009-11-12 |
20090279356 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A memory includes first selective transistors connected between one end of cell strings and bit lines; second selective transistors connected between the other end of the cell strings and a cell source line; a dummy cell string; a first dummy selective transistor connected between one end of the dummy cell string and a dummy bit line and whose gate is connected to a first selective gate line; a second dummy selective transistor connected between the other end of the dummy cell string and the cell source line and whose gate is connected to a second selective gate line, wherein at a time of writing in a selected memory cell, a voltage of a first dummy bit line selected is driven to a different voltage from a voltage of an unselected bit line, and any of the dummy cell transistors connected to the first dummy bit line is written. | 2009-11-12 |
20090279357 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF TESTING THE SAME - A nonvolatile semiconductor storage device includes a memory cell array including a plurality of memory cells arranged at intersection positions of word lines and bit lines in a matrix form, and a row decoder including a row sub-decoder to which a lower address for selecting a word line is input, wherein one unit of the row sub-decoder for selecting one word line is constituted of a first transistor of a first conduction type, and a second transistor of a second conduction type, and a gate electrode of each of the first and second transistors is arranged in a direction in which the bit lines are arranged. | 2009-11-12 |
20090279358 | SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME - A semiconductor device includes: a first sector ( | 2009-11-12 |
20090279359 | NAND WITH BACK BIASED OPERATION - Methods of programming, reading and erasing memory cells are disclosed. In at least one embodiment, program, sense, and erase operations in a memory are performed with back biased operation, such as to improve high voltage device isolation and cutoff in string drivers and bit line drivers, and no nodes of the circuitry are biased at zero volts | 2009-11-12 |
20090279360 | NAND based NMOS NOR flash memory cell, a NAND based NMOS nor flash memory array, and a method of forming a NAND based NMOS NOR flash memory array - A NOR flash nonvolatile memory device provides the memory cell size and a low current program process of a NAND flash nonvolatile memory device and the fast, asynchronous random access of a NOR flash nonvolatile memory device. The NOR flash nonvolatile memory device has an array of NOR flash nonvolatile memory circuits. Each NOR flash nonvolatile memory circuit includes a plurality of charge retaining transistors serially connected in a NAND string. A drain of a topmost charge retaining transistor is connected to a bit line associated with the serially connected charge retaining transistors and a source of a bottommost charge retaining transistor is connected to a source line associated with the charge retaining transistors. Each control gate of the charge retaining transistors on each row is commonly connected to a word line. The charge retaining transistors are programmed and erased with a Fowler-Nordheim tunneling process. | 2009-11-12 |
20090279361 | Addressable Memory Array - This document discloses non-volatile memory cells and methods of manufacturing the same. The memory arrays are byte, word, and/or page addressable without using a byte select transistor. The byte select transistor is eliminated by using the well, memory transistor control gates, and select transistor gates to selectively program a byte, word, or page. | 2009-11-12 |
20090279362 | PARTIAL SCRAMBLING TO REDUCE CORRELATION - Decorrelation is provided between data stored in respective pairs of adjacent memory cells in a plurality of bit lines of a flash memory. Each of the pairs of adjacent memory cells is located along a respective one of the bitlines and common to two adjacent wordlines. The decorrelation is achieved by storing scrambled data in at least one memory cell of each of the pairs of adjacent memory cells and storing unscrambled data in at least one memory cell of at least one of the pairs of adjacent memory cells. | 2009-11-12 |
20090279363 | METHOD AND SYSTEM FOR MINIMIZING NUMBER OF PROGRAMMING PULSES USED TO PROGRAM ROWS OF NON-VOLATILE MEMORY CELLS - A flash memory device programs cells in each row in a manner that minimizes the number of programming pulses that must be applied to the cells during programming. The flash memory device includes a pseudo pass circuit that determines the number of data errors in each of a plurality of subsets of data that has been programmed in the row. The size of each subset corresponds to the number of read data bits coupled from the memory device, which are simultaneously applied to error checking and correcting circuitry. During iterative programming of a row of cells, the pseudo pass circuit indicates a pseudo pass condition to terminate further programming of the row if none of the subsets of data have a number of data errors that exceeds the number of data errors that can be corrected by the error checking and correcting circuitry. | 2009-11-12 |
20090279364 | METHOD OF PROGRAMMING IN A FLASH MEMORY DEVICE - A method of programming a flash memory device includes programming a first memory cell coupled to an even bit line by applying a first program voltage to a word line, and verifying whether the first memory cell is programmed through a first verifying voltage. The first program voltage that is repeatedly increased by a step voltage when the first memory cell is not programmed. A second memory cell coupled to an odd bit line is programmed by applying the first program voltage to the word line. Whether the second memory cell is programmed is verified using a second verifying voltage that is higher than the first verifying voltage. The second memory cell is programmed using a program voltage that is repeatedly increased by the step voltage when the second memory cell is not programmed. | 2009-11-12 |
20090279365 | NON-VOLATILE SEMICONDUCTOR MEMORY SYSTEM - A non-volatile semiconductor memory system includes a first memory block group including a plurality of memory blocks each including a plurality of erasable and programmable non-volatile semiconductor memory cells and a second memory block group including a plurality of memory blocks each including a plurality of erasable and programmable non-volatile semiconductor memory cells. Block addresses of the second memory block group and block addresses of the first memory block group are non-continuous via blank addresses. | 2009-11-12 |
20090279366 | HYBRID SOLID-STATE MEMORY SYSTEM HAVING VOLATILE AND NON-VOLATILE MEMORY - A hybrid solid-state memory system is provided for storing data. The solid-state memory system comprises a volatile solid-state memory, a non-volatile solid-state memory, and a memory controller. Further, a method is provided for storing data in the solid-state memory system. The method comprises the following steps. A write command is received by the memory controller. Write data is stored in the volatile memory in response to the write command. Data is transferred from the volatile memory to the non-volatile memory in response to a data transfer request. | 2009-11-12 |
20090279367 | POWER SAVING SENSING SCHEME FOR SOLID STATE MEMORY - Methods and apparatus are disclosed, such as those involving a solid state memory device. One such method includes selecting a plurality of memory cells in a memory array. States of a plurality of data bits stored in the selected plurality of memory cells are determined. In determining the states of the plurality of data bits, a portion of the plurality of data bits are sensed faster than others. The plurality of data bits are sequentially provided as an output. In one embodiment, the portion of the plurality of data bits includes the first bit of the sequential output of the memory device. | 2009-11-12 |
20090279368 | CIRCUIT AND METHOD FOR GENERATING PUMPING VOLTAGE IN SEMICONDUCTOR MEMORY APPARATUS AND SEMICONDUCTOR MEMORY APPARATUS USING THE SAME - A circuit for generating a pumping voltage in a semiconductor memory apparatus includes a control signal generation block configured to generate a first control signal obtained by level-shifting a voltage level of a test signal to a first driving voltage level, a voltage application section configured to supply an external voltage to a first node in response to a first transmission signal, a first charge pump configured to raise a voltage level of the first node by a first predetermined level in response to an oscillator signal, and a first pumping voltage output section configured to select at least one of a first connection unit and a second connection unit in response to the first control signal, and to interconnect the first node with a second node using the selected connection unit when a second transmission signal is enabled, wherein a first pumping voltage is output through the second node. | 2009-11-12 |
20090279369 | DATA OUTPUT APPARATUS AND METHOD FOR OUTPUTTING DATA THEREOF - A data output apparatus includes a driver driving unit configured to generate driving signals by using input data when a data output enable signal is enabled, a data driver unit configured to drive an output terminal to a level corresponding to the input data in response to the driving signals to generate output data, and an output data level control unit configured to open a current path to control a level of the output data, wherein the current path is different from a current path for driving the output terminal to a level corresponding to the input data. | 2009-11-12 |
20090279370 | MEMORY CIRCUIT AND METHOD OF SENSING A MEMORY ELEMENT - The memory circuit comprises at least one memory element (T | 2009-11-12 |
20090279371 | HYBRID SENSE AMPLIFIER AND METHOD, AND MEMORY DEVICE USING SAME - Sense circuits, devices and methods are disclosed, including a sense amplifier circuit that has first and second complementary data lines and a sensing circuit. One of the data lines can be coupled to a memory cell for data sensing and the other data line can be used as reference. The sensing circuit has first and second complementary output nodes and is coupled to the data lines. In a first mode, the sensing circuit can sense a difference between a voltage on the first digit line and a voltage on the second digit line to generate a first voltage differential between the first and second output nodes. In a second mode, the sensing circuit can sense a difference between a current flow in the first digit line and a current flow in the second digit line to generate a second voltage differential between the first and second output nodes. Other sense circuits, devices and methods are also provided. | 2009-11-12 |
20090279372 | SEMICONDUCTOR MEMORY DEVICE AND SENSE AMPLIFIER - In a sense amplifier circuit having a plurality of sense amplifier portions arranged in order, each of the sense amplifier portions includes a transistor that supplies a bit line potential to a bit line pair in a corresponding column of a memory cell array and a gate electrode for supplying a precharge signal to a gate of the transistor. The gate electrode of the plurality of sense amplifier portions is provided as one piece as a whole and extends in a direction parallel to a row direction in the memory cell array. A gate electrode portion which is a connected portion between the gate electrode in a k-th sense amplifier portion and the gate electrode in a (k+1)-th sense amplifier portion is ring-shaped, where k is an odd number. | 2009-11-12 |
20090279373 | AUTO-REFRESH OPERATION CONTROL CIRCUIT FOR REDUCING CURRENT CONSUMPTION OF SEMICONDUCTOR MEMORY APPARATUS - An auto-refresh operation control circuit for a semiconductor memory apparatus is activated according to a bank active signal for executing a refresh operation and terminates the refresh operation by receiving a precharge signal. The auto-refresh operation control circuit is configured to prevent an over-driving operation during an auto-refresh operation and to delay the enablement of the precharge signal. The auto-refresh operation control circuit also delays the enablement of the precharge signal during the auto-refresh operation more than a delay of the precharge signal during a self-refresh operation. | 2009-11-12 |
20090279374 | SYSTEM AND METHOD FOR MITIGATING REVERSE BIAS LEAKAGE - The present disclosure includes devices, methods, and systems for programming memory, such as resistance variable memory. One embodiment can include an array of resistance variable memory cells, wherein the resistance variable memory cells are coupled to one or more data lines, a row decoder connected to a first side of the array, a column decoder connected to a second side of the array, wherein the second side is adjacent to the first side, a gap located adjacent to the row decoder and the column decoder, and clamp circuitry configured to control a reverse bias voltage associated with one or more unselected memory cells during a programming operation, wherein the clamp circuitry is located in the gap and is selectively coupled to the one or more data lines. | 2009-11-12 |
20090279375 | VOLTAGE DOWN CONVERTER FOR HIGH SPEED MEMORY - A voltage down converter (VDC) applicable to high-speed memory devices. The VDC includes a steady driver and active driver along with at least one additional transistor. The steady driver and active driver are coupled by a transistor switch during device start-up to provide fast ramp-up to operating voltage and current. After start-up, the steady driver and active drive function to maintain a steady operating voltage and current. An additional transistor is digitally controlled to drive up operating voltage and current upon issuance of an active command representing read, write, and/or refresh of memory. In this manner, the additional transistor provides fast compensation for fluctuations in operating voltage and current brought on by activity in the memory array. | 2009-11-12 |
20090279376 | METHOD AND SYSTEM FOR SELECTIVELY LIMITING PEAK POWER CONSUMPTION DURING PROGRAMMING OR ERASE OF NON-VOLATILE MEMORY DEVICES - A power supply circuit is used to supply power having a limited peak magnitude to an array of non-volatile memory cells during programming or erasing of the memory cells. The power supply circuit includes a reference current source supplying a reference current having a predetermined magnitude. The reference current source is coupled to a current generator, which supplies current to the array. The current generator may use current mirrors, and it supplies a current to the array having a predetermined relationship to the reference current. The current generator is selectively enabled by a control circuit so that current is supplied to the array during programming or erasing of at least some of the memory cells in the array. | 2009-11-12 |
20090279377 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a memory cell array including a plurality of mutually intersecting word lines and bit lines, and a plurality of memory cells connected at intersections thereof and each having a read port and a write port provided independently; and a plurality of word line drivers operative to drive the word lines. The elements contained in the memory cell have respective sizes in common with the elements contained in the word line driver. | 2009-11-12 |
20090279378 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device including a clock input for receiving a source clock and supplying a generated clock to a plurality of clock transmission lines; a plurality of clock amplifiers, each amplifying a respective generated clock loaded on one of the plurality of clock transmission lines in response to a column enable signal; and a data input/output for inputting/outputting a plurality of data in response to the amplified clocks output by the plurality of clock amplifiers. | 2009-11-12 |
20090279379 | Blender for containerized products - A blender mechanism for applying a mixing action on containerized non-homogenized products. The blender mechanism includes a housing having a drive roller and an idler roller with the rollers being mounted in spaced apart parallel relationship with respect to each other and disposed in a substantially horizontal attitude. A drive assembly is coupled to the drive roller for rotational driving thereof and the drive assembly preferably includes a variable speed electric motor which is coupled through a gear train to the drive roller. The housing and idler roller are configured so that the idler roller can be moved to increase the spacing between the idler and drive rollers to accommodate larger sizes of containerized products. Also, an additional idler roller can be installed in parallel spaced relationship with the first idler roller so that a second containerized product to be mixed can be supported upon the spaced apart idler rollers. | 2009-11-12 |
20090279380 | Water supply mixing process - A process and system mixes drinking water stored in large water tower type storage tanks, preventing stratification of the water, by generating large mixing s bubbles in the tank's standpipe, causing mixing of layers of water in the tank through turbulence created as the bubbles rise through the tank. Embodiments of the present invention, adapted for use in storage tanks in which the standpipe serves as both water inlet and outlet, detect flow in the standpipe and provide mixing only when the standpipe is not serving as a water outlet. | 2009-11-12 |
20090279381 | Water tank deicing mixer - A means for mitigating or precluding formation of ice in water stored in large storage tanks generates large mixing bubbles toward the bottom of the tank, causing mixing of thermally stratified layers of water in the tank through turbulence created as the bubbles rise through the tank. Incipient stratification of water along thermoclines is detected and the mixer is engaged only when temperatures of portions of stratified water in the tank approach freezing. | 2009-11-12 |
20090279382 | DEVICE, MIXER AND SYSTEM FOR MIXING AND DISPENSING OF A MATERIAL AND METHOD OF USE - A device for mixing and dispensing dental materials is provided, comprising a drive shaft for driving a mixer. The mixer is placeable on the drive shaft in a first and a second position, wherein in the first position a guiding section of the drive shaft is mated with an engagement section of the mixer, but an engagement section of the drive shaft is not engaged with the engagement section of the mixer, and in the second position the engagement section of the drive shaft is also engaged with the engagement section of the mixer. | 2009-11-12 |
20090279383 | Autonomous Data Relay Buoy - An easily deployable data relay buoy, in some embodiments, has a diesel powered alternator and storage battery, providing long service life. The data relay buoy has mechanical characteristics that allow it to maintain antenna stability in the presence of seas states from at least zero through four and to survive in sea states up to sea state six. | 2009-11-12 |
20090279384 | Control Methods for Distributed Nodes - A method of controlling distributed devices includes configuring the devices to respond to a controlled signal; positioning the devices in an area of interest; and transmitting the controlled signal into the earth. The earth acts as the signal transmission medium. The method may include controlling a signal generator with a controller to transmit the controlled signal. An illustrative controlled signal may have a fixed frequency, a fixed amplitude, a fixed wave form, a modulated frequency, a modulated amplitude, a modulated wave form, and/or a predetermined duration. In aspects, the method may include connecting the signal generator to the earth and transmitting the controlled signal into the earth using the signal generator. Afterwards, the signal generator may be operated to impart seismic energy into the earth. The devices may be used to detect and record seismic energy that has reflected from underground formations. | 2009-11-12 |
20090279385 | Control System for Positioning Marine Seismic Streamers - A method of controlling a streamer positioning device ( | 2009-11-12 |
20090279386 | METHOD FOR DETERMINING ADEQUACY OF SEISMIC DATA COVERAGE OF A SUBSURFACE AREA BEING SURVEYED - A method for assessing data coverage in a three dimensional marine seismic survey includes determining at least one Fresnel zone for at least one of a plurality of seismic data traces. A contribution is determined for each of the seismic data traces to each one of a set of bins in a defined pattern. Each contribution is based on the Fresnel zone associated with each seismic data trace. The contributions from all seismic data traces contributing to each bin are summed. The summed contribution for each bin are stored or displayed and the summed contributions in each bin are compared to a selected threshold to determine coverage. | 2009-11-12 |
20090279387 | Marine passive seismic method for direct hydrocarbon detection - A method for detection of hydrocarbon bearing formations below the bottom of a body of water from seismic signals includes moving a plurality of spatially distributed seismic sensors in a body of water and detecting seismic signals including response to any seismic energy having frequencies down to proximate zero. The method includes stacking the acquired seismic signals from the plurality of the sensors in both longitudinal and transverse directions with respect to motion of the sensors in the body water. The stacked signals are analyzed for presence of passive seismic energy indicative of hydrocarbon bearing formations below the bottom of the body of water. | 2009-11-12 |
20090279388 | METHOD FOR DETERMINING ADEQUACY OF SEISMIC DATA COVERAGE OF A SUBSURFACE AREA BEING SURVEYED AND ITS APPLICATION TO SELECTING SENSOR ARRAY GEOMETRY - A method for marine seismic surveying includes towing a seismic sensors in a plurality of streamers in the water, actuating a seismic energy source in the water at selected times and detecting seismic signals at the sensors resulting from the actuation of the source. A data trace is created for each of the detected signals. At least one Fresnel zone is determined for at least some of the seismic data traces. A contribution of each of the traces to each one of a plurality of bins defined in a predetermined pattern is computed, based on the Fresnel zone associated with each trace. Based on the computed contributions, a maximum lateral distance between corresponding seismic sensors is determined that will result in a contribution sum above a selected threshold. | 2009-11-12 |
20090279389 | ULTRASONIC SIGNAL COMMUNICATION DEVICE, COMMUNICATION DEVICE, COMMUNICATION DEVICE FOR DIVERS, COMMUNICATION SYSTEM, AND COMMUNICATION METHOD - An ultrasonic signal communication device that has an ultrasonic oscillation unit that has at least two resonance frequencies according to the oscillation mode, a transmission unit that generates a first ultrasonic signal at one of the two resonance frequencies and transmits the generated first ultrasonic signal from the ultrasonic oscillation unit, and a reception unit that receives from the ultrasonic oscillation unit a second ultrasonic signal that is transmitted at the other of the two resonance frequencies. | 2009-11-12 |
20090279390 | Thermoacoustic device - An apparatus includes an electromagnetic signal device, a medium, and a sound wave generator. The sound wave generator includes a carbon nanotube structure. The carbon nanotube structure includes one or more carbon nanotube films. Each carbon nanotube film includes a plurality of carbon nanotubes entangled with each other. The electromagnetic signal device transmits an electromagnetic signal to the carbon nanotube structure. The carbon nanotube structure converts the electromagnetic signal into heat. The heat transfers to the medium and causes a thermoacoustic effect. | 2009-11-12 |
20090279391 | APPARATUS FOR MEASURING PRESSURE IN A VESSEL USING MAGNETOSTRICTIVE ACOUSTIC TRANSDUCER - The present invention relates to an apparatus for measuring pressure inside a vessel using a magnetostrictive acoustic transducer. The apparatus includes a magnetostrictive acoustic transducer, including an exciting coil unit wound on a first magnetization yoke disposed on an outer position of a vessel, a receiving coil unit wound on the first magnetization yoke, and a vibration unit disposed on an inner position of the vessel in which the first magnetization yoke is installed; a control unit for supplying a predetermined excitation current signal to the exciting coil unit; and a pressure measuring unit for measuring an internal pressure of the vessel based on an ultrasonic wave signal received by the receiving coil unit and an excitation current signal into the exciting coil unit. | 2009-11-12 |
20090279392 | ELECTRONIC DEVICE AND METHOD PROVIDING IMPROVED INDICATION THAT AN ALARM CLOCK IS IN AN ON CONDITION - An improved electronic device and method provide an improved clock feature having an alarm clock function that advantageously provides an indication to a user that the alarm is set, i.e., is in an ON condition, by outputting the alarm time itself. | 2009-11-12 |
20090279393 | Playing data from an optical media drive - Example embodiments provide various techniques for playing data from an optical media drive. The optical media drive may detect certain media access information for use in accessing optical media. This media access information is stored in a memory that is configured to retain the media access information after the optical media drive is deactivated. The optical media drive reads the data from an optical media and this data is transferred to a buffer until, with reference to some threshold parameter, the optical media drive is deactivated. The optical media drive may be reactivated in reference to another threshold parameter and the media access information is thereafter retrieved from the memory. The optical media drive may then read from the optical media using the provided media access information. | 2009-11-12 |
20090279394 | DISC PROCESSING DEVICE AND CONTROL METHOD FOR DISC PROCESSING DEVICE - The effect of detection errors when detecting if a disc recording medium is in a disc drive is eliminated. A control unit | 2009-11-12 |
20090279395 | OPTICAL DISK DRIVES AND METHOD FOR CONTROLLING TRACK-SEEKING FOR OPTICAL DISK DRIVES - The invention provides an optical disk drive. The optical disk drive comprises a pickup head, a seek control device, a lens vision characteristic decoder, and an anti lens shift device. The pickup head comprises a sled and a lens for projecting a beam on a disk. The seek control device moves the sled, and shifts the lens with a shift distance relative to an origin at a center of the sled. The equalizer derives a servo signal from a reflection of the beam. The lens vision characteristic decoder obtains a vision characteristic of the lens according to the servo signal and determines a track-on direction according to the vision characteristic. The anti lens shift device triggers the seek control device to perform a track-on process according to the track-on direction. | 2009-11-12 |
20090279396 | Misjudgment correction circuit and optical disk drive - Disclosed herein is a misjudgment correction circuit, including, an edge detection section configured to detect, in a binarized full addition signal obtained by adding first and second signals of the same or opposite polarity, edges at which the logic value of the binarized signal changes, a push-pull signal acquisition section configured to acquire a binarized push-pull signal obtained by subtracting the second signal from the first signal, a majority decision calculation section configured to acquire, in chronologic order, a plurality of logic values of the push-pull signal between the two adjacent edges so as to determine, by a majority decision, the more numerous of the two logic values, and a wave correction section configured to correct the push-pull signal between the edges to the more numerous logic value determined by the majority decision calculation section. | 2009-11-12 |
20090279397 | CENTER ERROR MECHANICAL CENTER ADJUSTMENT - An apparatus comprising a center error creation circuit and a center error offset injection circuit. The center error creation circuit may be configured to generate a center error signal in response to light from a main laser reflected from a surface of an optical disc. The center error offset injection circuit may be configured to (i) determine a value of the center error signal when a lens in a sled housing is at a mechanical center and (ii) generate an offset signal based upon the value. The center error offset injection circuit generally measures an average value of the center error signal over a predetermined amount of time when a lens suspension which holds the lens in place is in a mechanical equilibrium state. | 2009-11-12 |
20090279398 | Portable recorder/players with power-saving buffers - In electronic devices such as combination CD-ROM and MP3 recorder/players power is conserved by buffering audio or visual data in a solid state memory, preferably of the FLASH or DRAM type, before writing the data to a rotating hard disk. Alternatively, audio and/or visual data, including musical works and still pictures and video, read from a rotating hard disk may be buffered in the same solid state memory while being played. By rotating the hard disk drive only for transfer of audio-visual data, which is normally compressed, in blocks, the hard drive may be stopped both during relative lengthy accumulation, and/or use, of this data, and energy conserved. | 2009-11-12 |
20090279399 | OPTICAL HEAD AND OPTICAL DISC DEVICE - A tilt can be detected highly accurately by minimizing the tilt detection error. An optical head includes: an objective lens for converging a light beam from a light source onto an optical disc; a photodetector section receiving the beam, reflected from the disc, at divided areas on its photodetection plane and outputting light detection signals from those areas; and a tilt detecting section for detecting a relative tilt between the lens and disc based on the detection signals. The tilt detecting section generates a first push-pull signal PP | 2009-11-12 |
20090279400 | INFORMATION REPRODUCING DEVICE AND METHOD, AND COMPUTER PROGRAM - An information reproducing apparatus ( | 2009-11-12 |
20090279401 | Recording Medium, Apparatus and Method for Recording/Reproducing Data on/From Recording Medium - A recording medium and an apparatus for recording/reproducing data on the recording medium, which are capable of controlling access to the recording medium by recording control information for controlling access for reading the data, are disclosed. When a function included in the recording medium cannot be performed, Unknown Rules are applied, and, when the function included in the recording medium can be performed, Known Rules are applied. Even in the Known Rules, a password may be used such that data reading is controlled. Accordingly, it is possible to compatibly reproduce the data from different versions of recording media. It is difficult for a user to access to the recording medium such that content protection can be improved. | 2009-11-12 |
20090279402 | INFORMATION RECORDING MEDIUM, INFORMATION RECORDING APPARATUS AND METHOD, AND COMPUTER PROGRAM - An information recording apparatus is for recording user data and recording management data onto an information recording medium being provided with: a first recording layer; and a second recording layer, each of the first recording layer and the second recording layer having a user data area to record therein at least the user data and a recording management area to record therein at least the recording management data for managing recording of the user data, the information recording apparatus is provided with: a recording device for dividing the recording management area into a plurality of recording management segments and for recording the recording management data into at least one of the plurality of recording management segments; and a first controlling device for controlling the recording device to dispose each of the plurality of recording management segments in a single recording layer. | 2009-11-12 |
20090279403 | OPTICAL DISC DEVICE - Light emitted from a radiation light source | 2009-11-12 |
20090279404 | Apparatus and Method for Writing Optical Information - An optical disk writing apparatus enhances writing accuracy by writing first data (e.g., test data) that encodes a first writing strategy within first patterns on an optical disk, in response to a first writing signal. A reproducing signal is generated in response to reading the first data from the optical disk. Variations between leading and trailing edges of the first writing signal and leading and trailing edges of the reproducing signal are detected. A correction value is determined using a jitter evaluation function to evaluate the detected variations. From these operations, a second writing strategy is determined using the correction value to modify the first writing strategy. Thereafter, second data (e.g., actual data) is written, which encodes the second writing strategy within second patterns on the optical disk. | 2009-11-12 |
20090279405 | OPTICAL DISC DRIVE, OPTICAL STORAGE MEDIUM, OPTICAL STORAGE MEDIUM INSPECTION APPARATUS, AND OPTICAL STORAGE MEDIUM INSPECTION METHOD - An optical disc drive having an optical pickup head emitting a light beam to an optical storage medium, detecting the light beam reflected from the optical storage medium, and outputting a signal based on the received reflected light, having a jitter measuring unit measuring jitter in signals output from the optical pickup head and having an evaluation unit determining from the measured jitter if the optical storage medium is good or defective. The jitter measuring unit measures jitter in a train of 3T or longer marks or spaces from an optical storage medium to which digital information is recorded as a train of marks or spaces of length kT based on a period T and an integer k of two or more. | 2009-11-12 |
20090279406 | HOLOGRAM RECORDING AND REPRODUCING SYSTEM - A hologram recording and reproducing system for recording or reproducing information to or from a hologram record carrier that stores an optical interference pattern of a reference beam and a signal beam therein as a diffraction grating, includes: light producing means that generates a reference beam and a signal beam based on a coherent beam in which the coherent beam is modulated into the signal beam according to information to be recorded; interference means that allows one of the reference and signal beams to propagate axially on an optical axis as a central region light flux and allows the other of the reference and signal beams to propagate coaxially and annularly in section as an annular region light flux surrounding the one spatially separated from the other in a same direction and converges both the reference beam and the signal beam on different focal points in the optical axis respectively through an objective lens optical system to cause interference between the reference beam and the signal beam; a hologram record carrier having a hologram record layer located on a side of a near one of the different focal points to the objective lens optical system and a reflection layer located on a side of a distant one of the different focal points from the objective lens optical system; and image detecting means arranged on the optical axis and for receiving a beam returning from the hologram record layer through the objective lens optical system when the reference beam is illuminated to the hologram record layer; wherein the hologram record carrier further comprising a servo guide layer which is placed at a position either nearer to the objective lens optical system than the hologram record layer or farther than the reflection layer from the objective lens optical system. The hologram recording and reproducing system further includes a servo control system for focusing a servo beam onto the servo guide layer and for receiving a reflection light returning from the servo guide layer to photoelectrically convert it to a signal and for driving the objective lens optical system in accordance with the signal photoelectrically converted, wherein the servo beam has a wavelength different from the coherent beam wavelength and passes through the central region coaxially with the central region light flux including the optical axis. | 2009-11-12 |
20090279407 | SETUP FOR STORING DATA IN A HOLOGRAPHIC STORAGE MEDIUM - The present invention relates to a setup for storing data in a holographic storage medium, comprising a spatial light modulator medium ( | 2009-11-12 |
20090279408 | OPTICAL DATA RECORDING/REPRODUCING SYSTEM PICKING UP MULTIPLE TRACKS BETWEEN GUARD BANDS - The present invention relates to an optical system for performing radial tracking on an optical record carrier ( | 2009-11-12 |
20090279409 | OPTIMAL DETECTION OF TWODOS SIGNALS - A method and a device for simultaneously reading information from a plurality of data tracks ( | 2009-11-12 |
20090279410 | METHOD AND APPARATUS FOR CONTROLLING SPHERICAL ABERRATION CORRECTION FOR AN OPTICAL DISK DRIVE - The invention provides a method for controlling spherical aberration correction for an optical disk drive. First, a collimator lens is moved to a first target position for spherical aberration correction. A driving time of motion of the collimator lens is then calculated. A prohibiting time is then determined according to the driving time. The collimator lens is then prevented from moving until the prohibiting time elapses. | 2009-11-12 |
20090279411 | INFORMATION RECORDING MEDIUM - In an information recording medium comprising at least a substrate, a recording layer, and a resin layer, the substrate is formed with at least a pit corresponding to a read only area | 2009-11-12 |
20090279412 | Information Recording Media, A Method For Recording/Reproducing Information, An Apparatus For Recording/Reproducing Information - An information recording medium includes a plurality of layers for recording or reproduction of information by irradiation, wherein each of the layers includes an emboss portion and wobble portion including wobbles of a first frequency and a second frequency that is different from the first frequency. The first frequency is constant in each of the plurality of layers, and a different signal is obtained from the wobbles of the first and second frequencies in each of the plurality of layers. | 2009-11-12 |
20090279413 | INFORMATION RECORDING MEDIUM - In an information recording medium comprising at least a substrate, a recording layer, and a resin layer, the substrate is formed with at least a pit corresponding to a read only area | 2009-11-12 |
20090279414 | INFORMATION RECORDING MEDIUM HAVING SUBSTRATE WITH MICROSCOPIC PATTERN AND REPRODUCING APPARATUS THEREFOR - A recording medium includes a substrate having a microscopic pattern, which includes a shape of continuous substance of approximately parallel grooves formed with a convex shaped section and a concave shaped section alternating on a surface of the substrate. A recording layer is formed on the microscopic pattern and a light transmitting layer has a thickness of 0.05 mm to 0.12 mm formed on the recording layer. The microscopic pattern satisfies a relation of P≦λ/NA, wherein P is a pitch of the convex shaped section, λ is a wavelength of a reproducing light beam and NA is a numerical aperture of an objective lens. The microscopic pattern also includes modulated address information formed on both side walls of the convex shaped section viewed from the light transmitting layer as a wobble, both the side walls being parallel to each other, and furthermore wherein the address information is modulated by the phase-shift keying modulation system. A reproducing apparatus is particularly suited for the recording medium. | 2009-11-12 |
20090279415 | INFORMATION RECORDING MEDIUM - In an information recording medium comprising at least a substrate, a recording layer, and a resin layer, the substrate is formed with at least a pit corresponding to a read only area | 2009-11-12 |
20090279416 | Optical disc and optical recording method - The invention provides an optical disc ( | 2009-11-12 |
20090279417 | INFORMATION RECORDING APPARATUS - An information recording apparatus is disclosed that includes a control unit that controls operations of recording user data on an information recording medium having plural recording layers. When a second layer following a first layer of the recording layers remains unrecorded at the time user data recording performed in response to a user data recording request is completed, the control unit records temporary lead-out information after the recorded user data. | 2009-11-12 |
20090279418 | OVERLAY MODULATION OF COFDM USING PHASE AND AMPLITUDE OFFSET CARRIERS - Systems and methods are presented for transmitting additional data over preexisting differential COFDM signals by modulating existing data carriers with a phase and an amplitude offset. In exemplary embodiments of the present invention, additional data capacity can be achieved for an COFDM signal which is completely backwards compatible with existing satellite broadcast communications systems. In exemplary embodiments of the present invention additional information can be overlayed on an existing signal as a combination of amplitude and phase offset from the original QPSK symbols, applied for each information bit of the overlay data. With two additional levels of modulation, a receiver can demodulate the information from each of the previous stages and combine the information into a suitable format for soft decoding. The first stage of demodulation will be recovery of overlay data from the amplitude modulated D8PSK. Because other amplitude variations due to multi-path are also expected, the data gathered from the FFT in the receiver must be equalized to the channel conditions. After channel equalization has been performed, soft overlay data can then be derived from the distance off the unit circle. In order to recover the phase modulated overlay data, the equalized symbols must first be differentially demodulated and corrected for any common phase error offset. After common phase removal, overlay phase information can be obtained. | 2009-11-12 |
20090279419 | COMMUNICATION APPARATUS AND COMMUNICATION METHOD - To efficiently compress the information amount for feedback when a communication apparatus sends back a result of performing discrete cosine transform on the reception quality information to a communication apparatus of a communicating destination. In a communication apparatus for transmitting feedback information generated based on a plurality of reception quality information to a communicating destination apparatus, the feedback information is a result of performing discrete cosine transform on the plurality of reception quality information, and performing respective different quantization on signal components of at least a group of samples among signal components of a plurality of samples obtained by the discrete cosine transform. | 2009-11-12 |
20090279420 | BASE STATION APPARATUS, RADIO TRANSMISSION SYSTEM, RADIO BASE STATION PROGRAM, AND TIMING ESTIMATION METHOD - A base station apparatus ( | 2009-11-12 |
20090279421 | APPARATUS AND METHODS FOR ESTIMATING AND COMPENSATING SAMPLING CLOCK OFFSET - An apparatus for sampling clock recovery (SCO) and methods for estimating and compensating SCO are provided. The apparatus comprises a symbol timing adjustment module for shifting forward or backward symbol timing of the transmitted OFDM symbols; a discrete Fourier transform (DFT) processor for performing DFT to an output from the symbol timing adjustment module; a channel estimator for undertaking a channel frequency response estimation based on a channel estimation sequence; a SCO phase rotator for receiving and performing phase shift on the transmitted OFDM symbols of a frame header and a frame payload; an SCO estimation stage for undertaking an SCO estimation based on a pilot-subcarrier-related output of the SCO phase rotator and the CFR estimation; and an SCO compensation distributor for dividing the SCO estimation into integer and fractional portions and then distributing them into the symbol timing adjustment module and the SCO phase rotator, respectively. | 2009-11-12 |
20090279422 | Single sideband and quadrature multiplexed continuous phase modulation - A class of bandwidth reduction techniques are used develop a broad class of modulation types collectively called SSB-FM. These signals can be used to construct communication systems that provide bandwidth-normalized performance gains of 10 dB or more when compared to popular prior art modulation methods. An aspect of the invention involves mapping trellis paths in a complex signal space onto corresponding real-valued trellis signals with desirable spectral properties. The invention can be used map continuous phase modulated (CPM) signals onto simpler amplitude-modulated trellis signals having double the channel capacity of prior art CPM signals. Multi-amplitude signaling and frequency division multiplexing may also be incorporated to further accommodate more information per symbol. | 2009-11-12 |
20090279423 | Recovering from Failures Without Impact on Data Traffic in a Shared Bus Architecture - Methods of detecting and recovering from communication failures within an operating network switching device that is switching packets in a communication network, and associated structures. The communication failures addressed involve communications between the packet processors and a host CPU over a shared communications bus, e.g., PCI bus. The affected packet processor(s)—which may be all or a subset of the packet processors of the network switch—may be recovered without affecting hardware packet forwarding through the affected packet processors. This maximizes the up time of the network switching device. Other packet processor(s), if any, of the network switching device, which are not affected by the communication failure, may continue their normal packet forwarding, i.e., hardware forwarding that does not involve communications with the host CPU as well as forwarding or other operations that do involve communications with the host CPU. | 2009-11-12 |
20090279424 | METHODS, COMMUNICATION NETWORKS, AND COMPUTER PROGRAM PRODUCTS FOR COMMUNICATING TIME DIVISION MULTIPLEXING TRAFFIC USING A TRAFFIC ENCAPSULATION STANDARD CONFIGURED TO SUPPORT STATISTICAL MULTIPLEXING (STATMUX) TRAFFIC - A communication network is operated by communicating Time Division Multiplexing (TDM) traffic and data (STATMUX) traffic over a single connection, where the single connection may include multiple aggregated lines using a traffic encapsulation standard configured to support STATMUX traffic. | 2009-11-12 |
20090279425 | METHOD, SYSTEM, AND NETWORK ELEMENT FOR SERVICE PROCESSING AFTER DATA OF NETWORK ELEMENT IS INVALID OR NETWORK ELEMENT FAILS - A method, a system, and a network element for service processing after data of a network element is invalid or a network element fails is provided. When the service network element receives the service request message from the network and is initiated to a called end and the user data is invalid, the service network element returns a data invalid message of the called end to the network. When a network element containing registration data of a user is abnormal and the registration data of the user is invalid, by using the present invention, the service unavailable time is shortened, and user services can be recovered rapidly. | 2009-11-12 |
20090279426 | SYSTEM AND METHOD FOR DEAD GATEWAY DETECTION - A system and method for detecting a next-hop dead gateway is disclosed. In one embodiment, a method for detecting the next-hop dead gateway includes sending an Internet Protocol (IP) packet by a host to a next-hop gateway associated with the host, receiving the IP packet by the host from the next-hop gateway upon reviewing a routing table and the destination field in the IP header associated with the IP packet, determining whether the IP packet is received from the next-hop gateway within a first predetermined time interval, if so, declaring the next-hop gateway as alive, and if not, declaring the next-hop gateway as dead. In some embodiments, source and destination fields in IP header associated with the IP packet include IP address associated with the host. The method may further include encapsulating the IP packet with a data link layer protocol associated with the host and the next-hop gateway. | 2009-11-12 |
20090279427 | Control of Quality of Service in Overlapping Basic Service Sets in Wireless Local Area Networks - Access priority for wireless devices located in an area in which radiofrequency (RF) coverage areas of a first wireless access point and a second wireless access point overlap is controlled by coordinating operation of the first wireless access point and the second wireless access point. The wireless devices access a common RF channel via a collision sense multiple access/collision avoidance mechanism. The probability of accessing the RF channel may be varied by adjusting the length of interframe spacings and the length of contention windows. The length of the interframe spacings and the length of the contention windows associated with the first access point and associated with the second access point are configured such that the probability of wireless devices associated with the first wireless access point accessing the RF channel is greater than the probability of wireless devices associated with the second wireless access point accessing the RF channel. | 2009-11-12 |
20090279428 | Frame transmitting apparatus and method thereof - A frame transmitting apparatus transmits a frame to a frame receiving apparatus. The frame transmitting apparatus includes a accumulated-capacity-value storage unit that has stored therein an accumulated capacity value calculated; a cycle and capacity storage unit that has stored therein a cycle and a frame read capacity at every cycle; an adding unit that adds the value indicative of the capacity of the frame to the accumulated capacity value; a subtracting unit that subtracts the value indicative of the frame read capacity from the accumulated capacity value; and a transmission controlling unit that controls frame transmission by using the accumulated capacity value. | 2009-11-12 |
20090279429 | OPTIMISATION PROCESS OF THE CONTROL OF TRAFFIC IN A PACKET TELECOMMUNICATIONS NETWORK - The invention relates to a process for optimizing the control of the traffic in a packet telecommunications network comprising at least one transmitter terminal ( | 2009-11-12 |
20090279430 | FEMTO CELL ACCESS POINT PASSTHROUGH MODEL - The subject innovation provides system(s) and method(s) to supply fixed, differentiated quality of service (QoS) for packetized traffic (e.g., voice and data) intended for femto cell coverage when transmitted concurrently with external broadband traffic. Quality of Service differentiation is supplied without an external implementation. Femto cell coverage is prioritized over concurrent packetized traffic to deliver a rich user experience for delay and jitter sensitive applications. A passthrough configuration for a femto access point (AP) facilitates supplying hard QoS for data packet streams, or flows, intended for femto cell coverage or non-femto-cell coverage. The femto AP receives a consolidated packet stream through backhaul link(s) and distinguishes flow(s) for femto coverage and flow(s) for auxiliary broadband coverage. The femto AP routes the flow(s) intended for femto with hard QoS according to QoS policy which can be determined by a network operator or a subscriber. | 2009-11-12 |
20090279431 | Load Balancing Pseudowire Encapsulated IPTV Channels Over Aggregated Links - A method for load balancing IPTV channels is described. In one embodiment of the invention, a first Provider Edge (PE) network element of a label switched network, coupled with a second PE network element over multiple member links of an aggregate link, receives IPTV packets. For each IPTV packet received, the first PE network determines layer 3 information of the IPTV packet, and generates one or more channel load balancing keys based on the layer 3 information. The PE network element generates a hash value from the channel load balancing keys and determines which one of multiple member links to transmit the IPTV packet on based on the hash value, and transmits the IPTV packet to the second PE network element on the determined member link. Other methods and apparatuses are also described. | 2009-11-12 |