47th week of 2011 patent applcation highlights part 59 |
Patent application number | Title | Published |
20110289243 | COMMUNICATION CONTROL DEVICE, DATA COMMUNICATION METHOD AND PROGRAM - A communication control device includes reception controllers capable of receiving data in a burst transfer mode in which packets are continuously transferred as one burst. There are dedicated buffers having a capacity of one packet for each of a plurality of endpoints and common buffers shared by the endpoints; a first packet of a burst transfer is stored in the dedicated buffer; and a common buffer is secured at the same time. The dedicated buffers and common buffers are controlled according to a transfer status. | 2011-11-24 |
20110289244 | TELEVISION WITH INTEGRATED ASYNCHRONOUS/SYNCHRONOUS KVMP SIGNAL SWITCH FOR CONSOLE AND PERIPHERAL DEVICES - A television with integrated signal switch ( | 2011-11-24 |
20110289245 | Memory Controller and Method Utilizing Equalization Co-Efficient Setting - A chip includes a transmitter circuit and a register provided to store a value representative of an equalization co-efficient setting. The transmitter circuit includes an output driver configured to adjust an output data signal based at least in part on the equalization co-efficient setting. | 2011-11-24 |
20110289246 | SUPER I/O MODULE, COMPUTER SYSTEM AND CONTROL METHOD THEREOF - A super I/O module for controlling at least one I/O port of a computer system is provided. The super I/O module includes a controller, a signal detector and a selector. The controller supports functions corresponding to the I/O port. The signal detector receives an input signal from the I/O port, and detects whether the input signal has an identification code. When detecting that the input signal has the identification code, the signal detector generates a selection signal according to the identification code. The selector receives the selection signal and selectively provides the input signal to the controller or a function circuit of the computer system according to the selection signal. | 2011-11-24 |
20110289247 | Autonomous positional addressing in stacked multi-board systems - A method includes receiving a first address over an address bus at a first module, modifying the first address to generate a second address, and transmitting the second address over the address bus to a second module. The method also includes determining at the first module if at least one of the first and second addresses has a specified value. Modifying the first address could include incrementing or decrementing the first address to generate the second address. Determining if at least one of the first and second addresses has the specified value could include determining if the first address has a value of zero or a value of 2 | 2011-11-24 |
20110289248 | Isolated communication bus and related protocol - A system includes a master device and multiple slave devices. The system also includes multiple bus interfaces forming a communication bus that couples the master and slave devices. Each bus interface includes a primary interface unit configured to communicate over first and second buses, where the first and second buses form a portion of the communication bus. Each bus interface also includes a secondary interface unit configured to communicate with the primary interface unit and to communicate with one of the slave devices over a third bus. Each bus interface further includes an isolator configured to electrically isolate the primary interface unit and the secondary interface unit. The primary interface unit is configured to receive multiple commands over the first bus, execute a first subset of commands, transmit a second subset of commands over the second bus, and transmit a third subset of commands over the third bus. | 2011-11-24 |
20110289249 | INTERRUPTION FACILITY FOR ADJUNCT PROCESSOR QUEUES - Interruption facility for adjunct processor queues. In response to a queue transitioning from a no replies pending state to a reply pending state, an interruption is initiated. This interruption signals to a processor that a reply to a request is waiting on the queue. In order for the queue to take advantage of the interruption capability, it is enabled for interruptions. | 2011-11-24 |
20110289250 | CARD ADAPTER - A card adapter includes a printed circuit board (PCB). The PCB includes a first memory slot to receive a memory module to be corrected, a connecting portion with several golden fingers to insert into a second memory slot of a computer system, and first and second switches. The memory slot of the PCB includes several terminals corresponding to pins of a serial presence detect (SPD) chip of the memory module. The golden fingers correspond to pins of the second memory slot. The first switch is set between the terminal corresponding to the serial data signal pin of the memory module and the golden finger corresponding to the serial data signal pin of the second memory slot. The second switch is set between the terminal corresponding to the serial clock signal pin of the memory module and the golden finger corresponding to serial clock signal pin of the second memory slot. | 2011-11-24 |
20110289251 | INTERFACE CARD QUICK PLUG-AND-UNPLUG DEVICE - An interface card quick plug-and-unplug device for use with a PCIe interface card is disclosed to include a shell covering a part of the PCIe interface card, and a locating member disposed at one side of the shell and/or the PCIe interface card for engagement with the PCIe slot upon insertion of the PCIe interface card into the PCIe slot. Biasing the locating member allows quick removal of the PCIe interface card from the PCIe slot without any tool. The interface card quick plug-and-unplug device enhances the flexibility of the design of computer circuit layout. | 2011-11-24 |
20110289252 | STORAGE ROUTER AND METHOD FOR PROVIDING VIRTUAL LOCAL STORAGE - A storage router and method for providing virtual local storage on remote storage devices to devices are provided. Devices are connected to a first transport medium, and a plurality of storage devices are connected to a second transport medium. In one embodiment, the storage router maintains a map to allocate storage space on the remote storage devices to devices connected to the first transport medium by associating representations of the devices connected to the first transport medium with representations of storage space on the remote storage devices, wherein each representation of a device connected to the first transport medium is associated with one or more representations of storage space on the remote storage devices and controls access from the devices connected to the first transport medium to the storage space on the remote storage devices in accordance with the map and using native low level block protocol. | 2011-11-24 |
20110289253 | INTERCONNECTION METHOD AND DEVICE, FOR EXAMPLE FOR SYSTEMS-ON-CHIP - Transactions of the request/response type between a first circuit module and a second circuit module operating with incompatible protocols or interfaces envisage organizing a queue of memory locations for storing transaction information items and transaction identifiers associated to said transactions and implementing the transactions via operations of reading/writing of the locations in the queue, mapping on the transaction identifiers information for management of the queue. | 2011-11-24 |
20110289254 | CONFIGURABLE DIGITAL AND ANALOG INPUT/OUTPUT INTERFACE IN A MEMORY DEVICE - Methods and memory devices are disclosed, for example a memory device that has both an analog path and a digital path that both share the same input/output pad. One of the two paths on each pad is selected in response to command signals that indicate the nature of the signal being either transmitted to the device or read from the device. Each digital path includes a latch for latching digital input data. Each analog path includes a sample/hold circuit for storing either analog data being read from or analog data being written to the memory device. | 2011-11-24 |
20110289255 | APPARATUSES FOR MANAGING AND ACCESSING FLASH MEMORY MODULE - A method for maintaining address mapping for a flash memory module is disclosed including: recording a first set of addresses corresponding to a first set of sequential logical addresses in a first section of a first addressing block; recording a second set of addresses corresponding to a second set of sequential logical addresses in a second section of the first addressing block; recording a third set of addresses corresponding to a third set of sequential logical addresses in a first section of a second addressing block; and recording a fourth set of addresses corresponding to a fourth set of sequential logical addresses in a second section of the second addressing block; wherein the second set of logical addresses is successive to the first set of logical addresses, and the third set of logical addresses is successive to the second set of logical addresses. | 2011-11-24 |
20110289256 | MEMORY BANKING SYSTEM AND METHOD TO INCREASE MEMORY BANDWIDTH VIA PARALLEL READ AND WRITE OPERATIONS - A cache memory and a tag memory are included in a banked memory system and used to effectively enable parallel write and read operations on each clock cycle, even though the memory banks consist of single-port devices that are not inherently capable of parallel write and read operations. | 2011-11-24 |
20110289257 | METHOD AND APPARATUS FOR ACCESSING CACHE MEMORY - A request for reading data from a memory location of a main memory is received, the memory location being identified by a physical memory address. In response to the request, a cache memory is accessed based on the physical memory address to determine whether the cache memory contains the data being requested. The data associated with the request is returned from the cache memory without accessing the memory location if there is a cache hit. The data associated is returned from the main memory if there is a cache miss. In response to the cache miss, it is determined whether there have been a number of accesses within a predetermined period of time. A cache entry is allocated from the cache memory to cache the data if there have been a predetermined number of accesses within the predetermined period of time. | 2011-11-24 |
20110289258 | MEMORY INTERFACE WITH REDUCED READ-WRITE TURNAROUND DELAY - Embodiments of a memory system that communicates bidirectional data between a memory controller and a memory IC via bidirectional links using half-duplex communication are described. Each of the bidirectional links conveys write data or read data, but not both. States of routing circuits in the memory controller and the memory IC are selected for a current command being processed so that data can be selectively routed from a queue in the memory controller to a corresponding bank set in the memory IC via one of the bidirectional links, or to another queue in the memory controller from a corresponding bank set in the memory IC via another of the bidirectional links. This communication technique reduces or eliminates the turnaround delay that occurs when the memory controller transitions from receiving the read data to providing the write data, thereby eliminating gaps in the data streams on the bidirectional links. | 2011-11-24 |
20110289259 | MEMORY SYSTEM CAPABLE OF ENHANCING WRITING PROTECTION AND RELATED METHOD - A memory system is disclosed. The memory system includes a memory device, a first control unit, and a second control unit. The memory device is utilized for storing data. The first control unit is coupled to the memory device for prohibiting a data writing process performed on the memory device during a writing protection period. The second control unit is coupled to the memory device for allowing the data writing process to be performed in the memory device according to a writing period after the writing protection period, wherein the writing period is related to the data writing process. | 2011-11-24 |
20110289260 | METHOD FOR PERFORMING BLOCK MANAGEMENT USING DYNAMIC THRESHOLD, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for performing block management is provided. The method is applied to a controller of a Flash memory, where the Flash memory includes a plurality of blocks. The method includes: adjusting a dynamic threshold according to at least one condition; and comparing a valid/invalid page count of a specific block of the plurality of blocks with the dynamic threshold to determine whether to erase the specific block. An associated memory device and a controller thereof are also provided, where the memory device includes the Flash memory and the controller. In particular, the controller includes a read only memory (ROM) arranged to store a program code, and further includes a microprocessor arranged to execute the program code to control access to the Flash memory and manage the plurality of blocks, where under control of the microprocessor, the controller operates according to the method. | 2011-11-24 |
20110289261 | METHOD AND SYSTEM FOR A STORAGE AREA NETWORK - In a system and method for a storage area network (SAN), a first controller receives a write request for a SAN an communicates with a first nested storage array module (NSAM), the first NSAM manages storage of data onto a shelf and presents the shelf as a logical unit, a buffer stores a portion of a write request from the first controller and aggregates data from the write request for the shelf, from a shelf with a second NSAM, the second NSAM provides a portion of data from the buffer to a third NSAM, the third NSAM manages storage of the portion of data from the buffer to a physical storage unit, and a second controller coupled to the first controller handles requests for the SAN in response to a failure of the first controller. | 2011-11-24 |
20110289262 | CONTROLLER FOR SOLID STATE DISK, WHICH CONTROLS SIMULTANEOUS SWITCHING OF PADS - Provided is a controller for a solid state disk, to control simultaneous switching of pads. The controller for the solid state disk may control simultaneous switching of a plurality of output pads or a plurality of input pads that correspond to a plurality of channels. In particular, the controller may properly delay signals driven to the output pads or input pads, to reduce power supplied to the pads, and to prevent ground bouncing, as well as, maintain a quality of signals. | 2011-11-24 |
20110289263 | SYSTEM INCLUDING A FINE-GRAINED MEMORY AND A LESS-FINE-GRAINED MEMORY - A data processing system includes one or more nodes, each node including a memory sub-system. The sub-system includes a fine-grained, memory, and a less-fine-grained (e.g., page-based) memory. The fine-grained memory optionally serves as a cache and/or as a write buffer for the page-based memory. Software executing on the system uses a node address space which enables access to the page-based memories of all nodes. Each node optionally provides ACID memory properties for at least a portion of the space. In at least a portion of the space, memory elements are mapped to locations in the page-based memory. In various embodiments, some of the elements are compressed, the compressed elements are packed into pages, the pages are written into available locations in the page-based memory, and a map maintains an association between the some of the elements and the locations. | 2011-11-24 |
20110289264 | Memory System Having Nonvolatile and Buffer Memories, and Reading Method Thereof - Disclosed is a method for reading data in a memory system including a buffer memory and a nonvolatile memory, the method being comprised of: determining whether an input address in a read request is allocated to the buffer memory; determining whether a size of requested data is larger than a reference unless the input address is allocated to the buffer memory; and conducting a prefetch reading operation from the nonvolatile memory if the requested data size is larger than the reference. | 2011-11-24 |
20110289265 | STORAGE SYSTEM AND STORAGE MANAGEMENT METHOD FOR CONTROLLING OFF-LINE MODE AND ON-LINE OF FLASH MEMORY - An object of the present invention is to provide a storage system and storage management method, which prevent a problem in the operation of stored data from being caused by unknown states of volume information and life information, when flash memories are placed in off-line mode and again placed in on-line mode. According to the present invention, there is provided a storage system | 2011-11-24 |
20110289266 | GARBAGE COLLECTION IN STORAGE DEVICES BASED ON FLASH MEMORIES - A solution for managing a storage device based on a flash memory is proposed. A corresponding method starts with the step for mapping a logical memory space of the storage device (including a plurality of logical blocks) on a physical memory space of the flash memory (including a plurality of physical blocks, which are adapted to be erased individually). The physical blocks include a set of first physical blocks (corresponding to the logical blocks) and a set of second—or spare—physical blocks (for replacing each bad physical block that is unusable). The method continues by detecting each bad physical block. Each bad physical block is then discarded, so to prevent using the bad physical block for mapping the logical memory space. | 2011-11-24 |
20110289267 | APPARATUS, SYSTEM, AND METHOD FOR SOLID-STATE STORAGE AS CACHE FOR HIGH-CAPACITY, NON-VOLATILE STORAGE - An apparatus, system, and method are disclosed for solid-state storage as cache for high-capacity, non-volatile storage. The apparatus, system, and method are provided with a plurality of modules including a cache front-end module and a cache back-end module. The cache front-end module manages data transfers associated with a storage request. The data transfers between a requesting device and solid-state storage function as cache for one or more HCNV storage devices, and the data transfers may include one or more of data, metadata, and metadata indexes. The solid-state storage may include an array of non-volatile, solid-state data storage elements. The cache back-end module manages data transfers between the solid-state storage and the one or more HCNV storage devices. | 2011-11-24 |
20110289268 | FACILITATING COMMUNICATION BETWEEN MEMORY DEVICES AND CPUS - According to one embodiment, an apparatus comprises one or more memory devices and one or more processors coupled to a circuit board. The memory devices are configured according to a second memory technology. The processors are configured to receive messages conforming to a first memory technology, translate the messages from the first memory technology to the second memory technology, and send the translated messages to the memory devices. | 2011-11-24 |
20110289269 | MEMORY SYSTEM AND METHOD HAVING POINT-TO-POINT LINK - A memory system includes a controller for generating a control signal and a primary memory for receiving the control signal from the controller. A secondary memory is coupled to the primary memory, the secondary memory being adapted to receive the control signal from the primary memory. The control signal defines a background operation to be performed by one of the primary and secondary memories and a foreground operation to be performed by the other of the primary and secondary memories. The primary memory and the secondary memory are connected by a point-to-point link. At least one of the links between the primary and secondary memories can be an at least partially serialized link. At least one of the primary and secondary memories can include an on-board internal cache memory. | 2011-11-24 |
20110289270 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR DATA TRANSFER MANAGEMENT - According to one aspect of the present disclosure a method and technique for managing data transfer is disclosed. The method includes comparing, by a processor unit of a data processing system, data to be written to a memory subsystem to a stored data pattern and, responsive to determining that the data matches the stored data pattern, replacing the matching data with a pattern tag corresponding to the matching data pattern. The method also includes transmitting the pattern tag to the memory subsystem. | 2011-11-24 |
20110289271 | SYSTEM AND METHOD FOR OPTIMIZING DATA RAMANENCE OVER HYBRID DISK CLUSTERS USING VARIOUS STORAGE TECHNOLOGIES - A method is implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions. The programming instructions are operable to optimize data ramanence over hybrid disk clusters using various storage technologies. The programming instructions are operable to determine one or more data storage technologies accessible by a file system. The programming instructions are operable to determine secure delete rules for each of the one or more storage technologies accessible by the file system. The secure delete rules include a number of overwrites required for data to be securely deleted from each of the one or more storage technologies. The programming instructions are operable to provide the secure delete rules to the file system upon a request for deletion of data for each of the one or more storage technologies a specific amount of times germane to secure delete data from the one or more storage technologies. | 2011-11-24 |
20110289272 | Apparatus and methods for restoring data in a RAID system - The present invention provides a RAID controller and an operation method thereof, to avoid buffer data loss due to accidental power loss for a long period of time. The RAID controller comprises a first memory, a switch and a functional module. The first memory stores a buffer data. The switch is coupled to the first memory. The functional module is coupled to the switch, and has a second memory. The functional module causes the switch to be connected to the first memory based on a pre—determined instruction, to backup the buffer data by means of the second memory. | 2011-11-24 |
20110289273 | DISK ARRAY DEVICE AND METHOD FOR CONTROLLING DISK ARRAY DEVICE - A disk array device includes, a cache memory, a plurality of types of disk drives of which data transfer capacity are different, redundant transmission paths that are data transfer paths between the cache memory and the disk drives, and a controller to divide the disk drives into two groups based on the data transfer capacity and allocate each of the two groups to each of the redundant transmission paths when the disk drives have three types. | 2011-11-24 |
20110289274 | Storage Device Realignment - Realigning storage devices arranged as storage arrays when one of the storage arrays enters a critical state after failure of a storage device is disclosed. The method is particularly useful for RAID groups of storage devices. The method may be used with hard disk drives, solid-state drives, and other storage devices arranged as groups. The method includes identifying that a storage array of a plurality of storage arrays is in a critical condition. A critical condition storage array and a healthy storage array are identified. Both the critical condition storage array and the healthy storage array are rebuilt. The rebuilding includes configuring the critical condition storage array to include a storage device from the healthy storage array and configuring the healthy storage array to function with one less storage device. The method may be implemented in hardware, firmware, software, or a combination thereof. | 2011-11-24 |
20110289275 | Fast Hit Override - In one embodiment, a cache comprises a tag memory and a comparator. The tag memory is configured to store tags of cache blocks stored in the cache, and is configured to output at least one tag responsive to an index corresponding to an input address. The comparator is coupled to receive the tag and a tag portion of the input address, and is configured to compare the tag to the tag portion to generate a hit/miss indication. The comparator comprises dynamic circuitry, and is coupled to receive a control signal which, when asserted, is defined to force a first result on the hit/miss indication independent of whether or not the tag portion matches the tag. The comparator also comprises circuitry coupled to receive the control signal and configured to inhibit a state change on an output of the dynamic circuitry during an evaluate phase of the dynamic circuitry to produce the first result responsive to an assertion of the control signal. | 2011-11-24 |
20110289276 | CACHE MEMORY APPARATUS - A cache memory apparatus includes an L1 cache memory, an L2 cache memory coupled to the L1 cache memory, an arithmetic logic unit (ALU) within the L2 cache memory, the combined ALU and L2 cache memory being configured to perform therewithin at least one of: an arithmetic operation, a logical bit mask operation; the cache memory apparatus being further configured to interact with at least one processor such that atomic memory operations bypass the L1 cache memory and go directly to the L2 cache memory. | 2011-11-24 |
20110289277 | INFORMATION PROCESSING SYSTEM, INFORMATION PROCESSING METHODS AND PROGRAMS - The present invention obtains with high precision, in a storage system, the effect of additional installation or removal of cache memory, that is, the change of the cache hit rate and the performance of the storage system at that time. For achieving this, when executing normal cache control in the operational environment of the storage system, the cache hit rate when the cache memory capacity has changed is also obtained. Furthermore, with reference to the obtained cache hit rate, the peak performance of the storage system is obtained. Furthermore, with reference to the target performance, the cache memory and the number of disks and other resources that are additionally required are obtained. | 2011-11-24 |
20110289278 | METHOD OF ESTIMATING READ LEVEL FOR A MEMORY DEVICE, MEMORY CONTROLLER THEREFOR, AND RECORDING MEDIUM - A method of estimating a read level for a memory device includes calculating first information corresponding to at least one among information about the number of cells having a particular logic level in data to be programmed and information about the number of cells having a particular cell state and storing the first information during a program operation; reading the data based on a threshold level that has been set and calculating second information about the number of cells in at least one state defined by the threshold level with respect to the read data; calculating third information about the number of cells in the at least one state, which corresponds to the second information, using a probability based on the first information; comparing the second information with the third information; and determining whether to change the threshold level according to the comparison result. | 2011-11-24 |
20110289279 | DATA CACHING IN A NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE - Described embodiments provide a method of coherently storing data in a network processor having a plurality of processing modules and a shared memory. A control processor sends an atomic update request to a configuration controller. The atomic update request corresponds to data stored in the shared memory, the data also stored in a local pipeline cache corresponding to a client processing module. The configuration controller sends the atomic update request to the client processing modules. Each client processing module determines presence of an active access operation of a cache line in the local cache corresponding to the data of the atomic update request. If the active access operation of the cache line is absent, the client processing module writes the cache line from the local cache to shared memory, clears a valid indicator corresponding to the cache line and updates the data corresponding to the atomic update request. | 2011-11-24 |
20110289280 | STORAGE SYSTEM, CONTROL METHOD THEREFOR, AND PROGRAM - A disk array device that can detect the successful completion of data overwrite/update at high speed only by checking a UDT is provided. When a DIF is used as a verification code appended to data, check information that detects the successful completion of overwrite is defined in the UDT, in addition to address information that detects positional errors. Upon request of overwrite/update of data stored in a cache, a check bit of the data in the cache is changed to a value different from a check bit to be appended to new data by a host adapter. Then, data transfer is initiated. Upon completion of the data overwrite, the check bit is changed back to the original value, whereby it is possible to detect the successful completion of overwrite/update (FIG. | 2011-11-24 |
20110289281 | Policy Based Data Retrieval Performance for Deduplicated Data - A method that includes, by one or more computer systems, determining a data retrieval rate policy based on at least one data retrieval rate parameter. The method also includes determining at least one storage subsystem performance parameter. The method further includes determining a fragmentation value based on the data retrieval rate policy and the at least one storage subsystem performance parameter. The method additionally includes determining a storage subsystem fragmentation of a first data object. The storage subsystem fragmentation includes fragmenting the first data object into a plurality of first data object fragments. The method also includes deduplicating the first data object based on the fragmentation value and the storage subsystem fragmentation. | 2011-11-24 |
20110289282 | Sessions for Direct Attached Storage Devices - A mechanism and a storage device are provided for registering a component of a computing device, with a user-removably attached storage device and managing sessions between the component and the storage device. The storage device may record time information regarding a beginning and an ending of an activity session with the component. The storage device may determine whether at least a logical block address range of a storage device medium, registered by the component, may have been modified by a different component, since a last session with the component. When the storage device indicates to the component that at least the logical block address range of the medium has not been modified since the last session, the component may trust contents of the medium. The computing device may provide time information to the storage device, such that the storage device may determine whether management operations are to be performed. | 2011-11-24 |
20110289283 | MEMORY DEVICE UTILIZATION IN A DISPERSED STORAGE NETWORK - A method begins by a processing module determining whether a memory device of a dispersed storage (DS) unit is unavailable to produce an unavailable memory device. The method continues with the processing module determining a methodology regarding DS encoded data stored in the unavailable memory device based on one or more dispersed storage network (DSN) conditions to produce a determined methodology when the memory device is unavailable. The method continues with the processing module initiating, in accordance with the determined methodology, a rebuilding function to rebuild the DS encoded data to produce rebuilt DS encoded data when the determined methodology includes a rebuilding component. The method continues with the processing module storing the rebuilt DS encoded data within available memory of the DS unit. | 2011-11-24 |
20110289284 | MULTI-PROCESSOR DEVICE AND INTER-PROCESS COMMUNICATION METHOD THEREOF - Provided are a multi-process device and an inter-process communication (IPC) method thereof. The multi-processor device includes a first processor, a second processor, a first memory connected to the first processor, and a second memory connected to the second processor. When an inter-process communication (IPC) operation is performed between the first processor and the second processor, data is exchanged between the first memory and the second memory. | 2011-11-24 |
20110289285 | CONTROL APPARATUS HAVING NON-VOLATILE RAM, PROTECTION APPARATUS AND METHOD APPLIED THERETO - A control apparatus including a non-volatile RAM divided into a plurality of memory regions including ROM region and RAM region, CPU capable of executing a plurality of types of access to the non-volatile RAM and a protecting portion intervening between the CPU and the non-volatile RAM. The protecting portion includes a register for storing address information capable of specifying address ranges corresponding to the ROM region and RAM region among the memory regions of the non-volatile RAM, access enabling means for enabling the CPU to write data to the ROM region while an enable signal inputted to the protecting portion externally is active, when the CPU performs a write-access to the ROM region, and initializing for initializing the address information stored in the register to be predetermined access information as an initial value when the enable signal is deactivated after activating the enable signal. | 2011-11-24 |
20110289286 | MEMORY CONTROLLER AND A METHOD FOR WRITING INFORMATION TO A K-LEVEL MEMORY UNIT - A method, a computer readable medium and a memory controller. The method for writing information to a K-level memory unit, includes: receiving a sequence of information bits; generating an information value that represents the sequence of information bits; applying a first function to the information value, to provide a first function result; selecting a first cell of the K-level memory unit as a current cell; wherein K is a positive integer that is greater than 1; writing the first function result to the first cell; and repeating the stages of: (a) reading a current cell to provide a current read result; (b) applying a second function to the current read result and to a function result that was written to the current cell, to provide a second function result; (c) selecting another cell as a current cell; and (d) writing the second function result to the current cell. | 2011-11-24 |
20110289287 | STORAGE APPARATUS AND DATA MANAGEMENT METHOD - Proposes the realization of the performance stability operation of virtual volumes and the stabilized access performance for the virtual volumes in the storage apparatus. In the storage apparatus which configures a pool of multiple types of storage tiers of different performances, provides virtual volumes to the host computer and, in accordance with a write request from an application to a virtual volume, assigns pages to the relevant virtual volume from the pool, a policy associating an application with the virtual volume with which the relevant application reads/writes data, a storage tier to assign pages to the relevant virtual volume, and the priority of the relevant storage tier is managed and, in accordance with a write request from the application, complying with the corresponding policy, among the storage tiers associated with the corresponding virtual volume, pages are assigned from the storage tier of the higher priority to the relevant virtual volume. | 2011-11-24 |
20110289288 | USING TYPE STABILITY TO FACILITATE CONTENTION MANAGEMENT - Various technologies and techniques are disclosed for providing type stability techniques to enhance contention management. A reference counting mechanism is provided that enables transactions to safely examine states of other transactions. Contention management is facilitated using the reference counting mechanism. When a conflict is detected between two transactions, owning transaction information is obtained. A reference count of the owning transaction is incremented. The system ensures that the correct transaction was incremented. If the owning transaction is still a conflicting transaction, then a contention management decision is made to determine proper resolution. When the decision is made, the reference count on the owning transaction is decremented by the conflicting transaction. When each transaction completes, the reference counts it holds to itself is decremented. Data structures cannot be deallocated until their reference count is zero. Dedicated type-stable allocation pools can be reduced using an unstable attribute. | 2011-11-24 |
20110289289 | BACKUP AND RESTORE OF ITEMS USING BOUNDED CHECKPOINT AND LOG BUFFERS IN MEMORY - Architecture that is an efficient checkpoint process that performs backup and restore of checkpoint data items using bounded checkpoint buffers and log buffers in memory. Checkpoint processing can be performed using sequential inputs/outputs to a non-volatile storage medium (e.g., hard disk) on which the checkpoint files are persisted. Checkpoint processing is performed is in response to memory parameters that indicate the number or size of log entries accumulating in-memory relative to a memory threshold. In other words, given a bounded memory (e.g., cache), the rate of change of the log entries in the bounded memory triggers checkpoint processing. | 2011-11-24 |
20110289290 | SPACE RESERVATION IN A DEDUPLICATION SYSTEM - Various embodiments for space reservation in a deduplication system are provided. A calculated factoring ratio is determined as a weighted ratio of current nominal data to physical data based on at least one storage capacity threshold and a used storage space currently physically consumed by one of backup and replication data. A maximal nominal estimated space in the computing storage environment is calculated. A remaining space, defined as the maximal nominal estimated space minus a current nominal space in the computing storage environment, is calculated. If the remaining space is one of equal and less than a user-configured reservation space for backup operations, data replication operations are accepted and stored in the computing storage environment. | 2011-11-24 |
20110289291 | CASCADE ORDERING - A system and a method of handling multiple backup processes have been provided. The method comprises receiving one or more instructions initiating a plurality of backup processes from a single source storage volume to a plurality of target storage volumes, adding each target storage volume to a cascade of target storage volumes from the source storage volume, the target storage volumes added to the cascade in an order inversely proportional to the copy rate of the respective backup process, and starting each backup process in turn, the backup processes started in an order from the most recent target storage volume added to cascade to the first target storage volume added to cascade. | 2011-11-24 |
20110289292 | STORAGE SYSTEM PERFORMING VIRTUAL VOLUME BACKUP AND METHOD THEREOF - The respective data fragments stored in each page assigned to the respective virtual areas of the virtual volume are copied to the logical volume, and information representing the respective copy source pages corresponding with information representing the respective virtual areas in the mapping information that indicates which storage area corresponds with which virtual area is updated to information representing the respective copy destination storage areas of the data fragments stored in the respective copy source pages and copies the updated mapping information to the logical volume which constitutes the data fragment copy destination. | 2011-11-24 |
20110289293 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device which is simple in configuration and resistant to tampering. A user input unit receives an authentication code input by a user. A CPU determines whether a user's access is legal based on the input authentication code and activates an enable signal if the user's access is legal. A normal row decoder decodes the row address specified by the CPU and selects a normal memory cell of any row based on the result of decode. A redundancy row decoder prohibits the selection by the normal row decoder when the specified row address agrees with the row address of a predetermined normal memory cell only if the enable signal is activated and selects a redundant memory cell of any row. | 2011-11-24 |
20110289294 | INFORMATION PROCESSING APPARATUS - An information processing apparatus includes: a CPU ( | 2011-11-24 |
20110289295 | SYSTEM, METHOD, AND MEDIA FOR NETWORK TRAFFIC MEASUREMENT ON HIGH-SPEED ROUTERS - A data structure is provided for storing network contact information based on an array of physical memory locations. Virtual vectors are constructed for each source, wherein each element in each virtual vector is assigned to a corresponding physical memory location within the array. The physical memory locations are shared between the virtual vectors uniformly at random so that the noise introduced by sharing can be predicted and removed. A method for storing network contact information is also provided in which a hash function is performed using the address of a source host to find a virtual vector for holding information about the source host. A second hash function is performed using the address of a destination host to find a virtual memory location, within the virtual vector, for holding information about the destination host. Finally, information is stored at a physical memory location assigned to the virtual memory location. Estimation range enhancement is further provided by performing multiple estimations with different sampling probabilities and selecting a best estimation based on a maximum likelihood method. | 2011-11-24 |
20110289296 | STORAGE APPARATUS AND CONTROL METHOD THEREOF - In order to prevent the degradation of performance of a storage apparatus caused by dynamic reallocation, the storage apparatus performs reassigning to a logical page the first physical page which is the physical page provided by the physical drive in Tier 1 which is the higher hierarchy than Tier 2 which is the hierarchy of the physical drive which provides the second physical page which is the physical page currently assigned to the logical page and, at the same time, by making the contents of the second physical page identical to the contents of the first physical page, performs the first migration for the logical page, associating and managing the second physical page and the first physical page and, when performing the second migration by reassigning the physical page provided by the physical drive in Tier 2 to the logical page to which the first physical page is assigned, and performs the second migration by reassigning the relevant second physical page to the logical page again when the second physical page is associated with the first physical page. | 2011-11-24 |
20110289297 | INSTRUCTION SCHEDULING APPROACH TO IMPROVE PROCESSOR PERFORMANCE - A processor instruction scheduler comprising an optimization engine which uses an optimization model for a processor architecture with: means to generate an optimization model for the optimization engine from a design of a processor and data representing optimization goals and constraints and a code stream, wherein the processor has at least two execution pipes and at least two registers, and wherein the design comprises data for processor instruction latency and execution pipes, and wherein the code stream comprises processor instructions with corresponding register selections; and reordering means to generate an optimized code stream from the code stream with the optimal solution provided by the optimization engine for the optimization model by reordering the code stream, such that optimum values for the optimization goals under the given constraints are achieved without affecting the operation results of the code stream. | 2011-11-24 |
20110289298 | SEMICONDUCTOR CIRCUIT AND DESIGNING APPARATUS - A semiconductor circuit includes a memory which stores data; a processing device which executes a program, writes argument data of a function of the program into the memory referring to an address stored in a stack pointer, when a value of a program counter, which indicates an address of the program under execution, reaches a hardware accelerator starting address, and outputs the address stored in the stack pointer; and a hardware accelerator which receives the address of the stack pointer from the processing device, when a value of the program counter of the processing device reaches the hardware accelerator starting address, reads the argument data of the function from the memory referring to the address stored in the stack pointer, and executes the function implemented in hardware using the argument data. | 2011-11-24 |
20110289299 | System and Method to Evaluate a Data Value as an Instruction - A system and method to evaluate a data value as an instruction is disclosed. For example, an apparatus configured to execute program code includes an execute unit configured to execute a first instruction associated with a location of a second instruction. The first instruction is identified by a program counter. The apparatus also includes a decode unit configured to receive the second instruction from the location and to decode the second instruction to generate a decoded second instruction without changing the program counter to point to the second instruction. | 2011-11-24 |
20110289300 | Indirect Branch Target Predictor that Prevents Speculation if Mispredict Is Expected - In one embodiment, a processor implements an indirect branch target predictor to predict target addresses of indirect branch instructions. The indirect branch target predictor may store target addresses generated during previous executions of indirect branches, and may use the stored target addresses as predictions for current indirect branches. The indirect branch target predictor may also store a validation tag corresponding to each stored target address. The validation tag may be compared to similar data corresponding to the current indirect branch being predicted. If the validation tag does not match, the indirect branch is presumed to be mispredicted (since the branch target address actually belongs to a different instruction). The indirect branch target predictor may inhibit speculative execution subsequent to the mispredicted indirect branch until the redirect is signalled for the mispredicted indirect branch. | 2011-11-24 |
20110289301 | Tracing Flow of Data in a Distributed Computing Application - A method is provided for tracing dataflow in a distributed computing application. For example, the method includes incrementally advancing a dataflow in a dataflow path of one or more dataflow paths according to two or more directives encoded in two or more data messages. The method further includes performing the two or more directives. The dataflow path includes one or more operators including at least one merge operator operative to merge the two or more data messages and merge the two or more directives. One or more of the incrementally advancing of the dataflow and the performing of the two or more directives are implemented as instruction code performed on a processor device. | 2011-11-24 |
20110289302 | DATA PROCESSING DEVICE AND METHOD - Overhead is significant when a timestamp according to a reference time is inserted. In view of this, there is provided an LSI which includes: a first time information conversion unit which converts, into time information of a reference time, time information from a first trace data source; a second time information conversion unit which converts, into time information of a reference time, time information from a second trace data source; and a packet merging unit. | 2011-11-24 |
20110289303 | SETJMP/LONGJMP FOR SPECULATIVE EXECUTION FRAMEWORKS - A process for check pointing in speculative execution frameworks, identifies calls to a set of setjmp/longjmp instructions to form identified calls to setjmp/longjmp, determines a control flow path between a call to a setjmp and a longjmp pair of instructions in the identified calls to setjmp/longjmp and replaces calls to the setjmp/longjmp pair of instructions with calls to an improved_setjmp and improved_longjmp instruction pair. The process creates a context data structure in memory, computes a non-volatile save/restore set and replaces the call to improved_setjmp of the setjmp/longjmp pair of instructions with instructions to save all required non-volatile and special purpose registers and replaces a call to improved_longjmp of the setjmp/longjmp pair of instructions with instructions to restore all required non-volatile and special purpose registers and to branch to an instruction immediately following a block of code containing the call to improved_setjmp. | 2011-11-24 |
20110289304 | SYSTEMS, METHODS, AND COMPUTER PROGRAM PRODUCTS FOR CONFIGURING NETWORK SETTINGS - A computer program product having a computer readable medium tangibly recording computer program logic for managing configurations in a computer system is disclosed. The computer program product includes code to configure network information in a first Operating System (OS) environment, code to pass the network information to a second OS environment, and code to effectuate the network information in the first and second OS environments without rebooting the first and second OS environments. | 2011-11-24 |
20110289305 | METHOD AND SYSTEM FOR REMOTE CONFIGURATIONOF A COMPUTING DEVICE - A method and system for remote configuration of a computing device includes generating initialization code configured to initialize a memory and/or processor of the computing device dependent on initialization data. The initialization data is generated based on platform data, which is validate based on predetermined criteria. The platform data identifies platform-specific parameters and may be received over a network from a platform manufacturer. In response to validation of the platform data, the initialization data is generated and transmitted to the platform manufacturer for incorporation into the computing device. Upon a processor reset, the initialization code is configured to use the initialization data to perform initialization procedures to initialize the memory and/or processor of the computing device. The platform data may be updated periodically by an end-user of the computing device. | 2011-11-24 |
20110289306 | METHOD AND APPARATUS FOR SECURE SCAN OF DATA STORAGE DEVICE FROM REMOTE SERVER - A method and device for providing a secure scan of a data storage device from a remote server are disclosed. In some embodiments, a computing device may include an in-band processor configured to execute an operating system and at least one host driver, communication circuitry configured to communicate with a remote server, and an out-of-band (OOB) processor capable of communicating with the remote server using the communication circuitry irrespective of the state of the operating system. The OOB processor may be configured to receive a block read request from the remote server, instruct the at least one host driver to send a storage command to a data storage device, receive data retrieved from the data storage device and authentication metadata generated by the data storage device, and transmit the data and the authentication metadata to the remote server. | 2011-11-24 |
20110289307 | SYSTEM AND METHOD FOR DIRECT SWITCHING OF DATA CONTENT - The invention may provide “undo” (e.g., rollback) features, along with data management simplification features, to an update package model of software suite development/evolution. New functions, which may have disruption effects for customers, may be installed into the core configuration data with inactive switches. Upon activation, a switch status may change, and a query filter may use the activated function (e.g., as associated with the switch ID). Original functions may be maintained, giving the user the ability to deactivate an activated function, and thereby reverting the system back to the prior configuration status. | 2011-11-24 |
20110289308 | TEAM SECURITY FOR PORTABLE INFORMATION DEVICES - A portable information device (PID) having a security module that conducts security-related functionality. At least some of the security-related functionality for the benefit of the PID is provided by a security team of at least one other PID. In one type of arrangement, when configured in a team processing mode, certain ones of the security functions or components operating for the benefit of the PID can be processed on one or more of the security team member devices. In another type of arrangement, the team of devices exchanges security-related information determined as a result of a single team member device's processing of one or more security-related tasks. | 2011-11-24 |
20110289309 | METHOD AND APPARATUS FOR PROVIDING CONTENT - Methods and systems for enabling content to be securely and conveniently distributed to authorized users are provided. More particularly, content is maintained in encrypted form on sending and receiving devices, and during transport. In addition, policies related to the use of, access to, and distribution of content can be enforced. Features are also provided for controlling the release of information related to users. The distribution and control of contents can be performed in association with a client application that presents content and that manages keys. | 2011-11-24 |
20110289310 | Cloud computing appliance - A cloud computing appliance is provided in exemplary embodiment. The cloud computing device includes a computer server. The computer server is configured to receive a user file having a user filename and a user data content. The computer server is further configured to record an index record for the user file including the user filename and a dynamically generated storage name. The computer server is further configured to encipher the user data content with a symmetric key, encipher the symmetric key with an asymmetric key, and transmit a cloud file having a filename of the dynamically generated storage name and a data content of the enciphered user data content and the enciphered symmetric key. | 2011-11-24 |
20110289311 | METHOD OF PERFORMANCE-AWARE SECURITY OF UNICAST COMMUNICATION IN HYBRID SATELLITE NETWORKS - A method and apparatus utilizes Layered IPSEC (LES) protocol as an alternative to IPSEC for network-layer security including a modification to the Internet Key Exchange protocol. For application-level security of web browsing with acceptable end-to-end delay, the Dual-mode SSL protocol (DSSL) is used instead of SSL. The LES and DSSL protocols achieve desired end-to-end communication security while allowing the TCP and HTTP proxy servers to function correctly. | 2011-11-24 |
20110289312 | TCP COMMUNICATION SCHEME - A TCP communication scheme which ensures safe communication up to the communication path near a terminal and eliminates direct attacks from hackers, etc. A terminal (A) and terminal (B) are connected to a relay apparatus (X) and relay apparatus (Y), where the terminal (A) and the terminal (B) are the endpoint terminals positioned at the two ends of a TCP communication connection. The relay apparatuses (X, Y) are each connected to a network (NET). The relay apparatuses (X and Y) are provided so as to be between the terminals (A and B) which had been performing conventional TCP communication, and neither of the relay apparatuses (X and Y) have IP addresses. The relay apparatuses (X and Y) take over the TCP connection between the terminal (A) and the terminal (B), divide the connection into three TCP connections, and establish TCP communication. | 2011-11-24 |
20110289313 | Ticket Authorization - A method for issuing tickets in a communication system comprising a plurality of nodes that are capable of establishing a communication connection between two or more clients, the method comprising a first client transmitting to a ticket-issuing service a request for a ticket authorizing the first client to establish a communication connection with a second client, the ticket-issuing service determining if the first client is authorized to establish the requested communication connection and if the first client is determined to be authorized to establish the requested communication connection, the ticket-issuing service transmitting to the first client one or more tickets designating the second client which authorizes the first client to establish the requested connection with the second client by means of one or more of the plurality of nodes. | 2011-11-24 |
20110289314 | PROXY AUTHENTICATION NETWORK - A Proxy Authentication Network includes a server that stores credentials for subscribers, along with combinations of devices and locations from which individual subscribers want to be authenticated. Data is stored in storage: the storage can be selected by the subscriber. The data stored in the storage, which can be personally identifiable information, can be stored in an encrypted form. The key used to encrypt such data can be divided between the storage and server. In addition, third parties can store portions of the encrypting key. Subscribers can be authenticated using their credentials from recognized device/location combinations; out-of-band authentication supports authenticating subscribers from other locations. Once authenticated, a party can request that the encrypted data be released. The portions of the key are then assembled at the storage. The storage then decrypts the data, generates a new key, and re-encrypts the data for transmission to the requester. | 2011-11-24 |
20110289315 | Generic Bootstrapping Architecture Usage With WEB Applications And WEB Pages - A method includes receiving at a network application function a request related to a generic bootstrapping architecture key originated from a user equipment. The received request includes a network application function identifier that includes a uniform resource locator, where the network application function has a fully qualified domain name. The method further includes causing a generic bootstrapping architecture key to be generated for the user equipment based at least in part on the uniform resource locator that is part of the network application function identifier. Apparatus and computer programs for performing the method are also disclosed. | 2011-11-24 |
20110289316 | USER AUTHENTICATION - Embodiments of the present invention relate to a method and system in which a URI is signed using a private key (PKI), and the signed URI is sent to a second server where the signature is validated using the public key. | 2011-11-24 |
20110289317 | METHOD AND APPARATUS FOR PROVIDING CONTENT AGGREGATION IN SUPPORT OF VIRTUAL CHANNELS - An approach is provided for content aggregation in support of virtual channels. Query information and authentication information of a user are received from a media application associated with a set-top box. A query request is generated for media content from a content provider using the query information, the authentication information, and an identifier of a service provider. Transmission of the query request is initiated to the content provider system. One or more search results are received in response to the query request. Transmission of the one or more search results is initiated to the media application. | 2011-11-24 |
20110289318 | System and Method for Online Digital Signature and Verification - A method to sign online documents may include the steps of loading a signing component from a remote server, automatically launching signing component at user local machine(PC, PDA or smart phone . . .), displaying signing component user interface in web page , entering a password and loading/applying a first key file in cooperation with the signing component, verifying the password and verifying first key, applying the first key to a document digest to generate a digital signature based on the document digest and first key. | 2011-11-24 |
20110289319 | METHOD FOR AUTHENTICATING KEY INFORMATION BETWEEN TERMINALS OF A COMMUNICATION LINK - With the help of a key management protocol, the transmitted key information (si) is authenticated by at least one certificate signed by the terminals (A, B), and at least one fingerprint (fp) of the public keys or certificate, which were used for authenticating the key information (si), is added to the useful part of an SIP message (INVITE). The identity information (idi) present in the header (SIPH) of an SIP message is additionally copied into a region of the header (SIPH) or the useful part (B), and a signature (S) is produced by way of the fingerprint (fp), the datum information (di) presented in the header (SIPH) of an SIP message, the copied identity information (idi′), and optionally the certificate reference information (hz), and is inserted into a further region of the header (SIPH) of the SIP message (INVITE). Advantageously, the additional signature that is produced and inserted according to the invention also remains uninfluenced during a transmission across several networks of different network operators, thereby achieving unique authentication of the transmitted key information. With the method according to the invention, accordingly attacks on the security of the authentication in the networks of the different network operators can be avoided. | 2011-11-24 |
20110289320 | NETWORK WATERMARK - A network communications method utilizing a network watermark for providing security in the communications includes creating a verifiable network communications path of nodes through a network for the transfer of information from a first end node to a second end node; verifying the network communications path of nodes, by the first end node, before communicating by the first end node information intended for receipt by the second end node; and once the network communications path of nodes is verified by the first end node, communicating by the first end node, via the verified communications path of nodes, the information intended for receipt by the second end node; wherein the network watermark represents the verifiable network communications path of nodes. | 2011-11-24 |
20110289321 | METHOD AND APPARATUS FOR A NON-REVEALING DO-NOT-CONTACT LIST SYSTEM - A method and apparatus for a non-revealing do-not-contact list system in which a do-not-contact list of one-way hashed consumer contact information is provided to a set of one or more entities. The set of entities determine whether certain consumers wish to be contacted with the do-not-contact list without discovering actual consumer contact information. | 2011-11-24 |
20110289322 | PROTECTED USE OF IDENTITY IDENTIFIER OBJECTS - This invention states that any and all physical and virtual objects meeting certain criteria may be used as Identity-Identifier-Objects to authenticate people, businesses, organizations, as well as other physical or virtual objects. While accomplishing said task, this invention discloses objects, methods, and special data structures to hide said Identity-Identifier-Objects from exposure to the public, while being used in their intended roles. Additionally, the objects and methods introduced use ownership property of virtual and physical objects to control access and to implement access and licensing rights of physical and virtual objects. Numerous applications areas such as allocation of digital rights, licensing, notarization of digital signatures, and controlled use of personal photographs, fingerprints and other biometric identifier-objects are also illustrated. | 2011-11-24 |
20110289323 | Signing program data payload sequence in progrm loading - Communicating program data between a first device and a second device comprises disassembling a first program file comprising program data into at least one logical data unit, partitioning each of the at least one logical data unit into at least one protocol data unit and computing a first fingerprint over the payload portion of the at least one protocol data unit of the at least one logical data unit. The format of the at least one protocol data unit is defined by a communication protocol and includes a payload portion. | 2011-11-24 |
20110289324 | Optimizing Use of Hardware Security Modules - Use of cryptographic key-store hardware security modules is optimized in a system having a first scarce high-security key storage device and a second more plentiful low-security key storage device comprising securing a cryptographic key to the higher security level by initially storing the key in the first storage device, then responsive to an event, evaluating the stored key against one or more rules, and subsequent to the evaluation, reclassifying the stored key for relocation, encrypting the reclassified key using a key-encryption key; relocating the reclassified key into the second, lower-security storage device, and storing the key-encryption key in the first storage device. | 2011-11-24 |
20110289325 | Data encryption device for storage medium - A data encryption device for storage medium has an encryption key input interface for acquiring a user encryption key; a block code encoder for encoding and decoding data; a scrambler connected with the encryption key input interface and the block code encoder to scramble and descramble data according to the user encryption keys respectively inputted; and a controller connected with the block code encoder and the scrambler, performing an encryption process transmit original data to the block code encoder for encoding, the encoded data to the scrambler for scrambling, and the scrambled data to a storage medium for storage, and performing a decryption process to transmit the scrambled data to the scrambler for descrambling, the encoded data to the block code encoder for decoding to acquire the original data when the user encryption keys respectively inputted in the encryption process and the decryption process are identical. | 2011-11-24 |
20110289326 | ELECTRONIC FILE ACCESS CONTROL SYSTEM AND METHOD - A digital file is associated with a security attribute in which identification data for a physical key is stored. The digital file content is encrypted, and may not be decrypted by a receiving computer unless a removable physical key that can be associated with the receiving computer includes identification data which matches the identification data stored in the file's security attribute. The digital content encrypted in the file may be compressed, and a portion of the security attribute may also be encrypted. When a portion of the security attribute is encrypted, the receiving computer may decrypt only the encrypted portion of the security attribute unless the identification data of the security attribute matches the identification data of a physical key physically or wirelessly coupled to the receiving computer. Improved security and reduction of pirating of the digital content are therefore provided. | 2011-11-24 |
20110289327 | CHASSIS POWER ALLOCATION USING EXPEDITED POWER PERMISSIONS - In one embodiment, a fixed chassis power budget is dynamically allocated to a plurality of servers inserted into a multi-server chassis. An inserted server may be inventoried by sequentially identifying server components, categorically-defined component power limits, and actual component power requirements of the inventoried components. A power permission may be granted to the inserted server prior to completion of the inventory, based on power-related information inferred from a chassis and server specification or from the inventoried components. | 2011-11-24 |
20110289328 | UNIVERSAL SERIAL BUS ASSEMBLY STRUCTURE - A USB (Universal Serial Bus) assembly structure is composed of a power supply device, a lead wire, an electromagnetic wave elimination device, a power adapter, and a plug, wherein a side of the lead wire is provided with a USB power supply device, such that when a computer is not turned on or is hibernated, power can be still supplied by the USB power supply device. In addition, when a computer is not provided with enough USB slots, it is still convenient to supply the USB power. | 2011-11-24 |
20110289329 | LEVERAGING SMART-METERS FOR INITIATING APPLICATION MIGRATION ACROSS CLOUDS FOR PERFORMANCE AND POWER-EXPENDITURE TRADE-OFFS - Managing power expenditures for hosting computer applications. A smart meter can receive electricity pricing information for a data center or other group of computing resources that host computer applications, such as a cloud computing environment. An application manager to determine how much electricity can be saved by operating the applications at a reduced performance level without compromising performance metrics for the applications. A site broker can determine how to sequence the performance levels of the applications to meet an electricity usage budget or to otherwise reduce electricity consumption or costs, for example during a peak load time period. The site broker can also select one or more applications to migrate to another cloud to meet the electricity usage budget or to reduce electricity consumption or costs. A hybrid cloud broker can interact with the site broker to migrate the selected application(s) to another cloud. | 2011-11-24 |
20110289330 | METHOD AND APPARATUS FOR POWER-EFFICIENCY MANAGEMENT IN A VIRTUALIZED CLUSTER SYSTEM - A method for power-efficiency management in a virtualized cluster system is disclosed, wherein the virtualized cluster system comprises a front-end physical host and at least one back-end physical host, and each of the at least one back-end physical host comprises at least one virtual machine and a virtual machine manager for managing the at least one virtual machine. In the method, flow characteristics of the virtualized cluster system are detected at a regular time cycle, then a power-efficiency management policy is generated for each of the at least one back-end physical host based on the detected flow characteristics, and finally the power-efficiency management policies are performed. The method can detect the real-time flow characteristics of the virtualized cluster system and make the power-efficiency management policies thereupon to control the power consumption of the system and perform admission control on the whole flow, thereby realizing optimal power saving while meeting the quality of service requirements, so that a virtualized cluster system with high power-efficiency can be provided. | 2011-11-24 |
20110289331 | STORAGE SYSTEM AND ITS INFORMATION PROCESSING METHOD - Returning a response to a host system in a range which does not cause time-out by the host system even if a disk device in a power saving status is an access target of the host system. A NAS controller determines an access request from a client terminal, outputs a command for spinning up a disk device in a spin off status to a disk controller if the access target includes shared folders corresponding with the disk devices in the spin off status, sends response information to the client terminal to the effect that processing for connection with the shared folder as the access target is being performed in response to the access request, and inhibits the client terminal from shifting to the time-out processing. | 2011-11-24 |
20110289332 | METHOD AND APPARATUS FOR POWER MANAGEMENT IN A MULTI-PROCESSOR SYSTEM - Techniques for power management in a multi-processor system are disclosed. One of the processors in the system monitors whether all threads on all central processing unit (CPU) cores in the multi-processor system halt, and send a message to a south bridge to cause at least a part of the system to enter a low power state if all threads in the multi-processor system halt. The processor sends another message to the south bridge to cause at least a part of the multi-processor system to wake up if at least one thread on any CPU core in the multi-processor system exits a halt. | 2011-11-24 |
20110289333 | METHOD FOR DYNAMICALLY DISTRIBUTING ONE OR MORE SERVICES IN A NETWORK COMPRISED OF A PLURALITY OF COMPUTERS - The invention relates to a method for dynamically distributing one or more services in a network comprised of a plurality of computers. According to certain aspects of the invention, a past chronological progression of a resource capacity required for a respective service according to a prescribed service requirement is derived from a past chronological progression of the resource demand for the respective service in a predetermined time interval. The past chronological progression of the resource capacity required for the respective service is then used to predict a chronological progression of the resource capacity required for the respective service. The services performed on the computers are finally distributed based on one or more optimization criteria, including that the respective computers provide enough resources for the services performed on the respective computers based on the predicted chronological progressions of the resource capacities required for the respective services. | 2011-11-24 |
20110289334 | DARK WAKE - Exemplary embodiments of methods, apparatuses, and systems for powering up select components of a computer from a sleep state, maintaining a network state, and powering down the select components of the computer to return the computer to the sleep state are described. For one embodiment, a network interface and a fan controller receive power during the network state maintenance but a display or audio components do not receive power during the network state maintenance. | 2011-11-24 |
20110289335 | ADAPTIVE GATE DRIVE SYSTEMS AND METHODS - Aspects of the invention pertain to optimization of multi-phase voltage converter efficiency regardless of load conditions. A processor is coupled to different stages of a power control system. Input and output voltages to the different stages are monitored and varied the processor. The processor is also configured to activate or deactivate different phases of the voltage converter in accordance with load current conditions. | 2011-11-24 |
20110289336 | Data transfer enabled uninterruptable power system - A power mains Uninterruptable Power Source including a data transfer system according to one embodiment of the present invention comprises a data transceiver, a first data path to the power mains over which a data path is maintained, and a second data path connected to the data transceiver output and provides a data connection to data equipment connected thereto. Further embodiments provide a power mains line conditioner device have a similarly connected data transceiver, and multiple data equipment data and/or power connections, and optional internal switching features. Thus, according to the present invention, an apparatus is provided for reliable data transfer over power mains even when a typically power mains data path interrupting device, e.g. a UPS or line conditioning device is included between the data equipment and the power mains. | 2011-11-24 |
20110289337 | Method And System Of Reporting Electrical Current To A Processor - Reporting electrical current to a processor. At least some of the illustrative embodiments are methods including providing operational power to a processor at a voltage indicated by the processor of a computer system, measuring electrical current actually drawn by the processor, and reporting to the processor a value of electrical current drawn by the processor. The value of electrical current reported different than the electrical current actually drawn by more than a measurement error of measuring the electrical current actually drawn. | 2011-11-24 |
20110289338 | AUTOMATIC REFERENCE FREQUENCY COMPENSATION - In a first embodiment of the present invention, a method for operating a device having a device reference clock, in a system including a host with a host reference clock is provided, the method comprising: beginning a link negotiation stage between the device and the host using the device reference clock; during the link negotiation stage, sampling data received from the host to determine a frequency offset of the host reference clock; applying the frequency offset to the device reference clock to create a corrected device reference clock; and completing the link negotiation stage using the corrected device reference clock. This completing may include either continuing the original link negotiation stage or restarting it. | 2011-11-24 |
20110289339 | Semiconductor device - A semiconductor device performs operation in synchronization with a certain clock signal. The semiconductor device includes a control unit for outputting operation control information, a storage unit for storing data, a first operation unit for performing operation on first data in accordance with first operation control information, and a second operation unit for performing operation on second data in accordance with second operation control information. The first operation unit includes a plurality of operation circuits. The number of logic gates constituting the entire operation circuits is m. The second operation unit includes at least one operation circuit in which the number of logic gates is n (n>m). Each of the total delay of the operation unit or the total delay of the operation unit is set at a value equal to or less than the cycle of the clock signal. | 2011-11-24 |
20110289340 | DYNAMIC SYSTEM CLOCK RATE - In a first embodiment of the present invention, a method for dynamically adjusting a system clock of a plurality of system clock-controlled components in a system is provided, the method comprising: detecting the receipt of a command at a non-system clock-controlled component of the system; and adjusting the system clock to a fast speed based on the detecting. This embodiment may also include: determining that the command has been completed; determining that there are no outstanding commands in the plurality of system clock-controlled components; and adjusting the system clock to a slow speed based on the determination that there are no outstanding commands in the plurality of system clock-controlled components. | 2011-11-24 |
20110289341 | CLOCK AND DATA RECOVERY (CDR) METHOD AND APPARATUS - Embodiments of methods and apparatus for clock and data recovery are disclosed. In some embodiments, a method for recovering data from an input data stream of a device is disclosed, the method comprising synchronizing, during an initialization phase, a data clock (DCK) with an input data stream; synchronizing, during the initialization phase, an edge clock signal (ECK) with the input data stream based at least in part on a phase relationship between the ECK and the synchronized DCK; and sampling, during the initialization phase, a rising edge of the input data stream with the synchronized ECK to generate a transition level reference voltage. Additional variants and embodiments may also be disclosed and claimed. | 2011-11-24 |
20110289342 | METHOD FOR THE FILE SYSTEM OF FIGURE 7 FOR THE CLUSTER - In general, an appliance that simplifies the creation of a cluster in a computing environment has a fairly straightforward user interface that abstracts out many of the complexities of the typical configuration processes, thereby significantly simplifying the deployment process. By using such appliance, system administrators can deploy an almost turn-key cluster and have the confidence of knowing that the cluster is well tuned for the application/environment that it supports. In addition, the present disclosure allows for configurations and integrations of specialty engines, such as Q processors or J processors, into the cluster. The disclosure provides systems and methods for configuring a cluster, managing a cluster, managing an MQ in a cluster, a user interface for configuring and managing the cluster, an architecture for using specialty engines in a cluster configuration, and interconnect between cluster components, and a file system for use in a cluster. | 2011-11-24 |