47th week of 2021 patent applcation highlights part 68 |
Patent application number | Title | Published |
20210367554 | FRESNEL LENS FOR CONCENTRATOR PHOTOVOLTAIC APPARATUS, CONCENTRATOR PHOTOVOLTAIC SYSTEM, AND METHOD OF MANUFACTURING FRESNEL LENS FOR CONCENTRATOR PHOTOVOLTAIC APPARATUS - A Fresnel lens for a concentrator photovoltaic apparatus includes: a glass substrate portion having a circular first corner portion; and a synthetic resin portion overlaid on one surface of the glass substrate portion and having a circular second corner portion having a radius equal to that of the first corner portion and coaxially overlapping the first corner portion. | 2021-11-25 |
20210367555 | METHOD FOR LIMITING VOLTAGE OF MODULE, AND APPARATUS AND SYSTEM FOR APPLYING THE SAME - A method for component voltage limitation, and an apparatus and a system for applying the same. At least one photovoltaic cell in a photovoltaic-cell string is controlled to operate in a voltage-limited mode, in response to receiving an instruction for enabling voltage limitation. Thereby, the voltage of the photovoltaic-cell string is reduced. A quantity of photovoltaic modules connected in series can be increased, while a highest voltage of the system is guaranteed not to exceed a corresponding requirement. A system cost is reduced. The photovoltaic cell operating in the voltage-limited mode is controlled to resume a normal output, in response to receiving the instruction for suspending voltage limitation. The output voltage of the photovoltaic-cell string is increased. Thereby, a rate of utilization on a direct voltage, and a PVIR of DC/AC are improved for the photovoltaic system. | 2021-11-25 |
20210367556 | MODULAR REMOVABLE BUILDING INTEGRATED THERMAL ELECTRIC ROOFING SYSTEM - An improved modular, removable system of building-integrated solar panel photovoltaics for easy residential and commercial roof installation for generating electrical and thermal energy. | 2021-11-25 |
20210367557 | AMPLIFYING CIRCUIT AND AMPLIFYING DEVICE WITH START-UP FUNCTION - An amplifying circuit is provided. The amplifying circuit includes a bias circuit receiving an operating voltage from a power supply circuit and generating a first bias voltage, a resistance circuit connected between the bias circuit and a gate node and transferring the first bias voltage to the gate node, a start-up circuit generating a high-level start-up voltage and supplying the start-up voltage to the gate node before the operating voltage is supplied, based on a control signal, and an amplifier started-up by receiving the start-up voltage and then receiving the operating voltage and the first bias voltage to amplify a high frequency signal input through the gate node. | 2021-11-25 |
20210367558 | DOHERTY AMPLIFIER - A Doherty amplifier includes a divider configured to divide input power into first input power and second input power, and a carrier amplifier configured to amplify the first input power. The Doherty amplifier includes an adaptive attenuator configured to attenuate the second input power, the adaptive attenuator being configured to increase an attenuation amount upon detecting that the second input power is less than a predetermined value. The Doherty amplifier includes a peaking amplifier configured to amplify the attenuated second input power, and a combiner configured to combine output power of the carrier amplifier with output power of the peaking amplifier. | 2021-11-25 |
20210367559 | POWER AMPLIFIER CIRCUIT - A power amplifier circuit is a Doherty type. A peak amplifier has a first transistor and a second transistor. A first source terminal is connected to a first constant potential line. A first drain terminal and a second source terminal are connected to a first node. A second drain terminal is connected to a second constant potential line having a higher potential than the first constant potential line. A first control terminal is connected to a first bias voltage application circuit, and an input signal is input to the first control terminal via a first alternating current coupling circuit. A second control terminal is connected to a second bias voltage application circuit and is connected to the first node via a second alternating current coupling circuit. The first node is connected to the first constant potential line via a third alternating current coupling circuit. | 2021-11-25 |
20210367560 | POWER AMPLIFIER - A power amplifier includes a first transistor with a gate to which input power is applied and a drain from which output power is provided, a bias circuit configured to apply a bias to the gate of the first transistor, and a coupler configured to distribute the input power to the gate of the first transistor and to the bias circuit. The bias circuit includes a voltage generator circuit including a second transistor with a gate to which the power distributed to the bias circuit by the coupler is applied, the voltage generator circuit being configured to generate a first DC voltage increasing in accordance with an increase in the power distributed to the bias circuit. The bias circuit includes a level shifter circuit configured to generate a second DC voltage increasing in accordance with an increase in the first DC voltage. | 2021-11-25 |
20210367561 | BIAS CIRCUIT - A bias circuit includes first to sixth transistors and first to fifth resistors. The collector of the fifth transistor is coupled to a node in a path connecting the collector of the fourth transistor and one end of the third resistor. The collector of the sixth transistor Tr | 2021-11-25 |
20210367562 | POWER AMPLIFIER WITH BIAS CURRENT GENERATING AND BIAS CURRENT LIMITING APPARATUS - An apparatus that generates and limits a bias current of a power amplifier is provided. The apparatus includes a bias current circuit that generates a bias current to bias the power amplifier, and critically limit an increase in bias current, and a band gap reference circuit that provides a reference voltage or a reference current to the bias current circuit. The bias current circuit is configured to critically limit the increase in bias current, as a first bias transistor that generates the bias current is converted from a triode region to a saturation region, based on the reference voltage or the reference current. | 2021-11-25 |
20210367563 | SYSTEMS AND METHODS FOR TIA BASE CURRENT DETECTION AND COMPENSATION - Described herein are systems and methods that can adjust the performance of a transimpedance amplifier (TIA) in order to compensate for changing environmental and/or manufacturing conditions. In some embodiments, the changing environmental and/or manufacturing conditions may cause a reduction in beta of a bipolar junction transistor (BJT) in the TIA. A low beta may result in a high base current for the BJT causing the output voltage of the TIA to be formatted as an unusable signal output. To compensate for the low beta, the TIA generates an intermediate signal voltage, based on the base current and beta that is compared with the PN junction bias voltage on another BJT. Based on the comparison, the state of a digital state machine may be incremented, and a threshold base current is determined. This threshold base current may decide whether to compensate the operation of the TIA, or discard the chip. | 2021-11-25 |
20210367564 | Linearization of Non-Linear Amplifiers - A linearization device ( | 2021-11-25 |
20210367565 | ACTIVE DIGITAL TELEVISION (DTV) AMPLIFIER WITH SIGNAL DETECTION AND DISPLAY FUNCTIONS - Disclosed is an active DTV amplifier for amplifying signals and detecting and displaying the intensity of signals of an antenna. The amplifier is connected between the antenna and a coaxial cable and includes a primary signal amplification circuit connected to the antenna for performing a primary amplification of a captured antenna signal, a secondary signal amplification circuit connected to the coaxial cable for performing a secondary amplification of the antenna signal and outputting the amplified signal to a feeder coaxial cable, a signal shunt circuit for splitting and the antenna signal processed by the primary amplification into two and assigning the split signals to the single detection circuit and the secondary signal amplification circuit, and a single detection circuit connected to a microcontroller for feeding the collected antenna signal back to the microcontroller which is connected to a display screen to instantly display the intensity of the signal. | 2021-11-25 |
20210367566 | AUDIO AMPLIFIER HAVING IDLE MODE - An audio amplifier employs an idle mode to reduce power consumption and improve efficiency of the amplifier. The audio amplifier comprises a modulator configured to receive an analog input signal. The modulator is operable to convert the analog input signal to differential first and second quantized signals, each having a common mode duty cycle. The modulator causes the common mode duty cycle of each of the first and second quantized signals to be shifted when the level of the analog input signal is below a threshold level so that the common mode duty cycle is one of greater than or less than fifty percent (50%). The amplifier further includes a power stage that receives the first and second quantized signals and generates corresponding first and second output signals configured to drive a load, wherein the first and second output signals switched between a supply voltage and a second voltage based on the respective first and second quantized signals. | 2021-11-25 |
20210367567 | TIME ENCODING MODULATOR CIRCUITRY - This application describes time-encoding modulator circuitry ( | 2021-11-25 |
20210367568 | BROADBAND DIPLEXED OR MULTIPLEXED POWER AMPLIFIER - A wideband amplifier includes a first diplexer receiving broadband input signals and divides them by frequency into a low band input signal and a high band input signal. The amplifier has separate high band and low band amplifiers coupled to amplify the low and high band input signals, and a second diplexer coupled to combine outputs of the low and high band amplifiers to form a wideband output. A method of amplification of an input signal includes separating the input signal into high and low band signals, separately amplifying the high and low band signals, and combining amplified high and low band signals into an output signal. | 2021-11-25 |
20210367569 | CHOPPER AMPLIFIERS WITH MULTIPLE SENSING POINTS FOR CORRECTING INPUT OFFSET - Chopper amplifiers with multiple sensing points for correcting input offset are disclosed herein. In certain embodiments, a chopper amplifier includes chopper amplifier circuitry including an input chopping circuit, an amplification circuit, and an output chopping circuit electrically connected in a cascade along a signal path. The chopper amplifier further incudes a multi-point sensed offset correction circuit that generates an input offset compensation signal based on sensing a signal level of the signal path at multiple signal points. Furthermore, the multi-point sensed offset correction circuit injects the input offset compensation signal into the signal path to thereby compensate for input offset voltage of the amplification circuit while suppressing output chopping ripple from arising. | 2021-11-25 |
20210367570 | OPERATIONAL AMPLIFIER - An operational amplifier 1 comprises transistors Q | 2021-11-25 |
20210367571 | OPERATIONAL AMPLIFIER AND DIRECT CURRENT VOLTAGE LEVEL CONTROL METHOD - An operational amplifier includes a differential amplifier circuit and a common mode feedback circuit. The differential amplifier circuit includes a bias circuit, an amplifier circuit, and a load circuit. The bias circuit generates a first operation voltage. The amplifier circuit receives a pair of input signals, and generates a pair of output signals according to the input signals and the first operation voltage. The load circuit is coupled to the amplifier circuit. The common mode feedback circuit generates at least one common mode feedback voltage based on a common mode voltage and a reference voltage. The common mode voltage is associated with the output signals. The at least one common mode feedback voltage is for controlling the bias circuit and the load circuit, to control a direct current (DC) voltage level of the differential amplifier circuit. | 2021-11-25 |
20210367572 | AMPLIFIERS WITH WIDE INPUT RANGE AND LOW INPUT CAPACITANCE - Amplifiers with wide input range and low input capacitance are provided. In certain embodiments, an amplifier input stage includes a pair of input terminals, a pair of n-type input transistors, a first pair of isolation switches connected between the input terminals and the n-type input transistors, a pair of p-type input transistors, and a second pair of isolation switches connected between the input terminals and the p-type input transistors. The amplifier input stage further includes a control circuit that determines whether to use the n-type input transistors and/or the p-type input transistors for amplification based on a detected common-mode voltage of the input terminals. The control circuit opens the first pair of isolation switches to decouple the input terminals from the n-type input transistors when unused, and opens the second pair of isolation switches to decouple the input terminals from the p-type input transistors when unused. | 2021-11-25 |
20210367573 | ELECTROPLATED HELICAL SLOW-WAVE STRUCTURES FOR HIGH-FREQUENCY SIGNALS - Traveling-wave tube amplifiers and methods for making slow-wave structures for the amplifiers are provided. The SWSs include helical conductors that are self-assembled via the release of stressed electrically conductive strips from a sacrificial material. The helical conductors can be electroplated post-self-assembly to fortify the helix, reduce losses, and tailor the dimensions and operating parameters of the helix. | 2021-11-25 |
20210367574 | AUDIO SIGNAL PROCESSING METHOD AND DEVICE FOR CONTROLLING LOUDNESS LEVEL - An audio signal processing device comprises: a receiver for receiving an input audio signal; a processor for generating loudness metadata corresponding to the input audio signal; and an outputter for transmitting the loudness metadata generated by the processor. The processor is configured to acquire loudness information analyzed from input content, acquires loudness information about the input audio signal by measuring the loudness of the input audio signal, generates the loudness metadata by converting the loudness information, and transmits, through the outputter, the generated loudness metadata to an output device for outputting the input audio signal. | 2021-11-25 |
20210367575 | FILTER CIRCUIT AND ELECTRONIC EQUIPMENT - A filter circuit and an electronic equipment are provided. The filter circuit, electrically connected between a power module and an integrated circuit control module, includes a capacitor unit, a ferrite bead component, and a filter capacitor. The capacitor unit is electrically connected to a first node of the power module. The ferrite bead component is electrically connected to a second node of the integrated circuit control module and the first node of the power module. The filter capacitor is electrically connected to the second node of the integrated circuit control module. The ferrite bead component has a zero resistance. This reduces the ripple of the power signal, outputted by the power module, after the power signal passes through the ferrite bead component, solving the above-mentioned EMI issue, and improving the performance of the IC. | 2021-11-25 |
20210367576 | INDUCTORLESS INTERFERENCE CANCELLATION FILTER - A programmable filter includes a first programmable filter instance comprising a first adjustable active inductance capacitively coupled to a signal receive path, the capacitive coupling comprising at least one adjustable capacitance, the adjustable active inductance and the at least one adjustable capacitance configurable to provide a filter response at a first selected frequency, and a second programmable filter instance comprising a second adjustable active inductance capacitively coupled to the signal receive path, the capacitive coupling comprising at least one adjustable capacitance, the second adjustable active inductance and the at least one adjustable capacitance configurable to provide a filter response at a second selected frequency. | 2021-11-25 |
20210367577 | MICRO-ACOUSTIC DEVICE WITH REFLECTIVE PHONONIC CRYSTAL AND METHOD OF MANUFACTURE - A micro-acoustic device comprises a confinement structure (CS) adapted to block propagation of acoustic waves of an acoustic wave resonator (TEL, PL, BEL; ES) at an operation frequency of the device to confine the acoustic waves to the acoustic path or the acoustic volume. It is proposed to use a phononic crystal material for producing the confinement structure. | 2021-11-25 |
20210367578 | METHOD FOR MANUFACTURING CERAMIC SUBSTRATE AND CERAMIC SUBSTRATE - A method for manufacturing a ceramic substrate that includes forming a mother multilayer body by positioning a hole in at least one ceramic green sheet among a plurality of laminated ceramic green sheets in a location that does not overlap with a recess formation-planned region in which a recess is to be formed after firing of the mother multilayer body and that overlaps with a singulation-planned line for singulating the mother multilayer body into pieces after firing; and forming the recess in the mother multilayer body before firing by performing press working on the recess formation-planned region of the mother multilayer body. | 2021-11-25 |
20210367579 | VIBRATOR AND METHOD FOR MANUFACTURING VIBRATOR - A method for manufacturing a vibrator that includes forming excitation electrodes, lead-out electrodes, and first sealing frames on the main surfaces of a crystal piece; forming second sealing frames on the main surfaces of a base part and a lid part; and sealing a crystal vibration element by bonding the first sealing frames to the second sealing frames. The first sealing frames each include a first Ti or Cr base layer | 2021-11-25 |
20210367580 | RESONATOR, AND FILTER AND DUPLEXER HAVING THE SAME - A resonator includes: interdigital transducer (IDT) including first electrode including first base on piezoelectric substrate and extended in reference direction, and first protrusions connected to the first base and extended in direction intersecting with the reference direction, and second electrode including second base on the piezoelectric substrate and extended in the reference direction, and second protrusions connected to the second base and extended in direction intersecting with the reference direction, each of the second protrusions extended to have one of the first protrusions inserted between the second protrusion and another second protrusion adjacent to the second protrusion, wherein a width of each of first specific protrusions included between one end of the IDT and first position at first distance from the one end, among the first protrusions and the second protrusions, decreases from first specific protrusion closest to the first position toward first specific protrusion closest to the one end. | 2021-11-25 |
20210367581 | RESONATOR AND FILTER - The disclosure provides a resonator and a filter. The resonator includes: a substrate; and a multilayer structure formed on the substrate. The multilayer structure successively includes a lower electrode layer, a piezoelectric layer and an upper electrode layer from bottom to top. A cavity is formed between the substrate and the multilayer structure, and the cavity includes a lower half cavity below an upper surface of the substrate and an upper half cavity beyond the upper surface of the substrate and protruding toward the multilayer structure. A resonator with novel structure and good performance is formed by providing the cavity with the lower half cavity below the upper surface of the substrate and the upper half cavity above the upper surface of the substrate. | 2021-11-25 |
20210367582 | BULK-ACOUSTIC WAVE RESONATOR AND METHOD FOR FABRICATING BULK-ACOUSTIC WAVE RESONATOR - A bulk-acoustic wave resonator includes: a substrate; and a resonator portion in which a first electrode, a piezoelectric layer, and a second electrode are sequentially stacked on the substrate. The piezoelectric layer is formed of aluminum nitride (AlN) containing scandium (Sc). The bulk-acoustic wave resonator satisfies the following expression: leakage current density×scandium (Sc) content<20. The leakage current density is a leakage current density of the piezoelectric layer in μA/cm2, and the scandium (Sc) content is a weight percentage (wt %) of scandium (Sc) in the piezoelectric layer. | 2021-11-25 |
20210367583 | Vibration Device And Oscillator - A vibration device includes a quartz substrate including a first vibration section, a second vibration section, and a third vibration section, a pair of first excitation electrodes formed at two principal surfaces of the quartz substrate, a pair of second excitation electrodes so formed as to sandwich the second vibration section in the thickness direction of the quartz substrate, and a pair of third excitation electrodes so formed as to sandwich the third vibration section in the thickness direction of the quartz substrate. At least one of the pair of second excitation electrodes is formed at a first inclining surface that inclines with respect to the two principal surfaces. At least one of the pair of third excitation electrodes is formed at a second inclining surface that inclines with respect to the two principal surfaces. The second inclining surface inclines with respect to the first inclining surface. | 2021-11-25 |
20210367584 | Arrangement for a Vehicle for Detecting an Activation Action for Activating a Function on the Vehicle - The invention relates to an arrangement ( | 2021-11-25 |
20210367585 | DOUBLE MODE SURFACE ACOUSTIC WAVE (SAW) FILTER - A double mode SAW (DMS) filter includes: a plurality of interdigital transducers (IDTs), each having a plurality of Type | 2021-11-25 |
20210367586 | OUTPUT DRIVING CIRCUIT - An output driving circuit includes a pull-down driver and a voltage stabilizer. The pull-down driver includes first, second, and third transistors connected in series between a pad and a ground node. The voltage stabilizer generates a stabilization voltage based on a voltage of the pad and a power voltage, and outputs the stabilization voltage to a control terminal of the second transistor. | 2021-11-25 |
20210367587 | High Speed Signal Adjustment Circuit - Disclosed herein is an apparatus that includes a data serializer including a plurality of first buffer circuits configured to receive a plurality of data, respectively, and a second buffer circuit configured to serialize the plurality of data provided from the plurality of first buffer circuits. At least one of the plurality of first buffer circuits and the second buffer circuit includes: a first circuit configured to drive a first signal node to one of first and second logic levels based on an input signal, the first circuit including a first adjustment circuit configured to adjust a driving capability of the first circuit when the first circuit drives the first signal node to the first logic level; and a second circuit configured to drive the first signal node to other of the first and second logic levels. | 2021-11-25 |
20210367588 | HIGH SPEED DIGITAL PHASE INTERPOLATOR WITH DUTY CYCLE CORRECTION CIRCUITRY - Described is a circuit and architecture that combines phase interpolator (PI) mixer with duty cycle correction (DCC), to prevent cross contention between the tristate inverter pairs of the mixer. The control code for the p-type and n-type networks in the PI mixer are decoupled, and DCC mechanism are blended in the PI mixer code decoding scheme to enable a low latency phase interpolation and duty cycle correction. The circuit comprises a first mixer circuitry controllable by a first code; a second mixer circuitry controllable by a second code; a node coupled to outputs of the first and second mixers; and a keeper circuitry coupled to the node, wherein the first and second mixers are tri-stable mixers. | 2021-11-25 |
20210367589 | CIRCUIT ARRANGEMENT WITH CLOCK SHARING, AND CORRESPONDING METHOD - In an embodiment, a system includes a slave circuit configured to receive an external clock signal from a master circuit, the slave circuit comprising first and second peripherals configured to receive respective clock signals obtained from the external clock signal, wherein the master circuit is configured to send to the slave circuit the external clock signal according to two different timing modes, wherein the slave circuit comprises a logic circuit configured to provide a locking signal to the first peripheral circuit when the logic circuit detects a given operating mode of the slave circuit, wherein the master circuit is configured to send the external clock signal according to a first timing mode before receipt of the locking signal, and wherein the master circuit is configured, following upon receipt of the locking signal, to send the external clock signal according to a second timing mode different from the first timing mode. | 2021-11-25 |
20210367590 | DRIVER CIRCUIT AND METHOD OF OPERATING THE SAME - A circuit includes a power supply voltage node having a power supply voltage level, a protection circuit that generates a first signal having first and second logical voltage levels based on the power supply voltage level, and a gate driver. The gate driver includes a first n-type HEMT between the power supply voltage node and a first node, a second n-type HEMT between the first node and a power supply reference node, and a DCFL circuit between the first node and an output terminal. A gate of the first n-type HEMT receives the first signal, a gate of the second n-type HEMT receives a second signal, and the DCFL circuit generates a third signal at the output terminal based on the second signal when the first signal has the first logical voltage level, and as a DC voltage level when the first signal has the second logical voltage level. | 2021-11-25 |
20210367591 | TEMPERATURE SENSOR CIRCUITS FOR INTEGRATED CIRCUIT DEVICES - An integrated circuit device having insulated gate field effect transistors (IGFETs) having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure has been disclosed. The integrated circuit device may include a temperature sensor circuit and core circuitry. The temperature senor circuit may include at least one portion formed in a region other than the region that the IGFETs are formed as well as at least another portion formed in the region that the IGFETs having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure are formed. By forming a portion of the temperature sensor circuit in regions below the IGFETs, an older process technology may be used and device size may be decreased and cost may be reduced. | 2021-11-25 |
20210367592 | VOLTAGE COMPARATOR - A circuit arrangement is disclosed for controlling the switching of a field effect transistor (FET). A current controlled amplifier may be configured to amplify a current in a current sense device to generate an amplified current, wherein the current in the current sense device indicates a current through the FET. A comparator may be coupled to the current sense amplifier to compare a voltage corresponding to the amplified current with a voltage reference and to generate a comparator output based on the comparison, wherein the comparator output controls whether the FET is on or off. | 2021-11-25 |
20210367593 | POWER TRANSISTOR MODULE AND CONTROLLING METHOD THEREOF - A power transistor module includes a power transistor device and a control circuit. The control circuit is electrically connected to the power transistor device for providing at least one gate voltage to drive the power transistor device, and adjusting the at least one gate voltage in response to an output power of the power transistor module. When the output power is greater than a predetermined power load, the at least one gate voltage has a first swing amplitude; and when the output power is less than or equal to the predetermined power load the at least one gate voltage has a second swing amplitude less than the first swing amplitude. | 2021-11-25 |
20210367594 | SEMICONDUCTOR SYSTEMS AND ELECTRONIC SYSTEMS - An electronic system includes a reception device and a transmission device. The reception device generates reception data from transmission data input to a reception node and includes a termination circuit which is coupled to the reception node to perform an impedance matching operation. The transmission device generates a drive control signal from internal data based on a mode signal and drives the transmission data based on the drive control signal. | 2021-11-25 |
20210367595 | CODE SHIFT CALCULATION CIRCUIT AND METHOD FOR CALCULATING CODE SHIFT VALUE - A code shift calculation circuit is provided. A first operation circuit of the code shift calculation circuit generates a first output value according to a temperature difference and a first change rate of a driving strength code to temperature. The temperature difference is a difference between a previous temperature when getting a previous ZQ command and a current temperature when getting a current ZQ command. A second operation circuit generates a second output value according to a voltage difference and a second change rate of the driving strength code to voltage. The voltage difference is a difference between a previous working voltage when getting the previous ZQ command and a current working voltage when getting the current ZQ command. A third operation circuit sums up the first output value and the second output value to generate a shift value, thereby adjusting the driving strength code calibrated by ZQ calibration. | 2021-11-25 |
20210367596 | IMPEDANCE CALIBRATION CIRCUIT - An impedance calibration circuit is provided. The impedance calibration circuit includes a first calibration circuit, a second calibration circuit and a control circuit. The first calibration circuit is adapted to be coupled to an external resistor through a calibration pad, and generate a first voltage according to a first control signal and a resistance value of the external resistor. The second calibration circuit generates a second voltage according to the first control signal and a second control signal. The control circuit is configured to compare the first voltage and a reference voltage to obtain a first comparison result, and compare the first voltage and the second voltage to obtain a second comparison result, and generate the first control signal according to the first comparison result, and generate the second control signal according to the second comparison result. | 2021-11-25 |
20210367597 | IMPEDANCE CALIBRATION CIRCUIT - An impedance calibration circuit includes first and second calibration circuits, a switch circuit and a control circuit. The first calibration circuit is coupled to an external resistance, and generates a first voltage. The second calibration circuit generates second and third voltages. The switch circuit is coupled to the first and second calibration circuits. The switch circuit selectively provides the first, second, and third voltages to first and second nodes. The control circuit is coupled to the first and second nodes. The control circuit generates first, second, and third control signals according to voltages of the first and second nodes. In a first time interval, the switch circuit provides the first voltage to the first and second nodes. In a second time interval, the switch circuit provides the second voltage to the first and second nodes, or provides the second and third voltages respectively to the first and second nodes. | 2021-11-25 |
20210367598 | TRANSMITTER FOR TRANSMITTING MULTI-BIT DATA - A transmitter includes a driving circuitry configured to drive a channel coupled to an output node by controlling an output impedance of a pull-up path, an output impedance of a pull-down path, or both, according to one or more multi-bit data signals, a pull-up control signal, and a pull-down control signal; a driving control circuit configured to generate the pull-up control signal and the pull-down control signal according to one or more calibration signals and the multi-bit data signals or according to the calibration signals and one or more duplicate multi-bit data signals, the duplicate multi-bit data signals duplicating the multi-bit data signals; and a look-up table storing values of the calibration signals. | 2021-11-25 |
20210367599 | PORT CONTROLLER DEVICE - A port controller device includes a pull-up resistor, a switching circuit, an enabling circuitry, and a protection circuitry. The pull-up resistor is configured to be coupled to a port, in which the port is configured to be coupled to a channel configuration pin of an electronic device. The switching circuit is configured to selectively transmit a supply voltage to the port via the pull-up resistor according to a first control signal, and turn off a signal path between the pull-up resistor and the port according to a second control signal. The enabling circuitry is configured to generate the first control signal according to an enable signal and the supply voltage. The protection circuitry is configured to generate the second control signal in response to a voltage from the port when the supply voltage is not powered, in order to limit a current from the port. | 2021-11-25 |
20210367600 | BUFFER CIRCUIT, RECEIVER CIRCUIT INCLUDING THE BUFFER CIRCUIT, AND SEMICONDUCTOR APPARATUS INCLUDING THE RECEIVER CIRCUIT - The present technology may include: a first logic gate coupled to an internal voltage terminal and configured to receive data and invert and output the data according to a first enable signal; and a second logic gate coupled to the internal voltage terminal and configured to invert an output of the first logic gate and to output an inverted output as a first buffer signal according to the first enable signal, and configured to compensate for a duty skew of the first buffer signal according to a level of an external voltage. | 2021-11-25 |
20210367601 | MULTI-LEVEL DRIVE DATA TRANSMISSION CIRCUIT AND METHOD - The disclosed multi-level driving data transmission circuit and operating method include: a first driving module including a first signal generating unit and a first three-state driver, and a second driving module, including a second three-state driver. The first input terminal of the second three-state driver is coupled to the output terminal of the first three-state driver. The first signal generating unit includes a first and second input terminals, and an output terminal. The output terminal of the first signal generating unit couples to the second input terminal of the first three-state driver. The first signal generating unit receives the first signal through its first input terminal and the first feedback signal of the first signal from the second driving module through its second input terminal. The resultant first control signal has an effective signal width wider than the first signal. The first control signal inputs to the first three-state driver. | 2021-11-25 |
20210367602 | LOGIC DEVICE USING SKYRMION - The present invention relates to a logic device using skyrmion, which comprises an input part; an output part; and an operation part located between the input part and the output part and includes at least one notch where the skyrmion can be annihilated, and in which the skyrmion moves from the input part to the output part by the applied current. The logic device provided in one aspect of the present invention consumes relatively little power, can have high integration, and has an effect of having a very simple structure compared to the conventional logic device by using the annihilation of skyrmion. | 2021-11-25 |
20210367603 | DYNAMIC MULTIPHASE INJECTION-LOCKED PHASE ROTATOR FOR ELECTRO-OPTICAL TRANSCEIVER - Presented herein are methodologies for generating clock signals for transceivers that rely on frequency and phase error correction functions. The methodology includes generating a differential clock signal at a fundamental frequency, generating, based on the differential clock signal and using a multiphase generator, four quadrature signals at the fundamental frequency, supplying the four quadrature signals to an injection-locked phase rotator, and outputting, from the injection-locked phase rotator, a phase adjusted multiphase clock signal based on the four quadrature signals. | 2021-11-25 |
20210367604 | SEMICONDUCTOR DEVICE - A semiconductor device includes a clock generating circuit and a jitter measurement circuit. The clock generating circuit is input with a control value for changing a cycle of the clock thereof. The jitter measurement circuit has a first logic circuit operated with using an output clock of the clock generating circuit as an input and a first delay element, and is configured to output the presence/absence of a jitter of the clock generating circuit. | 2021-11-25 |
20210367605 | METHOD OF READING DATA AND DATA-READING DEVICE - A method of reading data includes: receiving a digital signal, wherein the digital signal includes a sync signal and a data signal; performing an oversampling operation to the digital signal, and calculating a plurality of sampling points according to the oversampling operation; by a first counter counting the sampling points to obtain a first count value; based on the first count value defining a second count value; defining a unit interval; in the unit interval, defining a data reading range; and in the data reading range, reading the data signal corresponding to data of the unit interval as a first value when a potential of each of the sampling points counted is changed from a first potential to a second potential. | 2021-11-25 |
20210367606 | APPARATUS AND METHOD FOR FREQUENCY MULTIPLICATION - Disclosed is a frequency multiplication apparatus including a first frequency multiplier receiving a first signal having a first frequency and outputting a second signal having a second frequency by multiplying the first frequency by ‘n’ (‘n’ being a positive integer), a second frequency multiplier receiving the second signal and outputting a third signal having a third frequency by multiplying the second frequency by ‘m’ (‘m’ being a positive integer), and a coupler connected between an output of the first frequency multiplier and an input of the second frequency multiplier and outputting a part of the second signal. | 2021-11-25 |
20210367607 | TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER SYSTEM - A time-interleaved Analog-to-Digital Converter, ADC, system is provided. The time-inter- leaved ADC system includes time-interleaved first and second ADC circuits and a switching circuit. The switching circuit is configured to selectively supply an analog input signal for digitization to at least one of the first ADC circuit, the second ADC circuit or ground, and to selectively supply an analog calibration signal to at least one of the first ADC circuit, the second ADC circuit or ground. Further, the time-interleaved ADC system includes an output circuit configured to selectively generate, based on least one of a first digital signal output by the first ADC circuit and a second digital signal output by the second ADC circuit, a digital output signal. | 2021-11-25 |
20210367608 | Analog-Digital Converter - An embodiment target time comparison circuit corresponding to a target approximate voltage range among 2 | 2021-11-25 |
20210367609 | DEVICES AND METHODS FOR VOLTAGE REGULATION - A converter includes a switched capacitor circuit that includes at least one capacitor and a plurality of main switches to provide an output current in response to an input voltage applied to the switched capacitor circuit. The converter further includes one or more bypass transistor switches to selectively provide an additional output current. The converter includes a common controller that controls the plurality of main switches and the one or more bypass transistor switches. | 2021-11-25 |
20210367610 | APPARATUS AND METHOD FOR INTERPOLATING BETWEEN A FIRST SIGNAL AND A SECOND SIGNAL - An apparatus for interpolating between a first signal and a second signal is provided. The apparatus includes a first plurality of interpolation cells configured to generate a first interpolation signal at a first node. At least one of the first plurality of interpolation cells is configured to supply, based on a first number of bits of a control word, at least one of the first signal and the second signal to the first node. The apparatus further includes a second plurality of interpolation cells configured to generate a second interpolation signal at a second node. At least one of the second plurality of interpolation cells is configured to supply, based on a second number of bits of the control word, at least one of the first signal and the second signal to the second node. The apparatus additionally includes an interpolation circuit configured to weight the second interpolation signal based on a weighting factor, and to combine the first interpolation signal and the weighted second interpolation signal to generate a third interpolation signal. | 2021-11-25 |
20210367611 | SYSTEMS AND METHODS FOR PERFORMING ANALOG-TO-DIGITAL CONVERSION ACROSS MULTIPLE, SPATIALLY SEPARATED STAGES - The invention provides a signal processing system, for transferring analog signals from a probe to a remote processing unit. The system comprises a first ASIC at a probe, which is adapted to receive an analog probe signal. The first ASIC comprises an asynchronous sigma-delta modulator, wherein the asynchronous sigma-delta modulator is adapted to: receive the analog probe signal; and output a binary bit-stream. The system further comprises a second ASIC at the remote processing unit, adapted to receive the binary bit-stream. The asynchronous may further include a time gain function circuit, the first ASIC may further comprise a multiplexer, the second ASIC may further comprise a time-to-digital converter. The time to digital converter may be a pipelined time-to-digital converter. | 2021-11-25 |
20210367612 | Two-Dimensional Square Constraint Encoding and Decoding Method and Device - A two-dimensional square constraint encoding and decoding method and device, relating to the fields of data storage and data communication. The encoding method comprises: caching a one-dimensional data stream, and dividing the one-dimensional data stream into several sets of one-dimensional 2-bit data; according to an encoding table, encoding each set of 2-bit data into a 3*2 two-dimensional codeword in sequence by an encoder, and then cascading all the two-dimensional codewords into a two-dimensional constraint array in a specified order; the decoding method comprises: reading the two-dimensional constraint array by a decoder, and dividing the two-dimensional constraint array into several 3*2 two-dimensional codewords; decoding each two-dimensional codeword into the one-dimensional 2-bit data in sequence through a decoding table, and then successively assembling the generated one-dimensional 2-bit data into the one-dimensional data stream and outputting. The two-dimensional square constraint in the present invention means that in a binary data array composed of data “0” and “1”, along four directions of a horizontal direction, a vertical direction, a northeast direction and a southeast direction, the two data “1” cannot be directly adjacent to each other. | 2021-11-25 |
20210367613 | DATA COMPRESSION TECHNIQUES - Techniques and solutions are described for compressing data and facilitating access to compressed data. Compression can be applied to proper data subsets of a data set, such as to columns of a table. Using various methods, the proper data subsets can be evaluated to be included in a group of proper data subsets to be compressed using a first compression technique, where unselected proper data subsets are not compressed using the first compression technique. Data in the data set can be reordered based on a reordering sequence for the proper data subsets. Reordering data in the data set can improve compression when at least a portion of the proper data subsets are compressed. A data structure is provided that facilitates accessing specified data stored in a compressed format. | 2021-11-25 |
20210367614 | CONTROLLER AND MEMORY SYSTEM HAVING THE CONTROLLER - The present technology includes a controller and a memory system including the same. The controller includes a memory interface configured to receive a codeword from a memory device, and an error correction circuit configured to: perform an error correction decoding operation on the codeword received from the memory interface, compare a number of unsatisfied check nodes (UCNs) detected in the error correction decoding operation with a reference number, perform or stop the error correction decoding operation on the codeword according to a result of comparing the number of UCNs and the reference number, and output a retransmission request signal of the codeword to the memory interface in response to the result, wherein the memory interface requests the codeword to the memory device in response to the retransmission request signal. | 2021-11-25 |
20210367615 | BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 2/15 AND 4096-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME - A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 4096-symbol mapping. | 2021-11-25 |
20210367616 | DESCRAMBLER FOR MEMORY SYSTEMS AND METHOD THEREOF - A descrambler receives data from a memory device. The descrambler calculates a sub-syndrome weight for multiple bits in each of the plurality of descrambled sequences using a set parity check matrix to generate multiple sub-syndrome weights, one for each of the plurality of descrambled sequences. The descrambler selects a sub-syndrome weight among the multiple sub-syndrome weights. The descrambler determines, as a correct scrambler sequence for descrambling the data, a scrambler sequence corresponding to the selected sub-syndrome weight, among the plurality of scrambler sequences. | 2021-11-25 |
20210367617 | METHODS AND APPARATUS FOR POWER EFFICIENT DESIGN OF FORWARD ERROR CORRECTION FOR OPTICAL COMMUNICATION SYSTEMS - Consistent with a further aspect of the present disclosure, previously encoded data is stored in a memory, and an encoder accesses both input data and previously encoded data to generate new encoded data or a new codeword. Each codeword is stored in a row of the memory, and with each newly generated codeword, each previously stored code word is shifted to an adjacent row of the memory. In one example, the memory is delineated as a plurality of blocks including rows and columns of bits. When generating a new code word, randomly selected columns of bits in the memory are read from randomly selected blocks of the memory and supplied to the encoder. In this manner the number of times the memory is access is reduced and power consumption is reduced. | 2021-11-25 |
20210367618 | PARALLEL BIT INTERLEAVER - A bit interleaving method involves applying a bit permutation process to bits of a QC-LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword after the permutation process into a plurality of constellation words each including M bits, the codeword being divided into F×N′/M folding sections (N′ being a subset of N selected cyclic blocks and being a multiple of M/F), each of the constellation words being associated with one of the F×N′/M folding sections, and the bit permutation process being applied such that each of the constellation words includes F bits from each of M/F different cyclic blocks in a given folding section associated with a given constellation word. | 2021-11-25 |
20210367619 | ERROR DETECTION - A datum is written to a memory, by splitting a binary word, representative of the datum and an error correcting or detecting code, into a first part and a second part. The first part is written at a logical address in a first memory circuit. The second part is written at the logical address in a second memory circuit. The error correcting or detecting code is dependent on both the datum and the logical address. | 2021-11-25 |
20210367620 | PRE-CODING AND DECODING POLAR CODES USING LOCAL FEEDBACK - Disclosed are devices, systems and methods for precoding and decoding polar codes using local feedback are described. One example method for improving an error correction capability of a decoder includes receiving a noisy codeword vector of length n, the codeword having been generated based on a concatenation of a convolutional encoding operation and a polar encoding operation and provided to a communication channel prior to reception by the decoder, performing a successive-cancellation decoding operation on the noisy codeword vector to generate a plurality of polar decoded symbols (n), generating a plurality of information symbols (k) by performing a convolutional decoding operation on the plurality of polar decoded symbols, wherein k/n is a rate of the concatenation of the convolutional encoding operation and the polar encoding operation, and performing a bidirectional communication between the successive-cancellation decoding operation and the convolutional decoding operation. | 2021-11-25 |
20210367621 | SYSTEMS AND METHODS FOR SELECTING A COMMUNICATION CHANNEL - A method and system of transmitting data. The method comprises receiving data, in a memory of the server computing device, from an asset tracker device; determining, in a processor of the server computing device, one or more weighting factors representing a respective priority associated with one or more of a latency, a cost, a power utilization and a throughput associated with transmission of the data for each of a plurality of communication channels; and selecting, from the plurality of communication channels, a communication channel for transmission of the data based at least in part on the one or more weighting factors and a transmission schedule for the data. | 2021-11-25 |
20210367622 | RADIO FREQUENCY MODULE AND COMMUNICATION DEVICE - A radio frequency module ( | 2021-11-25 |
20210367623 | METHOD OF COMBINING LTE-UHB+LAA+SUB6-5G LNA PORTS - According to certain aspects, a chip includes a first port, a first amplifier, and a first input path coupling the first port to an input of the first amplifier. The chip also includes a second port, a second amplifier, and a second input path coupling the second port to an input of the second amplifier. The chip further includes a switchable path coupled between the first input path and the second input path. | 2021-11-25 |
20210367624 | DIGITAL RADIO FREQUENCY TRANSMITTER AND WIRELESS COMMUNICATION DEVICE INCLUDING THE SAME - A digital radio frequency (RF) transmitter including processing circuitry configured to generate first through third pattern signals based on a pattern of an inphase (I)-quadrature (Q) binary data pair and a pattern of an inverted I-Q binary data pair, the first through third pattern signals having a same pattern and different phases, and a switched-capacitor digital-to-analog converter (SC-DAC) configured to remove an n-th harmonic component of an RF analog signal by amplifying the first through third pattern signals to have a certain magnitude ratio and synthesizing the amplified first through third pattern signals into the RF analog signal, where “n” is an integer of at least 3, may be provided. | 2021-11-25 |
20210367625 | COVERAGE EXTENSION ANTENNA SYSTEM - A coverage extension antenna system includes a signal booster or a DAS. The signal booster or DAS includes a set of demodulators that convert incoming signals to baseband, and includes a set of modulators that modulate the baseband signals before transmitting the modulated signals to a base station or terminal equipment. | 2021-11-25 |
20210367626 | DATA TRANSMISSION METHOD AND DEVICE FOR MULTI-RADIO FREQUENCY SYSTEM, STORAGE MEDIUM AND TERMINAL - A data transmission method and device for a multi-radio frequency system, a storage medium and a terminal are provided. The multi-radio frequency system includes a shared radio frequency antenna and a non-shared radio frequency antenna, the shared radio frequency antenna is configured to transmit Wi-Fi data and non-Wi-Fi data, the non-shared radio frequency antenna is configured to transmit the Wi-Fi data, and the method includes: in at least a portion of a Wi-Fi time slice, if there is Wi-Fi data to be transmitted, transmitting the Wi-Fi data using the shared radio frequency antenna and the non-shared radio frequency antenna; and in a non-Wi-Fi time slice, if there is Wi-Fi data to be transmitted, transmitting the Wi-Fi data using the non-shared radio frequency antenna. Wi-Fi transmission efficiency and performance of the multi-radio frequency system are improved, which is conducive to coexistence of different radio frequency modes. | 2021-11-25 |
20210367627 | RADIO FREQUENCY MODULE AND COMMUNICATION DEVICE - A radio frequency module and a communication device capable of reducing a mounting substrate size. The radio frequency module includes a mounting substrate, a first filter, and a second filter. The mounting substrate has a first main surface and a second main surface that are on opposite sides of the mounting substrate. The first filter is provided on the first main surface and allows a first receiving signal in a first frequency band to pass through. The second filter is stacked on the first filter and allows a second receiving signal in a second frequency band different from the first frequency band to pass through. | 2021-11-25 |
20210367628 | IMPEDANCE MATCHING - A circuit device includes a directional coupler with a first port receiving a radiofrequency signal, a second port outputting a signal in response to signal received by the first port, and a third port outputting a signal in response to a reflection of the signal at the second port. An impedance matching network is connected between the second port and an antenna. The impedance matching network includes fixed inductive and capacitive components and a single variable inductive or capacitive component. A diode coupled to the third port of the coupler generates a voltage at a measurement terminal which is processed in order to select and set the inductance or capacitance value of the variable inductive or capacitive component. | 2021-11-25 |
20210367629 | DIGITAL RADIO HEAD CONTROL - Techniques are described related to digital radio control and operation. The various techniques described herein enable high-frequency local oscillator (LO) signal generation using injection locked cock multipliers (ILCMs). The techniques also include the use of LO signals for carrier aggregation applications for phased array front ends. Furthermore, the disclosed techniques include the use of array element-level control using per-chain DC-DC converters. Still further, the disclosed techniques include the use of adaptive spatial filtering and optimal combining of analog-to-digital converters (ADCs) to maximize dynamic range in digital beamforming systems. | 2021-11-25 |
20210367630 | RADIO FREQUENCY TRANSMITTER CAPABLE OF SELECTING OUTPUT POWER CONTROL RANGE AND WIRELESS COMMUNICATION DEVICE INCLUDING THE SAME - A radio frequency (RF) transmitter including a switched-capacitor digital-to-analog converter (SC-DAC) configured to selectively generate a first RF output signal having a first output power control range or a second RF output signal having a second output power control range from input signals received through a plurality of lines may be provided. | 2021-11-25 |
20210367631 | CONTROLLER DEVICE FOR A MOTOR VEHICLE, AND MOTOR VEHICLE - A controller device for a motor vehicle, in particular for an autonomously operable motor vehicle, having a controller for operating the motor vehicle, and a protective device for protecting the controller from electromagnetic interference fields or interfering signals. The protective device has a receiver device for acquiring electromagnetic interference fields or interfering signals, a processing device for providing information about an electromagnetic interference field or interfering signal acquired by the receiver device, and a control unit that evaluates the acquired field and/or interference signal as a function of the acquired information. | 2021-11-25 |
20210367632 | RECEIVING DEVICE AND METHOD FOR DYNAMICALLY ADJUSTING THE ATTENUATION OF THE RECEIVED SIGNAL - A receiving device is provided. The receiving device includes an antenna device, a filter circuit, a transceiver, an adjustable attenuator, a circulator, and a processor. The antenna device receives a received signal. The filter circuit separates an in-band signal and an out-band signal from the received signal. The adjustable attenuator adjusts the attenuation value corresponding to the in-band signal and transmits the adjusted in-band signal to the transceiver. The circulator receives the received signal from the antenna device and transmits the received signal to the filter circuit, and the circulator receives a reflected signal from the filter circuit. The processor determines how to adjust the attenuation value corresponding to the in-band signal according to information related to the out-band signal and information related to the in-band signal that has been processed by the adjustable attenuator and the transceiver. | 2021-11-25 |
20210367633 | PROCESSING SIGNALS TO ACCOUNT FOR MULTIPATH-REFLECTION PHENOMENA IN RF COMMUNICATIONS - Aspects of the present disclosure may involve use of a radio frequency receiver and in such a receiver, tracking multipath gains and delays of multipath reflections corresponding to an OFDM multipath transmission channel. The gains and delays are based on time-domain evolution of the channel impulse response. Multipath reflections are searched for and then used to calculate channel correlation information to provide channel estimations to aid in mitigating or cancelling distortion of the received signal. | 2021-11-25 |
20210367634 | SIGNAL RECEIVER AND METHOD OF MEASURING OFFSET OF SIGNAL RECEIVER - A signal receiver includes a first preliminary receiver circuit suitable for receiving an input signal and generating a first preliminary reception signal based on a first reference voltage, a second preliminary receiver circuit suitable for receiving the input signal and generating a second preliminary reception signal based on a second reference voltage, a reception circuit suitable for selecting one of the first preliminary reception signal and the second preliminary reception signal in response to a voltage level of a reception signal and generating the reception signal using the selected signal, and a reference voltage generation circuit suitable for adjusting a voltage level of the first reference voltage based on a first offset and adjusting a voltage level of the second reference voltage based on a second offset. | 2021-11-25 |
20210367635 | SINGLE CHANNEL RECEIVER AND RECEIVING METHOD - A single channel receiver includes an input terminal that receives an analog input signal, a mixer that down-mixes the analog input signal by use of a phase- and/or frequency-corrected oscillator frequency signal and shifts complex-valued information contained in the analog input signal to the real part (or alternatively to the imaginary part) to obtain an intermediate real-valued analog signal, an analog-to-digital-converter that converts the intermediate analog signal into an intermediate digital signal, a demodulator that demodulates the intermediate digital signal into a digital output signal, a phase tracking loop that detects zero-crossings in the intermediate digital signal to obtain phase error information representing a phase error in the intermediate digital signal, and an oscillator that generates the phase- and/or frequency-corrected oscillator frequency signal by compensating the phase and/or frequency error in the intermediate digital signal by correcting the phase of the oscillator frequency signal with the phase error information. | 2021-11-25 |
20210367636 | WIRELESS CHARGING OF MOBILE COMMUNICATION DEVICES - A communication device that emits radio frequency signals having a module to determine when the radio frequency signals may be present and are potentially harmful, and to activate a remedial signal generator if the radio frequency signals are considered to be potentially harmful; and the power to operate the module is from a power source that can be charged using wireless charging techniques. | 2021-11-25 |
20210367637 | OUTPUT POWER ADJUSTMENTS BASED ON SENSORS - An example electronic device includes a wireless communication component and a controller. The controller is to set an output power of the wireless communication component based on: whether a first external object is in proximity to a first side of the electronic device; whether the electronic device is stationary; and whether a second external object is in proximity to a second side of the electronic device, where the second side is opposite to the first side. | 2021-11-25 |
20210367638 | PHONE GRAVITY HOLDER - A phone gravity holder comprises a base, a pull rod configured to hold the phone, and a left clamping arm and a right clamping arm configured to clamp the phone, wherein the base is provided with a positioning shaft, the left clamping arm and the right clamping arm are both mounted on the positioning shaft in a rotatable manner, and the pull rod is respectively in transmission connection with the left clamping arm and the right clamping arm, respectively. When the phone is used, the phone is directly placed on the pull rod, and under the gravity effect of the phone, the pull rod drives the left clamping arm and the right clamping arm to rotate in reverse to clamp the phone. The phone can be clamped automatically by utilizing the gravity of the phone and simple mechanical principles, the structure is simple, and the production cost is greatly reduced. | 2021-11-25 |
20210367639 | RECEPTION DEVICE, WIRELESS COMMUNICATION SYSTEM, INTERFERENCE-POWER ESTIMATION METHOD, CONTROL CIRCUIT, AND RECORDING MEDIUM - A reception device includes an interference cancellation unit to extract a symbol from a received signal with a first signal inserted in a time direction of a data symbol, the symbol being a signal during an interval corresponding to the first signal, to reproduce an interference signal during an interval corresponding to the data symbol, and to output a first interference-cancelled signal obtained by extracting the data symbol from a signal obtained by cancelling the interference signal from the received signal, and an interference-power estimation unit to estimate desired signal power by subtracting second average power of a symbol of a first signal, extracted from the received signal, from first average power the data symbol to estimate first noise power by subtracting the desired signal power from third average power of the data symbol, to estimate second noise power from the first noise power, and to estimate interference power by subtracting the second noise power from the second average power. | 2021-11-25 |
20210367640 | ECHO CANCELLING SYSTEM AND ECHO CANCELLING METHOD - An echo cancelling system includes a data transmitter circuit and an echo canceller circuit. The data transmitter circuit is configured to receive a first transmitted signal. The first transmitted signal has a first sampling rate. The echo canceller circuit is configured to generate a second transmitted signal according to the first transmitted signal. The second transmitted signal has a second sampling rate. The second sampling rate is greater than the first sampling rate. The echo canceller circuit is further configured to generate an echo cancelling signal according to the second transmitted signal. The data transmitter circuit is further configured to generate an output signal according to a received signal and the echo cancelling signal. | 2021-11-25 |
20210367641 | SIGNAL SENSOR - The invention provides a signal sensor. The signal sensor comprises a housing, having a connector and a display unit; a tuner, configured to receive a cable signal; a microcontroller unit (MCU), electrically connected with the tuner and the display unit; a scanning switch, electrically connected with the MCU; a power supply, configured to supply a power to the MCU, the tuner and the white LED; and a power switch, electrically connected with the MCU. | 2021-11-25 |
20210367642 | POWER DISTRIBUTION AND DATA ROUTING IN A NETWORK OF DEVICES INTERCONNECTED BY HYBRID DATA/POWER LINKS - A method for execution in a central controller comprises obtaining an interconnection topology for a plurality of nodes interconnected via hybrid data/power links; obtaining a power distribution map associated with the topology; and causing DC power to be distributed to the nodes via the links according to the power distribution map. Also, such a node in which there is at least one power-receiving port and at least one power-transmitting port, a controller and power switching circuitry. The controller operates based on power drawn from a portion of the DC power received via the power-receiving port. The controller determines a destination of data packets received via any of the ports and outputting those of the received data packets that are not destined for the network device via another one of the ports. The controller also causes the power switching circuitry to output via plural power-transmitting ports respective portions of the received DC power received at the power-receiving port. | 2021-11-25 |
20210367643 | DATA TRANSMISSION METHOD FOR BLUETOOTH CARD READER AND ELECTRONIC DEVICE - The present application relates to a data transmission method for a Bluetooth card reader and an electronic device. The method includes: a CCID driver determines communication rate information corresponding to the Bluetooth card reader based on type information corresponding to the Bluetooth card reader; the CCID driver determines specific communication rate information based on card information and the communication rate information; the CCID driver carries the specific communication rate information in a communication rate confirming request and forwards, via the Bluetooth service program, the communication rate confirming request to the Bluetooth card reader for verification, where the Bluetooth card reader is connected with the Bluetooth service program via Bluetooth; and the CCID driver instructs, based on a communication rate acknowledgement response returned by the Bluetooth card reader, the Bluetooth card reader to transmit, with the specific communication rate information confirmed through the communication rate acknowledgement response, data to be transmitted. | 2021-11-25 |
20210367644 | Methods for Beam Tracking and Methods for Generating a Codebook - Disclosed are methods for beam tracking. In the methods, a transmitting unmanned aerial vehicle (UAV) receives motion state information (MSI) of a receiving UAV and determines a first beam angle from the transmitting UAV to the receiving UAV according to the MSI of the receiving UAV. Then the transmitting UAV selects a codeword from a codebook according to the first beam angle. Finally, the transmitting UAV determines an activated sub-array and a beam-forming vector of the CCA according to the size of the activated sub-array corresponding to the sub-codebook to which the codeword belongs, a second beam angle corresponding to the codeword and a location of a central antenna element of an activated sub-array corresponding to the codeword and transmits information using the beam-forming vector. One or more examples of the present disclosure also provide a method for beam tracking implemented by the receiving UAV, methods for generating a codebook. | 2021-11-25 |
20210367645 | TOMLINSON-HARASHIMA PRECODING IN AN OTFS COMMUNICATION SYSTEM - A method for signal transmission using precoded symbol information involves estimating a two-dimensional model of a communication channel in a delay-Doppler domain. A perturbation vector is determined in a delay-time domain wherein the delay-time domain is related to the delay-Doppler domain by an FFT operation. User symbols are modified based upon the perturbation vector so as to produce perturbed user symbols. A set of Tomlinson-Flarashima precoders corresponding to a set of fixed times in the delay-time domain may then be determined using a delay-time model of the communication channel. Precoded user symbols are generated by applying the Tomlinson-Flarashima precoders to the perturbed user symbols. A modulated signal is then generated based upon the precoded user symbols and provided for transmission over the communication channel. | 2021-11-25 |
20210367646 | Network Node, User Equipment and Methods Therein to Enable the UE to Determine a Precoder Codebook - A method performed by a base station of enabling a User Equipment (UE) to determine a precoder codebook in a wireless communication system is provided. The base station transmits, to the UE, information regarding precoder parameters enabling the UE to determine the precoder codebook. The precoder parameters are associated with a plurality of antenna ports of the base station. The precoder parameters relate to a first dimension and a second dimension of the precoder codebook. The plurality of antenna ports comprises a number of antenna ports that is a function of a number of antenna ports in the first dimension, and a number of antenna ports in the second dimension. | 2021-11-25 |
20210367647 | PMI FEEDBACK FOR TYPE II CSI FEEDBACK IN NR-MIMO - Precoding matrix indicator (PMI) feedback for Type II channel state information (CSI) feedback in new radio (NR) multiple input, multiple output (MIMO) operations is discussed. According to various aspects, a user equipment (UE) determines a plurality of CSI feedback components and identifies a set of discarded ones of these components based on a particular component value of a precoding matrix indicator (PMI) component. The UE may then generate an adjusted CSI report by adjusting how the discarded feedback components are treated. The resulting adjusted CSI report may then be transmitted to a serving base station. | 2021-11-25 |
20210367648 | BEAMFORMING ANTENNA, MEASUREMENT DEVICE, ANTENNA MEASUREMENT SYSTEM AND METHOD - The present invention provides a beamforming antenna ( | 2021-11-25 |
20210367649 | REPORTING WIDE BANDWIDTH OPERATION FOR BEAMFORMING - Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may transmit, to a base station, an indication of a range of frequencies outside an operational bandwidth of the UE based at least in part on the range of frequencies being compatible with one or more sets of analog beamforming beam weights associated with the operational bandwidth. The UE may communicate, with the base station, based at least in part on transmitting the indication of the range of frequencies outside of the operational bandwidth of the UE. Numerous other aspects are provided. | 2021-11-25 |
20210367650 | Pre-emption During CSI-RS Mobility Measurements - A base station communicates with a first user equipment (UE) and a second UE. The base station determines a first configuration for the first UE for a channel state information reference signal (CSI-RS) on a symbol, schedules a data transmission for the second UE on the symbol where the CSI-RS is configured so that the CSI-RS and the data transmission collide on the symbol and determines a second configuration for the first UE when the CSI-RS and the data transmission collide on the symbol. | 2021-11-25 |
20210367651 | ENHANCED MEASUREMENT AND REPORT CONFIGURATION FOR FULL-DUPLEX OPERATION - Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a first wireless node (e.g., a user equipment) may determine one or more measurements associated with a beam search performed during a downlink beam management process. The first wireless node may transmit, to a second wireless node (e.g., a base station), a report that indicates one or more candidate downlink receive beams, candidate uplink transmit beams, or candidate downlink receive and uplink transmit beam pairs suitable for full-duplex operation based at least in part on the one or more measurements. Numerous other aspects are provided. | 2021-11-25 |
20210367652 | Smaller Sub-Band Size for PMI than for CQI - A method performed by a wireless device ( | 2021-11-25 |
20210367653 | CHANNEL SMOOTHING WITH TX BEAMFORMING - A method for channel smoothing with transmit beamforming includes transmitting, by a first device, a non-data-packet (NDP) frame to a second device. The method also includes receiving, by the second device, the NDP frame and transmitting a compressed report to the first device. The method further includes receiving, by the first device, the compressed report and deriving a first beamforming matrix from the compressed report. A second beamforming matrix is generated employing a processing known to the second device, and a data frame is transmitted to the second device using the second beamforming matrix. | 2021-11-25 |