48th week of 2009 patent applcation highlights part 15 |
Patent application number | Title | Published |
20090289637 | System and Method for Determining the Impedance of a Medium Voltage Power Line - A system and method of using a computer system to provide utility information related to a plurality of underground power line cable segments connected on opposite ends to different distribution transformers is provided. In one embodiment the method comprises monitoring the impedance of each of the plurality of underground power line cable segments over time, detecting a change in the impedance of a set of the plurality of underground power line cable segments, storing in a memory information sufficient for identifying each underground power line cable segment of the set of the plurality of underground power line cable segments for which a change in impedance is detected, generating a report that identifies the set of the plurality of underground power line cable segments for which a change in impedance is detected, and outputting the report. | 2009-11-26 |
20090289638 | MICROWAVE READOUT FOR FLUX-BIASED QUBITS - A method for determining whether a quantum system comprising a superconducting qubit is occupying a first basis state or a second basis state once a measurement is performed is provided. The method, comprising: applying a signal having a frequency through a transmission line coupled to the superconducting qubit characterized by two distinct, separate, and stable states of differing resonance frequencies each corresponding to the occupation of the first or second basis state prior to measurement; and measuring at least one of an output power or phase at an output port of the transmission line, wherein the measured output power or phase is indicative of whether the superconducting qubit is occupying the first basis state or the second basis state. | 2009-11-26 |
20090289639 | INSULATION MEASUREMENT METHOD AND INSULATION MEASUREMENT APPARATUS - An insulation measurement method in an insulation measurement apparatus of a flying capacitor type, includes a first power supply charge voltage measurement process of applying a voltage of a power supply to a flying capacitor for a first charge time period a first grounding resistor measuring voltage measurement process of applying the voltage of the power supply to the flying capacitor via an insulation resistor on one electrode side of the power supply, a second power supply charge voltage measurement process of applying the voltage of the power supply to the flying capacitor for a second charge time period, a second grounding resistor measuring voltage measurement process of applying the voltage of the power supply to the flying capacitor via an insulation resistor on the other electrode side of the power supply, and an insulation resistor conversion process of obtaining a value of the insulation resistor based on measurement results of the first and second charge voltage measurement processes and the first and second grounding resistor measuring voltage measurement processes and an insulation resistor conversion expression. | 2009-11-26 |
20090289640 | INSULATION MEASUREMENT APPARATUS - An insulation measurement apparatus includes a path including a first resistor, a capacitor in a state electrically floated from a ground potential, and a second resistor coupled in series sequentially from a positive electrode side of a power supply to a negative electrode side of the power supply, a first switching element provided in a path from the positive electrode side of the power supply to the capacitor, a second switching element provided in a path from the capacitor to the negative electrode side of the power supply, a detection section which detects a charge voltage set to the capacitor and determines an insulation state of the power supply, and a voltage setting section which executes a power supply voltage measurement mode for controlling the first and second switching elements to charge the capacitor by a voltage of the power supply for a predetermined voltage applying time period for measuring the voltage of the power supply, and an insulation voltage measurement mode for charging a terminal of a positive electrode side or a negative electrode side of the capacitor via a resistor between the positive electrode or the negative electrode of the power supply and the ground potential for a predetermined voltage applying time period for measuring a voltage of the insulation resistor. | 2009-11-26 |
20090289641 | Area-variable type capacitive displacement sensor having mechanical guide - An area-variable type capacitive displacement sensor includes: a stationary element; a movable element; an elastic member for providing a force biasing one of the stationary element and the movable member towards a remaining one thereof in a direction perpendicular to a driving direction so that the stationary element and the movable member are maintained in close contact with each other; a power supply; and a signal detecting circuit. The sensor further includes a guide means for correcting an initial alignment error and reducing an operation alignment error between the stationary element and the movable element. | 2009-11-26 |
20090289642 | NON-DESTRUCTIVE METHOD FOR DETECTING ZONES WITH NON CONDUCTIVE MATERIALS IN A COMPOSITE PART - Non-destructive method for detecting zones with non-conductive materials, such as materials that include glass fibres, in a part made of a conductive composite, such as a composite whose reinforcing fibres are carbon fibres, provided with an organic coating, that comprises the following stages: a) providing a device for applying an electric potential on the surface of said part; b) determining the dielectric breakdown potential Pr corresponding to the thickness E of the coating; c) applying said dielectric breakdown potential Pr with said device to the part for the purpose of identifying those zones that have non-conductive materials when dielectric breakdown does not occur in them. | 2009-11-26 |
20090289643 | COORDINATE DETECTING DEVICE AND METHOD - A coordinate detecting device includes a resistive film disposed on a quadrangular substrate; a power source for applying a voltage to the resistive film; four electrodes connected to the power source and disposed in four corners of the resistive film; four switches each disposed between the power source and a corresponding electrode; four ammeters for measuring currents flowing through corresponding electrodes; and a grounded conductive film for detecting coordinates of a contact point on the resistive film when the conductive film is brought in contact with the resistive film. The voltage is applied sequentially to the electrodes by opening and closing the switches. When the conductive film is brought in contact with the resistive film, the ammeters sequentially measure currents flowing through the corresponding electrodes. The coordinates of the contact point are detected based on positions of the electrodes and resistances obtained using the measured currents. | 2009-11-26 |
20090289644 | APPARATUS AND METHOD FOR TESTING KEYBOARD OF MOBILE PHONE - An apparatus for testing a keyboard of a mobile phone, includes a testing controller, a key triggering device, an analog to digital (A/D) converter, and a switch assembly connected to the key triggering module. The switch assembly includes a plurality of switches. The key triggering device includes a key triggering module connected to the keyboard. The testing controller sends a controlling signal to trigger a key of the keyboard to turn on a switch corresponding to the key, triggering the key, and comparing activating information of the switch to the key value from the mobile phone to determine if the result is correct. | 2009-11-26 |
20090289645 | Methods And Apparatus For Multi-Modal Wafer Testing - Access to integrated circuits of a wafer for concurrently performing two or more types of testing, is provided by bringing a wafer and an edge-extended wafer translator into an attached state. The edge-extended wafer translator having wafer-side contact terminals and inquiry-side contact terminals disposed thereon, a first set of wafer-side contact terminals being electrically coupled to a first set of inquiry-side contact terminals, and a second set of wafer-side contact terminals being electrically coupled to a second set of inquiry-side contact terminals. The edge-extended wafer translator having a central portion generally coextensive with the attached wafer, and an edge-extended portion extending beyond the boundary generally defined by the outer circumferential edge of the wafer. A first set of pads of at least one integrated circuit is electrically coupled to the first set of wafer-side contact terminals, and a second set of pads of the integrated circuit is electrically coupled to the second set of wafer-side contact terminals. The edge-extended wafer translator may be shaped such that its edge-extended portion is not coplanar with the central portion thereof. | 2009-11-26 |
20090289646 | TEST PROBE - A test probe pin is disclosed. The test probe has a plurality of probes, each of which has a probe tip surface coated with a nano-film of conducting polymer, and the thickness of the nano-film is about 1-20 nm. The probes coated with the nano-film are installed on a test fixture for testing IC components, so that the probes can efficiently provide excellent no-clean property and stabler electro-conductivity for lowering the cleaning frequency of the probes, enhancing the yield of IC component testing, increasing the utility rate of the test fixture, reducing the total testing cost, elongating the usage lifetime of the test probe, and reducing the cost of probe material. Thus, due to the nano-film of conducting polymer, the probes made of metal material can provide almost the same electro-conductivity as a traditional probe by only plating a gold layer of one fifth of original thickness, so that the cost of whole probe material can be reduced. | 2009-11-26 |
20090289647 | INTERCONNECT SYSTEM - A test contact may include a first portion having an open-ended rounded shape. The first portion may define an opening therethrough. The test contact may include a second portion having a curved structure. The first portion and the second portion may be formed integrally, and the second portion may be configured to contact a portion of a device lead. | 2009-11-26 |
20090289648 | COAXIAL FOUR-POINT PROBE FOR LOW RESISTANCE MEASUREMENTS - Various exemplary embodiments provide probes, systems and methods for measuring an effective electrical resistance/resistivity with high sensitivity. In one embodiment, the measuring system can include an upper probe set and a similar lower probe set having a sample device sandwiched there-between. The device-under-test (DUT) samples can be sandwiched between two conductors of the sample device. Each probe set can have an inner voltage sense probe coaxially configured inside an electrically-isolated outer current source probe that has a large contact area with the sample device. The measuring system can also include a computer readable medium for storing circuit simulations including such as FEM simulations for extracting a bulk through-plane electrical resistivity and an interface resistivity for an effective electrical z-resistivity of the DUT, in some cases, having sub-micro-ohm resistance. | 2009-11-26 |
20090289649 | TESTER WITH LOW SIGNAL ATTENUATION - A tester with low signal attenuation and suitable for measuring an electrical characteristic of a subject to be tested includes a circuit board and a first probe. The circuit board has a first surface and a second surface respectively having a first signal transmission line and a second signal transmission line. The first probe has a contact end contacting the subject to be tested and a first signal end and a second signal end respectively connecting the first signal transmission line and the second signal transmission line. The first probe receives a testing signal from the first signal transmission line through the first signal end and transmits the testing signal from the contact end to the subject to be tested, such that the subject to be tested generates a response signal, and the first probe transmits the response signal to the second signal transmission line through the second signal end. | 2009-11-26 |
20090289650 | PROBE CARD AND METHOD FOR SELECTING THE SAME - A probe card includes a probe unit having multiple through holes arranged therein, multiple probe needles respectively press-fitted to the multiple through holes, a printed board having convex portions which presses down the probe needles located in predetermined positions, and a unit holder which supports the probe unit and the printed board. | 2009-11-26 |
20090289651 | PROBE CARD LAYOUT - Multi-touchdown, parallel test probe cards having probe elements arranged to provide greater efficiency during testing of a substrate having a plurality of die thereon. Probe elements may be arranged in a number of configurations that allow for efficient usage of the probe elements. | 2009-11-26 |
20090289652 | POGO PROBE, PROBE SOCKET, AND PROBE CARD - A pogo-type probe to be installed in a probe socket and a probe card for testing chip scale package of a semiconductor device is characterized in that the pogo probe has a hollow main body for receiving at least one resilient element internally and the main body comprises two end portions disposed with a first probe head and a second probe head respectively, wherein each of the probe heads is composed of a plurality of taper members to form a crown shape, and each of the taper members has an individual chamfer so that each chamfer has a tip to contact each contact pad of the semiconductor device under test for chip scale package. | 2009-11-26 |
20090289653 | Inspection apparatus and method for semiconductor IC - The connection between a PTC element | 2009-11-26 |
20090289654 | SYSTEM AND METHOD FOR REDUCING TEMPERATURE VARIATION DURING BURN IN - Systems and methods for reducing temperature variation during burn-in testing. In one embodiment, power consumed by an integrated circuit under test is measured. An ambient temperature associated with the integrated circuit is measured. A desired junction temperature of the integrated circuit is achieved by adjusting a body bias voltage of the integrated circuit. By controlling temperature of individual integrated circuits, temperature variation during burn-in testing can be reduced. | 2009-11-26 |
20090289655 | Process condition evaluation method for liquid crystal display module - A process condition evaluation method for a liquid crystal display module (LCM) includes: a first step of obtaining a threshold power measuring pattern, an analysis sample for a cell bonding status in an LCD fabrication process, and obtaining a lower substrate sample by separating an upper substrate from the threshold power measuring pattern; a second step of supplying voltages on a gate pad on the lower substrate sample with sequentially increasing a voltage level by a predetermined unit by using an electrical device, and obtaining a threshold current and a threshold voltage by measuring currents at a drain pad whenever voltage increased by a predetermined unit is applied to the gate pad; and a third step of obtaining threshold power based on the threshold current and the threshold voltage, and thereby evaluating process conditions of the LCM. | 2009-11-26 |
20090289656 | Dry-type high-voltage load system apparatus and method of preventing chain breaking and arc discharge for use therewith - A dry-type high-voltage load system apparatus has a space-saving structure, which is resistant to chain breaking, arc discharge and vibration, and a method of preventing the chain breaking and the arc discharge for use with the system apparatus. The system apparatus includes a dry-type high-voltage load system circuit including a low-voltage bank formed of lower-capacity configuration banks which include three-phase resistor circuits which are low-voltage resistor circuit. A high-voltage bank includes lower-capacity configuration banks for a high-voltage resistor circuit formed of three-phase resistor circuits. The three-phase resistor circuits are connected to a high-voltage power generator in parallel and are in the form of a Y-connection of three resistor arrays so that an isolated and independent neutral point is unconnected to other neutral points. The three phase resistor circuits may also be in the form of a Δ-connection. | 2009-11-26 |
20090289657 | SYSTEMS AND METHODS FOR PROVIDING DEFECT-TOLERANT LOGIC DEVICES - The present invention describes systems and methods to provide defect-tolerant logic devices. An exemplary embodiment of the present invention provides a defect-tolerant logic device including a plurality of CMOS gates and at least one defective CMOS gate included within the plurality of CMOS gates. Additionally, the at least one defective CMOS gate is enabled to be reconfigured into a pseudo-NMOS transistor if a P-network of the at least one defective CMOS gate is diagnosed as defective. Furthermore, the at least one defective CMOS gate is enabled to be reconfigured into a pseudo-PMOS transistor if the N-network of the at least one defective CMOS gate is diagnosed as defective. | 2009-11-26 |
20090289658 | IMPEDANCE CALIBRATION CIRCUIT, SEMICONDUCTOR MEMORY DEVICE WITH THE IMPEDANCE CALIBRATION CIRCUIT AND LAYOUT METHOD OF INTERNAL RESISTANCE IN THE IMPEDANCE CALIBRATION CIRCUIT - An impedance calibration circuit for impedance matching between a semiconductor memory device and an external device includes a driving circuit and a comparing circuit. The driving circuit has a plurality of internal resistances, with one or more of the internal resistances being a variable resistance. The driving circuit compares the impedance of the internal resistances to the input/output impedance of the external device in order to provide a calibration voltage. The comparing circuit compares the calibration voltage to a reference voltage and provides a code signal for calibrating the impedance corresponding to output data with the input/output impedance of the external device. The impedance calibration circuit calibrates an impedance mismatch between the impedance calibration circuit and a data input/output driver by adjusting the impedance of the impedance calibration circuit through the variable resistance. | 2009-11-26 |
20090289659 | Calibration circuit - In a calibration control circuit, a first clock gate circuit restricts passage of reference update clocks during a calibration period so as to stop a first one of the reference update clocks and supplies the restricted reference update clocks as first update clocks CLK | 2009-11-26 |
20090289660 | INTERCONNECTION AND INPUT/OUTPUT RESOURCES FOR PROGRAMMABLE LOGIC INTEGRATED CIRCUIT DEVICES - A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device. | 2009-11-26 |
20090289661 | Integrated Circuit With Crosslinked Interconnect Networks - The present invention provides in a first aspect a programmable interconnect network for an array of logic blocks, which comprises a plurality of switch boxes being connected in a tree-based hierarchical architecture and providing selection and connection for the logic blocks, switch boxes located at the lowest level of the tree structure are connected to the logic blocks; wherein said network comprises a crosslink established between two of said plurality of switch boxes. The present invention helps implement functions with more area and timing efficiency and/or placement-friendliness. | 2009-11-26 |
20090289662 | BRIDGE DESIGN FOR SD AND MMC DATA BUSES - A circuit with bi-directional signal transmission, including a first signal source, for generating a first signal comprising one bit per clock cycle during a first plurality of clock cycles, a second signal source, for generating a second signal including one bit per clock cycle during a second plurality of clock cycles, a first buffer, coupled with the first signal source, that outputs the first signal when the first buffer is enabled, a second buffer, coupled with the second signal source, that outputs the second signal when the second buffer is enabled, and a plurality of logical gates, coupled with the first signal source, the second signal source, the first buffer and the second buffer, that control enablement of the first buffer and the second buffer, such that (i) at any given clock cycle at least one of the first buffer and the second buffer is disabled, and (ii) when the first buffer and said the buffer are both disabled, subsequent generation of a ‘0’ bit in the first signal or the second signal causes enablement of the first buffer or the second buffer, respectively. | 2009-11-26 |
20090289663 | CIRCUIT FOR COMPARING TWO N-DIGIT BINARY DATA WORDS - The invention relates to a circuit for comparing two n-digit binary data words x[1](t), . . . , x[n](t) and x′[1](t), . . . , x′[n](t), which in the error-free case are either identical or inverted bit-by-bit with respect to each other, with a series connection of a combinatorial circuit for implementing a first combinatorial function, a controllable register and a combinatorial circuit for implementing another combinatorial function. | 2009-11-26 |
20090289664 | Signal detecting apparatus, signal receiving apparatus, and signal detecting method - A signal detecting apparatus detects a signal received based on a current received and includes a detecting unit that detects, in the current received, a peak equal to or higher than a threshold and a time counting unit that counts a given period of time from a point in time of detection of the peak by the detecting unit. The signal detecting apparatus further includes a determining unit that determines whether the detecting unit has detected the peak again within the given period of time counted by the time counting unit. An output unit of the signal detecting apparatus outputs information indicating detection of the signal received when the determining unit determines that the peak has been detected again. | 2009-11-26 |
20090289665 | Comparator - An electronic device compares a first voltage with a selected first reference voltage or second reference voltage. The electronic device includes a comparator having a first input receiving the first voltage, a second input receiving the selected reference voltage and an output providing an output signal based on a comparison. A control stage connected to the output of the comparator generates a control signal based on the output of the comparator. The electronic device selects either the first reference voltage or the second reference voltage in response to the control signal thus comparing the first voltage with the selected reference voltage. | 2009-11-26 |
20090289666 | Direct digital synthesis frequency synthesizer and associated methods - An acousto-optic system is provided that has an acousto-optic device coupled to a DDS IC controller. The DDS controller provides amplitude modulation to adjust output power synchronously with changes in frequency when activating a different frequency. | 2009-11-26 |
20090289667 | Clock Generation Using a Fractional Phase Detector - Circuits are provided that generate from an input signal one or more output clock signals having reduced skew. The input signal has transitions derived from the transitions of an original clock signal having a frequency that differs from the frequency of the output clock signal. The frequency of the output clock signal is a product from multiplying the frequency for the input signal and an integer ratio. The circuit includes an accumulator, a fractional phase detector, and a loop filter. The accumulator periodically adds a numerical offset value to a numerical phase value. The output clock signal is generated from this numerical phase value. The fractional phase detector generates from the numerical phase value a respective numerical phase error for each of the transitions of the input signal. The loop filter generates the numerical offset value from a filtering of the respective numerical phase errors. | 2009-11-26 |
20090289668 | Output driver circuit for an integrated circuit - An integrated circuit | 2009-11-26 |
20090289669 | CONTROLLING THE SLEW-RATE OF AN OUTPUT BUFFER - An output buffer provided according to an aspect of the present invention is designed to generate an output signal with a slew rate that is substantially independent of the threshold voltage of transistors contained within. An output buffer provided according to another aspect of the present invention provides output signals with different slew rates depending on the magnitude of the load capacitance at the output node of the output buffer. | 2009-11-26 |
20090289670 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A buffer circuit is provided between a gate terminal of a pull-down transistor and a threshold circuit receiving a gate signal as an input signal. A voltage applied to an output terminal of a power semiconductor element from an external battery power supply is supplied to the buffer circuit through a resistive element. The buffer circuit converts the level of an on-signal output from the threshold circuit into a voltage higher than the threshold of the pull-down transistor, so that the pull-down transistor operates surely to turn off the power semiconductor element even when the level of the gate signal is low. Thus, there is provided a semiconductor integrated circuit device having a power semiconductor element which can be turned off by sure operation of a pull-down semiconductor element. | 2009-11-26 |
20090289671 | FREQUENCY DIVIDER CIRCUIT - A frequency divider circuit comprises a plurality of T flip-flops, a first transmission gate, a second transmission gate and an inverter. The plurality of T flip-flops is connected in series. The output of the inverter is connected to a clock input of a first T flip-flop. The first transmission gate connects a clock signal and the other clock input of the first T flip-flop and the input of the inverter. The second transmission gate connects the inverted signal of the clock signal and the output of the first transmission gate. | 2009-11-26 |
20090289672 | Method of processing signal data with corrected clock phase offset - The present invention provides a method of processing signal data comprising generating a first clock signal and a second clock signal and processing the signal data using the first clock signal and the second clock signal. While processing the signal data, the phase difference between the first clock signal and the second clock signal is measured and corrected for so that a target phase difference between the first clock signal and the second clock signal is maintained. | 2009-11-26 |
20090289673 | VOLTAGE CONTROLLED OSCILLATORS AND PHASE-FREQUENCY LOCKED LOOP CIRCUIT USING THE SAME - A voltage controlled oscillator comprising first and second differential delay cells. The first differential delay cell has a first control voltage input terminal. The second differential delay cell is coupled to the first differential delay cell in a loop and has a second control voltage input terminal. The second voltage input terminal is disconnected from the first voltage control input terminal. The first voltage control input terminal receives a first voltage signal, and the second voltage control input terminal receives a second voltage signal different from the first voltage signal. | 2009-11-26 |
20090289674 | PHASE-LOCKED LOOP - A phase-locked loop includes a phase detector, a charge pump and a controllable oscillator. The phase detector is supplied by a first supply voltage and is utilized for comparing a phase difference between an reference input signal and a feedback signal based on an output signal to generate at least one detect signal. The charge pump is supplied by a second supply voltage, and is utilized for generating a control signal with charge amounts according to the detect signal, where the first supply voltage is different from the second supply voltage. The controllable oscillator is utilized for generating the output signal according to the control signal, wherein a frequency of the output signal is adjusted by the control signal. | 2009-11-26 |
20090289675 | DIFFERENTIAL TRANSMITTER AND AUTO-ADJUSTMENT METHOD OF DATA STROBE THEREOF - A differential transmitter and an auto-adjustment method of data strobe thereof are provided. The differential transmitter includes a phase-detecting unit, a switching unit, a rising edge strobe unit, and a falling edge strobe unit. The phase-detecting unit detects a phase relation between a clock signal and a data signal to outputs a detection result. The rising edge strobe unit latches the data signal at a rising edge of the clock signal, and converts a latching result to a first differential output signal. The falling-edge-strobe unit latches the data signal at a falling edge of the clock signal, and converts a latching result to a second differential output signal. The switching unit determines whether to switch the clock signal and data signal to the rising edge strobe unit or to the falling edge strobe unit according to the detection result. | 2009-11-26 |
20090289676 | DLL circuit - A DLL circuit includes a coarse delay adjustment circuit and a fine delay adjustment circuit, which further includes a first fine delay circuit and a second fine delay circuit serving as an interpolation circuit. The coarse delay adjustment circuit delays a reference clock signal by a plurality of delay stages so as to provide the first fine delay circuit with two phase signals having the phase difference of two delay stages, which are then converted into two delay signals having the phase difference of one delay stage. The delay signals are subjected to interpolation, thus producing an output clock signal. Due to a reduction of the phase difference in the first fine delay circuit, it is possible to reduce the minimum operation cycle of the interpolation circuit and to thereby increase the maximum operation frequency of the DLL circuit. | 2009-11-26 |
20090289677 | DEVICE - A device in which a clock generation circuit is connected to a counter circuit for controlling operation timing of a DLL circuit or the like, and the counter circuit is intermittently operated by intermittently supplying a clock signal to the counter circuit from the clock generation circuit. | 2009-11-26 |
20090289678 | METHOD OF CONTROL SLOPE REGULATION AND CONTROL SLOPE REGULATION APPARATUS - A control loop has a control slope associated therewith. The control loop is provided to control a unit under control. A method of regulating the control slope comprises the step of measuring the control slope of the control loop and modifying a parameter associated with the unit under control in order to maintain the control slope within a desired range. Lock of the control loop is therefore maintained. | 2009-11-26 |
20090289679 | Duty correction circuit - A duty correction circuit is formed using at least one delay circuit, which is constituted of a first inverter including three transistors of different conduction types and a second inverter including three other transistors of different conduction types and which delays and adjusts an input clock signal at the leading-edge/trailing-edge timing so as to convert it into an output clock signal based on a first or second bias voltage produced by a bias circuit detecting the duty ratio of the output clock signal. The duty correction circuit decreases the high-level period of the output clock signal having a high duty ratio based on the first bias voltage. Alternatively, the duty correction circuit increases the high-level period of the output clock signal having a low duty ratio based on the second bias voltage. | 2009-11-26 |
20090289680 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first duty determining circuit ( | 2009-11-26 |
20090289681 | High-speed cable with embedded power control - A High-Definition Multimedia Interface (HDMI) cable carries high speed encoded data which are transmitted differentially over data channels, along with a clock. High-frequency loss and differential skew within a differential signal may be compensated by analog circuits embedded in the cable. These embedded circuits are tuned at production for best performance by observing the quality of the recovered analog signal. The embedded circuits are powered by a combination of power sources, both carried within the cable, and harvested from the high-speed signals themselves. | 2009-11-26 |
20090289682 | Potential Converter Circuit - Embodiments of a potential converter circuit include a converter for converting a bipolar input signal to a unipolar output signal that only consumes current at a change of potential of the input signal. | 2009-11-26 |
20090289683 | Combination of analog and digital feedback for adaptive slew rate control - An apparatus for scaling a load device with frequency in a phase interpolator can include an analog loop and a digital loop. The load device of the phase interpolator can include a transistor and a plurality of resistors selectively configured in parallel with the transistor. The analog loop controls a resistance of the transistor based on a voltage applied to a control terminal of the transistor. For instance, the analog loop can tune the resistance of a PMOS device by adjusting a voltage applied to the PMOS device's gate terminal. In addition, the analog loop can include a comparator to compare a voltage across the transistor to a reference voltage such that an optimal voltage is maintained for an output swing of the phase interpolator. The analog loop can also include a low pass filter coupled to an output of the comparator to define frequency stability and loop bandwidth of the analog loop. The digital loop operates in conjunction with the analog loop and controls the plurality of resistors by incrementing or decrementing a number of resistors that are configured in parallel with the transistor in the load device. In combining the analog and digital loops to control the load device of the phase interpolator, this configuration takes advantage of the wide tuning range of the digital control and the smooth, continuous output of the analog control. Further, in operating the analog and digital loops in conjunction with each other, the present invention avoids a long observation time in locking the system, as seen in conventional designs, while guaranteeing frequency stability in the operation of both the analog and digital loops. | 2009-11-26 |
20090289684 | PULSE DETECTION DEVICE AND PULSE DETECTION METHOD - A pulse detection device detects a pulse signal having an intermediate potential in a predefined period. Furthermore, the pulse detection device includes a signal fixing section that fixes the intermediate potential of the pulse signal at a low level or a high level. Furthermore, the signal fixing section is preferably a pull-down resistor or a pull-up resistor connected to an input signal line to which the pulse signal is input. Note that a pulse detection method may fix the intermediate potential of the pulse signal at a low level or a high level. | 2009-11-26 |
20090289685 | Bias voltage generation for capacitor-coupled level shifter with supply voltage tracking and compensation for input duty-cycle variation - A circuit architecture, or topology, that provides a level shifter substantially independent of the duty cycle of an input signal includes an H-bridge arrangement of field effect transistors, a pair of capacitively coupled input terminals connected to the gates of the high-side transistors and circuitry to set the bias voltage at the gates of the high-side transistors, wherein the bias voltage generation circuitry receives at least information indicative of both the H-bridge power supply voltage and the modulation of the input signal. Various embodiments include a switchable element coupled in series with a voltage divider portion in the bias voltage generation circuitry. The ratio of on to off time of the switchable element determines the average current through the voltage divider and thus the bias voltage. To prevent excessive short-circuit current flow through the high-side transistors, the switchable elements are turned off responsive to detection of a short-circuit condition. | 2009-11-26 |
20090289686 | VOLTAGE LEVEL SHIFT CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - Provided is a voltage level shift circuit including: a first voltage level shift circuit formed of a P-channel enhancement type transistor (M | 2009-11-26 |
20090289687 | MIXER HAVING CONTROLLABLE LOAD WITH REDUCED EQUIVALENT LOAD VALUE DURING SWITCHING TRANSIENTS OF LOCAL OSCILLATING SIGNAL - A mixer has a controllable load, a signal mixing module, and a controller. The controllable load is controlled by a control signal to change an equivalent load value thereof. The signal mixing module has an output port coupled to the controllable load and an input port coupled to an input signal, and is used for mixing the input signal with a local oscillation signal. The controller is coupled to the controllable load, and is used for generating the control signal to reduce the equivalent load value of the controllable load during switching transients of the local oscillation signal. | 2009-11-26 |
20090289688 | SIGNAL ADJUSTING CIRCUIT - A signal adjusting circuit is provided. The signal adjusting circuit includes a first operational unit, a second operational unit, an auto-gain controller (AGC), a first clamp circuit, and a second clamp circuit is provided. The first operational unit performs an operation to a digital signal and a first gain value, to obtain a first adjusting signal. The second operational unit performs an operation to the digital signal and a second gain value, to obtain a second adjusting signal. The AGC generates a third gain value according to the first adjusting signal. The first clamp circuit receives and restricts the third gain value between a first upper limit and a first lower limit for generating the first gain value. The second clamp circuit receives and restricts the third gain value between a second upper limit and a second lower limit for generating the second gain value. | 2009-11-26 |
20090289689 | Signal output circuit and selector circuit using the same - A signal output circuit adapted to a selector circuit is constituted of an inverter circuit which activates propagation of an input signal therethrough in an active level of a control signal and which inactivates it in an inactive level of the control signal, and a control circuit which maintains the input terminal of the inverter circuit at a predetermined potential irrespective of the level of the input signal in the inactive level of the control signal. This achieves high-speed and high-precision propagation of the input signal. The selector circuit is formed using a plurality of signal output circuits so as to selectively output one of first and second input signals in response to the control signal. | 2009-11-26 |
20090289690 | SEMICONDUCTOR DEVICE WITH SWITCH ELECTRODE AND GATE ELECTRODE AND METHOD FOR SWITCHING A SEMICONDUCTOR DEVICE - A semiconductor device with switch electrode and gate electrode and a method for switching a semiconductor device. One embodiment provides a semiconductor substrate with an emitter region, a drift region, a body region and a source region. The drift region is formed between the emitter and the body region while the body region is formed between the drift and the source region. A first trench structure extends from the source region at least partially into the drift region. The first trench structure includes a gate electrode arranged next to the body region and a switch electrode arranged in portions next to the drift region, wherein the switch and gate electrodes are electrically insulated from each other in the trench structure. A first gate driver is electrically connected to the gate electrode while a second gate driver is electrically connected to the switch gate. | 2009-11-26 |
20090289691 | METHOD OF SWITCHING AND SWITCHING DEVICE FOR SOLID STATE POWER CONTROLLER APPLICATIONS - A solid state switching device (SSSD) for AC and DC high power solid state power controller includes, for DC applications, a MOSFET and an IGBT connected in parallel and an optional zener diode connecting a collector and a gate of the IGBT. For AC applications, the SSSD includes a “back to back” pair of MOSFETs connected in parallel with a pair of counter-parallel IGBTs, each in series with a diode, and, optionally, zener diodes “back to back” with conventional diodes connecting a collector and a gate of each of the IGBT. A method of switching establishes a sequence of turning on/off the MOSFET(s) and the IGBT(s) wherein the IGBT(s) turn on before and turn off after the MOSFET(s). A negative feedback prevents a voltage of SSSD rising above predetermined level. | 2009-11-26 |
20090289692 | Nagative voltage switch - A negative voltage switch includes a switch unit, a voltage level converting circuit, and a discharge circuit. The switch unit has an input terminal for receiving a negative input voltage and an output terminal coupled to a load. The voltage level converting circuit receives a control signal and switches the switch unit to a first state or a second state according to the control signal. The switch circuit is switched to the first state if the level of the control signal is higher than a predetermined level and is switched to the second state if the level of the control signal is lower than the predetermined level, and the predetermined level is higher than the level of the negative input voltage. | 2009-11-26 |
20090289693 | BI-DIRECTIONAL BUFFER AND METHOD FOR BI-DIRECTIONAL BUFFERING THAT REDUCE GLITCHES DUE TO FEEDBACK - A bi-directional buffer includes at least a first and second pair of one-shots and transistors. At least the first pair of one-shots and the first pair of transistors enable a second input/output (I/O) terminal to follow a first I/O terminal. At least the second pair of one-shots and the second pair of transistors enable the first I/O terminal to follow the second I/O terminal. There is a detection of whether the direction of a signal is from the first I/O terminal to second I/O terminal, or vise versa. If the direction is from the first I/O terminal to the second I/O terminal, there is an at least temporarily disabling the second pair of one-shots to thereby reduce feedback that may occur from the second I/O terminal to the first I/O terminal. If the direction is from the second I/O terminal to the first I/O terminal, there is an at least temporarily disabling the first pair of one-shots to thereby reduce feedback that may occur from the first I/O terminal to the second I/O terminal. | 2009-11-26 |
20090289694 | Current-Sensing Apparatus and Method for Current Sensing - At least one embodiment of the invention specifies a current-sensing apparatus and/or a method for its operation which is based on the current sensor provided being a GMR sensor in the form of a gradient sensor and on the gradient sensor, or a component which includes this gradient sensor, itself including a conductor section of a compensating circuit. As such, the current in the measurement circuit can be compensated for by a current in the compensating circuit and the compensating current can be evaluated as a measure of the electrical variable to be detected for the measurement circuit. | 2009-11-26 |
20090289695 | VOLTAGE DETECTION CIRCUIT AND VOLTAGE DETECTION METHOD - Disclosed herein is a voltage detection circuit including: a voltage detection section; a first voltage determination section; and a second voltage determination section. | 2009-11-26 |
20090289696 | Apparatus and Methods for Adjusting Performance of Integrated Circuits - A programmable logic device (PLD) includes a delay circuit and a body-bias generator. The delay circuit has a delay configured to represent a delay of user circuit implement in the PLD. The body-bias generator is configured to adjust the body bias of a transistor within the user circuit. The body-bias generator adjusts the body bias of the transistor in response to a level derived from the signal propagation delay of the delay circuit. | 2009-11-26 |
20090289697 | BANDGAP REFERENCE GENERATOR UTILIZING A CURRENT TRIMMING CIRCUIT - A circuit for providing a bandgap voltage. The circuit includes a classic bandgap reference voltage generation circuit including first end second serially connected transistors acting as a current mirror to another portion of the classical bandgap reference circuit and being coupled between a supply voltage V | 2009-11-26 |
20090289698 | ULTRA LOW POWER WAKE-UP CIRCUIT - An apparatus for selectively enabling power including a power supply, and a device having a controller and an input activated by a user. The controller is selectively powered by the power supply. While the device is in a sleep state, a sensing circuit senses activation of the input by the user and enables the power supply to provide power to the controller in response to the sensed activation of the input by the user. A latch circuit causes the power supply to continue to provide power to the controller. The controller is responsive to the sensed activation of the input by the user for enabling the latch circuit and for disabling the latch circuit, thereby reentering the device into a sleep state. | 2009-11-26 |
20090289699 | Output conductance automatic regulation circuit of differential current output type circuit and filter circuit - Output conductance of a differential current output type circuit constituting a filter body ( | 2009-11-26 |
20090289700 | FORWARDED CLOCK FILTERING - Some embodiments include a tunable bandpass filter to provide a filtered output signal; a circuit portion to provide an output signal in response to the filtered output signal; a comparator circuit to provide a comparison signal in response to the output signal from the circuit portion; and a feedback circuit to tune the tunable bandpass filter in response to the comparison signal provided by the comparator circuit. Other embodiments are described and claimed. | 2009-11-26 |
20090289701 | Self-Identifying Stacked Die Semiconductor Components - A semiconductor die having a functional circuit (e.g., a memory array) and a decode circuit suitable for use in a stacked die semiconductor component (e.g., a random access memory component) is described. The decode circuit permits individual die in a stacked die structure to automatically determine their location or position in the stack and, in response to this determination, selectively pass one or more external control signals (e.g., chip select and clock enable signals) to the decode circuit's associated functional circuit based on inter-die connection patterns. This “self-configuring” capability permits all die designated for a specified functionality (e.g., a memory module including four vertically aligned die) to be uniformly or consistently manufactured. This, in turn, can reduce the cost to manufacture stacked die components. | 2009-11-26 |
20090289702 | CURRENT GENERATOR - A current generator, including a chopper stabilization operational amplifier, a transistor, and an impedance unit is provided. The chopper stabilization operational amplifier includes a first input terminal, a second input terminal, and an output terminal. The transistor includes a gate coupled to the output terminal of the chopper stabilization operational amplifier, a first source/drain coupled to the first input terminal of the chopper stabilization operational amplifier, and a second source/drain serving as a current output terminal of the current generator. The impedance unit includes a first terminal coupled to the first source/drain of the transistor, and a second terminal coupled to a first voltage. | 2009-11-26 |
20090289703 | OFFSET CANCELLATION CIRCUIT AND DISPLAY DEVICE - In an offset cancellation circuit according to the present invention, a first capacitance is connected to a gate of a first transistor of a first active load, and a second capacitance is connected to a gate of a second transistor of the first active load. A switch sets a first time period and a second time period in connection states between the first and second transistors and the first and second capacitances. The connection states between the first and second transistors and the first and second capacitances are set so that a gate voltage of the first transistor is supplied to the first capacitance, and a gate voltage of the second transistor is supplied to the second capacitance during the first time period; and so that the first and second capacitances can retain charges, and the second time period becomes an output time period of the operational amplifier during the second time period. | 2009-11-26 |
20090289704 | AMPLIFICATION CIRCUIT FOR DRIVING A DIFFUSER - An amplification circuit for driving an audio signal diffuser that includes a generation circuit of a first pre-charging signal, the generation circuit including an amplifier provided with an input terminal for receiving the first pre-charging signal and provided with an output terminal for providing a second pre-charging signal as a function of the first pre-charging signal, and a decoupling capacitor of the amplifier from the diffuser, the capacitor connected to the output terminal for charging by the second pre-charging signal. | 2009-11-26 |
20090289705 | PULSE MODULATION TYPE ELECTRIC POWER AMPLIFIER - A pulse modulation type electric power amplifier includes a pulse modulator that receives as input a clock and an input signal, and converts the input signal to a pulse train, an output control circuit that receives as input the pulse train output by the pulse modulator, and controls output of the pulse train, an output circuit that performs switching according to the pulse train output by the output control circuit, a comparator that converts an output terminal voltage of the output circuit to a high or a low digital value, and a short-circuit determination circuit that determines whether an output short circuit has occurred based on a state of an output signal of the comparator, and outputs an output prohibition signal to the output control circuit when an output short circuit is detected. The output control circuit controls output of the pulse train when the output prohibition signal is input, so that the output circuit stops the switching operation. An output short-circuit protection circuit can thereby be configured simply with little circuitry, and is thus small, low power, and integrated easily. | 2009-11-26 |
20090289706 | Cube coordinate subspaces for nonlinear digital predistortion - A method or corresponding apparatus relates to a mathematical approach to efficiently search for and localize regions in a multi-dimensional signal space to enable inversion of power amplifier nonlinearities with a significant reduction in computational complexity and an efficient hardware implementation. To linearize a wideband power amplifier, an example embodiment of the present invention may represent a response of the wideband power amplifier using coefficients in a cube coefficient subspace, and search over the full multi-dimensional subspace according to an optimization criterion in order to identify a vector of cube coefficient subspace coefficients. The vector of coefficient subspace coefficients may be used to linearize the wide-band power amplifier. | 2009-11-26 |
20090289707 | DISTORTION COMPENSATION APPARATUS AND METHOD - The distortion compensation apparatus includes: a branching unit to branch a part of the output signal of an amplifier to a signal path to a distortion compensating unit; a switch to pass the output signal of the amplifier to the interference or branching unit; and a controlling unit to control an amount of the compensation of the distortion under a pass-permitted state in which the switch passes the output signal in response to a result of measurement of a signal transmitted through the signal path under a state where the switch is in an interruption state. | 2009-11-26 |
20090289708 | Predictive feedback compensation for PWM switching amplifiers - Methods and systems are disclosed for predictive feedback compensation (PFC) circuitry for suppressing distortions caused by supply voltage variations and output amplitude switching non-idealities in pulse width modulated (PWM) switching amplifiers by pre-compensating the PWM input based upon the supply voltage or output pulse amplitude. Output amplitude errors associated with previous PWM output signals are used to predict output amplitude errors expected for future PWM output signals. These predicted output amplitude errors are then used to adjust the pulse widths for the future PWM output signals. Traditional feedback techniques can also be used in conjunction with the predictive feedback compensation (PFC) circuitry. | 2009-11-26 |
20090289709 | Closed loop timing feedback for PWM switching amplifiers using predictive feedback compensation - Methods and systems are disclosed for closed loop feedback for pulse width modulated (PWM) switching amplifiers using predictive feedback compensation (PFC) for suppressing distortions caused by supply voltage variations and output amplitude switching non-idealities in pulse width modulated (PWM) switching amplifiers by pre-compensating the PWM input based upon the supply voltage or output pulse amplitude and using closed loop timing feedback. Output amplitude errors associated with previous PWM output signals are used to predict output amplitude errors expected for future PWM output signals. These predicted output amplitude errors are then used to adjust the pulse widths for the future PWM output signals. Timing differences between pulse widths for the uncompensated PWM input signal and the pre-compensated PWM signal are used as feedback to provide closed loop width adjustment. | 2009-11-26 |
20090289710 | AMPLIFIER PROVIDING POWER RECOVERY FROM A NARROW-BAND ANTENNA - A method, amplifier and system are provided for enabling power recovery from a narrow-band antenna when a signal having bandwidth exceeding that of the antenna is utilized. The amplifier provides amplification of a source signal to the antenna and recovery of power stored in the antenna during periods when the impedance of the antenna is negative to enable reverse current through the amplifier to a direct current (DC) power source. | 2009-11-26 |
20090289711 | TRANSCONDUCTANCE AMPLIFIER - An embodiment of the present invention has a differential pair including a first and second MOS transistors having their sources grounded; a third and fourth transistor with their source terminals connected to drain terminals of the first and second transistors, respectively; a voltage generating circuit for outputting tuning and common voltage so that the ratio between the common and tuning voltage is constant; and a differential pair input voltage generating circuit that receives the input and common voltage to output voltages Vip and Vin to gate terminals of the first and second transistors, respectively. The gate terminal of the fourth transistor is connected to the gate terminal of the third transistor, and the tuning voltage is input to the two terminals. | 2009-11-26 |
20090289712 | AMPLIFIER CIRCUIT - An amplifier circuit includes first and second transistor circuits, a current supply unit, and a current sink unit. The first transistor circuit is operatively responsive to a first input signal, and the second transistor circuit is operatively responsive to a second input signal. The current supply unit includes at least two symmetrically configured current mirrors connected to a source voltage, and provides a first current to the first transistor circuit and a second current to the second transistor circuit, where a magnitude of the first and second currents is the same. The current sink unit is responsive to an enable signal to sink the first and second currents supplied to the first and second transistor circuits to a ground voltage. | 2009-11-26 |
20090289713 | Differential amplifier circuit having offset adjustment circuit - A differential amplifier circuit includes an offset adjuster circuit for varying the active load to adjust the offset caused by the differential pair. The differential amplifier circuit includes fine adjustment cell sections including a plurality of transistors having the substantially same size, and shift cell sections including transistors, whose transistor size is larger than the transistors of the fine adjustment cell sections. | 2009-11-26 |
20090289714 | OPERATIONAL AMPLIFIER - The present invention relates generally to an operational amplifier. In one embodiment, the present invention is an operational amplifier including a transimpedance input stage, the transimpedance input stage including a first stage connected to a first resistor and a second resistor, and an output stage connected to the transimpedance input stage. | 2009-11-26 |
20090289715 | AMPLIFIER WITH IMPROVED LINEARIZATION - According to some embodiments, an amplifier may include a transconductance stage, a tail current source stage, and an adaptive biasing stage. The transconductance stage may be configured to receive an input voltage. The tail current source stage may be configured to provide current to the transconductance stage. The adaptive biasing stage may capacitively couple the transconductance stage to the tail current source stage. | 2009-11-26 |
20090289716 | Amplifier circuit having dynamically biased configuration - Methods and corresponding systems for amplifying an input signal include inputting first and second differential input signals into first and second circuit legs, respectively, wherein the first circuit leg includes a first transistor coupled in series with a first variable current source, and wherein the second circuit leg includes a second transistor coupled in series with a second variable current source. The first and second variable current sources are dynamically set to provide first and second bias currents in response to the first and second differential input signals, wherein the first bias current is set inversely proportional to the second bias current. The first and second bias currents are sunk in the first and second circuit legs, respectively. First and second differential output signals are output from the first and second circuit legs, respectively. | 2009-11-26 |
20090289717 | RADIO FREQUENCY (RF) POWER AMPLIFIER AND RF POWER AMPLIFIER APPARATUS - An RF power amplifier has a final-stage amplifier stage which generates an RF transmit output signal, a signal detector which detects an RF transmit output level, a first detector, a second detector and a control circuit. The final-stage amplifier stage includes a transistor and a load element and performs saturation type nonlinear amplification and non-saturation type linear amplification. The first detector and the control circuit maintain the RF transmit output signal approximately constant with respect to a variation in load at an antenna at the saturation type nonlinear amplification. The second detector and the control circuit reduce an increase in the output voltage of the final stage transistor with respect to an overload state of the antenna at the non-saturation type linear amplification. | 2009-11-26 |
20090289718 | INTEGRATED CIRCUIT ARRANGEMENT FOR GENERATING A DIGITAL VARIABLE GAIN CONTROL SIGNAL - The invention proposes an integrated circuit arrangement ( | 2009-11-26 |
20090289719 | Preserving Linearity of a RF Power Amplifier - A method and circuit for preserving linearity of a RF power amplifier, the power amplifier including a RF power output unit having a characteristic drive level and fed by a supply voltage, comprising measuring the output voltage of the RF power output unit; comparing the measured output voltage to at least one threshold voltage to produce a control signal; and adapting the drive level or the supply voltage of the RF power output unit by means of the control signal to operate the output unit below its saturation level. A method and circuit for stabilizing an antenna circuit comprising a RF power amplifier and a matching circuit by preserving linearity of a RF power amplifier, where the above power amplifier is used. | 2009-11-26 |
20090289720 | High-Efficiency Envelope Tracking Systems and Methods for Radio Frequency Power Amplifiers - High-efficiency envelope tracking (ET) methods and apparatus for dynamically controlling power supplied to radio frequency power amplifiers (RFPAs). An exemplary ET circuit includes a switch-mode converter coupled in parallel with a split-path linear regulator. The switch-mode converter is configured to generally track an input envelope signal Venv and supply the current needs of a load (e.g., an RFPA). The split-path linear regulator compensates for inaccurate envelope tracking by sourcing or sinking current to the load via a main current path. A current sense path connected in parallel with the main current path includes a current sense resistor used by a hysteresis comparator to control the switching of the switch-mode converter. The split-path linear regulator is configured so that current flowing in the current sense path is a lower, scaled version of the current flowing in the main current path. | 2009-11-26 |
20090289721 | CIRCUITS, PROCESSES, DEVICES AND SYSTEMS FOR FULL INTEGRATION OF RF FRONT END MODULE INCLUDING RF POWER AMPLIFIER - An electronic circuit comprising a transistor-based RF (radio frequency) power amplifier ( | 2009-11-26 |
20090289722 | Bonded Wafer Package Module - Bonded wafer packages having first and second wafers bonded together forming a matrix of sealed devices, at least one of the wafers having a plurality of passive devices formed thereon, including at least one BAW resonator within each of the sealed devices, the first wafer having conductor filled through-holes forming electrical connections between the passive devices and connections assessable from outside the sealed devices, the bonded wafers being diced to form individual sealed devices. The devices may be duplexers, interstage filters or other circuits such as VCOs and RF circuits. Various embodiments are disclosed. | 2009-11-26 |
20090289723 | PLL OSCILLATION CIRCUIT, POLAR TRANSMITTING CIRCUIT, AND COMMUNICATION DEVICE - Provided is a PLL oscillation circuit that can reduce the variability of modulation sensitivity of a VCO | 2009-11-26 |
20090289724 | FREQUENCY SYNTHESIZER AND METHOD FOR CONTROLLING SAME - A frequency synthesizer includes compensation variable capacitance diodes | 2009-11-26 |
20090289725 | Self-Biased Phase Locked Loop - The present invention discloses a self-bias PLL including a phase frequency detector, a charge pump, a loop filter, a voltage control oscillator, a divider and a bias current converter. A charging or discharging current output from the charge pump equals to a first control current. A resistor of the loop filter is controlled by a first control voltage a second control voltage which is adjusted according to the first control voltage and a second control current. The loop filter increases or decreases the first control voltage according to the charging or discharging current output from the charge pump. The voltage control oscillator generates a bias current and an oscillation voltage according to the first control voltage and increases or decreases an oscillation frequency according to the increase or decrease of the oscillation voltage. The circuit structure of the self-bias PLL is simple and the self-bias PLL has a low jitter. | 2009-11-26 |
20090289726 | Self-Biased Phase Locked Loop - A self-biased PLL includes a first charge pump and a second charge pump, an output terminal of the first charge pump is connected with a discharge-charge capacitor to output a control voltage, an output terminal of the second charge pump is connected with an output terminal of a bias generator for outputting a first bias voltage equal to the control voltage, wherein, a current output from the first charge pump is equal to a value obtained through dividing the production of a first constant with a bias current of a voltage control oscillator by a frequency division factor of a frequency divider; a current output from the second charge pump is equal to a value obtained through dividing the bias current of the voltage control oscillator by a second constant; and a multiple relation exists between an output resistance of the bias generator and an equivalent resistance of a differential buffer delay stage in the voltage control oscillator. | 2009-11-26 |
20090289727 | OSCILLATOR FOR GENERATING DIFFERENT OSCILLATIONS - An oscillator is provided that includes a first oscillation generating device for generating an oscillation in response to an excitation signal, whereby the first oscillation generating device has a first terminal and a second terminal; a second oscillation generating device for generating an oscillation in response to an excitation signal, whereby the second oscillation generating device has a third terminal and a fourth terminal; an excitation device, which is formed in a first mode to apply an excitation signal between the first and second terminal of the first oscillation generating device, and in the first mode to apply the excitation signal between the third terminal and the fourth terminal of the second oscillation generating device to obtain a first oscillation with a first characteristic value, and in a second mode to apply an excitation signal between the first terminal of the first oscillation generating device and the third terminal of the second oscillation generating device and in the second mode to apply the excitation signal between the second terminal of the first oscillation generating device and the fourth terminal of the second oscillation generating device to obtain a second oscillation with a second characteristic value. | 2009-11-26 |
20090289728 | Atomic frequency standard based on phase detection - This invention concerns the realization of a Coherent-Population-Trapping (CPT) atomic frequency standard by utilization of both the phase delay and the absorption of the light transmitted through an atomic vapor. The invented method enables the use of high modulation frequency and a fast lock of a low quality oscillator to the atomic hyperfine transition. | 2009-11-26 |
20090289729 | MODE SELECTIVE COUPLER FOR WHISPERING-GALLERY DIELECTRIC RESONATOR - A whispering gallery mode dielectric resonator includes a conductive enclosure comprising a top, a bottom and walls. The resonator also includes a dielectric element disposed in the enclosure and operative to support a desired resonant mode that is dependent on a shape and dimensions of the dielectric resonator; and a mode selective coupling structure disposed over the enclosure and configured to selectively couple electromagnetic energy of the desired mode and configured not to substantially couple electromagnetic energy of a spurious mode supported in a region between the enclosure and the dielectric element. | 2009-11-26 |
20090289730 | DIGITAL PHASE DETECTOR AND PHASE-LOCKED LOOP - A digital phase detector is provided that can be easily implemented in gate array or FPGA, to accurately quantize a phase difference of two clocks and convert to a digital value without using delay elements. The digital phase detector includes: a multiplier for, when two clocks have frequencies close to an integer ratio, receiving a first clock and multiplying by M/N; F/F for latching a second clock by an output clock of the multiplier; a differential circuit for differentiating an output of the F/F; a counter for receiving the output clock of the multiplier; a latch circuit for holding an output of the counter according to an output of the differential circuit; a first adder for adding an output of the latch circuit; a second adder for subtracting an output of the first adder from a fixed value; and an accumulator for sequentially integrating an output of the second adder. | 2009-11-26 |
20090289731 | RESONATOR CIRCUIT AND VOLTAGE-CONTROLLED OSCILLATOR USING THE SAME - A resonator circuit applied to a voltage-controlled oscillator comprises a switch and a wiring inductance. The switch is connected to a first node and a third node. The wiring inductance has multiple circles, and circles a center from an outermost node to an innermost node through an intermediate node. The outermost node is connected to the first node, the intermediate node is connected to the third node, and the innermost node is connected to the second node. | 2009-11-26 |
20090289732 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND FREQUENCY SYNTHESIZER - A semiconductor integrated circuit includes: a resonance circuit configured to determine an oscillation frequency; a first MOS transistor connected to the resonance circuit and configured to constitute an oscillation unit for delivering an oscillation output having the oscillation frequency; a second MOS transistor connected in parallel with the first MOS transistor; and a control unit configured to turn on and off the second MOS transistor according to the oscillation frequency, thereby enabling an equivalent gate width based on the first and second MOS transistors to be increased and decreased. Consequently, there is obtained an oscillation output having reduced phase noise, while an adequate oscillation margin is maintained. | 2009-11-26 |
20090289733 | METHOD OF FORMING AN OSCILLATOR CIRCUIT AND STRUCTURE THEREFOR - In one embodiment, an oscillator circuit is configured to oscillate at a base frequency. The oscillator is configured to receive a synchronization signal and restart a period of the oscillator signal responsively to the synchronization signal. | 2009-11-26 |
20090289734 | APPARATUS FOR SILENCING ELECTROMAGNETIC NOISE - Proposed is an apparatus for silencing electromagnetic noise, characterized by a plurality of centrally symmetrical ring-shaped through-via-hole crystalline units provided between a high voltage plane and a low voltage plane at a regular interval, thereby forming an omnidirectional noise suppression frequency band for reducing noise interference and electromagnetic radiation. In a first embodiment of the ring-shaped through-via-hole crystalline units, the through via holes are perpendicularly coupled between a metal plane and the low voltage plane. In a second embodiment of the ring-shaped through-via-hole crystalline units, the through via holes are perpendicularly coupled between two metal planes. Positioned at a regular interval, the through via holes enable provision of omnidirectional noise suppression frequency band, simplified design of a power plane, and reduction of production costs. | 2009-11-26 |
20090289735 | System and Method for Dynamic Impedance Tuning to Minimize Return Loss - A system for tuning an impedance at a node comprises a first component associated with a first impedance when the first component is operating and a second impedance when the first component is not operating. The system further comprises a second component coupled to the first component at a node. The second component is associated with a third impedance when the second component is operating and a fourth impedance when the second component is not operating. An impedance tuning circuit is coupled to the second component at the node and operable to tune an impedance at the node based at least in part upon a plurality of the first impedance, the second impedance, the third impedance, and the fourth impedance. | 2009-11-26 |
20090289736 | MAGNETIC SWITCHES FOR SPINWAVE TRANSMISSION - Spinwave transmission systems that include switching devices to direct the transmission of the spinwaves used for data transfer and processing. In one particular embodiment, a system for spinwave transmission has a first magnetic stripe configured for transmission of a spinwave and a second magnetic stripe for transmission of the spinwave, with a gap therebetween. The system includes a coupler that has a first orientation and a second orientation, where in the first orientation, no magnetic connection is made between the magnetic stripes, and in the second orientation, a connection is made between the magnetic stripes. The connection allows transmission of the spinwave from the first magnetic stripe to the second magnetic stripe. The first and second orientation may be the physical position of the coupler, moved by thermal, piezoelectric, or electrostatic forces, or, the first and second orientation may be a magnetic state of the coupler. | 2009-11-26 |