48th week of 2015 patent applcation highlights part 54 |
Patent application number | Title | Published |
20150340227 | METHOD FOR REPAIRING DAMAGES TO SIDEWALLS OF AN ULTRA-LOW DIELECTRIC CONSTANT FILM - A method for repairing damages to sidewalls of an ultra-low dielectric constant film is disclosed by the present invention comprises the following steps: depositing an ultra-low dielectric constant film on an semiconductor substrate; dry-etching the ultra-low dielectric constant film to form a sidewall structure thereof; performing wet cleaning by using a chemical agent containing an unsaturated hydrocarbon having —O—C(Re)x; and performing ultraviolet curing. The present invention can restore pores size and porosity of the ultra-low dielectric constant film, and to keep effective dielectric constant to a minimum. | 2015-11-26 |
20150340228 | GERMANIUM-CONTAINING SEMICONDUCTOR DEVICE AND METHOD OF FORMING - A germanium-containing semiconductor device and a method for forming a germanium-containing semiconductor device are described. The method includes providing a germanium-containing substrate, depositing a silicon-containing interface layer on the germanium-containing substrate, depositing an aluminum-containing diffusion barrier layer on the silicon-containing interface layer, and depositing a high-k layer on the aluminum-containing diffusion barrier layer. The germanium-containing semiconductor device includes a germanium-containing substrate, a silicon-containing interface layer on the germanium-containing substrate, an aluminum-containing diffusion barrier layer on the silicon-containing interface layer, and a high-k layer on the aluminum-containing diffusion barrier layer. | 2015-11-26 |
20150340229 | TRANSISTOR(S) WITH DIFFERENT SOURCE/DRAIN CHANNEL JUNCTION CHARACTERISTICS, AND METHODS OF FABRICATION - Field-effect transistors (FETs) and methods of fabricating field-effect transistors are provided, with one or both of a source cavity or a drain cavity having different channel junction characteristics. The methods include, for instance, recessing a semiconductor material to form a cavity adjacent to a channel region of the transistor, the recessing defining a bottom channel interface surface and a sidewall channel interface surface within the cavity; providing a protective liner over the sidewall channel interface surface, with the bottom channel interface surface being exposed within the cavity; processing the bottom channel interface surface to facilitate forming a first channel junction of the transistor; and removing the protective liner from over the sidewall channel interface surface, and subsequently processing the sidewall channel interface surface to form a second channel junction of the transistor, where the first and second channel junctions have different channel junction characteristics. | 2015-11-26 |
20150340230 | III NITRIDE EPITAXIAL SUBSTRATE AND METHOD OF PRODUCING THE SAME - A III nitride epitaxial substrate with reduced warp after the formation of a main laminate and improved vertical breakdown voltage, and a method of producing the same, a III nitride epitaxial substrate includes: a Si substrate; an initial layer in contact with the Si substrate; and a superlattice laminate formed on the initial layer, the superlattice laminate including first layers made of Al | 2015-11-26 |
20150340231 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A vertical super junction MOSFET and a lateral MOSFET are integrated on the same semiconductor substrate. The lateral MOSFET is electrically isolated from the vertical super junction MOSFET by an n-buried isolating layer and an n-diffused isolating layer. The lateral MOSFET is formed of a p-well region formed in an n | 2015-11-26 |
20150340232 | METHOD FOR FABRICATING A TEMPLATE OF CONDUCTORS ON A SUBSTRATE BY MEANS OF BLOCK COPOLYMERS - The method for fabricating patterns made from first material having: providing a substrate covered by a covering layer, forming a first mask by means of a self-assembled structure of block copolymers, the first mask having first patterns, making a second mask from the first mask, the second mask having a second series of patterns organized according to the first repetition pitch or an integral multiple of the first repetition pitch, the second series having less patterns than the first series, depositing and exposing a resin layer to form an intermediate mask on the first mask, the intermediate mask covering a part of the first patterns formed in the first mask and having second holes facing the first holes, etching the covering layer through the facing first and second holes to form third holes, filling the third holes with a first material to form the patterns made from first material. | 2015-11-26 |
20150340233 | Semiconductor Device Manufacturing Methods - Semiconductor device manufacturing methods are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes forming a first pattern in a hard mask using a first lithography process, and forming a second pattern in the hard mask using a second lithography process. A protective layer is formed over the hard mask. Portions of the hard mask and portions of the protective layer are altered using a self-aligned double patterning (SADP) method. | 2015-11-26 |
20150340234 | METHOD FOR PROCESSING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for processing a semiconductor device in accordance with various embodiments may include: depositing a first metallization material over a semiconductor body; performing a heating process so as to form at least one region in the semiconductor body including a eutectic of the first metallization material and material of the semiconductor body; and depositing a second metallization material over the semiconductor body so as to contact the semiconductor body via the at least one region in the semiconductor body. | 2015-11-26 |
20150340235 | DEPOSITING MATERIAL INTO HIGH ASPECT RATIO STRUCTURES - A method is provided, along with a corresponding apparatus, for filling a high aspect ratio hole without voids or for producing high aspect ratio structures without voids. A beam having a diameter smaller than the diameter of the hole is directed into the hole to induced deposition beginning in the center region of the hole bottom. After an elongated structure is formed in the hole by the beam-induced deposition, a beam can then be scanned in a pattern at least as large as the hole diameter to fill the remainder of the hole. The high aspect ratio hole can then be cross-sectioned using an ion beam for observation without creating artefacts. When electron-beam-induced deposition is used, the electrons preferably have a high energy to reach the bottom of the hole, and the beam has a low current, to reduce spurious deposition by beam tails. | 2015-11-26 |
20150340236 | METHOD FOR REDUCING DEFECTS IN POLYSILICON LAYERS - Present example embodiments relate generally to semiconductor devices and methods of fabricating a semiconductor device. The method comprises providing a substrate, forming an insulating layer over the substrate, and forming a conductive structure over the insulating layer. The conductive structure is formed by forming a first conductive layer, performing a degassing preparation process over a surface of the first conductive layer to substantially prevent a degassing of the first conductive layer from reaching a second conductive layer, and forming the second conductive layer over the first conductive layer. | 2015-11-26 |
20150340237 | Semiconductor Devices with Sharp Gate Edges and Methods to Fabricate Same - This application discloses semiconductor devices with sharp gate edges including 2D and 3D memory cells, High Electron Mobility Transistors and tri-gate transistors. Implementation of a gate with sharp edges may improve the read and write speed and reduce the program and erase voltages in memory cells. It may also improve the gate control over the channel in tri-gate transistors and HEMTs. Methods to fabricate such devices are also disclosed. | 2015-11-26 |
20150340238 | METHODS OF REMOVING FINS FOR FINFET SEMICONDUCTOR DEVICES - One illustrative method disclosed herein includes forming a plurality of initial fins in a substrate, wherein at least one of the initial fins is a to-be-removed fin, forming a material adjacent the initial fins, forming a fin removal masking layer above the plurality of initial fins, removing a desired portion of the at least one to-be-removed fin by: (a) performing a recess etching process on the material to remove a portion, but not all, of the material positioned adjacent the sidewalls of the at least one to-be-removed fin, (b) after performing the recess etching process, performing a fin recess etching process to remove a portion, but not all, of the at least one to be removed fin and (c) repeating steps (a) and (b) until the desired amount of the at least one to-be-removed fin is removed. | 2015-11-26 |
20150340239 | Method of Forming Multiple Patterning Spacer Structures - Disclosed herein is a method of forming a structure, comprising forming a mandrel layer over a substrate, masking the mandrel layer with a first mask and performing a first etch on the mandrel layer, the first etch forming a first opening exposing a first portion of the substrate. The mandrel layer is masked with a second mask and a second etch is performed on the mandrel layer. The second etch forms a second opening exposing a second portion of the substrate, and also forms a protective layer on the first portion of the substrate and in the first opening. | 2015-11-26 |
20150340240 | Self-Aligned Double Spacer Patterning Process - Embodiments of the present disclosure are a method of forming a semiconductor device and methods of patterning a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including forming a first hard mask layer over a semiconductor device layer, forming a set of mandrels over the first hard mask layer, and forming a first spacer layer over the set of mandrels and the first hard mask layer. The method further includes forming a second spacer layer over the first spacer layer, patterning the first spacer layer and the second spacer layer to form a mask pattern, and patterning the first hard mask layer using the mask pattern as a mask. | 2015-11-26 |
20150340241 | SILICON ETCHING LIQUID, SILICON ETCHING METHOD, AND MICROELECTROMECHANICAL ELEMENT - The present invention is able to provide: a silicon etching liquid which anisotropically dissolves single crystal silicon, and which is characterized by containing (1) potassium hydroxide or sodium hydroxide, (2) a hydroxyl amine and (3) a cyclic compound represented by general formula (I), which has a thiourea group and wherein N and N′ are linked; and a silicon etching method which uses this silicon etching liquid. | 2015-11-26 |
20150340242 | COMPOSITE SUBSTRATE OF GALLIUM NITRIDE AND METAL OXIDE - The present invention discloses a novel composite substrate which solves the problem associated with the quality of substrate surface. The composite substrate has at least two layers comprising the first layer composed of Ga | 2015-11-26 |
20150340243 | PLASMA ETCHING METHOD - In a plasma etching method, with respect to a substrate to be processed, which has a base layer, a silicon oxide film, and an etching mask formed in this order, the etching mask having an etching pattern formed thereon and being formed of polysilicon, a silicon-containing deposit is deposited on a surface of the etching mask using a plasma generated from a processing gas, while applying a negative direct current voltage to an upper electrode formed of silicon. Furthermore, in the plasma etching method, the silicon oxide film is etched using plasma generated from a first CF-based gas using, as a mask, the etching mask having the silicon-containing deposit deposited thereon. | 2015-11-26 |
20150340244 | SYSTEMS AND METHODS FOR ANNEALING SEMICONDUCTOR STRUCTURES - Systems and methods are provided for annealing a semiconductor structure. In one embodiment, the method includes providing an energy-converting structure proximate a semiconductor structure, the energy-converting structure comprising a material having a loss tangent larger than that of the semiconductor structure; providing a heat reflecting structure between the semiconductor structure and the energy-converting structure; and providing microwave radiation to the energy-converting structure and the semiconductor structure. The semiconductor structure may include at least one material selected from the group consisting of boron-doped silicon germanium, silicon phosphide, titanium, nickel, silicon nitride, silicon dioxide, silicon carbide, n-type doped silicon, and aluminum capped silicon carbide. The heat reflecting structure may include a material substantially transparent to microwave radiation and having substantial reflectivity with respect to infrared radiation. | 2015-11-26 |
20150340245 | HIGH-TEMPERATURE ISOTROPIC PLASMA ETCHING PROCESS TO PREVENT ELECTRICAL SHORTS - A method includes placing a device having a titanium nitride layer into a chamber. The device also has a mask that includes a photoresist material and an aluminum copper hardmask. The method also includes performing an ashing process on the mask using the chamber. The method further includes, after the ashing process, performing an etching process using the chamber to etch through portions of the titanium nitride layer. Performing the etching process includes flowing a gas mixture containing tetrafluoromethane (CF | 2015-11-26 |
20150340246 | METHOD OF FORMING PATTERNS AND METHOD OF MANUFACTURING INTEGRATED CIRCUIT DEVICE USING THE SAME - A method of forming patterns may use an organic reflection-preventing film including a polymer having an acid-liable group. A photoresist film is formed on the organic reflection-preventing film. A first area selected from the photoresist film is exposed to generate an acid in the first area. Hydrophilicity of a first surface of the organic reflection-preventing film facing the first area of the photoresist film may be increased. The photoresist film including the exposed first area is developed to remove a non-exposed area of the photoresist film. The organic reflection-preventing film and a target layer are anisotropically etched by using the first area of the photoresist film as an etch mask. | 2015-11-26 |
20150340247 | METHOD FOR FORMING A METAL CAP IN A SEMICONDUCTOR MEMORY DEVICE - Exemplary embodiments of the present invention are directed towards a method for fabricating a semiconductor memory device comprising selectively depositing a material to form a cap above a recessed cell structure in order to prevent degradation of components inside the cell structure in oxidative or corrosive environments. | 2015-11-26 |
20150340248 | FABRICATION METHOD OF PACKAGE HAVING ESD AND EMI PREVENTING FUNCTIONS - A package having ESD (electrostatic discharge) and EMI (electromagnetic interference) preventing functions includes: a substrate unit having a ground structure and an I/O structure disposed therein; at least a semiconductor component disposed on a surface of the substrate unit and electrically connected to the ground structure and the I/O structure; an encapsulant covering the surface of the substrate unit and the semiconductor component; and a metal layer disposed on exposed surfaces of the encapsulant and side surfaces of the substrate unit and electrically insulated from the ground structure, thereby protecting the semiconductor component against ESD and EMI so as to improve the product yield and reduce the risk of short circuits. | 2015-11-26 |
20150340249 | APPARATUS FOR MANUFACTURING SEMICONDUCTOR WAFER - An apparatus for manufacturing a semiconductor wafer comprises: a wafer chuck which holds the rear surface of a wafer having a via hole; a cap which is installed in such a way as to move up and down above the wafer chuck and has a sealed lip which forms a liquid reservoir by sealing the outer peripheral portion of the upper surface of the wafer; and a nozzle which injects and recovers processing liquids to and from a reaction chamber. | 2015-11-26 |
20150340250 | WET ETCHING NOZZLE, SEMICONDUCTOR MANUFACTURING EQUIPMENT INCLUDING THE SAME, AND WET ETCHING METHOD USING THE SAME - A wet etching nozzle, semiconductor manufacturing equipment including the same, and a wet etching method using the same are provided. The wet etching nozzle includes a first supply pipe configured to supply a first solution, for etching a partial area of an etched layer, to a substrate including the etched layer; a first suction pipe configured to suck the first solution from the substrate; a second supply pipe configured to supply a second solution for cleaning the partial area of the etched layer; and a second suction pipe configured to suck the second solution from the substrate. | 2015-11-26 |
20150340251 | SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS - A substrate processing method is implemented in a substrate processing apparatus including a substrate holding and rotating unit having a spin base rotatable about a predetermined vertical axis, and a processing cup surrounding the substrate holding and rotating unit and arranged to receive processing liquid splattering from the substrate rotated by the substrate holding and rotating unit, the substrate processing method including a substrate rotating step of rotating the spin base to rotate the substrate about the vertical axis at a predetermined liquid processing speed and, in parallel with the substrate rotating step, a processing liquid supplying step of supplying processing liquid onto the lower surface of the substrate at a predetermined first flow rate and supplying processing liquid onto the upper surface of the substrate at a second flow rate that is higher than the first flow rate. | 2015-11-26 |
20150340252 | RESIST REMOVING APPARATUS AND METHOD FOR REMOVING RESIST - A nozzle as a whole is formed into a cylindrical structure having a supply surface with a supply opening as a bottom surface, and the supply surface is narrower than a surface of a wafer main portion of a sectional recession wafer and has a shape that fits in the surface of the wafer main portion. Therefore, in a state where the center of the wafer main portion and the center of the supply surface coincide with each other in plan view, the nozzle is brought close to the surface of the wafer main portion of the sectional recession wafer, whereby the supply surface of the nozzle can be disposed in a close distance from the surface of the wafer main portion in a wafer inner space. | 2015-11-26 |
20150340253 | SEMICONDUCTOR PROCESSING ASSEMBLY AND FACILITY - A semiconductor processing assembly, comprising at least one semiconductor processing system and a substrate cassette stocker with stocker positions that are at least partially disposed within a footprint of the at least one semiconductor processing system. The semiconductor processing system also includes a local substrate cassette transport system for exchanging substrate cassettes with a global cassette transport system of a processing facility. The local substrate cassette transport system transports cassettes between its substrate cassette exchange station and the stocker positions. Also disclosed is a semiconductor processing facility, having a clean room bay area and a clean room chase area, disposed adjacent to the clean room bay area and separated therefrom by a clean room bounding wall. The facility also includes a semiconductor processing assembly having at least two semiconductor processing systems and a local substrate cassette transport system for transporting substrate cassettes between the semiconductor processing systems. | 2015-11-26 |
20150340254 | WAFER HOLDER AND DEPOSITION APPARATUS - According to an embodiment, a wafer holder includes a heat receiving portion, a heating portion, and a contact making portion. The heat receiving portion receives heat from a heat source. The heating portion heats a wafer using the heat received by the heat receiving portion. The contact making portion makes contact with an outer edge of the wafer. A heat-transfer suppressing portion is provided at least either for the contact making portion, or in between the heat receiving portion and the contact making portion, or in between the heating portion and the contact making portion. | 2015-11-26 |
20150340255 | ELECTROSTATIC CHUCK WITH INDEPENDENT ZONE COOLING AND REDUCED CROSSTALK - An electrostatic chuck is described with independent zone cooling that leads to reduced crosstalk. In one example, the chuck includes a puck to carry a substrate for fabrication processes, and a cooling plate fastened to and thermally coupled to the ceramic puck, the cooling plate having a plurality of different independent cooling channels to carry a heat transfer fluid to transfer heat from the cooling plate. | 2015-11-26 |
20150340256 | Thermal Treatment System and Method of Performing Thermal Treatment and Method of Manufacturing CIGS Solar Cell Using the Same - Disclosed is a thermal treatment system which enables a uniform temperature distribution and a uniform concentration distribution of reaction gas in an entire reaction space for a thermal treatment process, a method of performing a thermal treatment, and a method of manufacturing a CIGS solar cell using the same, wherein the thermal treatment system may include a reaction chamber with a reaction space, an external chamber surrounding the reaction chamber, a door chamber provided to open or close the reaction space of the reaction chamber, and an air flow adjusting apparatus for circulation of an flow inside the reaction space of the reaction chamber, wherein the air flow adjusting apparatus includes a driving axis, an air flow suction unit connected with the driving axis, and an air flow discharging unit connected with the air flow suction unit. | 2015-11-26 |
20150340257 | LIGHT PIPE WINDOW STRUCTURE FOR LOW PRESSURE THERMAL PROCESSES - Embodiments disclosed herein relate to a light pipe structure for thermal processing of semiconductor substrates. In one embodiment, a light pipe window structure for use in a thermal process chamber includes a transparent plate, and a plurality of light pipe structures formed in a transparent material that is coupled to the transparent plate, each of the plurality of light pipe structures comprising a reflective surface and having a longitudinal axis disposed in a substantially perpendicular relation to a plane of the transparent plate. | 2015-11-26 |
20150340258 | SUBSTRATE TRANSPORT APPARATUS - A substrate transport apparatus for detecting with high accuracy rubbing between a substrate held in a substrate holding tool, and a support which transports a substrate. The substrate transport apparatus includes: a stage for placing thereon the substrate holding tool; a substrate transport mechanism including the support for the substrate, and a back-and-forth movement mechanism for moving the support, the mechanism configured to transfer a substrate to/from the substrate holding tool; a lifting mechanism for moving the support up and down with respect to the substrate holding tool; a sound amplifying section for amplifying a contact sound generated by contact between a substrate held in the substrate holding tool and the support; and a detection section for detecting rubbing between a substrate and the support based on a detection signal from a vibration sensor which detects a solid-borne sound, propagating through the substrate holding tool, and outputs the detection signal. | 2015-11-26 |
20150340259 | SUBSTRATE PROCESSING APPARATUS, COVER OPENING AND CLOSING MECHANISM,SHIELDING MECHANISM, AND METHOD FOR PURGING CONTAINER - Provided is a substrate processing apparatus that can suppress the amount of inert gas and dry gas used and also can prevent reductions in throughput. A substrate processing apparatus is provided with: a loader module; an opener that removes a cover from a FOUP having a main body, an opening and the cover, to communicate the inside of the FOUP with the inside of the loader module through the opening; an N | 2015-11-26 |
20150340260 | WAFER TRANSPORT SYSTEM AND METHOD FOR OPERATING THE SAME - The present invention relates to a wafer transport system and a method of operating the same. The wafer transport system comprises at least one semiconductor apparatus, a track, a transfer device, a positioning device, a carrier and a cleaning device. The wafer transport system transports wafers along the at least one semiconductor apparatus via the carrier riding on the track. The transfer device transfers the wafers from the carrier to the at least one semiconductor apparatus. The positioning device identifies and controls the position of the carrier on the track. The cleaning device maintains the cleanliness of the wafers. The present invention provides advantages for improving the yield rate of a wafer, shortening the fabrication time of a wafer, and offering the flexibility and the extendibility to a wafer transport system. | 2015-11-26 |
20150340261 | ELECTROSTATIC CHUCK AND SEMICONDUCTOR-LIQUID CRYSTAL MANUFACTURING APPARATUS - An electrostatic chuck includes a base plate including a penetration hole, a placing table arranged on the base plate, and including an electrode at a position corresponding to the penetration hole, a first cylindrical insulating component arranged on an upper side inside the penetration hole of the base plate, a second cylindrical insulating component arranged on the first cylindrical insulating component, a third cylindrical insulating component arranged under the first cylindrical insulating component, and having an inner diameter smaller than an inner diameter of the first cylindrical insulating component, a connector arranged in the penetration hole, a cylindrical member included in the connector, and including an elastic body in an inner part, and a power feeding terminal included in the connector, and connected to the elastic body. The power feeding terminal touches the electrode of the placing table. | 2015-11-26 |
20150340262 | MASS TRANSFER SYSTEM - Micro pick up arrays for transferring micro devices from a carrier substrate are disclosed. In an embodiment, a micro pick up array includes a compliant contact for delivering an operating voltage from a voltage source to an array of electrostatic transfer heads. In an embodiment, the compliant contact is moveable relative to a base substrate of the micro pick up array. | 2015-11-26 |
20150340263 | SUBSTRATE TREATING APPARATUS AND SUBSTRATE TREATING METHOD - An embodiment includes a substrate treating apparatus comprising: a tape supply member configured to supply a tape to be attached to a substrate; a tape collection member configured to collect a surplus tape that remains after the tape is attached to the substrate; a support member disposed between the tape supply member and the tape collection member and configured to support the substrate while the tape is attached to the substrate; and a temperature adjustment member configured to adjust a temperature of the tape that is supplied from the tape supply member to the support member. | 2015-11-26 |
20150340264 | METHOD OF APPLICATION OF A CARRIER TO A DEVICE WAFER - A device wafer having a main surface including an edge region and a carrier having a further main surface including an annular surface region corresponding to the edge region of the device wafer are provided. An adhesive is applied in the edge region and/or in the annular surface region, but not on the remaining areas of the main surfaces. The device wafer is fastened to the carrier by the adhesive. The main surface and the further main surface are brought into contact with one another when the device wafer is fastened to the carrier, while the main surface and the further main surface are fastened to one another only in the edge region. The device wafer is removed from the carrier after further process steps, which may include the formation of through-wafer vias in the device wafer. | 2015-11-26 |
20150340265 | Use of Vacuum Chucks to Hold a Wafer or Wafer Sub-Stack - Techniques are described for holding a wafer or wafer sub-stack to facilitate further processing of the wafer of sub-stack. In some implementations, a wafer or wafer sub-stack is held by a vacuum chuck in a manner that can help reduce bending of the wafer or wafer sub-stack. | 2015-11-26 |
20150340266 | THERMAL PROCESSING SUSCEPTOR - In one embodiment, a susceptor for thermal processing is provided. The susceptor includes an outer rim surrounding and coupled to an inner dish, the outer rim having an inner edge and an outer edge. The susceptor further includes one or more structures for reducing a contacting surface area between a substrate and the susceptor when the substrate is supported by the susceptor. At least one of the one or more structures is coupled to the inner dish proximate the inner edge of the outer rim. | 2015-11-26 |
20150340267 | Deep Trench Isolation Structure and Method for Improved Product Yield - A semiconductor structure having a deep trench isolation structure for improved product yield is disclosed. The semiconductor structure includes a deep trench having a filler material therein. The deep trench is adjacent to field oxide regions in a semiconductor substrate. A high density plasma (HDP) oxide layer, substantially free of thermal oxide, is situated over the filler material in the deep trench. The HDP oxide layer has a substantially co-planar top surface with at least one of the field oxide regions. According to the present disclosure, formation of nodules in the deep trench is prevented. | 2015-11-26 |
20150340268 | Silicon on Nothing Devices and Methods of Formation Thereof - In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a first cavity within a substrate. The first cavity is disposed under a portion of the substrate. The method further includes forming a first pillar within the first cavity to support the portion of the substrate. | 2015-11-26 |
20150340269 | METHOD OF PLANARIZING RECESSES FILLED WITH COPPER - A structure includes a substrate having an upper surface provided with recesses and coated with a continuous barrier layer topped with a continuous copper layer filling at least the recesses. The structure is planarized by: a) chemical-mechanical polishing of the copper, such a polishing being selective with respect to the barrier layer so that copper remains in the recesses and is set back with respect to the upper surface of the substrate; b) depositing on the exposed surface of the structure a material covering at least the copper at the level of the recesses; and c) chemical-mechanical planarizing of the structure to expose the substrate with the copper remaining buried under the material. Two such structures are then direct bonded to each other with opposite areas of material having a same topology. | 2015-11-26 |
20150340270 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - Provided is a semiconductor device that suppresses the occurrence of defects due to photocorrosion. A method for manufacturing the semiconductor device includes the steps of: forming an insulating layer with a concave portion over a substrate; forming a conductive film over the insulating film and the inside of the concave portion; polishing and removing the conductive film positioned over the insulating layer; and cleaning the insulating layer in a light-shielded state. Between the step of polishing and the step of cleaning, or after the step of cleaning, the substrate SUB is moved by detecting the presence or absence of the substrate SUB in the light-shielded state using an infrared sensor. | 2015-11-26 |
20150340271 | GAN POWER DEVICE WITH SOLDERABLE BACK METAL - A method for fabricating a vertical gallium nitride (GaN) power device can include providing a GaN substrate with a top surface and a bottom surface, forming a device layer coupled to the top surface of the GaN substrate, and forming a metal contact on a top surface of the vertical GaN power device. The method can further include forming a backside metal by forming an adhesion layer coupled to the bottom surface of the GaN substrate, forming a diffusion barrier coupled to the adhesion layer, and forming a protection layer coupled to the diffusion barrier. The vertical GaN power device can be configured to conduct electricity between the metal contact and the backside metal. | 2015-11-26 |
20150340272 | STI REGION FOR SMALL FIN PITCH IN FINFET DEVICES - The present invention relates generally to semiconductor devices, and particularly to fabricating a shallow trench isolation (STI) region in fin field effect transistors (FinFETs) having a small fin pitch. According to one embodiment, a method of using selective etching techniques to remove a single fin to form a fin trench and to form an isolation trench having a width approximately equal to a width of the single fin below the removed fin is disclosed. The fin trench and the isolation trench may be filled with isolation material to form an isolation region. | 2015-11-26 |
20150340273 | SILICON WAVEGUIDE ON BULK SILICON SUBSTRATE AND METHODS OF FORMING - Various methods include: forming an optical waveguide in a bulk silicon layer, the optical waveguide including a set of shallow trench isolation (STI) regions overlying a silicon substrate region; ion implanting the silicon substrate to amorphize a portion of the silicon substrate; forming a set of trenches through the STI regions and into the underlying silicon substrate region; undercut etching the silicon substrate region under the STI regions through the set of trenches to form a set of cavities, wherein the at least partially amorphized portion of the silicon substrate etches at a rate less than an etch rate of the silicon substrate; and sealing the set of cavities. | 2015-11-26 |
20150340274 | METHODS FOR PRODUCING INTEGRATED CIRCUITS WITH AN INSULTATING LAYER - Methods for producing integrated circuits are provided. A method for producing an integrated circuit includes forming an insulating layer overlying a substrate, where the insulating layer is formed within a trench. The insulating layer is infused with water, and the insulating layer is annealed while being irradiated. The insulating layer is annealed at a dry anneal temperature of about 800 degrees centigrade or less. | 2015-11-26 |
20150340275 | METHOD OF PRODUCING A MICROELECTRONIC DEVICE IN A MONOCRYSTALLINE SEMICONDUCTOR SUBSTRATE WITH ISOLATION TRENCHES PARTIALLY FORMED UNDER AN ACTIVE REGION - A method of producing a microelectronic device in a substrate including a first semiconductor layer, a dielectric layer and a second monocrystalline semiconductor layer, the method including: etching a trench through the first semiconductor layer and the dielectric layer, and such that the trench delimits one active region of the microelectronic device; chemical vapor etching the second semiconductor layer, at a level of a bottom wall of the trench, according to at least two crystalline planes of the second semiconductor layer such that an etched part of the second semiconductor layer extends under a part of the active region; filling the trench and the etched part of the second semiconductor layer with a dielectric material. | 2015-11-26 |
20150340276 | METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE - A method of filling a dielectric trench includes forming two adjacent conductors on a substrate, forming a dielectric layer over a surface of the conductors and the substrate, removing a portion of the dielectric layer, treating a top surface of the dielectric layer with phosphorous plasma, and repeating the forming the dielectric layer, the removing the portion of the dielectric layer, and the treating the top surface of the dielectric layer in a multi cycle fashion. A narrowest width of the dielectric trench between the two adjacent conductors is smaller than about 30 nm. | 2015-11-26 |
20150340277 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device in accordance with various embodiments may include: forming an opening in a first region of a semiconductor substrate, the opening having at least one sidewall and a bottom; implanting dopant atoms into the at least one sidewall and the bottom of the opening; configuring at least a portion of a second region of the semiconductor substrate laterally adjacent to the first region as at least one of an amorphous or polycrystalline region; and forming an interconnect over at least one of the first and second regions of the semiconductor substrate. | 2015-11-26 |
20150340278 | METHOD FOR MANUFACTURING A STRUCTURE BY DIRECT BONDING - The method includes the steps of: a) providing first and second layers, each including a bonding surface, at least one of said layers including recesses and the bonding surface of one of the two layers being formed at least partially of a silicon oxide film; b) bringing the bonding surfaces into contact with one another, such as to create a direct bonding interface; c) filling at least one recess with a fluid including water molecules; and d) applying a thermal budget such as to generate bond annealing. Further relating to a structure including a direct bonding interface between two bonding surfaces of two layers, the bonding surface of at least one of the layers being formed at least partially of a silicon oxide film, and the direct bonding interface includes recesses filled with a fluid including water molecules. | 2015-11-26 |
20150340279 | METHOD FOR MANUFACTURING SOI WAFER AND SOI WAFER - The present invention provides a method for manufacturing SOI wafer, wherein, after plasma treatment has been performed on at least one surface of a bonding interface of the bond wafer and a bonding interface of the base wafer, bonding is performed through the oxide film, and the bond wafer is delaminated at the ion implanted layer by the delamination heat treatment comprising a first heat treatment at 250° C. or less for 2 hours or more and a second heat treatment at 400° C. to 450° C. for 30 minutes or more. Thereby, the method of manufacturing the SOI wafer that is small in SOI layer film thickness range, is small in surface roughness of the SOI layer surface, is smooth in shape of a terrace part and has no defects such as voids, blisters and so forth in the SOI layer can be provided. | 2015-11-26 |
20150340280 | THROUGH SILICON VIA (TSV) PROCESS - A through silicon via structure is located in a recess of a substrate. The through silicon via structure includes a barrier layer, a buffer layer and a conductive layer. The barrier layer covers a surface of the recess. The buffer layer covers the barrier layer. The conductive layer is located on the buffer layer and fills the recess, wherein the contact surface between the conductive layer and the buffer layer is smoother than the contact surface between the buffer layer and the barrier layer. Moreover, a through silicon via process forming said through silicon via structure is also provided. | 2015-11-26 |
20150340281 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a first conductive structure on a substrate, forming an insulation layer on a sidewall of the first conductive structure, forming a second conductive structure a distance apart from the first conductive structure with the insulation layer therebetween, first removing a portion of the insulation layer by performing a first dry cleaning operation, second removing a reactant product used in the first dry cleaning operation or a first byproduct generated as a result of the first dry cleaning operation by performing a first purge operation, and third removing at least a portion of the remaining insulation layer by performing a second dry cleaning operation to form an air gap between the first and second conductive structures. | 2015-11-26 |
20150340282 | CONDUCTIVE INTERCONNECT STRUCTURES INCORPORATING NEGATIVE THERMAL EXPANSION MATERIALS AND ASSOCIATED SYSTMES, DEVICES, AND METHODS - Semiconductor devices having interconnects incorporating negative expansion (NTE) materials are disclosed herein. In one embodiment a semiconductor device includes a substrate having an opening that extends at least partially through the substrate. A conductive material having a positive coefficient of thermal expansion (CTE) partially fills the opening. A negative thermal expansion (NTE) having a negative CTE also partially fills the opening. In one embodiment, the conductive material includes copper and the NTE material includes zirconium tungstate. | 2015-11-26 |
20150340283 | INTERCONNECT STRUCTURE AND METHODS OF MAKING SAME - A method of manufacturing a semiconductor interconnect structure may include forming a low-k dielectric layer over a substrate and forming an opening in the low-k dielectric layer, where the opening exposes a portion of the substrate. The method may also include filling the opening with a copper alloy and forming a copper-containing layer over the copper alloy and the low-k dielectric layer. An etch rate of the copper-containing layer may be greater than an etch rate of the copper alloy. The method may additionally include patterning the copper-containing layer to form interconnect features over the low-k dielectric layer and the copper alloy. | 2015-11-26 |
20150340284 | METHODS FOR FABRICATING SEMICONDUCTOR DEVICES - The present inventive concepts provide methods for fabricating semiconductor devices. The method may comprise providing a substrate, stacking a conductive layer and a lower mask layer on the substrate, forming a plurality of hardmask layers each having an island shape on the lower mask layer, forming a plurality of upper mask patterns having island shapes arranged to expose portions of the lower mask layer, etching the exposed portions of the lower mask layer to expose portions of the conductive layer, and etching the exposed portions of the conductive layer to form a plurality of contact holes each exposing a portion of the substrate. | 2015-11-26 |
20150340285 | 3D IC METHOD AND DEVICE - A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface. Alternatively, first and/or second contact structures are not exposed at bonding, and a via is etched and filled after bonding to electrically interconnect first and second contact structures and provide electrical access to interconnected first and second contact structure to a surface. Also, a device may be formed in a first substrate, the device being disposed in a device region of the first substrate and having a first contact structure. A via may be etched, or etched and filled, through the device region and into the first substrate before bonding and the first substrate thinned to expose the via, or filled via after bonding. | 2015-11-26 |
20150340286 | Preventing Over-Polishing of Poly Gate in Metal-Gate CMP - A method for manufacturing a semiconductor device includes providing a substrate containing a front-end device that includes a first gate in a first-type transistor region and a second gate in a second-type transistor region, forming an interlayer dielectric layer on the semiconductor substrate, and planarizing the interlayer dielectric layer to expose the surface of the first and second gates. The method also includes forming a hard mask layer on the second gate, removing the first gate using the hard mask layer as a mask to form a trench, forming sequentially a work function metal layer and a metal gate layer in the trench, and removing a portion of the first work function metal layer and a portion of the metal gate layer that are higher than the interlayer dielectric layer to form a metal gate. | 2015-11-26 |
20150340287 | SEMICONDUCTOR DEVICE INCLUDING A HIGH VOLTAGE P-CHANNEL TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device in which a reliable high voltage p-channel transistor is formed without an increase in cost and the number of manufacturing steps. The transistor includes: a semiconductor substrate having a main surface and a p-type region therein; a p-type well region located over the p-type region and in the main surface, having a first p-type impurity region to obtain a drain electrode; an n-type well region adjoining the p-type well region along the main surface and having a second p-type impurity region to obtain a source electrode; a gate electrode between the first and second p-type impurity regions along the main surface; and a p-type buried channel overlying the n-type well region and extending along the main surface. The border between the n-type and p-type well regions is nearer to the first p-type impurity region than the gate electrode end near to the first p-type impurity region. | 2015-11-26 |
20150340288 | FINFET WITH DIELECTRIC ISOLATION BY SILICON-ON-NOTHING AND METHOD OF FABRICATION - An improved finFET and method of fabrication using a silicon-on-nothing process flow is disclosed. Nitride spacers protect the fin sides during formation of cavities underneath the fins for the silicon-on-nothing (SON) process. A flowable oxide fills the cavities to form an insulating dielectric layer under the fins. | 2015-11-26 |
20150340289 | METHODS OF FABRICATING SEMICONDUCTOR FIN STRUCTURES - Methods of fabricating one or more semiconductor fin structures are provided which include: providing a substrate structure including a first semiconductor material; providing a fin stack(s) above the substrate structure, the fin stack(s) including at least one semiconductor layer, which includes a second semiconductor material; depositing a conformal protective film over the fin stack(s) and the substrate structure; and etching the substrate structure using, at least in part, the fin stack(s) as a mask to facilitate defining the one or more semiconductor fin structures. The conformal protective film protects sidewalls of the at least one semiconductor layer of the fin stack(s) from etching during etching of the substrate structure. As one example, the first semiconductor material may be or include silicon, the second semiconductor material may be or include silicon germanium, and the conformal protective film may be, in one example, silicon nitride. | 2015-11-26 |
20150340290 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same. An example method may include: forming a first semiconductor layer and a second semiconductor layer sequentially on a substrate; patterning the second and first semiconductor layers to form an initial fin; forming an isolation layer on the substrate, wherein the isolation layer exposes partially the first semiconductor layer, and thus defines a fin above the isolation layer; and forming a gate stack intersecting the fin on the isolation layer, wherein the first semiconductor layer comprises a compound semiconductor, with at least one component whose concentration has a graded distribution in a stack direction of the first and second semiconductor layers. | 2015-11-26 |
20150340291 | COMPLEX CIRCUITS UTILIZING FIN STRUCTURES - A method of forming a semiconductor structure includes forming a multilayer lattice matched structure having an unstrained layer, a first strained layer, and a second strained layer formed between the unstrained and the first strained layer. A first opening in the multilayer structure is etched and a second strained fill material having a same material as the second strained layer is deposited. A second opening in the multilayer structure is etched and an unstrained fill material having a same material as the unstrained layer is deposited. A first strained fill material having a same material as the first strained layer is then deposited between the unstrained fill and the second strained fill. A second strained fin is formed from the deposited second strained fill material, a first strained fin is formed from the deposited first strained fill material, and an unstrained fin is formed from the deposited unstrained fill material. | 2015-11-26 |
20150340292 | PATTERNING PROCESS FOR FIN IMPLANTATION - After forming an organic planarization layer (OPL) atop a substrate which includes a plurality of semiconductor fins and a gate structure thereon, the OPL is recessed such that uppermost surfaces of remaining portions of the OPL are located below an uppermost surface of the gate structure but above top surfaces of the semiconductor fins. The remaining portions of the OPL are patterned to expose semiconductor fins in a pFinFET region for subsequent ion implantation. Portions of the OPL that remain on the semiconductor fins in an nFinFET region act as an implantation mask to shield the semiconductor fins in the nFinFET region from the ion implantation. | 2015-11-26 |
20150340293 | Method and Apparatus For Enhancing Channel Strain - Various methods include providing a substrate, forming a projection extending upwardly from the substrate, the projection having a channel region therein, and forming a gate structure engaging the projection adjacent to the channel region, the gate structure having spaced first and second conductive layers and a strain-inducing conductive layer disposed between the first and second conductive layers. The method also includes forming epitaxial growths on portions of the projection at each side of the gate structure, the epitaxial growths imparting a first strain to the channel region, and imparting a second strain to the channel region, including performing at least one stress memorization technique on the gate structure such that the strain-inducing conductive layer imparts the second strain to the channel region, and removing the capping layer, wherein the imparting the second strain is carried out in a manner that imparts tensile strain to the channel region. | 2015-11-26 |
20150340294 | STRUCTURE AND METHOD FOR EFFECTIVE DEVICE WIDTH ADJUSTMENT IN FINFET DEVICES USING GATE WORKFUNCTION SHIFT - Embodiments of the present invention provide methods and structures by which the inherent discretization of effective width can be relaxed through introduction of a fractional effective device width, thereby allowing greater flexibility for design applications, such as SRAM design optimization. A portion of some fins are clad with a capping layer or workfunction material to change the threshold voltage (Vt) for a part of the fin, rendering that part of the fin electrically inactive, which changes the effective device width (Weff). Other fins are unclad, and provide maximum area of constant threshold voltage. In this way, the effective device width of some devices is reduced. Therefore, the effective device width is controllable by controlling the level of cladding of the fin. | 2015-11-26 |
20150340295 | Space and Cost Efficient Incorporation of Specialized Input-Output Pins on Integrated Circuit Substrates - In some embodiments an Integrated Circuit package includes a plurality of system functional pins, at least one system functional pin depopulation zone, and at least one non-system functional pin located in the at least one functional pin depopulation zone. Other embodiments are described and claimed. | 2015-11-26 |
20150340296 | PLANAR METROLOGY PAD ADJACENT A SET OF FINS OF A FIN FIELD EFFECT TRANSISTOR DEVICE - Approaches for providing a substrate having a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. Specifically, the FinFET device comprises a finned substrate, and a planar metrology pad formed on the substrate adjacent the fins in a metrology measurement area of the FinFET device. Processing steps include forming a first hardmask over the substrate, forming a photoresist over a portion of the first hardmask in the metrology measurement area of the FinFET device, removing the first hardmask in an area adjacent the metrology measurement area remaining exposed following formation of the photoresist, patterning a set of openings in the substrate to form the set of fins in the FinFET device in the area adjacent the metrology measurement area, depositing an oxide layer over the FinFET device, and planarizing the FinFET device to form the planar metrology pad in the metrology measurement area. | 2015-11-26 |
20150340297 | POWER SEMICONDUCTOR MODULE - A power semiconductor module is equipped with: a frame made of an insulator; a first electrode plate made of a metal and fixed to a bottom opening of the frame; semiconductor chips electrically and physically connected to the first electrode plate; a multilayer substrate fixed to a principal surface of the first electrode plate; wiring members that electrically connect front surface electrodes of the semiconductor chips and a circuit plate of the multilayer substrate; a second electrode plate fixed to a top opening of the frame; and a metal block that has a first surface having a projected portion and a second surface disposed on a side opposite to the first surface and that is tapered from the first surface to the second surface, the projected portion being electrically and physically connected to the circuit plate of the multilayer substrate and the second surface being electrically and physically connected to the second electrode plate. | 2015-11-26 |
20150340298 | CERAMIC COMBO LID WITH SELECTIVE AND EDGE METALLIZATIONS - A frame lid for use with a semiconductor package is disclosed. First, a mask is applied to a top surface of the lid and over a central area of the top surface to define a peripheral area. Next, a seal ring is formed by metallizing the peripheral area and the sidewall of the plate. The mask can then be removed obtain the frame lid. Next, a solder preform can be attached to the seal ring. This reduces pullback and shrinkage of the metallized layer, while lowering the manufacturing cost and process times. | 2015-11-26 |
20150340299 | CURABLE RESIN COMPOSITION, AND CURED PRODUCT OF SAME - Provided is a curable resin composition capable of forming a cured product that has excellent heat resistance, transparency, and flexibility and, in particular, offers superior reflow resistance and barrier properties to a corrosive gas. | 2015-11-26 |
20150340300 | SEMICONDUCTOR DEVICE, MANUFACTURING APPARATUS FOR SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR MODULE - A semiconductor device includes: a semiconductor element; a frame which has a first surface, holds the semiconductor element on the first surface, and is electrically connected with the semiconductor element; and a seal which has electrical insulation properties and seals the semiconductor element and the frame, wherein a through-hole is formed in the seal, the through-hole has a hole axis which extends in a direction intersecting with the first surface, and an inner peripheral end surface of the seal exposed inside the through-hole is inclined with respect to the hole axis. | 2015-11-26 |
20150340301 | SUBSTRATELESS POWER DEVICE PACKAGES - A vertical conductive power semiconductor device may include a substrate with a top metal layer located on a top surface of the substrate, solder bumps deposited on top of the top metal layer, and wafer level molding surrounding the solder bumps and leaving the solder bumps at least partly exposed. | 2015-11-26 |
20150340302 | Passivation Structure of Fin Field Effect Transistor - A FinFET comprises a substrate comprising a major surface; a fin structure protruding from the major surface comprising a lower fin portion comprising a first semiconductor material having a first lattice constant; an upper fin portion comprising a second semiconductor material having a second lattice constant greater than the first lattice constant; a middle fin portion comprising a third semiconductor material having a third lattice constant between the first lattice constant and the second lattice constant; and a passivation structure surrounding the fin structure comprising a lower passivation portion surrounding the lower fin portion comprising a first oxynitride of the first semiconductor material; an upper passivation portion surrounding the upper fin portion comprising a second oxynitride of the second semiconductor material; and a middle passivation portion surrounding the middle fin portion comprising a third oxynitride of the third semiconductor material. | 2015-11-26 |
20150340303 | MULTI CHIP PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A multi chip package includes a protective layer having an upper surface that surrounds a first chip and a second chip, which are mounted over a first substrate, to expose an upper surface of the first chip and an upper surface of the second chip, a heat spreader disposed over the upper surfaces, and a thermal interface material disposed at an interface between the heat spreader and the upper surfaces. | 2015-11-26 |
20150340304 | Power Semiconductor Package - A semiconductor package that includes a substrate having a metallic back plate, an insulation body and a plurality of conductive pads on the insulation body, and a semiconductor die coupled to said conductive pads, the conductive pads including regions readied for direct connection to pads external to the package using a conductive adhesive. | 2015-11-26 |
20150340305 | STACKED DIE PACKAGE WITH REDISTRIBUTION LAYER - A packaged semiconductor device has lead fingers that define a cavity, and a first die located within the cavity. A second die abuts an inactive side of the first die. The second die is electrically connected to one or more of the lead fingers. A redistribution layer abuts an active side of the first die. Metal structures are situated on an outer surface of the redistribution layer. The redistribution layer electrically connects (i) one or more of the metal structures to one or more of the lead fingers and (ii) one or more of the metal structures to one or more bond pads on the active side of the first die. | 2015-11-26 |
20150340306 | SEMICONDUCTOR DEVICE PACKAGE HAVING ASYMMETRIC CHIP MOUNTING AREA AND LEAD WIDTHS - A semiconductor device package includes a solid metal base with a top surface and an electrically conductive chip mounting area on the top surface. First and second pairs of conductive leads are attached to the base and extend away from one another in opposite directions. First and second amplifiers are attached to the top surface and are electrically connected to the first and second pairs of leads. The first pair is separated from the second pair by a horizontal gap between inner edge sides of the leads. A reference line in the horizontal gap that extends perpendicular to edges of the base divides the chip mounting area into first and second chip mounting sections. An area of the first chip mounting section is smaller than an area of the second chip mounting section. The first and second leads have a smaller width than the third and fourth leads. | 2015-11-26 |
20150340307 | Molded chip package and method of manufacturing the same - A method of manufacturing a molded chip package is provided which comprises arranging an electronic chip on a supporting structure; forming an isolation layer at least on portions of the electronic chip; and molding an encapsulation which covers the electronic chip and the supporting structure at least partially by using a molding material comprising a matrix material and a conductive filler material. | 2015-11-26 |
20150340308 | RECONSTITUTED INTERPOSER SEMICONDUCTOR PACKAGE - A reconstituted semiconductor package and a method of making a reconstituted semiconductor package are described. An array of die-attach substrates is formed onto a carrier. A semiconductor device is mounted onto a first surface of each of the die-attach substrates. An interposer substrate is mounted over each of the semiconductor devices. The interposer substrates are electrically connected to the first surface of the respective die-attach substrates. A molding compound is filled in open spaces within and between the interposer substrates mounted to their respective die-attach substrates to form an array of reconstituted semiconductor packages. Electrical connections are mounted to a second surface of the die-attach substrates. The array of reconstituted semiconductor packages is singulated through the molding compound between each of the die-attach substrates and respective mounted interposer substrates. | 2015-11-26 |
20150340309 | PRINTED WIRING BOARD, SEMICONDUCTOR PACKAGE, AND METHOD FOR MANUFACTURING PRINTED WIRING BOARD - A printed wiring board includes a first interlayer, a first conductive layer on first-surface side of the first interlayer, a second conductive layer on second-surface side of the first interlayer, a first buildup layer including interlayers and conductive layers and formed on first surface of the first interlayer, and a second buildup layer including interlayers and conductive layers and formed on second surface of the first interlayer. The first conductive layer is formed such that the first conductive layer is embedded in the first interlayer and exposing surface on the first surface of the first interlayer, the second conductive layer is formed on the second surface of the first interlayer, and the interlayers in the first buildup layer include a second interlayer positioned adjacent to the first conductive layer and having the greatest thickness among the first interlayer and interlayers in the first and second buildup layers. | 2015-11-26 |
20150340310 | METHOD AND STRUCTURES FOR HEAT DISSIPATING INTERPOSERS - An interconnect element includes a semiconductor or insulating material layer that has a first thickness and defines a first surface; a thermally conductive layer; a plurality of conductive elements; and a dielectric coating. The thermally conductive layer includes a second thickness of at least 10 microns and defines a second surface of the interconnect element. The plurality of conductive elements extend from the first surface of the interconnect element to the second surface of the interconnect element. The dielectric coating is between at least a portion of each conductive element and the thermally conductive layer. | 2015-11-26 |
20150340311 | SEMICONDUCTOR DEVICE INCLUDING PLURAL SEMICONDUCTOR CHIPS STACKED ON SUBSTRATE - A semiconductor chip at least includes a row of first electrode pad group, which includes at least one first independent electrode pad and multiple first common electrode pads. The interval between the first independent electrode pad and an electrode pad adjacent thereto is defined as “first pitch”, and the interval between adjacent electrode pads making up the multiple first common electrode pads is defined as “second pitch”. The first pitch is determined to be larger than the second pitch. | 2015-11-26 |
20150340312 | MICROELECTRONIC PACKAGE AND STACKED MICROELECTRONIC ASSEMBLY AND COMPUTING SYSTEM CONTAINING SAME - A microelectronic package comprises a die ( | 2015-11-26 |
20150340313 | Semiconductor Devices Having Nonlinear Bitline Structures - Semiconductor devices are provided including a plurality of nonlinear bit lines formed on a substrate including a plurality of active areas; a plurality of word lines that pass through the plurality of active areas; an integral spacer that covers two sidewalls of the plurality of nonlinear bit lines and defines a plurality of spaces that expose two adjacent ones of the plurality of active areas; two conductive patterns that respectively abut on the two adjacent active areas in one of the plurality of spaces that is selected; and a contact separating insulation layer that is formed between the two conductive patterns in the one selected space. | 2015-11-26 |
20150340314 | SEMICONDUCTOR DEVICES INCLUDING PROTECTION PATTERNS AND METHODS OF FORMING THE SAME - Semiconductor devices including a protection pattern for reducing galvanic corrosion and methods of forming the semiconductor devices are provided. The semiconductor devices may include a substrate including a keep out zone (KOZ) and a plurality of interconnections, which may be disposed outside of the KOZ on the substrate. The semiconductor devices may also include a through silicon via (TSV) in the KOZ. The TSV may pass through the substrate. The semiconductor device may further include a protection pattern, which may be electrically insulated from the TSV, may be disposed in the KOZ and may include a different conductive material from the TSV. A lower end of the protection pattern may be disposed at a level higher than a lower end of the TSV. | 2015-11-26 |
20150340315 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a micro CMOS region including a micro CMOS and a micro interconnect that is connected to the micro CMOS; and a high breakdown voltage device region including a high breakdown voltage device that has a breakdown voltage higher than that of the micro CMOS, and drain and source interconnects that are connected to the high breakdown voltage device and have a width greater than that of the micro interconnect in a plan view. In the high breakdown voltage device region, an electrically-isolated dummy interconnect is not provided adjacent to at least the drain interconnect and the source interconnect. | 2015-11-26 |
20150340316 | NOVEL SEMICONDUCTOR DEVICE AND STRUCTURE - A 3D device, including: a first layer including a first memory including a first transistor; and a second layer including a second memory including a second transistor; where the second transistor is self-aligned to the first transistor, and where the first transistor and the second transistor each being a junction-less transistor. | 2015-11-26 |
20150340317 | E-FUSE STRUCTURE OF SEMICONDUCTOR DEVICE - Provided is an e-fuse structure of a semiconductor device. the e-fuse structure may include a fuse link formed of a first metal material to connect a cathode with an anode, a capping dielectric covering a top surface of the fuse link, and a dummy metal plug penetrating the capping dielectric and being in contact with a portion of the fuse link. The dummy metal plug may include a metal layer and a barrier metal layer interposed between the metal layer and the fuse link. The barrier metal layer may be formed of a second metal material different from the first metal material. | 2015-11-26 |
20150340318 | DEVICE ARCHITECTURE AND METHOD FOR PRECISION ENHANCEMENT OF VERTICAL SEMICONDUCTOR DEVICES - Improvement of key electrical specifications of vertical semiconductor devices, usually found in the class of devices known as discrete semiconductors, has a direct impact on the performance achievement and power efficiency of the systems in which these devices are used. Imprecise vertical device specifications cause system builders to either screen incoming devices for their required specification targets or to design their system with lower performance or lower efficiency than desired. Disclosed is an architecture and method for achieving a desired target specification for a vertical semiconductor device. Precise trimming of threshold voltage improves targeting of both on-resistance and switching time. Precise trimming of gate resistance also improves targeting of switching time. Precise trimming of a device's effective width improves targeting of both on-resistance and current-carrying capability. Device parametrics are trimmed to improve a single device, or a parametric specification is targeted to match specifications on two or more devices. | 2015-11-26 |
20150340319 | E-FUSE STRUCTURE FOR AN INTEGRATED CIRCUIT PRODUCT - An e-fuse device disclosed herein includes an anode and a cathode that are conductively coupled to the doped region formed in a substrate, wherein the anode includes a first metal silicide region positioned on the doped region and a first conductive metal-containing contact that is positioned above and coupled to the first metal silicide region, and the cathode includes a second metal silicide region positioned on the doped region and a second conductive metal-containing contact that is positioned above and conductively coupled to the second metal silicide region. A method disclosed herein includes forming a doped region in a substrate for an e-fuse device and performing at least one common process operation to form a first conductive structure on the doped region of the e-fuse device and a second conductive structure on a source/drain region of a transistor. | 2015-11-26 |
20150340320 | SEMICONDUCTOR DEVICES INCLUDING BULB-SHAPED TRENCHES - A method of creating a trench having a portion of a bulb-shaped cross-section in silicon is disclosed. The method comprises forming at least one trench in silicon and forming a liner in the at least one trench. The liner is removed from a bottom surface of the at least one trench to expose the underlying silicon. A portion of the underlying exposed silicon is removed to form a cavity in the silicon. At least one removal cycle is conducted to remove exposed silicon in the cavity to form a bulb-shaped cross-sectional profile, with each removal cycle comprising subjecting the silicon in the cavity to ozonated water to oxidize the silicon and subjecting the oxidized silicon to a hydrogen fluoride solution to remove the oxidized silicon. A semiconductor device structure comprising the at least one trench comprising a cavity with a bulb-shaped cross-sectional profile is also disclosed. | 2015-11-26 |
20150340321 | SEMICONDUCTOR INTEGRATED CIRCUIT - Disclosed herein is a semiconductor integrated circuit including: a cell layout region including circuit cells subject to power control the supply and interruption of power to which is controlled by a power switch, and always-on circuit cell groups which are always powered after the activation; a main line laid out in the cell layout region and applied with a source or reference voltage; and first and second branch lines which branch from the main line in the cell layout region. | 2015-11-26 |
20150340322 | RF SWITCH STRUCTURE HAVING REDUCED OFF-STATE CAPACITANCE - An RF switch structure having reduced off-state capacitance is disclosed. The RF switch structure includes an RF switch branch having at least three transistors coupled in series within a device layer. Inter-metal dielectric (IMD) layers are disposed over the device layer. At least one of the IMD layers has an effective dielectric constant that is lower than 3.9. In one exemplary embodiment, the IMD layers are made of silicon dioxide having micro-voids. In another exemplary embodiment, the IMD layers are made of silicon dioxide that includes carbon doping. In either exemplary embodiment, an effective dielectric constant ranges from about 3.9 to around 2.0. In another exemplary embodiment, the IMD layers are made of silicon dioxide having trapped air bubbles that provide an effective dielectric constant that ranges from about 2.0 to 1.1. | 2015-11-26 |
20150340323 | SELF-FORMING EMBEDDED DIFFUSION BARRIERS - Interconnect structures containing metal oxide embedded diffusion barriers and methods of forming the same. Interconnect structures may include an M | 2015-11-26 |
20150340324 | Integrated Circuit Die And Package - A semiconductor package assembly includes a substrate having an upper surface with a die attachment region thereon. A layer of die attachment material is positioned on top of the die attachment region. The semiconductor package assembly also includes an integrated circuit (“IC”) die. The die has a top portion including a laterally extending top wall surface and a plurality of generally vertically extending wall surfaces extending downwardly from the top wall surface. The die has a metallized bottom portion. The bottom portion has at least two metallized laterally extending wall surfaces and a plurality of metallized generally vertically extending connecting surfaces that connect the metallized laterally extending surfaces of the bottom portion. The layer of die attachment material interfaces with one or both of the metallized laterally extending surfaces and the plurality of metallized generally vertically extending connecting wall surfaces. | 2015-11-26 |
20150340325 | SEMICONDUCTOR DEVICE - A semiconductor device of the present invention includes a semiconductor element having an upper surface and a lower surface, a metal plate thermally connected to the lower surface, an upper surface electrode soldered to the upper surface, an insulating sheet formed on the upper surface electrode so as to be in surface contact with the upper surface electrode, a shielding plate formed on the insulating sheet so as to be in surface contact with the insulating sheet, the shielding plate shielding against radiation noise, and a resin with which the semiconductor element is covered, while a portion of the upper surface electrode, a portion of the shielding plate and a lower surface of the metal plate are exposed to the outside, wherein the heat conductivity of the insulating sheet is higher than the heat conductivity of the resin. | 2015-11-26 |
20150340326 | SHUNT OF P GATE TO N GATE BOUNDARY RESISTANCE FOR METAL GATE TECHNOLOGIES - An integrated circuit includes a component with a metal gate NMOS transistor and a metal gate PMOS transistor in which a metal gate structure of the NMOS transistor is disposed in electrical series with, and abuts, a metal gate structure of the PMOS transistor. A gate shunt is formed over a boundary between the metal gate structure of the NMOS transistor and the metal gate structure of the PMOS transistor. The gate shunt provides a low resistance connection between the metal gate structure of the NMOS transistor and the metal gate structure of the PMOS transistor. The gate shunt is free of electrical connections to other components through interconnect elements of the integrated circuit. | 2015-11-26 |