48th week of 2014 patent applcation highlights part 16 |
Patent application number | Title | Published |
20140346529 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor-device manufacturing method of the present invention includes a step of selectively implanting impurity ions into a surface of an SiC semiconductor layer and forming impurity regions and a step of activating the impurity ions by annealing the SiC semiconductor layer at a temperature of 1400° C. or more when the surface of the SiC semiconductor layer is covered with an insulating film. | 2014-11-27 |
20140346530 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to an embodiment of the present invention includes a SiC substrate, an AlN layer provided on the SiC substrate and having a maximum valley depth Rv of 5 nm or less in an upper surface, a channel layer provided on the AlN layer and composed of a nitride semiconductor, an electron supply layer provided on the channel layer and having a greater band gap than the channel layer, and a gate electrode, a source electrode and a drain electrode provided on the electron supply layer. | 2014-11-27 |
20140346531 | SiC SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a method which heats a layer including nickel and titanium on a SiC substrate ( | 2014-11-27 |
20140346532 | OPTICAL INPUT/OUTPUT DEVICE, OPTICAL ELECTRONIC SYSTEM INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE SAME - Disclosed are an optical input/output device and an opto-electronic system including the same. The device includes a bulk silicon substrate, at least one vertical-input light detection element monolithically integrated on a portion of the bulk silicon substrate, and at least one vertical-output light source element monolithically integrated on another portion of the bulk silicon substrate adjacent to the vertical-input light detection element. The vertical-output light source element includes a III-V compound semiconductor light source active layer combined with the bulk silicon substrate by a wafer bonding method. | 2014-11-27 |
20140346533 | SOLID STATE LIGHTING COMPONENT PACKAGE WITH CONFORMAL REFLECTIVE COATING - A solid state lighting package is provided. The package comprising at least one LED element positioned on a top surface of a substrate and a conformal reflective layer of inorganic particles, whereby at least of portion of the light emitted by the LED element is reflected by the conformal reflective layer. A method of manufacturing a solid state lighting package comprising the distribution of inorganic particles, and a method of increasing the luminous flux thereof, is also provided. | 2014-11-27 |
20140346534 | PIXEL UNIT AND AN ARRAY SUBSTRATE - A pixel unit and an array substrate are provided. The pixel unit includes a scan line extended along a first extension direction; a data line extended along a second extension direction; a solder pad electrically connects to the scan line and the data line; an insulation layer covering the scan line and the data line, and having a through hole; and multiple strip electrodes disposed on the insulation layer and extending along a third extension direction, wherein, the multiple strip electrodes electrically connect to the solder pad by the through hole. The solder pad and the multiple strip electrodes are all made of a transparent conductive material. A shape of the solder pad is a polygon and is parallel to the third extension direction. The present invention can effectively suppress the “dark fringes” phenomenon around the solder pad. | 2014-11-27 |
20140346535 | DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - A display device includes a display substrate, an encapsulation substrate facing the display substrate, a filling material between the display substrate and the encapsulation substrate, the filling material including a norbornene-based resin, and a sealing material joining the display substrate with the encapsulation substrate. | 2014-11-27 |
20140346536 | LIGHT-EMITTING DEVICE AND LIGHTING APPARATUS USING THE SAME - A light-emitting device including: a substrate; LEDs arranged on the substrate in a row; electrode pad pairs each including electrode pads at opposite sides of a corresponding LED in a row direction; Zener diodes (protective elements) in one-to-one correspondence to circuits (groups) U | 2014-11-27 |
20140346537 | LIGHT EMITTING DIODE DISPLAY PANEL - A light emitting diode (LED) display panel includes a plurality of pixel units, a plurality of first bar-shaped electrode layers arranged along a first direction and a plurality second bar-shaped electrode layers arranged along a second direction. The first bar-shaped electrode layers are coupled to a first power supply and the pixel units, and the second bar-shaped electrode layers are also coupled to the first power supply. Only a non-complete portion of overlap positions between the first and second bar-shaped electrode layers have first conductive paths configured to couple the first bar-shaped electrode layers to the corresponding second bar-shaped electrode layers. | 2014-11-27 |
20140346538 | Light-Emitting Device and Electronic Device Using the Same - It is an object to provide a light-emitting device and an electronic device which can provide an image with excellent image quality. One of the present inventions is a light-emitting device including a plurality of light-emitting elements each exhibiting a different emission color. At least one of the plurality of light-emitting elements has n light-emitting layers (n is a natural number, n≧2) between a pair of electrodes. Further, at least one of the n light-emitting layers includes a substance which provides emission from a triplet excitation state. In a light-emitting device having such a structure, an image is displayed by combining emissions from the plurality of light-emitting elements. | 2014-11-27 |
20140346539 | DIODE MATRIX DEVICE WITH ENHANCED STABILITY - The invention relates to a device comprising a substrate supporting a matrix ( | 2014-11-27 |
20140346540 | LIGHT EMITTING DIODE DIE - A light emitting diode (LED) die includes a first semiconductor layer, a second semiconductor layer, an active layer interposed between the first and second semiconductor layers, a transparent electrically conductive layer formed on the second semiconductor layer, and a passivation layer formed on the transparent electrically conductive layer. A first electrode is electrically connected with the first semiconductor layer, and a second electrode is is electrically connected with the second semiconductor layer. The transparent electrically conductive layer is made of tin doped indium oxide. The passivation layer is made of silicon nitride having a refractive index close to that of the transparent electrically conductive layer. | 2014-11-27 |
20140346541 | METHOD FOR PRODUCING AN OPTOELECTRONIC SEMICONDUCTOR CHIP AND OPTOELECTRONIC SEMICONDUCTOR CHIP - A method of producing an optoelectronic semiconductor chip includes providing a growth substrate, producing a III nitride nucleation layer on the growth substrate by sputtering, wherein a material of the growth substrate differs from a material of the nucleation layer, and growing a III nitride semiconductor layer sequence having an active layer onto the nucleation layer. | 2014-11-27 |
20140346542 | HIGH LIGHT EXTRACTION EFFICIENCY NITRIDE BASED LIGHT EMITTING DIODE BY SURFACE ROUGHENING - A III-nitride light emitting diode (LED) and method of fabricating the same, wherein at least one surface of a semipolar or nonpolar plane of a III-nitride layer of the LED is textured, thereby forming a textured surface in order to increase light extraction. The texturing may be performed by plasma assisted chemical etching, photolithography followed by etching, or nano-imprinting followed by etching. | 2014-11-27 |
20140346543 | LIGHT-EMITTING DEVICE - A light-emitting device of the invention includes a base, at least one light-emitting element, a wavelength transferring cover and a heat-conducting structure. The light-emitting element is disposed on the base and electrically connected to the base. The wavelength transferring cover is disposed on the base and covers the light-emitting element. The heat-conducting structure is disposed on the base and directly contacts the wavelength transferring cover. | 2014-11-27 |
20140346544 | Light-Emitting Element Having a Reflective Structure with High Efficiency - A light-emitting element includes a reflective layer; a first transparent layer on the reflective layer; a light-emitting stack having an active layer on the first transparent layer; and a cavity formed in the first transparent layer. | 2014-11-27 |
20140346545 | LED DEVICES WITH REDUCED REFLECTION AND AN LED DISPLAY INCLUDING SAME - LED devices are provided including an LED package including an LED and an optical element in an optical receiving relationship with the LED. The optical element has a higher light absorbing property at an exit surface away from the LED than at a bottom surface proximal to the LED. The optical element may include different epoxies, dye, and opaque particles. Methods for producing disclosed LED devices are also disclosed. | 2014-11-27 |
20140346546 | GALLIUM-NITRIDE-ON-HANDLE SUBSTRATE MATERIALS AND DEVICES AND METHOD OF MANUFACTURE - A gallium and nitrogen containing substrate structure includes a handle substrate member having a first surface and a second surface and a transferred thickness of gallium and nitrogen material. The structure has a gallium and nitrogen containing active region grown overlying the transferred thickness and a recessed region formed within a portion of the handle substrate member. The substrate structure has a conductive material formed within the recessed region configured to transfer thermal energy from at least the transferred thickness of gallium and nitrogen material. | 2014-11-27 |
20140346547 | Light Emitting Device Package - Disclosed is a light emitting device package. The light emitting device package includes a body part provided therein with a cavity, a light emitting chip in the cavity, a cover part to cover the cavity, and a light conversion part provided on a bottom surface of the cover part while being separated from the light emitting chip. | 2014-11-27 |
20140346548 | LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A light emitting device includes a light emitting element having electrodes on a lower surface side thereof; a phosphor layer covering a surface of the light emitting element; a transparent covering member disposed on at least one side surface of the light emitting device; and a reflection member that covers the covering member. | 2014-11-27 |
20140346549 | PHOSPHOR SHEET, LIGHT-EMITTING DEVICE HAVING THE PHOSPHOR SHEET AND METHOD OF MANUFACTURING THE SAME - Disclosed herein is a light emitting device including: a substrate; a light emitting diode (LED) chip disposed on the substrate; and a phosphor sheet disposed on an upper portion of the LED chip and including alignment members formed on a lower surface thereof. The alignment members contact the LED chip, such that the phosphor sheet is aligned with the LED chip. | 2014-11-27 |
20140346550 | CURABLE COMPOSITION - Provided are a curable composition and its use. The curable composition may provide a cured product having excellent processability, workability, and adhesive property, and having no whitening and surface stickiness. The curable composition has excellent thermal resistance at a high temperature, gas barrierability, and crack resistance, and thus, when applied to a semiconductor device, may stably maintain performance of the device at a high temperature for a long time. | 2014-11-27 |
20140346551 | Carrier Structure And Lighting Device - Various examples of a carrier structure and lighting device are described. A carrier structure configured to carry an LED includes a housing and a lead frame. The housing has a concave. The lead frame includes a main board portion having a main board through hole, at least two insertion portions extending from the main board portion into the main board through hole, and two electrode portions configured to be electrically coupled to the LED. The housing is disposed over the at least two insertion portions with the at least two insertion portions inserted into the housing. The concave of the housing expose the electrode portions. Each of the electrode portions has a respective protrusion sub-portion that extends outside of the housing. Additionally, a lighting device utilizing the carrier structure is also provided. | 2014-11-27 |
20140346552 | Three-Terminal Light Emitting Device (LED) - A three-terminal light emitting device (LED) chip, associated fabrication method, and LED array are provided. The method forms an n-doped semiconductor layer overlying a substrate, an active semiconductor layer overlying the n-doped semiconductor layer, and a p-doped semiconductor layer overlying the active semiconductor layer. A trench is formed through the p-doped and active semiconductor layers, exposing the n-doped semiconductor layer. In one aspect, the trench is formed at least part way, but not completely, through the n-doped semiconductor layer. Then, an LED P electrode is formed overlying a first region of the p-doped semiconductor layer, a diode P electrode is formed overlying a second region of the p-doped semiconductor layer that is separated from the first region of the p-doped semiconductor layer by the trench, and an N electrode is formed overlying a top surface of the exposed n-doped semiconductor layer in the trench, shared by the LED and diode. | 2014-11-27 |
20140346553 | VERTICAL LIGHT EMITTING DEVICES WITH NICKEL SILICIDE BONDING AND METHODS OF MANUFACTURING - Various embodiments of light emitting devices, assemblies, and methods of manufacturing are described herein. In one embodiment, a method for manufacturing a lighting emitting device includes forming a light emitting structure, and depositing a barrier material, a mirror material, and a bonding material on the light emitting structure in series. The bonding material contains nickel (Ni). The method also includes placing the light emitting structure onto a silicon substrate with the bonding material in contact with the silicon substrate and annealing the light emitting structure and the silicon substrate. As a result, a nickel silicide (NiSi) material is formed at an interface between the silicon substrate and the bonding material to mechanically couple the light emitting structure to the silicon substrate. | 2014-11-27 |
20140346554 | LEDS WITH EFFICIENT ELECTRODE STRUCTURES - Aspects include Light Emitting Diodes that have a GaN-based light emitting region and a metallic electrode. The metallic electrode can be physically separated from the GaN-based light emitted region by a layer of porous dielectric, which provides a reflecting region between at least a portion of the metallic electrode and the GaN-based light emitting region. | 2014-11-27 |
20140346555 | Sealed Thin-Film Device as well as Method of Repairing, System for Repairing and Computer Program Product - The invention relates to a sealed thin-film device, to a method of repairing a sealing layer applied to a thin-film device to produce the sealed thin-film device, to a system for repairing the sealing layer applied to the thin-film device to generate the sealed thin-film device and to a computer program product. The sealed thin-film device comprises a thin-film device and a sealing layer applied on the thin-film device for protecting the thin-film device from environmental influence. The sealing layer comprises at least a first and a second barrier layer and a getter layer arranged between the first and the second barrier layer. The sealed thin-film device further comprises locally applied mending material for sealing a local breach in an outer one of said barrier layers. | 2014-11-27 |
20140346556 | CURABLE COMPOSITION - Provided are a curable composition and its use. The curable composition may provide a cured product having excellent processability, workability, and adhesive property, and having no whitening and surface stickiness. The curable composition has excellent thermal resistance and crack resistance, and low gas permeability, and thus provides a device having excellent initial performance when being applied to a semiconductor device and maintaining stable performance when being used at a high temperature for a long time. | 2014-11-27 |
20140346557 | NITRIDE SEMICONDUCTOR LIGHT-EMITTING ELEMENT - A nitride semiconductor light-emitting element includes a layered semiconductor body which is made of a group III nitride semiconductor, and includes a light-emitting facet, and a multilayer protective film which is formed to cover the light-emitting facet of the layered semiconductor body, and includes a plurality of insulating films. The multilayer protective film includes a first protective film and a second protective film covering the first protective film. The first protective film is a crystalline film which is made of nitride containing aluminum, and is at least partially crystallized. The second protective film is a crystalline film which is made of oxide containing aluminum, and is at least partially crystallized. | 2014-11-27 |
20140346558 | RECTIFYING DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein are a rectifying device and a method of fabricating the same. The rectifying device includes a first electrode formed in a flat shape, an insulating layer deposited on the first electrode and a second electrode formed on a preset region of the insulating layer in a nanaopillar shape in a longitudinal direction to be asymmetrical to the first electrode, thereby increasing current flow. | 2014-11-27 |
20140346559 | Ultra-Fast Breakover Diode - In a first embodiment, an ultra-fast breakover diode has a turn on time T | 2014-11-27 |
20140346560 | PROTECTION DEVICE AND RELATED FABRICATION METHODS - Protection device structures and related fabrication methods are provided. An exemplary semiconductor protection device includes a base well region having a first conductivity type, an emitter region within the base well region having a second conductivity type opposite the first conductivity type, a collector region having the second conductivity type, a first floating region having the second conductivity type within the base well region between the emitter region and the collector region, and a second floating region having the first conductivity type within the base well region between the first floating region and the collector region. The floating regions within the base well region are electrically connected to reduce current gain and improve holding voltage. | 2014-11-27 |
20140346561 | SEMICONDUCTOR DEVICE - In a semiconductor substrate of a semiconductor device, a drift layer, a body layer, an emitter layer, and a trench gate electrode are formed. When the semiconductor substrate is viewed in a plane manner, the semiconductor substrate is divided into a first region covered with a heat dissipation member, and a second region not covered with the heat dissipation member. A density of trench gate electrodes in the first region is equal to a density of trench gate electrodes in the second region. A value obtained by dividing an effective carrier amount of channel parts formed in the first region by an area of the first region is larger than a value obtained by dividing an effective carrier amount of channel parts formed in the second region by an area of the second region. | 2014-11-27 |
20140346562 | TRENCH INSULATED-GATE BIPOLAR TRANSISTOR AND MANUFACTURE METHOD THEREOF - A Trench Insulated Gate Bipolar Transistor (IGBT) and a manufacture method thereof are provided by the present invention, which belongs to the field of IGBT technical field. The manufacture method includes following steps: (1) preparing a semiconductor substrate; (2) forming an epitaxial layer grow on a first side of the semiconductor substrate by epitaxial growth; (3) preparing and forming a gate and an emitter of the Trench Insulated Gate Bipolar Transistor on a second side of the semiconductor substrate; (4) thinning the epitaxial layer to form a collector region; (5) metalizing the collector region to form a collector. The cost of the manufacture method is low and the performance of the Trench IGBT formed by the manufacture method is good. | 2014-11-27 |
20140346563 | ANALOG SWITCH WITH HIGH BIPOLAR BLOCKING VOLTAGE IN LOW VOLTAGE CMOS PROCESS - The disclosed technology relates to an apparatus for protection against transient electrical events. In one aspect, the apparatus includes an analog switch with high bipolar blocking voltage comprising a first p-type well region, a second p-type well region, a first n-type well region disposed between the first and second p-type well regions, and a deep n-type well region surrounding the first p-type well region, the second p-type well region, and the first n-type well region. The apparatus additionally includes a first native n-type region disposed between the first p-type well region the n-type well region and a second native n-type region disposed between the second p-type well region and n-type well region. The apparatus is configured such that the first p-type well region serves as an emitter/collector of a bidirectional PNP bipolar transistor. In addition, the apparatus is configured such that the first native n-type region, the first n-type well region, and the second native n-type region serves as a base of the bidirectional PNP bipolar transistor. Furthermore, the apparatus is configured such that the second p-type well region is configured as a collector/emitter of the bidirectional PNP bipolar transistor. | 2014-11-27 |
20140346564 | Multi-Threshold Voltage FETs - A multi-threshold voltage (V | 2014-11-27 |
20140346565 | MOS TRANSISTORS AND FABRICATION METHODS THEREOF - A method is provided for fabricating MOS transistors. The method includes providing a semiconductor substrate having at least a first region and a second region; and forming first transistors on the semiconductor substrate. Wherein source/drain regions of the first transistors are configured as SiGe growth regions; and a first density of SiGe growth regions in the first region is smaller than a second density of SiGe growth regions in the second region. The method also includes forming dummy SiGe growth regions in the first region to increase the first density such that the total density of SiGe growth regions in the first region is in a range similar to the second density; and forming trenches in the first region and the second region and the dummy SiGe growth region. Further, the method includes forming embedded source/drain regions of the first transistors and dummy SiGe regions. | 2014-11-27 |
20140346566 | CONTACT METALLURGY FOR SELF-ALIGNED HIGH ELECTRON MOBILITY TRANSISTOR - A metallization scheme employing a first refractory metal barrier layer, a Group IIIA element layer, a second refractory metal barrier layer, and an oxidation-resistant metallic layer is employed to form a source region and a drain region that provide electrical contacts to a compound semiconductor material layer. The first and second refractory metal barrier layer are free of nitrogen, and thus, do not introduce additional nitrogen into the compound semiconductor layer, while allowing diffusion of the Group IIIA element to form locally doped regions underneath the source region and the drain region. Ohmic contacts may be formed at a temperature as low as about 500° C. This enables fabrication of FET whose source and drain are self-aligned to the gate. | 2014-11-27 |
20140346567 | ELEMENTAL SEMICONDUCTOR MATERIAL CONTACTFOR HIGH ELECTRON MOBILITY TRANSISTOR - Portions of a top compound semiconductor layer are recessed employing a gate electrode as an etch mask to form a source trench and a drain trench. A low temperature epitaxy process is employed to deposit a semiconductor material including at least one elemental semiconductor material in the source trench and the drain trench. Metallization is performed on physically exposed surfaces of the elemental semiconductor material portions in the source trench and the drain trench by depositing a metal and inducing interaction with the metal and the at least one elemental semiconductor material. A metal semiconductor alloy of the metal and the at least one elemental semiconductor material can be performed at a temperature lower than 600° C. to provide a high electron mobility transistor with a well-defined device profile and reliable metallization contacts. | 2014-11-27 |
20140346568 | Low Temperature Ohmic Contacts for III-N Power Devices - The disclosure relates to a method for manufacturing an Au-free ohmic contact for an III-nitride (III-N) device on a semiconductor substrate and to a III-N device obtainable therefrom. The III-N device includes a buffer layer, a channel layer, a barrier layer, and a passivation layer. A 2DEG layer is formed at an interface between the channel layer and the barrier layer. The method includes forming a recess in the passivation layer and in the barrier layer up to the 2DEG layer, and forming an Au-free metal stack in the recess. The metal stack comprises a Ti/Al bi-layer, with a Ti layer overlying and in contact with a bottom of the recess, and a Al layer overlying and in contact with the Ti layer. A thickness ratio of the Ti layer to the Al layer is between 0.01 to 0.1. After forming the metal stack, a rapid thermal anneal is performed. Optionally, prior to forming the Ti/Al bi-layer, a silicon layer may be formed in contact with the recess. | 2014-11-27 |
20140346569 | Gate Voltage Control for III-Nitride Transistors - A semiconductor die includes a III-nitride semiconductor substrate, a power HEMT (high-electron-mobility transistor) disposed in the III-nitride semiconductor substrate, and a first gate driver HEMT monolithically integrated with the power HEMT in the III-nitride semiconductor substrate. The power HEMT and the first gate driver HEMT each have a gate, a source and a drain. The first gate driver HEMT logically forms part of a driver, and is electrically connected to the gate of the power HEMT. The first gate driver HEMT is operable to turn the power HEMT off or on responsive to an externally-generated control signal received from the driver or other device. Additional embodiments of semiconductor dies and methods of manufacturing are also described. | 2014-11-27 |
20140346570 | SEMICONDUCTOR DEVICE - A semiconductor device having high breakdown withstand voltage includes a first element which is a normally-on type transistor made of nitride compound semiconductor, a second element which is connected to the first element in series and is a transistor having withstand voltage between a source and a drain lower than withstand voltage of the first element, a first diode which is connected between a gate of the first element or a gate of the second element and a drain of the first element so that a cathode of the first diode is connected at the drain's side and has predetermined avalanche withstand voltage, and a first resistance connected to the gate to which the first diode is connected. The avalanche withstand voltage of the first diode is lower than breakdown voltage of the first element. | 2014-11-27 |
20140346571 | THREE DIMENSIONAL INTEGRATED CIRCUITS - A three-dimensional semiconductor device, comprising: a first module layer having a plurality of circuit blocks; and a second module layer positioned substantially above the first module layer, including a plurality of configuration circuits; and a third module layer positioned substantially above the second module layer, including a plurality of circuit blocks; wherein, the configuration circuits in the second module control a portion of the circuit blocks in the first and third module layers. | 2014-11-27 |
20140346572 | IMAGE SENSOR PIXEL CELL WITH GLOBAL SHUTTER HAVING NARROW SPACING BETWEEN GATES - A pixel cell includes a photodiode, a storage transistor, a transfer transistor and an output transistor disposed in a semiconductor substrate. The transfer transistor selectively transfers image charge accumulated in the photodiode from the photodiode to the storage transistor. The output transistor selectively transfers the image charge from the storage transistor to a readout node. A first isolation fence is disposed over the semiconductor substrate separating a transfer gate of the transfer transistor from a storage gate of the storage transistor. A second isolation fence is disposed over the semiconductor substrate separating the storage gate from an output gate of the output transistor. Thicknesses of the first and second isolation fences are substantially equal to spacing distances between the transfer gate and the storage gate, and between the storage gate and the output gate, respectively. | 2014-11-27 |
20140346573 | SEMICONDUCTOR DEVICE INCLUDING EMBEDDED CRYSTALLINE BACK-GATE BIAS PLANES, RELATED DESIGN STRUCTURE AND METHOD OF FABRICATION - A method of forming a semiconductor device is disclosed. The method includes forming a first dielectric layer on a substrate; forming a set of bias lines on the first dielectric layer; covering the set of bias lines with a second dielectric layer; forming a semiconductor layer on the second dielectric layer; and forming a set of devices on the semiconductor layer above the set of bias lines. | 2014-11-27 |
20140346574 | ASYMMETRIC FINFET SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME - Asymmetric FinFET devices and methods for fabricating such devices are provided. In one embodiment, a method includes providing a semiconductor substrate comprising a plurality of fin structures formed thereon and depositing a conformal liner over the fin structures. A first portion of the conformal liner is removed, leaving a first space between the fins structures and forming a first metal gate in the first space between the fin structures. A second portion of the conformal liner is removed, leaving a second space between the fin structures and forming a second metal gate in the second space between the fin structures. | 2014-11-27 |
20140346575 | SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACT AND METHOD OF MANUFACTURING THE SAME - A semiconductor device with a self-aligned contact and a method of manufacturing the same, wherein the method comprises the step of forming a 1st dielectric layer on gate structures, form a self-aligned contact trench between two gate structures, forming an 2nd dielectric layer on the 1st dielectric layer and in the self-aligned contact trench; patterning the 2nd dielectric layer into a 1st portion on the 1st dielectric layer and a 2nd portion filling in the self-aligned contact trench, using the 2nd dielectric layer as a mask to etch the 1st dielectric layer, and forming a metal layer and a self-aligned contact simultaneously in the 1st dielectric layer and in the self-aligned contact trench. | 2014-11-27 |
20140346576 | MOSFETS WITH MULTIPLE DISLOCATION PLANES - A method includes forming a metal-oxide-semiconductor field-effect transistor (MOSFET). The Method includes performing an implantation to form a pre-amorphization implantation (PAI) region adjacent to a gate electrode of the MOSFET, forming a strained capping layer over the PAI region, and performing an annealing on the strained capping layer and the PAI region to form a dislocation plane. The dislocation plane is formed as a result of the annealing, with a tilt angle of the dislocation plane being smaller than about 65 degrees. | 2014-11-27 |
20140346577 | ELECTRONIC DEVICE WITH ASYMMETRIC GATE STRAIN - The use of strained gate electrodes in integrated circuits results in a transistor having improved carrier mobility, improved drive characteristics, and reduced source drain junction leakage. The gate electrode strain can be obtained through non symmetric placement of stress inducing structures as part of the gate electrode. | 2014-11-27 |
20140346578 | SOLID-STATE IMAGE SENSOR, METHOD OF MANUFACTURING THE SAME, AND IMAGE CAPTURING SYSTEM - A solid-state image sensor including a pixel unit arranged on a semiconductor substrate and including a plurality of photoelectric converters, and a peripheral circuit unit arranged on the semiconductor substrate and including MOS transistors and a capacitive element portion, wherein a gate insulating film of the MOS transistor in the peripheral circuit unit and an insulating film between facing electrodes of the capacitive element portion are nitrided, and a density of nitrogen atoms in the nitrided insulating film of the capacitive element portion is higher than the density of the nitrogen atoms in the nitrided insulating film of the MOS transistor in the peripheral circuit unit. | 2014-11-27 |
20140346579 | MAGNETIC FIELD SENSOR DEVICE - A magnetic field sensor device having a semiconductor body, whereby the semiconductor body has a top side and a bottom side, and whereby the semiconductor body has a substrate layer and a passivation layer formed above the substrate on the top side of the semiconductor body, and one or more integrated electronic components are formed in the substrate layer of the semiconductor body, and a Hall plate is provided on the top side of the semiconductor body above the passivation layer, and the Hall plate is formed of a graphene compound. | 2014-11-27 |
20140346580 | SEMICONDUCTOR DEVICES CAPABLE OF SELF-CURING - A semiconductor device includes a plurality of first signal lines crossing a plurality of second signal lines. At least one of the first signal lines has a first end to receive a first voltage and a second end to receive a second voltage. The first and second voltages are applied simultaneously to respective ones of the first and second ends. A difference between the first and second voltages causes joule heating in the at least one first signal line. The joule heating may correct one or more defects in the semiconductor device. | 2014-11-27 |
20140346581 | SEMICONDUCTOR DEVICE - The performances of a semiconductor device are improved. A semiconductor device has a first electrode and a dummy electrode formed apart from each other over a semiconductor substrate, a second electrode formed between the first electrode and the dummy electrode, at the circumferential side surface of the first electrode, and at the circumferential side surface of the dummy electrode, and a capacitive insulation film formed between the first electrode and the second electrode. The first electrode, the second electrode, and the capacitive insulation film form a capacitive element. Further, the semiconductor device has a first plug penetrating through the interlayer insulation film, and electrically coupled with the first electrode, and a second plug penetrating through the interlayer insulation film, and electrically coupled with the portion of the second electrode formed at the side surface of the dummy electrode opposite to the first electrode side. | 2014-11-27 |
20140346582 | NON-VOLATILE MEMORY SEMICONDUCTOR DEVICES AND METHOD FOR MAKING THEREOF - The disclosed technology generally relates to memory devices, and more particularly to memory devices having an intergate dielectric stack comprising multiple high k dielectric materials. In one aspect, a planar non-volatile memory device comprises a hybrid floating gate structure separated from an inter-gate dielectric structure by a first interfacial layer which is designed to be electrically transparent so as not to affect the program saturation of the device. The inter-gate structure comprises a stack of three layers having a high-k/low-k/high-k configuration and the interfacial layer has a higher k-value than its adjacent high-k layer in the inter-gate dielectric structure. A method of making such a non-volatile memory device is also described. | 2014-11-27 |
20140346583 | INVERTED-T WORD LINE AND FORMATION FOR NON-VOLATILE STORAGE - A non-volatile memory system, comprising non-volatile storage device with word lines having an inverted T-shape over floating gates. The inverted T-shape shape has a wider bottom portion and a thinner top portion. The thinner top portion increases the separation between adjacent word lines relative to the separation between the wider bottom portions. An air gap may separate adjacent word lines. The thinner top portion of the word lines increases the path length between adjacent word lines. The likelihood of word line to word line short may be decreased by reducing the electric field between adjacent word lines. | 2014-11-27 |
20140346584 | MEMORY DEVICE WITH CONTROL GATE OXYGEN DIFFUSION CONTROL AND METHOD OF MAKING THEREOF - An embodiment relates to a memory device that includes a semiconductor channel, a tunnel dielectric located over the semiconductor channel, a charge storage region located over the tunnel dielectric, a blocking dielectric located over the charge storage region, and a control gate located over the blocking dielectric. An interface between the blocking dielectric and the control gate substantially prevents oxygen diffusion from the blocking dielectric into the control gate. | 2014-11-27 |
20140346585 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor memory device includes a lower gate layer, a stacked body including a plurality of electrode layers and a plurality of insulating layers, alternately stacked on the lower gate layer, a channel body extending within the stacked body from the topmost electrode layer to the lower gate layer, and a memory film provided between the electrode layer and the channel body. The memory film includes a charge storage film. The electrode layer includes a step portion in which a step is formed in a stacking direction of the stacked body. The channel body and the memory film pass through the step portion. | 2014-11-27 |
20140346586 | NON-VOLATILE MEMORY STRUCTURE - A non-volatile memory structure, including a substrate, a plurality of stacked structures, a plurality of first conductive type doped regions, at least one second conductive type doped region, a conductive layer, and a first dielectric layer, is provided. The stacked structures are disposed on the substrate, and each of the stacked structures includes a charge storage structure. The first conductive type doped regions are disposed in the substrate under the corresponding charge storage structures respectively. The second conductive type doped region is disposed in the substrate between the adjacent charge storage structures and has an overlap region with each of the charge storage structures. The conductive layer covers the second conductive type doped region. The first dielectric layer is disposed between the conductive layer and the second conductive type doped region. | 2014-11-27 |
20140346587 | INTEGRATED CIRCUIT HAVING MOSFET WITH EMBEDDED STRESSOR AND METHOD TO FABRICATE SAME - A method includes forming a recess into a crystalline semiconductor substrate, the recess being disposed beneath and surrounding a channel region of a transistor; depositing a layer of crystalline dielectric material onto a surface of the substrate that is exposed within the recess; and depositing stressor material into the recess such that the layer of dielectric material is disposed between the stressor material and the surface of the substrate. A structure includes a gate stack or gate stack precursor disposed on a SOI layer disposed upon a BOX that is disposed upon a surface of a crystalline semiconductor substrate. A transistor channel is disposed within the SOI layer. The structure further includes a channel stressor layer disposed at least partially within a recess in the substrate and disposed about the channel, and a layer of crystalline dielectric material disposed between the stressor layer and a surface of the substrate. | 2014-11-27 |
20140346588 | SUPERJUNCTION POWER DEVICE AND MANUFACTURING METHOD - A method for manufacturing a semiconductor power device, comprising the steps of: forming a trench in a semiconductor body having a first type of conductivity; partially filling the trench with semiconductor material via epitaxial growth so as to obtain a first column having a second type of conductivity and having an internal cavity. The epitaxial growth includes simultaneously supplying a gas containing dopant ions of the second type of conductivity, hydrochloric acid HCl in gaseous form and dichlorosilane DCS in gaseous form, so that the ratio between the amount of HCl and the amount of DCS has a value of from 3.5 to 5.5. | 2014-11-27 |
20140346589 | Semiconductor Device with Charge Compensation - A semiconductor device includes a semiconductor body and a source metallization arranged on a first surface of the body. The body includes: a first semiconductor layer including a compensation-structure; a second semiconductor layer adjoining the first layer, comprised of semiconductor material of a first conductivity type and having a doping charge per horizontal area lower than a breakdown charge per area of the semiconductor material; a third semiconductor layer of the first conductivity type adjoining the second layer and comprising at least one of a self-charging charge trap, a floating field plate and a semiconductor region of a second conductivity type forming a pn-junction with the third layer; and a fourth semiconductor layer of the first conductivity type adjoining the third layer and having a maximum doping concentration higher than that of the third layer. The first semiconductor layer is arranged between the first surface and the second semiconductor layer. | 2014-11-27 |
20140346590 | Semiconductor Device, Method of Manufacturing a Semiconductor Device and Integrated Circuit - A semiconductor device formed in a semiconductor substrate includes a source region, a drain region, a gate electrode, and a body region disposed between the source region and the drain region. The gate electrode is disposed adjacent at least two sides of the body region, and the source region and the gate electrode are coupled to a source terminal. A width of the body region between the two sides of the body region is selected so that the body region is configured to be fully depleted. | 2014-11-27 |
20140346591 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device includes forming a device isolation film defining an active region, forming a recess configured to expose a seam contained in the device isolation film by etching the active region and the device isolation film, forming a sacrificial film to fill the exposed seam, and forming a gate at a lower part of the recess. | 2014-11-27 |
20140346592 | SEMICONDUCTOR DEVICE - A vertical MOSFET includes: a semiconductor substrate comprising a drain layer, a drift layer, a body layer, and a source layer; and a trench gate penetrating through the source layer and the body layer from an upper surface of the semiconductor substrate and reaching the drift layer. The trench gate includes a gate electrode; a first insulating film disposed on a bottom surface of a trench formed in the semiconductor substrate; a second insulating film disposed at least on a side surface of the trench, and in contact with the body layer; and a third insulating film disposed between the gate electrode and the second insulating film, and formed of a material of which dielectric constant is higher than a dielectric constant of the second insulating film. | 2014-11-27 |
20140346593 | SUPER-JUNCTION TRENCH MOSFETS WITH SHORT TERMINATIONS - A super-junction trench MOSFET with a short termination area is disclosed, wherein the short termination area comprising a charge balance region and a channel stop region formed near a top surface of an epitaxial layer with a trenched termination contact penetrating therethrough. | 2014-11-27 |
20140346594 | SEMICONDUCTOR DEVICE WITH SCHOTTKY DIODE AND MANUFACTURING METHOD THEREOF - A semiconductor device with an embedded schottky diode and a manufacturing method thereof are provided. A semiconductor device having a schottky diode include: an epilayer of a first conductivity type, a body layer of a second conductivity type, and a source layer of the first conductivity type arranged in that order; a gate trench that extends from the source layer to a part of the epilayer; a body trench formed a predetermined distance from the gate trench and extends from the source layer to a part of the epilayer; and a guard ring of the second conductivity type that contacts an outer wall of the body trench and formed in the epilayer. | 2014-11-27 |
20140346595 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes a semiconductor device may include, but is not limited to, a semiconductor substrate, an isolation electrode, a gate electrode, a gate insulating film, and a first insulating film. The semiconductor substrate has a first groove and a second groove. An isolation electrode is positioned in the first groove. The gate electrode is positioned in the second groove. The gate insulating film is adjacent to the gate electrode. The first insulating film is adjacent to the isolation electrode. The isolation electrode is greater in threshold voltage than the gate electrode. | 2014-11-27 |
20140346596 | HIGH VOLTAGE LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR - High-voltage LDMOS devices with voltage linearizing field plates and methods of manufacture are disclosed. The method includes forming an array of poly islands and a control gate structure by patterning a poly layer formed over a deep well region and a body of a substrate. The method further includes forming a metal shield in contact with the control gate structure and over the array of poly islands. | 2014-11-27 |
20140346597 | HIGH VOLTAGE LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR - High-voltage LDMOS devices with voltage linearizing field plates and methods of manufacture are disclosed. The method includes forming an insulator layer of varying depth over a drift region and a body of a substrate. The method further includes forming a control gate and a split gate region by patterning a layer of material on the insulator layer. The split gate region is formed on a first portion of the insulator layer and the control gate is formed on a second portion of the insulator layer, which is thinner than the first portion. | 2014-11-27 |
20140346598 | HIGH VOLTAGE PMOS (HVPMOS) TRANSISTOR WITH A COMPOSITE DRIFT REGION AND MANUFACTURE METHOD THEREOF - In one embodiment, method of making a high voltage PMOS (HVPMOS) transistor, can include: (i) providing a P-type substrate; (ii) implanting N-type dopants in the P-type substrate; (iii) dispersing the implanted N-type dopants in the P-type substrate to form a deep N-type well; (iv) implanting P-type dopants of different doping concentrations in the deep N-type well along a horizontal direction of the deep N-type well; and (v) dispersing the implanted P-type dopants to form a composite drift region having an increasing doping concentration and an increasing junction depth along the horizontal direction of the deep N-type well. | 2014-11-27 |
20140346599 | FINFET SEMICONDUCTOR DEVICES WITH LOCAL ISOLATION FEATURES AND METHODS FOR FABRICATING THE SAME - FinFET semiconductor devices with local isolation features and methods for fabricating such devices are provided. In one embodiment, a method for fabricating a semiconductor device includes providing a semiconductor substrate comprising a plurality of fin structures formed thereon, wherein each of the plurality of fin structures has sidewalls, forming spacers about the sidewalls of the plurality of fin structures, and forming a silicon-containing layer over the semiconductor substrate and in between the plurality of fin structures. The method further includes removing at least a first portion of the silicon-containing layer to form a plurality of void regions while leaving at least a second portion thereof in place and depositing an isolation material in the plurality of void regions. | 2014-11-27 |
20140346600 | Integrated Circuit Having MOSFET with Embedded Stressor and Method to Fabricate Same - A structure includes a gate stack or gate stack precursor disposed on a SOI layer disposed upon a BOX that is disposed upon a surface of a crystalline semiconductor substrate. A transistor channel is disposed within the SOI layer. The structure further includes a channel stressor layer disposed at least partially within a recess in the substrate and disposed about the channel, and a layer of crystalline dielectric material disposed between the stressor layer and a surface of the substrate. | 2014-11-27 |
20140346601 | SEMICONDUCTOR DEVICE - A semiconductor device includes a gate electrode, source regions and drain regions, a body contact region, and a body bias control electrode. The gate electrode includes a plurality of first portions arranged in parallel with a first distance therebetween, and a second portion connecting the plurality of first portions. The source regions and the drain regions are provided between the plurality of first portions. The body contact region is disposed on the other side of the source regions and the drain regions relative to the second portion. The body bias control electrode is provided on the body contact region in parallel with the second portion at a second distance from the second portion that is greater than the first distance, and is electrically connected to the body contact region. | 2014-11-27 |
20140346602 | SEMICONDUCTOR DEVICES INCLUDING PROTRUDING INSULATION PORTIONS BETWEEN ACTIVE FINS - A semiconductor device can include a field insulation layer including a planar major surface extending in first and second orthogonal directions and a protruding portion that protrudes a particular distance from the major surface relative to the first and second orthogonal directions. First and second multi-channel active fins can extend on the field insulation layer, and can be separated from one another by the protruding portion. A conductive layer can extend from an uppermost surface of the protruding portion to cross over the protruding portion between the first and second multi-channel active fins. | 2014-11-27 |
20140346603 | TRANSISTOR DEVICES HAVING AN ANTI-FUSE CONFIGURATION AND METHODS OF FORMING THE SAME - Transistor devices having an anti-fuse configuration and methods of forming the transistor devices are provided. An exemplary transistor device includes a semiconductor substrate including a first fin. A first insulator layer overlies the semiconductor substrate and has a thickness less than a height of the first fin. The first fin extends through and protrudes beyond the first insulator layer to provide a buried fin portion and an exposed fin portion. A gate electrode structure overlies the exposed fin portion. A gate insulating structure is disposed between the first fin and the gate electrode structure. The gate insulating structure includes a first dielectric layer overlying a first surface of the first fin. The gate insulating structure further includes a second dielectric layer overlying a second surface of the first fin. A potential breakdown path is defined between the first fin and the gate electrode structure through the first dielectric layer. | 2014-11-27 |
20140346604 | THIN FILM TRANSISTOR, DISPLAY APPARATUS INCLUDING THE THIN FILM TRANSISTOR, AND METHOD OF MANUFACTURING THE THIN FILM TRANSISTOR - A thin film transistor includes: a substrate, a semiconductor layer disposed on the substrate, a first gate electrode and a second gate electrode disposed on the semiconductor layer, a gate insulating layer disposed between the semiconductor layer and the first and second gate electrodes and having a first through hole between the first and second gate electrodes and a capping layer covering the first gate electrode and contacting the semiconductor layer via the first through hole. The capping layer includes a conductive material. | 2014-11-27 |
20140346605 | INTEGRATED CIRCUITS WITH IMPROVED SOURCE/DRAIN CONTACTS AND METHODS FOR FABRICATING SUCH INTEGRATED CIRCUITS - Integrated circuits and methods for fabricating integrated circuits are provided. In accordance with an exemplary embodiment, an integrated circuit includes a semiconductor substrate with a fin structure overlying the semiconductor substrate and having a source region, a drain region, and a channel region between the source region and drain region. The source region and the drain region each have a recessed surface. A source contact is adjacent the recessed surface in the source region and a drain contact is adjacent the recessed surface in the drain region. Linear current paths are defined from the channel region to the source contact and from the channel region to the drain contact. | 2014-11-27 |
20140346606 | GATE ROUNDING FOR REDUCED TRANSISTOR LEAKAGE CURRENT - Gate-rounding fabrication techniques can be implemented to increase an effective channel length of a transistor and to consequently reduce the leakage current and static power consumption associated with the transistor. The transistor comprises a substrate region that includes a source region and a drain region. The transistor can also comprise a gate region that includes a main gate portion, one or more gate tips, and one or more corresponding gate-rounded portions. Each of the one or more gate tips is formed at a suitable position along the side of the main gate portion. During fabrication, the junction between the main gate region and each of the gate tips takes on a rounded shape to form a corresponding gate-rounded region. The gate-rounded regions increase the average length of the gate region and the effective channel length of the transistor. | 2014-11-27 |
20140346607 | Tuning Tensile Strain on FinFET - A fin field effect transistor (FinFET) having a tunable tensile strain and an embodiment method of tuning tensile strain in an integrated circuit are provided. The method includes forming a source/drain region on opposing sides of a gate region in a fin, forming spacers over the fin, the spacers adjacent to the source/drain regions, depositing a dielectric between the spacers; and performing an annealing process to contract the dielectric, the dielectric contraction deforming the spacers, the spacer deformation enlarging the gate region in the fin. | 2014-11-27 |
20140346608 | SEMICONDUCTOR DEVICE AND A METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device is provided. A plurality of first gate electrode structure is formed on a substrate. A recess is formed in the substrate, wherein the recess is formed between two adjacent first gate electrode structures of the plurality of first gate electrode structure. A diffusion prevention layer includes a first material and is formed on the recess of the substrate. A first pre-silicide layer includes a second material different from the first material and is formed on the diffusion prevention layer. A metal layer is formed on the first pre-silicide layer. The first pre-silicide layer and the metal layer are changed to a first silicide layer by performing an annealing process to the substrate. The diffusion prevention layer prevents metal atoms of the metal layer from diffusing to the substrate, and the first silicide layer comprises a monocrystalline layer. | 2014-11-27 |
20140346609 | CMOS Process To Improve SRAM Yield - An integrated circuit containing an SAR SRAM and CMOS logic, in which sidewall spacers on the gate extension of the SAR SRAM cell are thinner than sidewall spacers on the logic PMOS gates, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. A process of forming an integrated circuit containing an SAR SRAM and CMOS logic, including selectively etch the sidewall spacers on the on the gate extension of the SAR SRAM cell, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. A process of forming an integrated circuit containing an SAR SRAM and CMOS logic, including selectively implanting extra p-type dopants in the drain node SRAM PSD layer, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. | 2014-11-27 |
20140346610 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first MIS transistor and a second MIS transistor. The first MIS transistor includes a first gate insulating film which is formed on a first active region of a semiconductor substrate and has a first high dielectric constant film, and a first gate electrode formed on the first gate insulating film. The second MIS transistor includes a second gate insulating film which is formed on a second active region of the semiconductor substrate and has a second high dielectric constant film, and a second gate electrode formed on the second gate insulating film. The second high dielectric constant film contains first adjusting metal. The first high dielectric constant film has a higher nitrogen concentration than the second high dielectric constant film, and does not contain the first adjusting metal. | 2014-11-27 |
20140346611 | SEMICONDUCTOR DEVICE - A semiconductor device may include a voltage supply unit suitable for supplying a voltage, a first conductive line coupled to the voltage supply unit, a second conductive line formed over the first conductive line, a voltage contact plug formed over the second conductive line, a voltage transmission line formed over the voltage contact plug, and a switching element suitable for switching the voltage transferred from the voltage transmission line. | 2014-11-27 |
20140346612 | BULK SEMICONDUCTOR FINS WITH SELF-ALIGNED SHALLOW TRENCH ISOLATION STRUCTURES - A silicon-carbon alloy layer and a silicon-germanium alloy layer are sequentially formed on a silicon-containing substrate with epitaxial alignment. Trenches are formed in the silicon-germanium alloy layer by an anisotropic etch employing a patterned hard mask layer as an etch mask and the silicon-carbon alloy layer as an etch stop layer. Fin-containing semiconductor material portions are formed on a bottom surface and sidewalls of each trench with epitaxial alignment with the silicon-germanium alloy layer and the silicon-carbon alloy layer. The hard mask layer and the silicon-germanium alloy layer are removed, and an oxygen-impermeable spacer is formed on sidewalls of each fin-containing semiconductor material portion. Physically exposed semiconductor portions are converted into semiconductor oxide portions, and the oxygen-impermeable spacers are removed. The remaining portions of the fin-containing semiconductor portions include semiconductor fins, which can be employed to form semiconductor devices. | 2014-11-27 |
20140346613 | METHODS OF FABRICATING FIN STRUCTURES - There is provided fin methods for fabricating fin structures. More specifically, fin structures are formed in a substrate. The fin structures may include two fins separated by a channel, wherein the fins may be employed as fins of a field effect transistor. The fin structures are formed below the upper surface of the substrate, and may be formed without utilizing a photolithographic mask to etch the fins. | 2014-11-27 |
20140346614 | SEMICONDUCTOR DEVICE - A semiconductor device includes a gate structure over a substrate, a source region in the substrate, where the source region is adjacent to the gate structure. Additionally, the semiconductor device includes a drain region in the substrate, where the drain region is adjacent to the gate structure. Moreover, the semiconductor device includes a first dislocation in the substrate between the source region and the drain region. Furthermore, the semiconductor device includes a second dislocation in the substrate between the source region and the drain region, where the second dislocation is substantially parallel to the first dislocation. | 2014-11-27 |
20140346615 | ENHANCEMENT-MODE TRANSISTORS WITH INCREASED THRESHOLD VOLTAGE - A field effect transistor that has a source, a drain, a gate, a semiconductor region, and a dielectric region. The dielectric region is located between the semiconductor region and the gate. Negatively charged ions are located within the dielectric layer underneath the gate. | 2014-11-27 |
20140346616 | TRANSISTOR AND SEMICONDUCTOR STRUCTURE - A semiconductor structure includes a work function metal layer, a (work function) metal oxide layer and a main electrode. The work function metal layer is located on a substrate. The (work function) metal oxide layer is located on the work function metal layer. The main electrode is located on the (work function) metal oxide layer. A semiconductor process forming said semiconductor structure is also provided. | 2014-11-27 |
20140346617 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes an interlayer insulating film on a substrate, the interlayer insulating film including first and second trenches, a gate insulating film in the first and second trenches, a first conductivity type work function control film on the gate insulating film in the first trench, a second conductivity type work function control film on the gate insulating film in the second trench, a first gate metal on the first conductivity type work function control film, the first gate metal filling the first trench, a second gate metal on the gate insulating film in the second trench, and a carrier mobility improving film on the second conductivity type work function control film, the carrier mobility improving film filling the second trench. | 2014-11-27 |
20140346618 | SURFACE TREATED SILICON CONTAINING ACTIVE MATERIALS FOR ELECTROCHEMICAL CELLS - Provided are active materials for electrochemical cells. The active materials include silicon containing structures and treatment layers covering at least some surface of these structures. The treatment layers may include aminosilane, a poly(amine), or a poly(imine). These layers are used to increase adhesion of the structures to polymer binders within active material layers of the electrode. As such, when the silicon containing structures change their size during cycling, the bonds between the binder and the silicon containing structure structures or, more specifically, the bonds between the binder and the treatment layer are retained and cycling characteristics of the electrochemical cells are preserved. Also provided are electrochemical cells fabricated with such active materials and methods of fabricating these active materials and electrochemical cells. | 2014-11-27 |
20140346619 | DETECTING SUDDEN CHANGES IN ACCELERATION IN SEMICONDUCTOR DEVICE OR SEMICONDUCTOR PACKAGING CONTAINING SEMICONDUCTOR DEVICE - An approach for detecting sudden changes in acceleration in a semiconductor device or semiconductor package containing the semiconductor device is disclosed. In one embodiment, a piezoelectric sensor is embedded in a semiconductor die. The piezoelectric sensor is configured to sense a mechanical force applied to the semiconductor die. An excessive force indicator is coupled to the piezoelectric sensor. The excessive force indicator is configured to generate an excessive force indication in response to the piezoelectric sensor sensing that the mechanical force applied to the semiconductor die has exceeded a predetermined threshold indicative of an excessive mechanical force. | 2014-11-27 |
20140346620 | MEMS MICROPHONE WITH REDUCED PARASITIC CAPACITANCE - A MEMS microphone has reduced parasitic capacitance. The microphone includes a trench electrically separating an acoustically active section of the backplate from an acoustically inactive section of the backplate. | 2014-11-27 |
20140346621 | MEMS BACKPLATE, MEMS MICROPHONE COMPRISING A MEMS BACKPLATE AND METHOD FOR MANUFACTURING A MEMS MICROPHONE - A MEMS backplate enables MEMS microphones with reduced parasitic capacitance. A MEMS backplate includes a central area and a perforation in the central area. A suspension area surrounds the central area at least partially. An aperture is disposed in the suspension area. | 2014-11-27 |
20140346622 | Forming Semiconductor Structure with Device Layers and TRL - A semiconductor wafer is formed with a first device layer having active devices. A handle wafer having a trap rich layer is bonded to a top surface of the semiconductor wafer. A second device layer having a MEMS device or acoustic filter device is formed on a bottom surface of the semiconductor wafer. The second device layer is formed either by monolithic fabrication processes or layer-transfer processes. | 2014-11-27 |
20140346623 | Film-Covered Open-Cavity Sensor Package - Techniques for covering open-cavity integrated-circuit packages in a batch process are disclosed. In an example method, a plurality of open-cavity packages are molded on a single batch leadframe or substrate, each open-cavity package comprising a floor and a plurality of walls arranged around the floor to form a cavity, each of said the walls having a bottom end adjoining said floor and having a top side opposite the bottom end. At least one semiconductor device is attached to the floor and within the cavity of each of the open-cavity packages, and a single flexible membrane is affixed to the top sides of the walls of the plurality of open-cavity packages, so as to substantially cover all of the cavities. The flexible membrane is then severed, between the packages. | 2014-11-27 |
20140346624 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: a first member including a selection transistor on a front surface side of a first substrate; and a second member including a resistance change device and a connection layer that comes in contact with the resistance change device, the connection layer being bonded to a back surface of the first member. | 2014-11-27 |
20140346625 | MAGNETORESISTANCE DEVICE INCLUDING LAYERED FERROMAGNETIC STRUCTURE, AND METHOD OF MANUFACTURING THE SAME - A layered ferromagnetic structure is composed of a first ferromagnetic layer positioned over a substrate; a second ferromagnetic layer positioned over the first ferromagnetic layer; and a first non-magnetic layer placed between the first and second ferromagnetic layers. The top surface of the first ferromagnetic layer is in contact with the first non-magnetic layer. The first ferromagnetic layer includes a first orientation control buffer that exhibits an effect of enhancing crystalline orientation of a film formed thereon. | 2014-11-27 |
20140346626 | MEMORY ELEMENT AND MEMORY APPARATUS - According to some aspects, a layered structure includes a memory layer, a magnetization-fixed layer, and a tunnel insulating layer. The memory layer has magnetization perpendicular to a film face in which a direction of the magnetization is configured to be changed according to information by applying a current in a lamination direction of the layered structure. The magnetization-fixed layer has magnetization parallel or antiparallel to the magnetization direction of the memory layer and comprises a laminated ferripinned structure including a plurality of ferromagnetic layers and one or more non-magnetic layers, and includes a layer comprising an antiferromagnetic material formed on a first ferromagnetic layer of the plurality of ferromagnetic layers and situated between the first ferromagnetic layer and the non-magnetic layer. The tunnel insulating layer is located between the memory layer and the magnetization-fixed layer. | 2014-11-27 |
20140346627 | IMAGE PICKUP ELEMENT HOUSING PACKAGE, AND IMAGE PICKUP DEVICE - An imaging device accommodating package includes an insulating base body and an imaging device connecting pad. The insulating base body includes a lower surface, a through-hole and a bonding area on the bottom surface of the recess. The lower surface includes a recess. The through-hole is formed in a bottom surface of the recess in a perspective plan view. The bonding area is used for an imaging device. The imaging device connecting pad is formed on an upper surface of the insulating base body or on an inner surface of the through-hole. | 2014-11-27 |
20140346628 | SOLD-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS - A solid-state imaging device includes a semiconductor layer on which a plurality of pixels are arranged along a light-receiving surface being a main surface of the semiconductor layer, photoelectric conversion units provided for the respective pixels in the semiconductor layer, and a trench element isolation area formed by providing an insulating layer in a trench pattern formed on a light-receiving surface side of the semiconductor layer, the trench element isolation area being provided at a position displaced from a pixel boundary between the pixels. | 2014-11-27 |