48th week of 2014 patent applcation highlights part 21 |
Patent application number | Title | Published |
20140347029 | DC-DC Converter With Circuit For Reproducing A Current Flowing Through A Storage Inductor - A circuit for emulating a current via a power inductor of a DC-to-DC converter includes
| 2014-11-27 |
20140347030 | RAMP CIRCUIT AND DIRECT CURRENT (DC)- DC CONVERTER THEREOF - Provided are a ramp circuit and a DC-DC converter. The ramp circuit generates a current flowing in a resistor using voltages affected by an output voltage and an input voltage of a DC-DC converter, and generates a ramp signal through copying of the current and charging and discharging of a capacitor using a current mirror unit. The ramp signal is generated by considering the input voltage and the output voltage, and thus the ramp signal has an optimal slope to provide an adaptive response to state change in the input voltage and the output voltage. The DC-DC converter uses such a ramp circuit to facilitate its operation. | 2014-11-27 |
20140347031 | CONTROL DEVICE FOR A DC-DC CONVERTER - A control device for a dc-dc converter. The control device is designed for an increase and a decrease in the output power of the dc-dc converter, and the increase in the output power occurs at a different speed than the decrease. | 2014-11-27 |
20140347032 | CHIP DETECTOR - A chip detector includes a plug configured to be coupled to a housing. The plug includes a first magnetic member and a second magnetic member spaced apart from each other so as to define a gap therebetween. Each of the first magnetic member and the second magnetic member is a rare earth magnet. A first electric contact is electrically coupled with the first magnetic member and a second electric contact is electrically coupled with the second magnetic member. A resistor is electrically coupled between the first electric contact and the second electric contact. An energy storage device is configured to provide a voltage difference between the first electric contact and the second electric contact. An indicating member is configured to provide an indication of a flow of current between the first and second electric contacts due to collection of chips in the gap between the first and second magnetic members. | 2014-11-27 |
20140347033 | MEASURING ARRANGEMENT - A measuring arrangement for determining at least one measured variable with a sensor device ( | 2014-11-27 |
20140347034 | AC INPUT VOLTAGE INTERRUPTION DETECTION METHOD AND CIRCUIT - A selector circuit selects either a class upper-limit voltage or a class lower-limit voltage as a reference voltage of a comparator. A control logic controls the selector circuit, and generates a count-up signal or a count-down signal in accordance with the output of the comparator. An up/down counter counts up upon reception of the count-up signal from the control logic, and counts down upon reception of the count-down signal. A digital-analog converter outputs the class upper-limit voltage and the class lower-limit voltage in accordance with a digital value that is outputted by the up/down counter. A timer circuit is configured to be reset by the count-up signal from the control logic to the up/down counter. | 2014-11-27 |
20140347035 | METHOD FOR MEASURING THE FREQUENCY OF AN ELECTRICAL SIGNAL AND AN ELECTRICAL MEASURING SYSTEM - Described is an electrical measuring system with a six-gate circuit and a delay line. An electrical signal is fed from a resonator, at least one of directly and or via the delay line, to the six-gate circuit. The frequency of the signal is computed by the six-gate circuit in dependence on the length of the delay line. | 2014-11-27 |
20140347036 | CURRENT MONITORING APPARATUS AND CURRENT MONITORING SYSTEM USING THE SAME - Disclosed are a current monitoring apparatus for monitoring an electrical current flowing through a wire, and a current monitoring system using the same. The current monitoring apparatus includes a power generation part connected to a wire to generate alternating current (AC) power due to electromagnetic induction with the wire, and a current measurement part connected to the wire and measures the electrical current flowing through the wire. The current monitoring apparatus uses the power generated by the power generation part. | 2014-11-27 |
20140347037 | Apparatus for Mounting an Overhead Monitoring Device - An apparatus is provided for securing to and collecting power from an electrical conductor, including a current transformer comprising a core and an electrical winding that receives an induced current from magnetic flux generated according to alternating current present on the electrical conductor, and a clamping mechanism that attaches the apparatus to the electrical conductor. According to various aspects, apparatus may include a housing that encloses circuitry for monitoring conditions of the electrical conductor, where the circuitry includes one or more sensors, and wireless communications circuitry. | 2014-11-27 |
20140347038 | Method of Reconstructing Electrical Probes - A probe, comprising: a shank region having a top surface integrally connected to a bottom surface of a conical region; a pyramidal tip region having a base surface integrally connected to a top surface of the conical region; and wherein the base surface of the pyramidal tip region is contained within a perimeter of the top surface of the conical region. Also a method of fabricating the probe and a method of probing devices under test. | 2014-11-27 |
20140347039 | SYSTEMS AND METHODS FOR MEASURING ELECTRICAL POWER USAGE IN A STRUCTURE AND SYSTEMS AND METHODS OF CALIBRATING THE SAME - A magnetic field sensing device can include two or more magnetic field sensors configured to detect a magnetic field in a current carrying conductor. The magnetic field sensing device also can include a phase detector electrically coupled to outputs of the two or more magnetic field sensors. The magnetic field sensing device further can include a phase indicator electrically coupled to the phase detector. The phase indictor can include a display that indicates when the two or more magnetic field sensors are in a position in relation to the current carrying conductor. Other embodiments are provided. | 2014-11-27 |
20140347040 | ROTATION-ANGLE DETECTION DEVICE, IMAGE PROCESSING APPARATUS, AND ROTATION-ANGLE DETECTION METHOD - A rotation-angle detection device includes: an amplitude adjustment unit that performs correction to match amplitude values of multiple detection signals output from multiple rotation detection units to output corrected signals, the rotation detection units changing outputs in accordance with a rotation angle of a rotor and being provided such that the rotation detection units output the detection signals having different phases; a vector generation unit that performs addition and subtraction on two signals out of the corrected signals to generate two vector component signals that are perpendicular to each other; an amplitude correction unit that performs correction to match amplitudes of the two vector component signals to output corrected vector component signals; and a rotation-angle searching unit that searches for the rotation angle of the rotor on basis of a vector that is represented by the two corrected vector component signals to output a detection angle. | 2014-11-27 |
20140347041 | DEFECT INSPECTION DEVICE OF STEEL PLATE - Provided is a defect inspection device of a steel plate. The defect inspection device according to the present invention includes a plurality of inspection units arranged in a width direction of the steel plate, wherein each of the plurality of inspection units includes a first magnetized pole and a second magnetized pole corresponding to each other. Also, the inspection unit includes: a magnetizing part generating a magnetic flux for magnetizing the steel plate in a direction inclined at a predetermined angle with respect to a rolling direction through the first magnetized pole and the second magnetized pole; and a detection part detecting a leakage flux that leaks due to defects existing in or on the steel plate by using the flux generated by the magnetizing part. Thus, the defects may be correctly detected through the defect inspection device. | 2014-11-27 |
20140347042 | MODULAR EXCITATION SYSTEM - An excitation device for high-energy tests of stator cores of electric generators or motors is disclosed. The excitation device includes one or more excitation modules. Each excitation module includes an excitation winding and a power supply configured to drive an excitation current through the excitation winding which contributes to the overall excitation of the stator core. The excitation module further includes a capacitor. The power supply of the excitation module acts as current source at its output. | 2014-11-27 |
20140347043 | MONITORING ENGINE COMPONENTS - A method for monitoring local defects in a rotating engine component such as a gear uses one or more eddy current sensor(s) arranged to interact with the engine component as it is rotating during service. The eddy current sensor(s) may be carried by one or more teeth of a monitoring gear. A device is arranged to measure an output signal from the eddy current sensor(s) resulting from interaction with the rotating engine component. The output signal is processed so as to detect a change in shape of the output signal indicative of a local defect. | 2014-11-27 |
20140347044 | Magnetic Field Sensor for Detecting a Magnetic Field In Any Direction Above Thresholds - A magnetic field sensor includes first, second, and third magnetic field sensing elements having respective first, second and third maximum response axes, the first second and third maximum response axes pointing along respective first, second, and third different coordinate axes. In response to a magnetic field, the first, second, and third magnetic field sensing elements are operable to generate first second, and third magnetic field signals. Signals representative of the first, second, and third magnetic field signals are compared with thresholds to determine if the magnetic field is greater than the thresholds. A corresponding method is also provided. | 2014-11-27 |
20140347045 | THREE-DIMENSIONAL HALL SENSOR FOR DETECTING A SPATIAL MAGNETIC FIELD - A three-dimensional Hall sensor can be used for detecting a spatial magnetic field. A method for measuring a spatial magnetic field can be performed using this Hall sensor. The Hall sensor comprises an electrically conducting base body and at least three electrode pairs, wherein each electrode pair has a first terminal and a second terminal, which are arranged such on the base body, that a current can flow from the first terminal to the second terminal through the base body. At least three first terminals are arranged on a first surface of the base body and at least three second terminals are arranged on the second surface, different from the first surface of the base body, wherein the first and the second surfaces oppose each other. | 2014-11-27 |
20140347046 | USE OF FLEXIBLE MAGNETIC THIN LAYER SENSOR ELEMENTS - The invention concerns the field of electrical, materials and mechanical engineering and relates to the use of flexible magnetic thin layer sensor elements, which can be used for measuring magnetic flux density in electromagnetic energy converters and magnetomechanical energy converters. The aim of the invention is to specify the use of flexible magnetic thin layer sensor elements in electric machines and magnetic bearings, which can be placed in air gaps without substantially limiting the air gap widths. Said aim is achieved by the use of at least one flexible magnetic thin layer sensor element, which is attached to non-planar surfaces in the air gap on at least one of the main elements of electromagnetic energy converters and magnetomechanical energy converters and at least partially covers the non-planar surface of at least one of the main elements in the air gap in order to measure the magnetic flux density in the air gap and/or to regulate and/or monitor electromagnetic energy converters and magnetomechanical energy converters. | 2014-11-27 |
20140347047 | MAGNETORESISTIVE SENSOR - A magnetoresistive sensor is provided. Specifically, multiple layers of or single layer of conductor line are formed at the same level as an insulating layer on a substrate as a bottom conductive layer. A magnetoresistive structure is formed on the bottom conductive layer and has opposite first surface and second surface. The second surface faces toward the substrate and is contacted with the bottom conductive layer. Afterward, another insulating layer is formed on the first surface, a slot is formed at the same level as the another insulating layer and a conductor line is formed in the slot and contacted with the first surface, so that one layer or multiple layers of conductor line can be formed as a top conductive layer. A lengthwise extending direction of each of the bottom and top conductor layers is intersected a lengthwise extending direction of the magnetoresistive structure with an angle. | 2014-11-27 |
20140347048 | SYSTEMS AND METHODS FOR REDUCING MAGNETIC RESONANCE (MR) IMAGING ACOUSTIC NOISE IN MR INFLOW IMAGING - Systems and methods for reducing acoustic noise in a Magnetic Resonance Imaging (MRI) are provided. One method includes applying a labeling phase of an arterial spin labeling (ASL) pulse sequence to a region of interest, applying a three-dimensional (3D) radial pulse sequence to the region of interest to generate a tag image, applying a control phase of the ASL pulse sequence to the region of interest, and applying the 3D radial pulse sequence to the region of interest to generate a control image. | 2014-11-27 |
20140347049 | METHOD AND SYSTEM FOR MEASURING AND CALIBRATING IMAGING MAGNETIC FIELD IN MAGNETIC RESONANCE APPARATUS - A method and a system for measuring and calibrating an imaging magnetic field in a magnetic resonance apparatus are provided. The method includes: providing the imaging magnetic field, where the imaging magnetic field is adapted for scanning an object; sampling a signal corresponding to the imaging magnetic field; processing the signal to obtain an actual magnetic field intensity; and calibrating based on a difference between the actual magnetic field intensity and a target magnetic field intensity. The system includes: a magnetic component, adapted for scanning an object to be imaged; a sampling unit, adapted for sampling a signal corresponding to the imaging magnetic field; a processing unit, adapted for processing the signal to obtain an actual magnetic field intensity; a calibration unit, adapted for calibrating based on a difference between the actual magnetic field intensity and a target magnetic field intensity; and a control unit, adapted for controlling the system. | 2014-11-27 |
20140347050 | SYSTEM AND METHOD FOR REDUCING ACOUSTIC NOISE LEVEL IN MR IMAGING - A system and method for reducing MRI-generated acoustic noise is disclosed. A system control of an MRI apparatus causes a plurality of gradient coils and an RF coil assembly in the MRI apparatus to generate pulse sequences that each cause an echo train to form and acquire blades of k-space data of the subject of interest from the pulse sequences, with the blades being rotated about a section of k-space compared to every other blade. The system control also causes the plurality of gradient coils to generate gradient pulses in each pulse sequence having an optimized gradient waveform that reduces an acoustic noise level generated thereby and causes the RF coil assembly to generate a 180 degree prep pulse subsequent to generation of an RF excitation pulse and prior to generation of a first RF refocusing pulse, the 180 degree prep pulse minimizing echo spacing in the echo train. | 2014-11-27 |
20140347051 | System and Method for Acquiring Multiple Different Images Using A Single Magnetic Resonance Imaging Scan With Multiple Magnetization Preparation Radio Frequency Pulses - Described here are a system and method for obtaining multiple different images when performing a single scan of a subject with a magnetic resonance imaging (“MRI”) system. The scan includes the application of two or more magnetization preparation radio frequency (“RF”) pulses, such as inversion recovery (“IR”) pulses. Data is acquired after the application of each magnetization preparation RF pulse, thus allowing the acquisition of multiple different images of the subject in a single scan. Using this approach, the same information that used to require multiple different scans of the subject can be acquired in one single scan, and in less time than would be required to perform the multiple scans. | 2014-11-27 |
20140347052 | MAGNETIC RESONANCE IMAGING APPARATUS AND FREQUENCY SHIFT MEASURING METHOD - According to one embodiment, a magnetic resonance imaging apparatus includes a phase image generating unit, an image value acquisition unit and a frequency shift calculation unit. The phase image generating unit executes a sequence including an application of a bipolar gradient pulse and thereby generates a first phase image. The image value acquisition unit acquires an image value of the first phase image. The frequency shift calculation unit determines an amount of frequency shift per unit amount of gradient magnetic field based on magnetic field strength of the bipolar gradient pulse and on the image value of the first phase image. | 2014-11-27 |
20140347053 | Split Magnetic Resonance Imaging System - A magnetic resonance imaging (MRI) system includes a split magnet system having a pair of MRI magnet housings separated by gap. A pair of main MRI magnets are disposed within respective MRI magnet housings. A plurality of buttress assemblies are attached to the MRI magnet housings. Some or all of the buttress assemblies are provided with removable connections to the MRI magnet housings. This allows for partial disassembly of the MRI system for improved transport and maneuverability for relocating the MRI system. The MRI system can include a gantry in the gap for supporting a radiation therapy system. Also, the removably buttress assemblies can be used for housing conduits, such as electrical and fluid conduits, between the pair of MRI magnet housings. | 2014-11-27 |
20140347054 | Magnetic Resonance System with Whole-Body Transmitting Array - A magnetic resonance system includes a basic magnet that surrounds a cylindrical examination volume of the magnetic resonance system, the cylindrical examination volume defining a longitudinal axis, and a send structure configured to generate a high frequency excitation field (B | 2014-11-27 |
20140347055 | SUPER-RESOLUTION FORMATION FLUID IMAGING WITH CONTRAST FLUIDS - Cross-well electromagnetic (EM) imaging is performed using high-power pulsed magnetic field sources, time-domain signal acquisition, low-noise magnetic field sensors, spatial oversampling and super-resolution image enhancement and injected contrast fluids. The contrast fluids increase the electromagnetic character of the formation and fluids, either the magnetic permeability or the dielectric permittivity. The acquired signals are processed and inter-well images are generated mapping electromagnetic (EM) signal speed (group velocity) rather than conductivity maps. EM velocity maps with improved resolution for both native and injected fluids are provided. | 2014-11-27 |
20140347056 | Method and System for Calibrating a Downhole Imaging Tool - System and methods of generating calibrated downhole images of a subterranean formation ( | 2014-11-27 |
20140347057 | APPARATUS AND METHOD FOR PROVIDING BATTERY INFORMATION, AND USER TERMINAL THEREFOR - A battery information providing apparatus includes a short-range communication module for performing short-range communication; an information detector for detecting battery information; and a microprocessor for controlling the battery information to be transmitted by the short-range communication module. | 2014-11-27 |
20140347058 | METHOD FOR MONITORING A STATE OF A RECHARGEABLE BATTERY BASED ON A STATE VALUE WHICH CHARACTERIZES THE RESPECTIVE STATE OF THE RECHARGEABLE BATTERY - A method for monitoring a state of a rechargeable battery based on a state value which characterizes the respective state of the rechargeable battery, characterized in that, during at least one time interval, an electrical energy which is output by the rechargeable battery and an electrical energy which is received by the rechargeable battery are detected, and in that an instantaneous state of charge or an instantaneous no-load voltage of the rechargeable battery is detected, wherein the detected electrical energy which is output by the rechargeable battery, the detected electrical energy which is received by the rechargeable battery and the respectively detected instantaneous state of charge or the respectively detected instantaneous no-load voltage of the rechargeable battery are evaluated in order to generate the state value. | 2014-11-27 |
20140347059 | SECONDARY BATTERY STATE DETECTION DEVICE AND SECONDARY BATTERY STATE DETECTION METHOD - To accurately determine whether an engine can be started while accurately detecting a degree of deterioration of a secondary battery, in a secondary battery state detecting device detecting a state of a secondary battery mounted on a vehicle, a measurement unit measures a value of an internal resistance of the secondary battery at an engine stop time. An estimation unit estimates a value of a diffusion resistance resulting from diffusion of an ion generated at an electrolytic solution of the secondary battery by supplying electric power to a starter motor at a starting time of the engine. A calculation unit calculates a starting voltage being a voltage for the starting of the engine from a resistance value obtained by adding the value of the diffusion resistance estimated by the estimation unit to the value of the internal resistance measured by the measurement unit. | 2014-11-27 |
20140347060 | System for Power Balance Monitoring in Batteries - A system for power balance monitoring in an energy storage battery comprising a plurality of energy modules connected in a series-parallel configuration. The energy storage module comprises a plurality of cells. Each module is a three-terminal module. The three terminals comprise a positive output terminal and a negative output terminal for connecting the modules in a series string to a load and an energy sharing terminal for sharing energy between modules is other battery strings. A module power management sub-system comprising a current monitoring circuit is connected to each of the energy sharing terminals. Each module power management sub-system is in communication with a battery power management sub-system so that a weak module can be detected based on module current output. Advantageously, the module power management sub-system is not connected across the main power pathway of the module and so does not appreciably increase module impedance. | 2014-11-27 |
20140347061 | ELECTROSTATIC DETECTING CIRCUIT AND METHOD THEREOF - An electronic detecting circuit includes at least one electrostatic protective module, at least one detection module, and a microprocessor controller module. The at least one detection module is respectively connected to the at least one electrostatic protective module, and the at least one detection module generates a driving record signal according to a driving state of the at least one electrostatic protective module. The microprocessor controller module is coupled with the at least one detection module, wherein the microprocessor controller module records the driving record signal when the at least one detection module transmits the driving record signal to the microprocessor controller module. | 2014-11-27 |
20140347062 | Photo ionization detector for gas chromatography having at least two separately ionizing sources - A detector for gas chromatography using two or more ionization sources within a single body to separately provide ionization energy to a column gas eluent to provide electrical discharge to two or more collecting electrodes provides improved selectivity and may be so used. Use is made of combined bias/collecting electrodes or of sets of separated bias and collecting electrodes. The use of multiple ionization sources permits generation of multiple detector outputs from within a common body and of a common constituent flow. The ionization sources and any applicable discharge gas and dopant may be selected based on desired selectivity. | 2014-11-27 |
20140347063 | FAN TEST DEVICE - A fan test device to connect a motherboard and a fan includes a power terminal, a first diode, a second diode, a control chip, a first connector, a second connector, a first electronic switch and a second electronic switch. The control chip is connected to signal pins and sensing pins of the first and second connectors. The first electronic switch is connected between the control chip and a power pin of the first connector. The second electronic switch is connected between the control chip and a power pin of the second connector. The control chip outputs different signals corresponding to the connection of the first and second connectors. | 2014-11-27 |
20140347064 | DEVICE FOR TESTING FAN - A fan testing device connects to the fan and a motherboard. The fan testing device includes a first connection module, a second connection module, a control chip, and an alarm module. The control chip is coupled to signal pins of the first and second connectors. The control chip outputs different signals to control the alarm module according to the connections of the first and second connection modules. | 2014-11-27 |
20140347065 | Sub-Harmonic Arc Fault Detection System and Method - Embodiments of the invention provide systems and methods for detecting a sustained arc in an electrical system. Over a time period, current and voltage data for a load signal are collected, from which spectral information is extracted. The spectral information has a frequency component and an amplitude component. The load signal is processed to remove a line frequency signature from the spectral information. One or more sub-harmonic frequency bands are extracted from the load signal and analyzed to determine the presence of an arc signature therein. The sub-harmonic frequency bands may be centered on frequencies corresponding to an integer number of half line cycle periods. Analysis of the sub-harmonic frequency bands can include detecting the peak amplitudes of the rectified sub-harmonic frequency bands to obtain an indicator signal and determining if the indicator signal exceeds a threshold that indicates the presence of the sustained arc. | 2014-11-27 |
20140347066 | Arc Fault Detection System and Method - Embodiments of the invention provide systems and methods for detecting a sustained arc in an electrical system containing polymer-based, semi-conducting components which derive their conductivity from carbon black, carbon nanotubes or other conductive materials. Over a time period, current and voltage data for a cable signal are collected, from which spectral information is extracted. The spectral information has a frequency component and an amplitude component. The cable signal is processed to remove a line frequency signature that includes the electrical system's line current frequency and its harmonics. One or more off-harmonic frequency bands are extracted from the cable signal and analyzed to determine the presence of an arc signature therein. Analysis of the off-harmonic frequency bands can include applying a matched filter to the off-harmonic frequency bands to obtain an indicator signal and determining if the indicator signal exceeds a threshold that indicates the presence of the sustained arc. | 2014-11-27 |
20140347067 | Fault Detection Device For Inverter System - To provide a fault detection device for an inverter system, that detects a fault in the inverter system including an inverter circuit | 2014-11-27 |
20140347068 | SIGNAL INTEGRITY TEST SYSTEM AND METHOD - A signal integrity test system includes a signal generator, a CPLD, and an indicating light. The signal generator is electrically connected to an input end of transmission lines to generate a simulation signal having a waveform simulating a waveform from a signal source. The CPLD includes a switching module, a sampling module, and a judging module. The switching module generates a sampling clock corresponding to the waveform of the simulation signal. The sampling module is electrically connected to the switching module and samples the simulation signal by the sampling clock, and then transmits a sampling result to the judging module. The judging module compares the sampling result with a standard waveform and displays a comparison result through the indicating light. The disclosure further provides a signal integrity test method. | 2014-11-27 |
20140347069 | ARC DETECTION - In a method for detection of an arc in a current path of a converter arrangement ( | 2014-11-27 |
20140347070 | Measuring Method Using a Measuring Apparatus for Cable Diagnosis and/or Cable Testing - A measuring apparatus is connected to a cable to perform testing and diagnosis of the cable. The measuring apparatus includes a voltage source, a resistance, a switch, and an inductance forming a charging circuit, and two anti-parallel thyristors or switched diodes together with the inductance forming a series resonant circuit loop. The apparatus produces a low frequency alternating voltage signal train including a low frequency test signal followed by a low frequency diagnostic signal. The diagnostic signal is a damped decaying signal oscillation in the resonant circuit connected to the test cable. At least one of the signals is bipolar. Both cable testing and cable diagnosis can be performed using the same single measuring apparatus in a single measuring procedure. | 2014-11-27 |
20140347071 | DEVICE AND METHOD FOR ASSESSING THE DEGRADATION OF THE INSULATION OF AN OIL-INSULATED TRANSFORMER | 2014-11-27 |
20140347072 | Variable Resistor Arrangement, Measurement Bridge Circuit and Method for Calibrating a Measurement Bridge Circuit - A measurement bridge circuit includes a first branch and a second branch. The first branch contains a first resistor which is sensitive to measured variables and an invariable resistor connected in series. A first tap point is located between the first resistor and the invariable resistor. The second branch contains a second resistor which is sensitive to measured variables and a variable resistor arrangement connected in series. The variable resistor arrangement includes a first component having an invariable electrical resistance value and a second component having a variable electrical resistance value. The second component is connected in parallel with the first component in order to vary a total electrical resistance value for the variable resistor arrangement. A second tap point is located between the second resistor and the variable resistor arrangement. | 2014-11-27 |
20140347073 | CONTACT-FREE PHOTOMIXING PROBE FOR DEVICE AND INTEGRATED CIRCUIT MEASUREMENT OR CHARACTERIZATION - A device for measuring and characterizing solid-state devices or integrated circuits at RF frequencies up to 1.0 THz and beyond is provided that includes a transmitting photomixing probe structure and a receiving photomixing probe structure. The transmitting photomixing probe structure and the receiving photomixing probe structure are ac-coupled to the solid-state device or integrated circuit in a contact-free manner. | 2014-11-27 |
20140347074 | LOCKING SYSTEM FOR DETECTING AND TRACKING THE CENTER FREQUENCY OF ABSORPTION LINES IN GASES - A method to detect a gas absorption line that includes alternately transmitting and sweeping two radio frequency (RF) signals through an absorption cell, wherein the two RF signals are transmitted at different frequencies separated by a range and are swept across a span of frequencies in a microwave and millimeter wave regions of a frequency spectrum. Receiving the RF signals by a receiver and analyzing the received signals by a closed loop system for relative absorption by a gas due to an absorption line of the gas in the span of the swept frequencies. Detecting the absorption line of the gas when the two RF signals straddle the gas absorption line and the relative absorption by the two RF signals is equal. | 2014-11-27 |
20140347075 | POSITION DETECTION DEVICE - A detection coil is incorporated in a self-oscillation circuit. The oscillation frequency of the self-oscillation circuit, which comprises the coil and a capacitor, is set to a high frequency band (e.g., around 1 MHz or higher). A target section whose relative position to the coil section varies in response to displacement of a detection object, and includes a magnetism-responsive member constructed to cause inductance of the coil to vary with the relative position. A rectifier circuit extracts an amplitude level of an oscillation output signal of the self-oscillation circuit and outputs the extracted level as detected position data. For example, a plurality of self-oscillation circuits are provided. Alternatively, a single self-oscillation circuit forms a plurality of series circuits by, for each coil pair, connecting in series the two coils of the coil pair, and includes the result of connecting the series circuits in parallel as an inductor element for self-oscillation. | 2014-11-27 |
20140347076 | TOUCH SENSOR ELECTRODE WITH PATTERNED ELECTRICALLY ISOLATED REGIONS - An electrode layer has a plurality of substantially parallel electrodes disposed along a first direction. At least one electrode has a length along the first direction and a width from a first edge to a second edge along a second direction transverse to the first direction. At least one electrode comprises across its width at least one edge section, at least one intermediate section, and at least one central section, wherein an intermediate section is disposed along the electrode width between an edge section and the central section. At least one electrode edge section and intermediate section includes a plurality of electrically isolated regions arranged in a pattern along the electrode length. An electrode conductive area of the edge section is less than an electrode conductive area of the intermediate section. | 2014-11-27 |
20140347077 | UTILITY METERING - An apparatus has an input section arranged to receive values representative of the total instantaneous supply of electrical current as a function of time from an alternating voltage supply. Current waveforms comprising sets of values representative of the cyclic waveform of the electric current supply are obtained. A delta waveform generator calculates the difference between a current waveform and an earlier current waveform. An edge detector is arranged to detect an edge or edges in the delta waveform. An analysis section is arranged to identify at least one appliance load based at least on information on the edge or edges detected by the edge detector, and to determine the electrical energy consumed by said appliance load. | 2014-11-27 |
20140347078 | CURRENT SENSING OF SWITCHING POWER REGULATORS - Apparatus and methods for current sensing in switching regulators are disclosed. In certain implementations, a current sensing circuit senses current of a power stage of a power converter. The power converter can include first and second transistors. The current sensing circuit comprises a transistor that is a scaled version of one of the transistors of the power converter. A circuit of the current sensing circuit matches a drain-to-source voltage of the transistor of the current sensing circuit to the corresponding transistor of the power converter. A current mirror generates a current that mirrors the current flowing through the transistor of the current sensing circuit. A first resistor converts the mirrored current to a current sensed signal. | 2014-11-27 |
20140347079 | SYSTEM AND METHOD FOR ELECTROSTATIC DISCHARGE TESTING OF DEVICES UNDER TEST - A system and method for electrostatic discharge (ESD) testing devices under test (DUTs) uses an ESD gun attached to a robotic arm to execute ESD testing processes. The system and method also uses a relay station to place a DUT after an ESD testing process is performed on one major side of the DUT so the ESD testing can be performed on the other major side of the DUT. | 2014-11-27 |
20140347080 | ELECTRONIC DEVICE AND PRINTED CIRCUIT BOARD TESTING METHOD - An exemplary printed circuit board testing method includes determining whether there is an open shielding box every a time interval. The method then transmits a first control signal including a first predetermined path to a robot when there is an open shielding box. Next, the method obtains an image captured by a camera and recognizes a unique identifier of a to-be-tested PCB in the obtained image. The method then determines a second predetermined path corresponding to the determined open shielding box, and transmits a second control signal comprising the determined second predetermined path to the robot. Next, the method closes the determined shielding box when a duration after transmitting the second control signal reaches a predetermined time, and controls a testing software to test the to-be-tested PCB, to generate a testing result corresponding to the unique identifier of the to-be-tested PCB. | 2014-11-27 |
20140347081 | SEMICONDUCTOR DEVICE ASSESSMENT APPARATUS - A semiconductor device assessment apparatus that electrically assesses a semiconductor device formed on a semiconductor substrate includes a holding unit having a surface to hold the semiconductor substrate thereon, and a detection unit to detect irregularity on the surface of the holding unit. The holding unit on the surface includes a plurality of grooves formed such that when the semiconductor substrate is held on the surface, the grooves overlap a periphery of the semiconductor substrate and also have a portion located outer than the periphery of the semiconductor substrate. | 2014-11-27 |
20140347082 | SEMICONDUCTOR DEVICE TEST SOCKET - A test socket for connecting a device under test (DUT) electrically to a high-frequency power source comprises a plurality of pogo pins each having an electrode, an electron-to-heat conversion plate supporting bottoms of the pogo pins, the electron-to-heat conversion plate configured to convert kinetic energy of free electrons emitted from the pogo pins to thermal energy, and a heat sink wall formed on the electron-to-heat conversion plate, the heat sink wall having a predetermined height and isolating the plurality of pogo pins from one another. | 2014-11-27 |
20140347083 | SILICON-ON-INSULATOR (SOI) BODY-CONTACT PASS GATE STRUCTURE - A circuit for testing a floating body field-effect transistor (FET), and a related method, are provided. Embodiments of this invention include a circuit including a contacted-body FET structure that can be operated in a floating body mode or a body-contacted mode, and a passgate FET. A body of the contacted-body FET structure is connected to the drain of the passgate FET. Voltage can be applied to the passgate FET to either allow or restrict current flow through the passgate FET, to operate the contacted-body FET structure in body contacted mode or floating body mode. Data can be taken in each mode and compared to extract a floating body voltage. | 2014-11-27 |
20140347084 | LOW OVERDRIVE PROBES WITH HIGH OVERDRIVE SUBSTRATE - A method for testing a semiconductor device is disclosed. The method comprises positioning a probe card comprising a plurality of probes above the semiconductor device and moving the probe card in a vertical direction towards the semiconductor device. The plurality of probes are moving in a vertical direction towards a plurality of electrical structures of the semiconductor device until each probe of the plurality of probes has made mechanical contact with a corresponding electrical structure of the plurality of electrical structures with a minimum quantity of force. The each probe of the plurality of probes absorbs a portion of vertical overdrive after contacting their corresponding electrical structures. The probe card absorbs any remaining vertical overdrive. The vertical overdrive is a continuing vertical movement of the plurality of probes after a first probe of the plurality of probes mechanically contacts a first corresponding electrical structure. | 2014-11-27 |
20140347085 | TEST PROBE CARD - A testing probe card for wafer level testing semiconductor IC packaged devices. The card includes a circuit board including testing circuitry and a testing probe head. The probe head includes a probe array having a plurality of metallic testing probes attached to a substrate including a plurality of conductive vias. In one embodiment, the probes have a relatively rigid construction and have one end that may be electrically coupled to the vias using a flip chip assembly solder reflow process. In one embodiment, the probes may be formed from a monolithic block of conductive material using reverse wire electric discharge machining. | 2014-11-27 |
20140347086 | METHOD AND APPARATUS FOR MULTI-PLANAR EDGE-EXTENDED WAFER TRANSLATOR - An apparatus, suitable for coupling a pads of integrated circuits on wafer to the pogo pins of a pogo tower in a test system without the need of a probe card, includes a body having a first surface and a second surface, the body having a substantially circular central portion, and a plurality of bendable arms extending outwardly from the central portion, each bendable arm having a connector tab disposed at the distal end thereof; a first plurality of contact terminals disposed on the second surface of the central portion of the body, the first plurality of contact terminals arranged in pattern to match the layout of pads on a wafer to be contacted; at least one contact terminal disposed on the first surface of the plurality of connector tabs; and a plurality of electrically conductive pathways disposed in the body such that each of the first plurality of contact terminals is electrically connected to a corresponding one of the contact terminals on the first surface of the connector tabs. | 2014-11-27 |
20140347087 | BAR FOR ELECTRONICALLY CONTACTING AN ELECTRICALLY CONDUCTIVE SUBSTRATE - The present invention relates to a bar for the electrical contacting of an electrically conductive substrate in the form of a thin, electrically conducting and resilient contact. The bar comprises a current-collecting bar on which a plurality of contact fingers is fitted. The invention is distinguished by the contact fingers being configured resiliently in the direction of the contact to be produced. | 2014-11-27 |
20140347088 | Method and Circuit Of Pulse-Vanishing Test - Various aspects of the disclose techniques relate to techniques of testing interconnects in stacked designs. A single-pulse signal, generated by a first circuit state element on a first die, is applied to a first end of an interconnect and captured at a second end of the interconnect using a clock port of a second circuit state element on a second die. A faulty interconnect may cause the single-pulse signal too distorted to reach the threshold voltage of the second circuit element. | 2014-11-27 |
20140347089 | Testing of Thru-Silicon Vias - A system and a method are disclosed for testing thru-silicon vias (TSVs) in a silicon die. A silicon die containing multiple TSVs is mounted on a wafer tape. Two probe points are probed on the exposed side of the silicon die. A resistance is measured between the two probe points and an electrical integrity is determined based on the measured resistance. | 2014-11-27 |
20140347090 | SYSTEM AND METHOD FOR TESTING LAYOUT OF POWER PIN OF INTEGRATED CHIP ON PRINTED CIRCUIT BOARD - A testing system includes a layout information obtaining module, a first power pin sorting module, a transmission line sorting module, a power pin filtering module, a distance calculating module, a comparing module, and a report generating module. The layout information obtaining module obtains layout information. The first power pin sorting module sorts a power pin from a plurality of pins of a IC. The transmission line sorting module sorts transmission lines. The power pin filtering module filters power pins from a plurality of pins of capacities in same transmission line. The distance calculating module calculates distances between the power pin of the IC and each of the power pins of the capacities. The comparing module compares each of the distances with a threshold distance. The report generating module generates a testing report to depict whether or not the sorted power pins of the IC are qualified. | 2014-11-27 |
20140347091 | DEVICE FOR DETECTING PARTIAL DISCHARGE FOR POWER TRANSFORMER - The present invention relates to a device for detecting a partial discharge for a power transformer which detects an electromagnetic signal occurring due to faulty insulation. The device includes an antenna unit receiving electromagnetic waves, an insulator including the antenna unit, a metallic air-tight unit that seals a connector connected to the insulator and connecting a coaxial cable, and the coaxial cable exposed to the outside of the metallic air-tight unit. Thus, it is possible to enhance broadband properties through an internal conductor of a drain valve. | 2014-11-27 |
20140347092 | MODULATED ON-DIE TERMINATION - Alternating on-die termination impedances are applied within an integrated circuit device to up-convert signal reflections to higher frequencies that are attenuated by the signaling channel as the reflections propagate toward an intended signal receiver. Through this approach, the disruptive effect of reflected signals may be significantly reduced with relatively little overhead within the interconnected integrated circuit devices and little or no change to the printed circuit board or other interconnect medium. Changes to the printed circuit board or other interconnect medium can be made to further increase attenuation over the frequency band of the up-converted reflection and outside of the transmission band of signals of interest. | 2014-11-27 |
20140347093 | SEMICONDUCTOR APPARATUS - An internal voltage generation circuit of a semiconductor apparatus includes: an active driver configured to output an internal voltage to an output node; a standby driver configured to output the internal voltage to the output node; and a voltage stabilizer connected to the output node. The voltage stabilizer starts a voltage stabilization operation of supplying or receiving electric charges to or from the output node when an active enable signal is disabled, and stops the voltage stabilization operation in a predetermined time after the active enable signal is enabled. | 2014-11-27 |
20140347094 | RECONFIGURABLE CIRCUIT BLOCK SUPPORTING DIFFERENT INTERCONNECTION CONFIGURATIONS FOR RATE-CONVERSION CIRCUIT AND PROCESSING CIRCUIT AND RELATED METHOD THEREOF - A reconfigurable circuit block includes a rate-conversion circuit, a processing circuit, a first asynchronous interface circuit, and a second asynchronous interface circuit. The rate-conversion circuit converts a first input signal into a first output signal. The processing circuit processes a second input signal to generate a second output signal. The first asynchronous interface circuit outputs a third output signal asynchronous with the first output signal. The second asynchronous interface circuit outputs a fourth output signal asynchronous with the second output signal. The controllable interconnection circuit transmits the third output signal to the processing circuit to serve as the second input signal when controlled to have a first interconnection configuration, and transmits the fourth output signal to the rate-conversion circuit to serve as the first input signal when controlled to have a second interconnection configuration. | 2014-11-27 |
20140347095 | Bidirectional Buffer and Control Method Thereof - Bidirectional buffer | 2014-11-27 |
20140347096 | NON-LUT FIELD-PROGRAMMABLE GATE ARRAYS - New logic blocks capable of replacing the use of Look-Up Tables (LUTs) in integrated circuits, such as Field-Programmable Gate Arrays (FPGAs), are disclosed herein. In one embodiment, the new logic block is a tree structure comprised of a number of levels of cells with each cell consisting of a logic gate or the functional equivalent of a logic gate, one or more selectable inverters, and wherein the inputs of the logic block consist of the inputs to the logic gate or functional equivalent of the logic gate and inputs to the selectable inverters. The new logic blocks can map circuits more efficiently than LUTs, because they include multi-output blocks and can cover more logic depth due to the higher input and output bandwidth. | 2014-11-27 |
20140347097 | SINGLE COMPONENT SLEEP-CONVENTION LOGIC (SCL) MODULES - A multi-rail module having mutually exclusive outputs. The module includes first and second-rail logic circuits, first and second-rail driver circuits, and a PMOS transistor sourcing V | 2014-11-27 |
20140347098 | Systems and Methods for Data Receipt from Devices of Disparate Types - Systems and methods are provided for a receiver device for receiving data signals from devices of disparate types. An amplifier is configured to receive a voltage reference signal and a data signal, the data signal being received from a device, the amplifier being configured to output an output signal based on a comparison of the data signal to the voltage reference signal. A voltage reference level shifter is configured to selectively level shift the voltage reference signal supplied to the amplifier based on a type of device with which the receiver is communicating. A data signal level shifter is configured to selectively level shift the data signal supplied to the amplifier based on the type of device with which the receiver is communicating. | 2014-11-27 |
20140347099 | APPARATUSES, CIRCUITS, AND METHODS FOR REDUCING METASTABILITY IN DATA SYNCHRONIZATION - Apparatuses, circuits, and methods are disclosed for reducing or eliminating unintended operation resin ling from metastability in data synchronization. In one such example apparatus, a sampling circuit is configured to provide four samples of a data input signal. A first and a second of the four samples are associated with a first edge of a latching signal, and a third and a fourth of the four samples are associated with a second edge of the latching signal. A masking circuit is configured to selectively mask a signal corresponding to one of the four samples responsive to the four samples not sharing a common logic level. The masking circuit is also configured to provide a decision signal responsive to selectively masking or not masking the signal. | 2014-11-27 |
20140347100 | METHOD AND APPARATUS FOR DETERMINING TIME-VARYING LIMITATIONS OF A POWER SOURCE - A low-power method and apparatus is provided for adapting to time-varying limitations of a power source, such as a vehicle power source which is in a more-limited state when the engine is off. The supply voltage is monitored for changes using an unclocked, low-power first stage having an analog section, a voltage comparator. Upon detecting voltage changes reflective of a potential power source state change, the first stage generates an interrupt. In response, a second stage transitions from a low-power standby mode to a higher-power active mode. The second stage may include a microprocessor and is configured to confirm or disconfirm the state change. Upon confirmation, further operations are triggered. Upon disconfirmation, the second stage returns to standby mode. The first stage may include an operational amplifier whose two inputs are indicative of the supply voltage, one input having a different response rate to voltage variations than the other. | 2014-11-27 |
20140347101 | OPTIMAL HVDC BY-PASS POINT-ON-WAVE INDUCTIVE LOAD SWITCHING - The invention relates to a method of opening a shunt switch carrying a current, the switch being connected in parallel with at least one thyristor of a high voltage DC network, interruption of the current flowing through the switch being initiated at the time of a current zero of the current flowing through the switch, the method being characterized in that it includes, based on a measurement effected by means for measuring the current flowing through the switch, a step of adjusting a control angle of the thyristor to position the current zero in a zone in which the time derivative of the measured current is a continuous function and the absolute value of a peak value of the measured current is substantially equal to the absolute value of the inaccuracy of the measurement of the current zero. | 2014-11-27 |
20140347102 | Anti-Shoot-Through Automatic Multiple Feedback Gate Drive Control Circuit - Automatic and robust anti-shoot-through glitch-free operation of half-bridge control pre-driver and power stage circuits have been achieved by using multiple feedback control signals. These feedback signals are taken both from the gates of power devices on high side and low sides and from the gates of one or more devices on both high side and low side that enable power device ON state. No duty cycle limitation is required of the input signal. The control logic uses NAND/NOR RS latches. The solution disclosed can readily be scaled to higher order of feedback loops providing even greater level of robustness | 2014-11-27 |
20140347103 | FAULT-TOLERANT POWER SEMICONDUCTOR SWITCHING DEVICE CONTROL SYSTEM - We describe a fault-tolerant power semiconductor switching device control system ( | 2014-11-27 |
20140347104 | CIRCUIT FOR GENERATING A VOLTAGE WAVEFORM - A circuit for generating a voltage waveform at an output node. The circuit includes a voltage rail connected to the output node via a voltage rail switch; an anchor node connected to the output node via an inductor and a bidirectional switch, wherein the bidirectional switch includes two or more transistors connected in series; and a control unit configured to change the voltage at the output node by controlling the voltage rail switch and the bidirectional switch so that, if a load capacitance is connected to the output node, a resonant circuit is established between the inductor and the load capacitance. The circuit may be included in an apparatus for use in processing charged particles, e.g. for use in performing mass spectrometry or ion mobility spectrometry. | 2014-11-27 |
20140347105 | COMPENSATION OF SLOW TIME-VARYING VARIATIONS IN VOLTAGE CONTROLLED OSCILLATOR (VCO) FREQUENCY IN CELLULAR TRANSCEIVERS - Various configurations and arrangements of systems and methods for compensating for variations in VCO output frequencies are described. A system in accordance with the disclosure can include an oscillator circuit including an oscillator, a first variable capacitance diode coupled to the oscillator and a second variable capacitance diode coupled to the oscillator. The system further includes a voltage source configured to apply a first voltage to the oscillator circuit to cause the output signal to comprise a selected frequency, the selected frequency being based on a received reference voltage. The system further includes a controller circuit configured to compare an operating voltage of the oscillator to the reference voltage while the first voltage is applied to the oscillator; and apply a second voltage to the oscillator circuit based on the comparison. The second voltage compensates for a difference between the reference voltage and the first voltage. | 2014-11-27 |
20140347106 | DELAY-LOCKED LOOP (DLL) OPERATION MODE CONTROLLER CIRCUIT AND METHOD FOR CONTROLLING THEREOF - A delay-locked loop (DLL) operation mode control circuit and corresponding method are provided in which one of the output values from a display driver IC (DDI) is detected to switch a DLL block to standby mode. In examples, a CLKP/N frequency and CLKP/N common terminal voltage status are used to switch mode. Accordingly, since inoperable frequency domains otherwise present in a normal mode interval of the DLL block is included into standby mode, more stable operation of the DLL circuit is provided. | 2014-11-27 |
20140347107 | DELAY-LOCKED LOOP (DLL) CIRCUIT APPARATUS AND METHOD FOR LOCKING THEREOF - A DLL circuit apparatus and a DLL locking method are provided. A control signal voltage value corresponding to a DLL locking state is stored, and a DLL unlocking state is detected when a change in control signal voltage value or a phase difference of clock signals occurs. When the DLL unlocking occurs, the DLL is locked again using the stored control signal voltage value. Accordingly, DLL unlocking from DLL locking state is quickly detected, and a fast DLL locking time occurs. | 2014-11-27 |
20140347108 | METHOD AND APPARATUS FOR SOURCE-SYNCHRONOUS SIGNALING - A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals. | 2014-11-27 |
20140347109 | HYBRID PHASE-LOCKED LOOPS - A circuit may include an oscillator configured to generate an output signal based on an analog signal and a digital signal and a controller configured to generate an offset signal based on a comparison of a first analog control signal and a second analog control signal. The circuit may also include a divider configured to generate a feedback signal based on the output signal and the offset signal. The circuit may also include an analog control signal unit configured to generate the second analog control signal based on the feedback signal and a reference signal and a coupling unit configured to select either the first analog control signal or the second analog control signal as the analog signal. | 2014-11-27 |
20140347110 | CAPACITIVE LOAD PLL WITH CALIBRATION LOOP - A circuit includes a capacitive-load voltage controlled oscillator having an input configured to receive a first input signal and an output configured to output an oscillating output signal. A calibration circuit is coupled to the voltage controlled oscillator and is configured to output one or more control signals to the capacitive-load voltage controlled oscillator for adjusting a frequency of the oscillating output signal. The calibration circuit is configured to output the one or more control signals in response to a comparison of an input voltage to at least one reference voltage. | 2014-11-27 |
20140347111 | SLEW RATE CONTROL FOR MULTIPLE VOLTAGE DOMAINS - A reference output device includes a low side selector configured to select a first voltage level as an output signal. The output signal is a reference voltage. The reference output device also includes a high side selector configured to select a second voltage level as the output signal. The reference output device also includes a slew rate control configured to switch the output signal between the first voltage level and the second voltage level at a constant slew rate. | 2014-11-27 |
20140347112 | VARIABLE PULSE WIDTH SIGNAL GENERATOR - The present invention concerns a signal generator circuit powered by a supply voltage and including flip flop means including a first input to which is connected a continuous input signal whose amplitude is defined, a second input to which is connected a clock signal whose duty cycle is defined, and a third, reset input, and outputting an output signal whose duty cycle is that of the clock signal and whose amplitude is that of the input signal, characterized in that said circuit further includes regulating means arranged to compare the output signal to a set point signal representative of the desired duty cycle and to deliver a control signal connected to the third input of the flip flop means so as to activate the reset to modify the duty cycle of the output signal. | 2014-11-27 |
20140347113 | POSITIVE EDGE FLIP-FLOP WITH DUAL-PORT SLAVE LATCH - In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. The clock signals CLK and CLKN and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D | 2014-11-27 |
20140347114 | NEGATIVE EDGE FLIP-FLOP WITH DUAL-PORT SLAVE LATCH - In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. The clock signals CLK and CLKN and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CLK and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CLK, CLKN, RET, RETN, SS and SSN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode. | 2014-11-27 |
20140347115 | VOLTAGE LEVEL TRANSLATOR - A voltage level translator includes an inverter circuit configured to switch an output of the inverter circuit between a first voltage level and a second voltage level. The voltage level translator also includes a capacitor connected to the output of the inverter circuit. The voltage level translator also includes a load connected to the capacitor. The capacitance of the capacitor is approximately 10 times larger than a capacitance of the load. An output signal of the voltage level translator has at least one of a different voltage swing and a different voltage domain than an input signal to the inverter circuit. | 2014-11-27 |
20140347116 | LEVEL SHIFT CIRCUIT - A level shift circuit of an embodiment includes first and second MOSFETs using signals with phases same as and opposite to the phase of an input signal as gate inputs; first and second resistance elements, each having one end connected to a shift level power terminal that supplies high-level output voltage of a level-shifted output signal, and each having the other end connected to a corresponding drain of the first and second MOSFETs; a comparator having a pair of differential input terminals, individually connected to respective drains of the first and second MOSFETs; and a current control circuit that controls an amount of first current flowing through the first MOSFET via the first resistance element and an amount of second current flowing through the second MOSFET via the second resistance element in synchronization with a rising and a falling of a signal level of the input signal. | 2014-11-27 |
20140347117 | IMPEDANCE TRANSFORMER FOR USE WITH A QUADRATURE PASSIVE CMOS MIXER - An impedance transformer for use with a quadrature passive mixer is disclosed. In an exemplary embodiment, an apparatus includes a mixer configured to generate an up-converted signal at a mixer output port in response to local oscillator (LO) signals, and an impedance transformer configured to provide a complex impedance at the mixer output port. The complex impedance configured to generate a selected level of the reverse isolation for the mixer thereby generating a selected amplitude flatness symmetry characteristic for the up-converted signal. | 2014-11-27 |
20140347118 | ELECTRONIC SWITCH WITH COMPENSATION OF NON-LINEAR DISTORTIONS - An electronic switch contains an input terminal, and output terminal and at least one first switch element, which provides a voltage-dependent characteristic. In this context, the first switch element connects the input terminal to the output terminal in a selective manner. The electronic switch further comprises a compensation element, which provides a voltage-dependent characteristic. In this context, the compensation element is arranged in such a manner that it at least partially compensates the frequency-dependent characteristic of the switch element. | 2014-11-27 |
20140347119 | CIRCUIT ARRANGEMENT - A circuit arrangement including a first transistor, a second transistor and a third transistor. The first transistor and the second transistor are configured so that the current flowing through the first transistor is proportional to the current flowing through the second transistor and the third transistor. The first transistor, the second transistor and the third transistor are configured to operate in an ohmic mode. The second transistor and the third transistor are coupled in series to each other. The first transistor, the second transistor and the third transistor match each other in at least one characteristic. | 2014-11-27 |
20140347120 | Controlled Transformation of Non-Transient Electronics - Systems and methods of the invention generally relate to altering the functionality of a non-transient electronic device. A container holding an agent is located proximal to a non-transient electronic device capable of performing at least one function. The agent is capable of rendering the device incapable of performing the at least one function. The container is configured to controllably release the agent to the electronic device in a variety of passive and active eventualities. | 2014-11-27 |
20140347121 | LOCAL VOLTAGE CONTROL FOR ISOLATED TRANSISTOR ARRAYS - Self-biasing transistor switching circuitry includes a main transistor, a biasing transistor, a first capacitor, and a second capacitor. The body of the main transistor is isolated from the gate, the drain, and the source of the main transistor by an insulating layer. The first capacitor is coupled between the source and the gate of the main transistor. The second capacitor is coupled between the source and the body of the main transistor. The body and the drain of the main transistor are coupled together. The gate and the drain of the biasing transistor are coupled to the gate of the main transistor. The drain of the biasing transistor is coupled to the drain of the main transistor. The self-biasing transistor switching circuitry is adapted to receive an oscillating signal at the drain of the main transistor, and use the oscillating signal to appropriately bias the main transistor. | 2014-11-27 |
20140347122 | PERIODICALLY RESETTING INTEGRATION ANGLE DEMODULATION DEVICE AND METHOD USING THE SAME - A periodically resetting integration angle demodulation device and a method using the same is disclosed, which uses a waveform multiplier and a periodically resetting integrator to modulate a continuous-time angle modulation signal into a discrete-time signal. The waveform multiplier multiplies the continuous-time angle modulation signal by a square wave signal whose frequency is integer times a carrier frequency, and then transmits the continuous-time angle modulation signal to a periodically resetting integrated circuit. The periodically resetting integrated circuit performs integration during a carrier period to generate a discrete-time angle modulation output signal. The present invention can greatly reduce the difficulty for designing an optical sensing system in the front end without limiting a modulation depth. Besides, the present invention achieves a small volume, high speed, high sensitivity, high reliability, high performance and high condition-adapting properties. | 2014-11-27 |
20140347123 | AMPLIFIER - An amplifier ( | 2014-11-27 |
20140347124 | POWER AMPLIFIER CONTROL CIRCUITS - Circuits for reducing power consumption in power amplifier circuits are disclosed. In certain embodiments, a circuit for power control in the transmitter includes a coupling circuit, a first power amplifier circuit and a second power amplifier circuit. The coupling circuit includes a primary winding inductively associated with a first secondary winding and a second secondary winding. The coupling circuit provides a signal at output terminals of the first secondary winding and the second secondary winding in response to a signal at the primary winding. A first power amplifier circuit is coupled with output terminals of the first secondary winding, and a second power amplifier is coupled with output terminals of the second secondary winding. The first power amplifier circuit and second power amplifier circuit are configured to be enabled or disabled based on a bias voltage. | 2014-11-27 |
20140347125 | EFFICIENT POWER AMPLIFICATION OVER LARGE OPERATING AVERAGE POWER RANGE - Embodiments of a Doherty power amplifier that maintain efficiency over a large operating average power range are disclosed. In one embodiment, the Doherty power amplifier includes reconfigurable main and auxiliary output matching networks and a fixed combining network. The reconfigurable main and auxiliary output matching networks can be reconfigured such that together the reconfigurable main output matching network, the reconfigurable auxiliary output matching network, and the fixed combining network provide proper load modulation for multiple different back-off power levels. As a result, the Doherty power amplifier maintains high efficiency over an extended back-off power level range. | 2014-11-27 |
20140347126 | LOW COMPLEXITY DIGITAL PREDISTORTION FOR CONCURRENT MULTI-BAND TRANSMITTERS - Systems and methods are disclosed for digital predistortion for a concurrent multi-band transmitter using a single adaptor and a same set of predistortion coefficients for separate digital predistorters for each band. In one embodiment, the single adaptor is configured to adaptively configure a set of predistortion coefficients based on a memory polynomial digital baseband model of the digital predistorters having a same set of predistortion coefficients for each of the digital predistorters. By using the same set of predistortion coefficients for the separate digital predistorters for each band, a complexity of the digital predistortion is substantially reduced. | 2014-11-27 |
20140347127 | SWITCHING POWER AMPLIFIER AND METHOD FOR CONTROLLING THE SWITCHING POWER AMPLIFIER - A switching power amplifier includes: a first transistor controlled by a first digital signal to selectively output a first output signal; a second transistor controlled by a second digital signal to selectively output a second output signal; and a control circuit arranged to generate the second digital signal according to the first digital signal and a third digital signal; wherein the first output signal and the second output signal are outputted on a common connected node of the first transistor and the second transistor. | 2014-11-27 |
20140347128 | Digital Class-D Amplifier and Digital Signal Processing Method - A digital class D amplifier ( | 2014-11-27 |