48th week of 2017 patent applcation highlights part 60 |
Patent application number | Title | Published |
20170345724 | METHOD FOR THE FORMATION OF TRANSISTORS PDSO1 AND FDSO1 ON A SAME SUBSTRATE - The present invention relates to a method for forming an electronic device intended to accommodate at least one fully depleted transistor of the FDSOI type and at least one partially depleted transistor of the PDSOI type, from a stack of layers ( | 2017-11-30 |
20170345725 | METHOD OF EXTRACTING DEFECTS - A method provides a design layout having a pattern of features. The design layout is transferred onto a substrate on a semiconductor substrate using a mask. A scanning parameter is determined based on the design layout. An image of the substrate is generated using the determined scanning parameter. A substrate defect is identified by comparing a first number of closed curves in a region of the image and a second number of polygons in a corresponding region of the design layout. | 2017-11-30 |
20170345726 | Testing, Manufacturing, and Packaging Methods for Semiconductor Devices - Methods of testing, manufacturing, and packaging semiconductor devices are disclosed. In some embodiments, a method of testing a semiconductor device includes providing an integrated circuit die having contacts disposed thereon, forming an insulating material over the integrated circuit die and the contacts, and forming an opening in the insulating material over the contacts. A eutectic material is formed in the openings over the contacts, and the integrated circuit die is electrically tested by contacting the eutectic material disposed over the contacts. The eutectic material is removed. | 2017-11-30 |
20170345727 | DEPOSITION SUPPORTING SYSTEM, DEPOSITING APPARATUS AND MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE - According to one embodiment, deposition supporting system, depositing apparatus and manufacturing method of a semiconductor device includes a depositing apparatus that deposits stacked bodies on wafers allocated to stations and a host computer. The host computer evaluates feature amounts convertible to misalignments at predetermined points on the stacked bodies of the respective wafers, and specifies the stations to which the wafers are to be allocated based on the feature amounts of the stacked bodies in the respective stations. The depositing apparatus allocates the wafers to the stations based on the specification from the host computer. | 2017-11-30 |
20170345728 | FLOW METERING FOR DISPENSE MONITORING AND CONTROL - Methods and systems of accurately dispensing a viscous fluid onto a substrate. In an embodiment, a method includes using an electronic flow meter device to produce electrical flow meter output signals and performing a responsive control function in a closed loop manner by adjusting at least one dispensing parameter to correct for a difference between an output data set and a reference data set. In another embodiment, a system includes a control operatively coupled to a gas flow meter device and to a weigh scale allowing for a density of an amount of viscous material to be determined. In another embodiment, a method includes using a control coupled to both a gas flow meter device and a weigh scale and performing a responsive control function in a closed loop manner by adjusting at least one dispensing parameter using gas flow meter output signals and weigh scale output signals. | 2017-11-30 |
20170345729 | SEMICONDUCTOR MODULE - It is an object of the present invention to provide a semiconductor module that reduces an excessive stress on a sealed object due to the expansion and contraction of a sealing gel to thus improve the reliability. A semiconductor module according to the present invention includes: a semiconductor element bonded to a metal pattern on an insulating substrate contained in a case; a sealing gel sealing the insulating substrate and the semiconductor element within the case; and a sealing-gel-expansion suppressing plate disposed in the upper portion of the sealing gel to be at least partially in contact with the sealing gel. The sealing-gel-expansion suppressing plate includes a surface facing the sealing gel and inclined to the upper surface of the sealing gel. | 2017-11-30 |
20170345730 | RESIN COMPOSITION FOR ENCAPSULATING, MANUFACTURING METHOD OF ON-VEHICLE ELECTRONIC CONTROL UNIT, AND ON-VEHICLE ELECTRONIC CONTROL UNIT - Provided is a resin composition for encapsulating which is used for forming an encapsulating resin of an on-vehicle electronic control unit including a wiring substrate, a plurality of electronic components mounted on the wiring substrate, and the encapsulating resin encapsulating the electronic component, the resin composition including: a thermosetting resin; and imidazoles, in which when a torque value is measured over time under conditions of the number of rotations of 30 rpm and a measurement temperature of 175° C. by using Labo Plastomill, a time T | 2017-11-30 |
20170345731 | SENSOR PACKAGES AND MANUFACTURING MEHTODS THEREOF - Sensor packages and manufacturing methods thereof are disclosed. One of the sensor packages includes a semiconductor chip and a redistribution layer structure. The semiconductor chip has a sensing surface. The redistribution layer structure is arranged to form an antenna transmitter structure aside the semiconductor chip and an antenna receiver structure over the sensing surface of the semiconductor chip. | 2017-11-30 |
20170345732 | 3DIC Packaging with Hot Spot Thermal Management Features - A package includes a substrate having a conductive layer, and the conductive layer comprises an exposed portion. A die stack is disposed over the substrate and electrically connected to the conductive layer. A high thermal conductivity material is disposed over the substrate and contacting the exposed portion of the conductive layer. The package further includes a contour ring over and contacting the high thermal conductivity material. | 2017-11-30 |
20170345733 | POWER MODULE - A power module includes a connection terminal for external connection, the connection terminal protruding from the side surface of a package, and a dummy terminal protruding from the side surface of the package and shorter than the connection terminal. The dummy terminal is processed to have a bottom surface with an inclination. In other words, the distance between a plane containing a heat dissipation surface of the package and the dummy terminal increases toward the extremity of the dummy terminal. Accordingly, when a heat dissipation fin is attached to the heat dissipation surface, the extremity of the dummy terminal is more distant from the heat dissipation fin than the rest of the dummy terminal. | 2017-11-30 |
20170345734 | Thermally Conductive Sheet - The thermally conductive sheet includes a sheet-like formed body produced by curing a mixed composition containing an uncured polymer matrix, a flat graphite powder, and a thermally conductive filler having an aspect ratio of 2 or less, flat surfaces of particles of the flat graphite powder being aligned in a thickness direction of the sheet. The thermally conductive sheet contains the thermally conductive filler together with the flat graphite powder and thus contains the thermally conductive material densely charged and has good flexibility and good tackiness on the surfaces of the sheet. | 2017-11-30 |
20170345735 | PLUG-IN TYPE POWER MODULE AND SUBSYSTEM THEREOF - A plug-in type power module includes a power unit and a heat-transfer unit vertically disposed on the power unit and extending outwardly away from two sides of the power unit. A first ceramic layer is disposed between the power unit and the heat-transfer unit. Therefore, heat generated by the power unit can be transferred from the first ceramic layer to the heat-transfer unit to increase the speed of heat dissipation. A subsystem having the plug-in type power module is also provided. | 2017-11-30 |
20170345736 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE - A semiconductor device includes: a semiconductor element; a heat radiator body having a housing recess wherein a bottom surface of the housing recess is thermally connected to the upper surface of the semiconductor element; a heat sink which is thermally connected to an upper surface of the heat radiator body through adhesive agent; a sealing resin which covers the lower surface and a side surface of the heat radiator body, an inner side surface of the housing recess, and the lower surface and a side surface of the semiconductor element; and a wiring structure body formed on a lower surface of the sealing resin. The sealing resin includes a covering portion having an upper surface which is substantially flush with the bottom surface of the housing recess and covering the side surface of the heat radiator body. The adhesive agent contacts the side surface of the heat radiator body. | 2017-11-30 |
20170345737 | ADVANCED THROUGH SUBSTRATE VIA METALLIZATION IN THREE DIMENSIONAL SEMICONDUCTOR INTEGRATION - A method providing a high aspect ratio through substrate via in a substrate is described. The through substrate via has vertical sidewalls and a horizontal bottom. The substrate has a horizontal field area surrounding the through substrate via. A metallic barrier layer is deposited on the sidewalls of the through substrate via. A nitridation process converts a surface portion of the metallic barrier layer to a nitride surface layer. The nitride surface layer enhances the nucleation of subsequent depositions. A first metal layer is deposited to fill a portion of the through substrate via and cover the horizontal field area. A thermal anneal step to reflow a portion of the first metal layer on the horizontal field area into the through substrate via. A second metal layer is deposited over the first metal layer to fill a remaining portion of the through substrate via. Another aspect of the invention is a device created by the method. | 2017-11-30 |
20170345738 | ADVANCED THROUGH SUBSTRATE VIA METALLIZATION IN THREE DIMENSIONAL SEMICONDUCTOR INTEGRATION - A method providing a high aspect ratio through substrate via in a substrate is described. The through substrate via has vertical sidewalls and a horizontal bottom. The substrate has a horizontal field area surrounding the through substrate via. A first metallic barrier layer is deposited on the sidewalls of the through substrate via. A nitridation process converts a surface portion of the metallic barrier layer to a nitride surface layer. The nitride surface layer enhances the nucleation of subsequent depositions. A first metal layer is deposited to fill the through substrate via. A selective etch creates a recess in the first metal layer in the through substrate via. A second barrier layer is deposited over the recess. A second metal layer is patterned over the second barrier layer filling the recess and creating a contact. Another aspect of the invention is a device produced by the method. | 2017-11-30 |
20170345739 | ADVANCED THROUGH SUBSTRATE VIA METALLIZATION IN THREE DIMENSIONAL SEMICONDUCTOR INTEGRATION - An advanced through silicon via structure for is described. The device includes a substrate including integrated circuit devices. A high aspect ratio through substrate via is disposed in the substrate. The through substrate via has vertical sidewalls and a horizontal bottom. The substrate has a horizontal field area surrounding the through substrate via. A metallic barrier layer is disposed on the sidewalls of the through substrate via. A surface portion of the metallic barrier layer has been converted to a nitride surface layer by a nitridation process. The nitride surface layer enhances the nucleation of subsequent depositions. A first metal layer fills the through substrate via and has a recess in an upper portion. A second barrier layer is disposed over the recess. A second metal layer is disposed over the second barrier layer and creates a contact. | 2017-11-30 |
20170345740 | SEMICONDUCTOR PACKAGE, SMART CARD AND METHOD FOR PRODUCING A SEMICONDUCTOR PACKAGE - A semiconductor package includes a chip, a layer which is thermally coupled to the chip and which is formed from a material having a triggering temperature of greater than or equal to 200° C., starting from which an exothermic reaction takes place, and encapsulating material which at least partly covers the chip and the layer. The layer is configured in such a way and is arranged relative to the chip in such a way that, in the case of a triggered exothermic reaction of the material of the layer, at least one component of the chip is damaged on account of the temperature increase caused by the exothermic reaction. | 2017-11-30 |
20170345741 | INTEGRATED FAN-OUT PACKAGE AND METHOD OF FABRICATING THE SAME - An integrated fan-out package is described. The integrated fan-out package comprises a first die and a second die arranged adjacent to each other. A molding compound encapsulates the first and second dies. A redistribution structure is disposed over the molding compound and on the first and second dies. The redistribution structure comprises a first connection structure electrically connected to the first die, a second connection structure electrically connected to the second die and an inter-dielectric layer located between the first and second connection structures and separating the first connection structure from the second connection structure. The ball pad is disposed on the redistribution structure and electrically connected with the first die or the second die. The bridge structure is disposed on the first connection structure and on the second connection structure and electrically connects the first die with the second die. | 2017-11-30 |
20170345742 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A lead frame includes a plurality of circuit patterns which each have a die pad and an electrode terminal portion and are disposed in a band shape, a tie bar, a frame portion and a suspension lead. Cut are a connection portion between electrode terminals and the frame portion, a connection portion between the frame portion and the tie bar at both end portions in a disposition direction of circuit patterns, and a connection portion from a connection part of the frame portion with the tie bar, between the circuit patterns to a part of the frame portion extending in the disposition direction. The electrode terminal portion is bent to extend to a direction of an upper surface of a semiconductor element. The lead frame is collectively resin-sealed while exposing the tie bar and the electrode terminal portion above the tie bar. | 2017-11-30 |
20170345743 | LEADFRAME STRIP WITH VERTICALLY OFFSET DIE ATTACH PADS BETWEEN ADJACENT VERTICAL LEADFRAME COLUMNS - A leadframe strip for use in making leaded integrated circuit packages includes a plurality of integrally connected leadframes that each have a die attach pad and first and second dam bars located adjacent to opposite first and second sides of the die attach pad, respectively. A plurality of continuous lead structures extend, uninterrupted by other structure, between opposing ones of the dam bars of horizontally adjacent leadframes. The plurality of integrally connected leadframes are arranged in a plurality of vertical columns, wherein die attach pads in one vertical column are vertically offset from die attach pads in adjacent vertical columns. | 2017-11-30 |
20170345744 | EXPOSED SOLDERABLE HEAT SPREADER FOR FLIPCHIP PACKAGES - A flipchip may include: a silicon die having a circuit side with solder bumps and a non-circuit side; a leadframe attached to the solder bumps on the circuit side of the silicon die; a heat spreader attached to the non-circuit side of the silicon die; and encapsulation material encapsulating the silicon die, a portion of the leadframe, and all but one exterior surface of the heat spreader. The leadframe may have NiPdAu plating on the portion that is not encapsulated by the encapsulation material and no plating on the portion that is attached to the solder bumps. | 2017-11-30 |
20170345745 | HIGH DENSITY SEMICONDUCTOR PACKAGE AND RELATED METHODS - Implementations of semiconductor packages may include: a first semiconductor die having a plurality of balls coupled to a first side thereof, a second semiconductor die, a lead frame having a die attach area on a first side of the lead frame, the die attach area containing an opening therethrough and one or more wire bonds. The first semiconductor die may be coupled to a backside of the second semiconductor die by an adhesive on a second side of the first semiconductor die opposing the first side. The second semiconductor die may be mechanically and electrically coupled to the lead frame through one or more wire bonds at the die attach area. The first semiconductor die may be positioned within the opening in the center of the lead frame. | 2017-11-30 |
20170345746 | INTEGRATED CIRCUIT PACKAGE WITH SOLDER BALLS ON TWO SIDES - An integrated circuit package with solder balls on two major sides of the package and a method of making. The integrated circuit package includes at least one die encapsulated in an encapsulant. A work piece panel is formed with encapsulated die. Solder balls are attached to two major opposing sides of the panel. Afterwards, the panel is singulated into individual integrated circuit packages. | 2017-11-30 |
20170345747 | MULTILAYER SUBSTRATE AND MANUFACTURING METHOD FOR SAME - A multilayer substrate includes a component mounting substrate having component mounting and non-mounting surfaces and including connection pads on both the mounting surfaces, a sealing resin layer having an upper surface in close contact with the non-mounting surface and a flat lower surface, a semiconductor element having an electrode formation surface on which electrodes are formed, and embedded in the sealing resin layer with the electrode formation surface exposed at the flat lower surface, an insulating layer formed in close contact with the electrode formation surface and the flat lower surface, through-holes continuously penetrating through the insulating layer and the sealing resin layer and having bottom ends defined by the connection pads on the non-mounting substrate, via holes penetrating through the insulating layer and having bottom ends defined by the electrodes, and wiring conductors formed inside the through-holes and the via holes and on a surface of the insulating layer. | 2017-11-30 |
20170345748 | COMPOUND CARRIER BOARD STRUCTURE OF FLIP-CHIP CHIP-SCALE PACKAGE AND MANUFACTURING METHOD THEREOF - A compound carrier board structure of Flip-Chip Chip-Scale Package and manufacturing method thereof provides a baseplate with an opening bonded to a carrier board in order to form a compound carrier board structure. A die is placed in the opening and bonded to the carrier board. A sealant is filled in a gap between surrounding walls of the opening and the die at a height lower than the die to fixedly place the die within the opening and to leave a non-active surface of the die exposed. | 2017-11-30 |
20170345749 | POWER COMMUTATION MODULE - A power commutation module includes a printed circuit board, a first plate-shaped bus bar, and a first plurality of power switches each including a plurality of connection pins which are connected on the upper face of the printed circuit board and a metal base plate which is applied against the bus bar. The first plurality of power switches is mounted on the first bus bar. The power switches are generally aligned along a longitudinal edge of the first bus bar, in that said longitudinal edge of the first bus bar is arranged along a first longitudinal edge of the printed circuit board, and the portion of the first bus bar on which the power switches are mounted is arranged next to the printed circuit board. | 2017-11-30 |
20170345750 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Characteristics of a semiconductor device are improved. The semiconductor device is configured to include an SOI substrate including an active region and an element isolation region (element isolation insulating film), a gate electrode formed in the active region via a gate insulating film, and a dummy gate electrode formed in the element isolation region. A dummy sidewall film is formed on both sides of the dummy gate electrode, and is arranged to match or overlap a boundary between the active region and the element isolation region (element isolation insulating film). According to such a configuration, a plug can be prevented from deeply reaching, for example, an insulating layer and a support substrate even when a contact hole is formed to be shifted. | 2017-11-30 |
20170345751 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first line pattern and a second line pattern formed in parallel on a semiconductor substrate, third line patterns formed in parallel between the first line pattern and the second line pattern, fourth line patterns formed in parallel between the first line pattern and the second line pattern, a first connection structure configured to couple a first of the third line patterns with a first of the fourth lines patterns, which are adjacent to the first line pattern, and a second connection structure configured to couple a second of the first lines patterns with a second of the fourth lines patterns, which are adjacent to the second line pattern. | 2017-11-30 |
20170345752 | DEVICES AND METHODS OF FORMING LOW RESISTIVITY NOBLE METAL INTERCONNECT - Devices and methods of fabricating integrated circuit devices for forming low resistivity interconnects are provided. One method includes, for instance: obtaining an intermediate semiconductor interconnect device having a substrate, a cap layer, and a dielectric matrix including a set of trenches and a set of vias; depositing a barrier layer along a top surface of the semiconductor interconnect device; depositing and annealing a metal interconnect material over a top surface of the barrier layer, wherein the metal interconnect material fills the set of trenches and the set of vias; planarizing a top surface of the intermediate semiconductor interconnect device; exposing a portion of the barrier layer between the set of trenches and the set of vias; and depositing a dielectric cap. Also disclosed is an intermediate device formed by the method. | 2017-11-30 |
20170345753 | INTEGRATED CIRCUIT HAVING SLOT VIA AND METHOD OF FORMING THE SAME - An integrated circuit includes a first conductive line on a first metal level of the integrated circuit. The integrated circuit further includes a second conductive line on a second metal level of the integrated circuit. The integrated circuit further includes a slot via electrically connecting the first conductive line with the second conductive line. The slot via overlaps with the first conductive line and the second conductive line. The slot via extends beyond a periphery of at least one of the first conductive line or the second conductive line. | 2017-11-30 |
20170345754 | THREE-DIMENSIONAL INDUCTOR STRUCTURE AND STACKED SEMICONDUCTOR DEVICE INCLUDING THE SAME - A three-dimensional (3D) inductor structure comprising: a first semiconductor die including: a first conductive pattern; and a second conductive pattern spaced apart from the first conductive pattern; a second semiconductor die stacked on the first semiconductor die, the second semiconductor die including: a third conductive pattern; a fourth conductive pattern spaced apart from the third conductive pattern; a first through-substrate via (TSV) penetrating the second semiconductor die and electrically connecting the first conductive pattern with the third conductive pattern; and a second TSV penetrating the second semiconductor die and electrically connecting the second conductive pattern with the fourth conductive pattern, and a first conductive connection pattern included in the first semiconductor die and electrically connecting a first end of the first conductive pattern with a first end of the second conductive pattern, or included in the second semiconductor die and electrically connecting a first end of the third conductive pattern with a first end of the fourth conductive pattern. | 2017-11-30 |
20170345755 | SEMICONDUCTOR DEVICE, ELECTRICAL ENERGY MEASUREMENT INSTRUMENT, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device | 2017-11-30 |
20170345756 | POWER MODULE AND POWER DEVICE - A power module and a power device having the power module are disclosed. The power device includes a main board. The power module is inserted in the main board and includes a PCB, a magnetic element, a primary winding circuit and at least one secondary winding circuit. The magnetic element is provided on the PCB and includes a core structure, a primary winding and at least one secondary winding. The core structure has a first side and a second side opposite to each other, and a third side and a fourth side opposite to each other. The primary winding circuit is provided on the PCB and positioned in the vicinity of the first or second side of the core structure. The secondary winding circuit is provided on the PCB and positioned in the vicinity of the third or fourth side of the core structure. | 2017-11-30 |
20170345757 | ANTIFUSE HAVING COMB-LIKE TOP ELECTRODE - Antifuse structures are provided for use in applications such as field programmable gate arrays and programmable read-only memories. High aspect ratio channels within an antifuse dielectric layer are used to form antifuse electrode projections. The projections are configured to enhance the electric field across the antifuse structures, thereby facilitating dielectric breakdown. The antifuse structures can enable low-voltage programming. | 2017-11-30 |
20170345758 | Electrical Fuse Structure and Method of Formation - Various fuse structures are disclosed herein that exhibit improved performance, such as reduced electro-migration. An exemplary fuse structure includes an anode, a cathode, and a fuse link extending between the anode and the cathode. A plurality of anode contacts are coupled to the anode, and a plurality of cathode contacts are coupled to the cathode. The plurality of cathode contacts are arranged symmetrically with respect to a centerline of the fuse link. | 2017-11-30 |
20170345759 | A METHOD OF FORMING CONTACT TRENCH - A method of fabricating a semiconductor device is disclosed. The method includes forming a first gate stack and a second gate stack over a substrate. Each of them has gate spacers disposed along its respective sidewalls. The method also includes forming a source/drain (S/D) feature disposed between the first and second gate stacks. The gate spacers and a top surface of the S/D feature define a space. The method also includes forming a first dielectric layer over the S/D feature in the space, forming a capping layer along the gate spacers in the space, forming a second dielectric layer over the first dielectric layer in the space and forming a contact trench extending through the second dielectric layer, the first dielectric layer and the capping layer to expose the top surface of the S/D feature. | 2017-11-30 |
20170345760 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME - The semiconductor device includes: a transistor having a gate electrode formed on a semiconductor substrate and first and second source/drain regions formed in portions of the semiconductor substrate on both sides of the gate electrode; a gate interconnect formed at a position opposite to the gate electrode with respect to the first source/drain region; and a first silicon-germanium layer formed on the first source/drain region to protrude above the top surface of the semiconductor substrate. The gate interconnect and the first source/drain region are connected via a local interconnect structure that includes the first silicon-germanium layer. | 2017-11-30 |
20170345761 | PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A package structure has a first die, a second die, the third die, a molding compound, a first redistribution layer, an antenna and conductive elements. The first die, the second die and the third die are molded in a molding compound. The first redistribution layer is disposed on the molding compound and is electrically connected to the first die, the second die and the third die. The antenna is located on the molding compound and electrically connected to the first die, the second die and the third die, wherein a distance of an electrical connection path between the first die and the antenna is smaller than or equal to a distance of an electrical connection path between the second die and the antenna and a distance of an electrical connection path between the third die and the antenna. The conductive elements are connected to the first redistribution layer, wherein the first redistribution layer is located between the conductive elements and the molding compound. | 2017-11-30 |
20170345762 | CONDUCTIVE PATTERN AND INTEGRATED FAN-OUT PACKAGE HAVING THE SAME - A conductive pattern including a teardrop shaped portion, a routing line, and a connection portion is provided. The routing line links to the teardrop shaped portion through the connection portion, and a width of the connection portion decreases along an extending direction from the teardrop shaped portion to the routing line. Furthermore, an integrated fan-out package including the above-mentioned conductive pattern is also provided. | 2017-11-30 |
20170345763 | FLEXIBLE PACKAGING ARCHITECTURE - A flexible packaging architecture is described that is suitable for curved package shapes. In one example a package has a first die, a first mold compound layer over the first die, a wiring layer over the first mold compound layer, a second die over the wiring layer and electrically coupled to the wiring layer, and a second mold compound layer over the second die. | 2017-11-30 |
20170345764 | INTEGRATED FAN-OUT PACKAGE AND METHOD OF FABRICATING THE SAME - A method for fabricating an integrated fan-out package is provided. The method includes the following steps. A plurality of conductive posts are placed in apertures of a substrate. A carrier having an adhesive thereon is provided. The conductive posts are transferred to the carrier in a standing orientation by adhering the conductive posts in the apertures to the adhesive. An integrated circuit component is mounted onto the adhesive having the conductive posts adhered thereon. An insulating encapsulation is formed to encapsulate the integrated circuit component and the conductive posts. A redistribution circuit structure is formed on the insulating encapsulation, the integrated circuit component, and the conductive posts, wherein the redistribution circuit structure is electrically connected to the integrated circuit component and the conductive posts. The carrier is removed. At least parts of the adhesive are removed (e.g. patterned or entirely removed) to expose surfaces of the conductive posts. A plurality of conductive terminals are formed on the surfaces of the conductive posts exposed by the openings. | 2017-11-30 |
20170345765 | CONTACT STRUCTURE AND FORMATION THEREOF - A semiconductor device and methods of formation are provided. A semiconductor device includes an annealed cobalt plug over a silicide in a first opening of the semiconductor device, wherein the annealed cobalt plug has a repaired lattice structure. The annealed cobalt plug is formed by annealing a cobalt plug at a first temperature for a first duration, while exposing the cobalt plug to a first gas. The repaired lattice structure of the annealed cobalt plug is more regular or homogenized as compared to a cobalt plug that is not so annealed, such that the annealed cobalt plug has a relatively increased conductivity or reduced resistivity. | 2017-11-30 |
20170345766 | DEVICES AND METHODS OF FORMING LOW RESISTIVITY NOBLE METAL INTERCONNECT WITH IMPROVED ADHESION - Devices and methods of fabricating integrated circuit devices for forming low resistivity interconnects with improved adhesion are provided. One method includes, for instance: obtaining an intermediate semiconductor interconnect device having a substrate, a cap layer, and a dielectric matrix including a set of trenches and a set of vias; depositing a metal interconnect material directly over and contacting a top surface of the dielectric matrix, wherein the metal interconnect material fills the set of trenches and the set of vias; depositing a barrier layer over a top surface of the device; annealing the barrier layer to diffuse the barrier layer to a bottom surface of the metal interconnect material; planarizing a top surface of the intermediate semiconductor interconnect device; and depositing a dielectric cap over the intermediate semiconductor interconnect device. | 2017-11-30 |
20170345767 | MULTILAYER WIRING SUBSTRATE, DISPLAY UNIT, AND ELECTRONIC APPARATUS - In a case of a multilayer wiring structure in which an insulating layer provided between wires is made of a material having high transmittance of light in a visible range containing ultraviolet rays, wires in the upper layer and those in a lower layer may be recognized together when defects of an upper layer are visually inspected. In this case, the lower layer may be noise for the inspection of the wires in the upper layer, lowering inspection accuracy. This lowered inspection accuracy has inhibited improvement in manufacturing yields and reliability. In order to solve this issue, a multilayer wiring substrate of the disclosure includes: a substrate; and a first wire and a second wire that are provided on the substrate with an insulating layer having a light transmitting property in between, and one or both of which are subjected to a surface treatment. | 2017-11-30 |
20170345768 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate including a main chip region and a remaining scribe lane region surrounding the main chip region, a passivation layer on the main chip region, the passivation layer including a plurality of bridge patterns extending from the main chip region in a first direction across the remaining scribe lane region, a plurality of bump pads exposed by the passivation layer on the main chip region, a plurality of dam structures along edges of the main chip region on the remaining scribe lane region, the plurality of bridge patterns arranged on the plurality of dam structures at a first pitch in the first direction, a seed layer on the plurality of bump pads, and bumps on the seed layer. | 2017-11-30 |
20170345769 | SEAL RING STRUCTURE AND FABRICATION METHOD THEREFOR - A method of fabricating a semiconductor structure. The method includes forming a dummy structure over a semiconductor body. The method further includes depositing an inter-layer dielectric (ILD) over the semiconductor body. The method further includes removing a dummy material of the dummy structure to form an opening in the ILD. The method further includes filling the opening with a dielectric material to form a dielectric structure. The method further includes stacking a plurality of interconnect elements over the dielectric structure. | 2017-11-30 |
20170345770 | METHOD FOR MAKING EMI SHIELDING LAYER ON A PACKAGE - A method for making EMI shielding layer of a package is disclosed to include the steps of: a) disposing a UV curable adhesive, which can be thermally released, on a surface of a package panel having solder pads to cover the solder pads; b) curing the UV curable adhesive; c) performing a singulating process to form the plurality of the packages disposed by the UV curable adhesive; d) forming an EMI shielding layer on the package; and e) thermally releasing the UV curable adhesive. | 2017-11-30 |
20170345771 | PACKAGE SUBSTRATE WITH EMBEDDED NOISE SHIELDING WALLS - A package substrate with embedded noise shielding walls is disclosed. One of the embodiment comprises a signal line S sandwiched by a left shielding wall W | 2017-11-30 |
20170345772 | METHODS AND APPARATUS FOR SCRIBE STREET PROBE PADS WITH REDUCED DIE CHIPPING DURING WAFER DICING - An example apparatus includes a semiconductor wafer with a plurality of probe pads each formed centered in scribe streets and intersected by saw kerf lanes. Each probe pad includes a plurality of lower level conductor layers arranged in lower level conductor frames, a plurality of lower level vias extending vertically through lower level insulator layers and electrically coupling the lower level conductor frames; a plurality of upper level conductor layers, each forming two portions on two outer edges of the probe pad, the two portions aligned with, spaced from, and on opposite sides of the saw kerf lane, the coverage of the upper level conductor layers being less than about twenty percent; and a plurality of upper level vias extending vertically through upper level insulator layers and coupling the upper level conductor layers electrically to one another and to the lower level conductor layers. Methods are disclosed. | 2017-11-30 |
20170345773 | SEMICONDUCTOR DEVICES - The semiconductor devices may include a semiconductor substrate, and a guard ring and a crack sensing circuit on the semiconductor substrate. The semiconductor substrate may include a main chip region that is defined by the guard ring and includes the crack sensing circuit, a central portion of the main chip region surrounded by the crack sensing circuit, and a chamfer region that is in a corner portion of the main chip region and is defined by the guard ring and the crack sensing circuit. The semiconductor devices may also include at least one gate structure on the semiconductor substrate in the main chip region, a plurality of metal pattern structures on the at least one gate structure in the chamfer region, and an insulating layer on the plurality of metal pattern structures. The plurality of metal pattern structures may extend in parallel to one another and may have different lengths. | 2017-11-30 |
20170345774 | CRACK PROPAGATION PREVENTION AND ENHANCED PARTICLE REMOVAL IN SCRIBE LINE SEALS OF SEMICONDUCTOR DEVICES - Disclosed embodiments include an integrated circuit having a semiconductor substrate with insulator layers and conductor layers overlying the semiconductor substrate. A scribe region overlying the semiconductor substrate and a periphery of the integrated circuit includes a crack arrest structure and a scribe seal. The crack arrest structure provides first vertical conductor structure that surrounds the periphery of the integrated circuit. The scribe seal is spaced from and surrounded by the crack arrest structure and provides a second vertical conductor structure. The scribe seal includes first and second vias spaced from each other and connected to one of the conductor layers. The first via is a trench via and the second via is a stitch via, with the second via being located closer to the crack arrest structure than the first via. | 2017-11-30 |
20170345775 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device with improved reliability is provided. The semiconductor device is characterized by its embodiments in that sloped portions are formed on connection parts between a pad and a lead-out wiring portion, respectively. This feature suppresses crack formation in a coating area where a part of the pad is covered with a surface protective film. | 2017-11-30 |
20170345776 | Thermal Flow Meter - Provided is a thermal flow meter that can be prevented from being eroded due to adhesion of water or like to a cut end portion of the lead exposed from the mold resin of the circuit package. A thermal flow meter | 2017-11-30 |
20170345777 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A first film ( | 2017-11-30 |
20170345778 | HYPERFREQUENCY HOUSING OCCUPYING A SMALL SURFACE AREA AND MOUNTING OF SUCH A HOUSING ON A CIRCUIT - A package, able to encapsulate at least one component, forming a closed cavity of Faraday cage type having side walls resting on a base and that are surmounted by a cover, wherein at least one of the side walls includes exterior electrical connection elements linked electrically to the interior of the cavity, the exterior connection elements able to interconnect with an exterior circuit such that the side wall faces the exterior circuit when the exterior connection elements are interconnected with the circuit. | 2017-11-30 |
20170345779 | POLYMER RESIN AND COMPRESSION MOLD CHIP SCALE PACKAGE - A method for fabricating a chip scale package, comprising: providing a wafer; applying a polymer resin on at least part of a first surface of the wafer and to one or more sides of the wafer; and applying a compression mold on at least part of a second surface of the wafer and to one or more sides of the wafer, said first and second surfaces opposing each other. | 2017-11-30 |
20170345780 | Surface Conditioning And Material Modification In A Semiconductor Device - A plasma-based ashing process for surface conditioning and material modification to improve bond pad metallurgical properties as well as semiconductor device performance. Residue materials generated in a removal process at a process layer having recessed features with Ni—Pd surfaces are ashed in a plasma reactor to reduce defect count and improve surface conditioning associated with bond pads of the semiconductor device. | 2017-11-30 |
20170345781 | ELEMENT CHIP MANUFACTURING METHOD - An element chip manufacturing method includes a preparation process of preparing a substrate which includes a first surface having an exposed bump and a second surface opposite to the first surface and includes a plurality of element regions defined by dividing regions, a bump embedding process of embedding at least a head top part of the bump into the adhesive layer, a mask forming process of forming a mask in the second surface. The method for manufacturing the element chip includes a holding process of arranging the first surface to oppose a holding tape supported on a frame and holding the substrate on the holding tape, a placement process of placing the substrate on a stage provided inside of a plasma processing apparatus through the holding tape, after the mask forming process and the holding process. | 2017-11-30 |
20170345782 | CONNECTION STRUCTURE AND CONNECTING METHOD OF CIRCUIT MEMBER - There is provided a connection structure of a circuit member including: a first circuit member having a first main surface provided with a first electrode; a second circuit member having a second main surface provided with a second electrode; and a joining portion which is interposed between the first main surface and the second main surface, in which the joining portion has a solder portion which electrically connects the first electrode and the second electrode to each other, in which the solder portion contains a bismuth-indium alloy, and in which an amount of bismuth contained in the bismuth-indium alloy exceeds | 2017-11-30 |
20170345783 | BUMP ON PAD (BOP) BONDING STRUCTURE IN SEMICONDUCTOR PACKAGED DEVICE - The embodiments described above provide enlarged overlapping surface areas of bonding structures between a package and a bonding substrate. By using elongated bonding structures on either the package and/or the bonding substrate and by orienting such bonding structures, the bonding structures are designed to withstand bonding stress caused by thermal cycling to reduce cold joints. | 2017-11-30 |
20170345784 | Manufacturing Method for Electronic Element - The present invention provides a manufacturing method for an electronic element of an electronic apparatus. The electronic element includes a substrate, a bump and at least one under bump metal (UBM) layer. The manufacturing method includes sequentially disposing the UBM layer and the bump onto the substrate; and processing an etching operation at the UBM layer to form a breach structure. | 2017-11-30 |
20170345785 | Contact Area Design for Solder Bonding - A package component includes a dielectric layer and a metal pad over the dielectric layer. A plurality of openings is disposed in the metal pad. The first plurality of openings is separated from each other by portions of the metal pad, with the portions of the metal pad interconnected to form a continuous metal region. | 2017-11-30 |
20170345786 | Structure and Method of Forming a Joint Assembly - A method of manufacturing a semiconductor device structure includes forming a bond or joint between a first device and a second device. The first device comprises an integrated passive device (IPD) and a first contact pad disposed over the IPD. The second device comprises a second contact pad. The first contact pad has a first surface with first lateral extents. The second contact pad has a second surface with second lateral extents. The width of the second lateral extents is less than the width of the first lateral extents. The joint structure includes the first contact pad, the second contact pad, and a solder layer interposed therebetween. The solder layer has tapered sidewalls extending in a direction away from the first surface of the first contact pad to the second surface of the second contact pad. At least one of the first surface or the second surface is substantially planar. | 2017-11-30 |
20170345787 | METHODS OF FORMING WIRE INTERCONNECT STRUCTURES - A method of forming a wire interconnect structure includes the steps of: (a) forming a wire bond at a bonding location on a substrate using a wire bonding tool; (b) extending a length of wire, continuous with the wire bond, to another location; (c) pressing a portion of the length of wire against the other location using the wire bonding tool; (d) moving the wire bonding tool, and the pressed portion of the length of wire, to a position above the wire bond; and (e) separating the length of wire from a wire supply at the pressed portion, thereby providing a wire interconnect structure bonded to the bonding location. | 2017-11-30 |
20170345788 | Warpage Control of Semiconductor Die Package - Various embodiments of mechanisms for forming a die package using a compressive dielectric layer to contact and to surround through substrate vias (TSVs) in the die package are provided. The compressive dielectric layer reduces or eliminates bowing of the die package. As a result, the risk of broken redistribution layer (RDL) due to bowing is reduced or eliminated. In addition, the compressive dielectric layer, which is formed between the conductive TSV columns and surrounding molding compound, improves the adhesion between the conductive TSV columns and the molding compound. Consequently, the reliability of the die package is improved. | 2017-11-30 |
20170345789 | Encapsulated Circuit Module, And Production Method Therefor - To provide a technique of preventing, in an encapsulated circuit module having a metal shield layer covering a surface of a resin layer containing filler, the shield layer from falling off. | 2017-11-30 |
20170345790 | LOCKING DUAL LEADFRAME FOR FLIP CHIP ON LEADFRAME PACKAGES - A method of assembling a flip chip on a leadframe package. A locking dual leadframe (LDLF) includes a top metal frame portion including protruding features and a die pad and a bottom metal frame portion having apertures positioned lateral to the die pad. The protruding features and apertures are similarly sized and alignable. A flipped integrated circuit (IC) die having a bottomside and a topside including circuitry connected to bond pads having solder balls on the bond pads is mounted with its topside onto the top metal frame portion. The top metal frame portion is aligned to the bottom metal frame portion so that the protruding features are aligned to the apertures. The bottomside of the IC die is pressed with respect to a top surface of the bottom frame portion, wherein the protruding features penetrate into the apertures. | 2017-11-30 |
20170345791 | Integrated Circuit Structure with Active and Passive Devices in Different Tiers - An integrated circuit structure includes a two-tier die including a first tier and a second tier over and bonded to the first tier. The first tier includes a first substrate including a semiconductor material, an active device at a surface of the first substrate, and a first interconnect structure over the first substrate, wherein the first tier is free from passive devices therein. The second tier includes a second substrate bonded to and in contact with the first interconnect structure, and a second interconnect structure over the second substrate, wherein metal lines in the second interconnect structure are electrically coupled to the first interconnect structure. The second tier further includes a plurality of through-vias penetrating through the second substrate, wherein the plurality of through-vias lands on metal pads in a top metal layer of the first interconnect structure, and a passive device in the second interconnect structure. | 2017-11-30 |
20170345792 | HALF-BRIDGE POWER SEMICONDUCTOR MODULE AND METHOD OF MANUFACTURING SAME - A half-bridge power semiconductor module includes an insulating wiring board including a positive-electrode wiring conductor, a bridge wiring conductor, and a negative-electrode wiring conductor arranged on or above a single insulating plate in such a way as to be electrically insulated from each other. The back-surface electrodes of a high-side power semiconductor device and a low-side power semiconductor device are joined to the front sides of the positive-electrode wiring conductor and the bridge wiring conductor. Front-surface electrodes of the high-side power semiconductor device and the low-side power semiconductor device are connected to the bridge wiring conductor and the negative-electrode wiring conductor by a plurality of bonding wires and a plurality of bonding wires. | 2017-11-30 |
20170345793 | SEMICONDUCTOR DEVICE - A semiconductor device includes an electronic component and a wiring structural body located below the electronic component. The wiring structural body includes an insulation layer and a wiring layer that is connected to an electrode terminal of the electronic component. The semiconductor device also includes a wiring shield body arranged on a side surface of the wiring structural body, an encapsulation resin covering an upper surface of the wiring structural body and a side surface of the electronic component, and a component shield body covering a surface of the encapsulation resin and continuously covering an upper surface side of the electronic component. The wiring shield body is connected to the component shield body. The wiring shield body includes an exposed side surface that is coplanar with a side surface of the component shield body. | 2017-11-30 |
20170345794 | PACKAGE-ON-PACKAGE STRUCTURE WITH EPOXY FLUX RESIDUE - A structure includes a first package and a second package. The second package is coupled to the first package by one or more connectors. Epoxy flux residue is disposed around the connectors and in contact with the connectors. A method includes providing a first package having first connector pads and providing a second package having corresponding second connector pads. Solder paste is printed on each of the first connector pads. Epoxy flux is printed on each of the solder paste. The first and second connector pads are aligned and the packages are pressed together. The solder paste is reflowed to connect the first connector pads to the second connector pads while leaving an epoxy flux residue around each of the connections. | 2017-11-30 |
20170345795 | PACKAGE STRUCTURES, POP DEVICES AND METHODS OF FORMING THE SAME - Package structures, PoP devices and methods of forming the same are disclosed. A package structure includes a first chip, a redistribution layer structure, a plurality of UBM pads, a plurality of connectors and a separator. The redistribution layer structure is electrically connected to the first chip. The UBM pads are electrically connected to the redistribution layer structure. The connectors are electrically connected to the UBM pads. The separator is over the redistribution layer structure and surrounds the connectors. | 2017-11-30 |
20170345796 | ELECTRONIC DEVICE WITH STACKED ELECTRONIC CHIPS - An electronic device includes a carrier substrate, a first electronic chip and a second chip. The first chip is mounted on the carrier substrate via interposed electrical connection elements electrically connecting a front electrical connection network of the first chip and an electrical connection network of the carrier substrate. The second chip is mounted on the first chip via interposed electrical connection elements electrically connecting a front electrical connection network of the second chip and a back electrical connection network of the first chip Electrical connection wires electrically connect the back electrical connection network of the first chip to the electrical connection network of the carrier substrate. | 2017-11-30 |
20170345797 | SEMICONDUCTOR ADHESIVE, AND SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor adhesive used for sealing connection portions of a semiconductor device, wherein: in the semiconductor device, the connection portion of a semiconductor chip and the connection portion of a wiring circuit substrate are electrically connected to each other or the connection portions of a plurality of semiconductor chips are electrically connected to each other; the semiconductor adhesive comprises a (meth)acrylic compound and a curing agent; and when the semiconductor adhesive is kept at 200° C. for 5 seconds, a curing reaction rate thereof is 80% or more. | 2017-11-30 |
20170345798 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A semiconductor structure includes: a first semiconductor workpiece; a second semiconductor workpiece, bonded to a first surface of the first semiconductor workpiece, wherein the second semiconductor workpiece includes two adjacent semiconductor dies; a dielectric material, disposed between the two adjacent semiconductor dies; a first electrically conductive via, formed in the dielectric material and extended to electrically connect the first semiconductor workpiece; a third semiconductor workpiece, bonded to a second surface of the first semiconductor workpiece, the second surface being opposite to the first surface; and a second electrically conductive via, extended into the first semiconductor workpiece and substantially aligned with the first electrically conductive via such that the first electrically conductive via connects the second electrically conductive via. | 2017-11-30 |
20170345799 | POWER MODULE - A power module may include a first bus bar having a first plurality of tabs, wherein each of the first plurality of tabs is electrically coupled to a respective conductive trace of a plurality of conductive traces disposed on a first side; a second bus bar having a second plurality of tabs, wherein each of the second plurality of tabs is electrically coupled to a respective conductive trace of a plurality of conductive traces disposed on a second side; and a third bus bar having a third plurality of tabs, wherein at least one tab of the third plurality of tabs is electrically coupled to a respective conductive trace of the plurality of conductive traces disposed on the first side and at least one tab of the third plurality of tabs is electrically coupled to a respective conductive trace of the plurality of conductive traces disposed on the second side. | 2017-11-30 |
20170345800 | LED MODULE - An LED module includes: a substrate having a main surface and a back surface which face in opposite directions from each other in a thickness direction; a first LED chip including a first electrode pad bonded to a surface facing the same direction as the main surface; a first wire having one end bonded to the first electrode pad; and a wiring pattern having a main surface electrode formed in the main surface, wherein the main surface electrode includes a first die pad portion which supports the first LED chip, and when viewed from the thickness direction, the first die pad portion includes a main pad portion to which the first LED chip is bonded and an auxiliary pad portion which protrudes from the main pad portion in a direction toward a position of the first electrode pad from the center position in the first LED chip. | 2017-11-30 |
20170345801 | DISPLAY APPARATUS AND FABRICATING METHOD THEREOF - A display apparatus and a fabricating method thereof are provided. The display apparatus includes a substrate, a light emitting diode, a first bump, a first insulating layer and a second insulating layer. The light emitting diode has a first surface and a second surface opposite each other, wherein the first surface faces the substrate. The light emitting diode is bonded to the substrate through the first bump. The first insulating layer is disposed on a periphery of the first bump and the light emitting diode, and contacts the first bump and the first surface. The second insulating layer is disposed on the substrate and surrounds at least a portion of the first insulating layer. | 2017-11-30 |
20170345802 | DISPLAY DEVICE USING SEMICONDUCTOR LIGHT EMITTING DEVICE AND FABRICATION METHOD THEREOF - The present disclosure relates to a display device using a semiconductor light emitting device and a fabrication method thereof. A display device may include a plurality of semiconductor light emitting device packages; a wiring substrate coupled to the plurality of semiconductor light emitting device packages; and a plurality of wiring electrodes. A semiconductor light emitting device packages may include a plurality of semiconductor light emitting devices; a support substrate coupled to the plurality of semiconductor light emitting devices; and a conversion layer configured to covert a color of light emitted from at least some of the plurality of semiconductor light emitting devices to a different color, forming a red sub-pixel, a green sub-pixel, and a blue sub-pixel. A semiconductor light emitting device corresponding to the red or green sub-pixel and a semiconductor light emitting device corresponding to the blue sub-pixel may have light emitting areas that are of different sizes. | 2017-11-30 |
20170345803 | MODULE STACKING MECHANISM WITH INTEGRATED GROUND - Printed circuit board (PCB) structures and methods of assembling them are described herein. In some embodiments, a PCB structure may include a first mounting hole; first, second, and third projections radiating from the first mounting hole; and a second mounting hole adjacent to the third projection. The first and second mounting holes located at opposite ends of the third projection. The second mounting hole to cause an electrical coupling of a bottom integrated circuit (IC) module to a connection structure included in a PCB, and the first mounting hole, the first projection, and the second projection to cause positioning of a top IC module above the bottom IC module and electrical coupling of the top IC module to the connection structure. | 2017-11-30 |
20170345804 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - The present disclosure provides a method of manufacturing a structure. The method comprises: providing a substrate; forming an interconnect layer over the substrate; forming a plurality of conductive pads over the interconnect layer; forming conductive pillars over the interconnect layer; disposing a first semiconductor die over the conductive pads, the semiconductor die being spaced apart from the conductive pillars; and bonding a second semiconductor die with the conductive pillars. | 2017-11-30 |
20170345805 | PACKAGE INCLUDING STACKED DIE AND PASSIVE COMPONENT - Disclosed herein is an electronic device including a substrate having a conductive area formed thereon. A first molding level is stacked on the substrate. A die is formed on the substrate and within the first molding level. A second molding level is stacked on the first molding level. At least one passive component is within the second molding level. A conductive structure extends between the second molding level and the substrate and electrically couples the at least one passive component to the conductive area. | 2017-11-30 |
20170345806 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a first substrate, an insulation layer, and a first electrode. The first substrate contains a first semiconductor material. The insulation layer includes a first surface, a second surface, and a third surface. The first electrode includes a fourth surface, a fifth surface, and a sixth surface, and contains a porous first conductive material. The second surface and the fifth surface configure the same surface. The third surface faces the sixth surface. A distance between the first surface and the first substrate is less than a distance between the second surface and the first substrate. A distance between the fourth surface and the first substrate is less than a distance between the fifth surface and the first substrate. | 2017-11-30 |
20170345807 | Multi-Stack Package-on-Package Structures - A package includes a first device die, and a first encapsulating material encapsulating the first device die therein. A bottom surface of the first device die is coplanar with a bottom surface of the first encapsulating material. First dielectric layers are underlying the first device die. First redistribution lines are in the first dielectric layers and electrically coupling to the first device die. Second dielectric layers are overlying the first device die. Second redistribution lines are in the second dielectric layers and electrically coupling to the first redistribution lines. A second device die is overlying and electrically coupling to the second redistribution lines. No solder region connects the second device die to the second redistribution lines. A second encapsulating material encapsulates the second device die therein. A third device die is electrically coupled to the second redistribution lines. A third encapsulating material encapsulates the third device die therein. | 2017-11-30 |
20170345808 | ELECTRIC POWER CONVERSION CIRCUIT INCLUDING SWITCHES AND BOOTSTRAP CIRCUITS, AND ELECTRIC POWER TRANSMISSION SYSTEM INCLUDING ELECTRIC POWER CONVERSION CIRCUIT - An electric power conversion circuit includes: first and second input terminals; first and second output terminals; first and third switches connected to the first output terminal; second and fourth switches connected to the second output terminal; first through fourth diodes that are bridge-connected between the first and second switches; fifth through eighth diodes that are bridge-connected between the third and fourth switches; a first bootstrap circuit that is connected to control terminals of the second and fourth switches; and a second bootstrap circuit that is connected to control terminals of the first and third switches. | 2017-11-30 |
20170345809 | CIRCUIT WITH COMBINED CELLS AND METHOD FOR MANUFACTURING THE SAME - In some embodiments, a first cell layout and a second cell layout are provided and combined into a third cell layout. Each of the first cell layout and the second cell layout includes a higher power line, a lower power line, an output pin, at least one up transistor and at least one down transistor formed to electrically couple the output pin to the higher power line and the output pin to the lower power line, respectively. The at least one up transistor and the at least one down transistor of the second cell layout include a gate line. For the combining, the gate line is non-selectively electrically coupled to the output pin of the first cell layout to form a first node. A design layout in which the third cell layout is used at different locations is generated. | 2017-11-30 |
20170345810 | Semiconductor Devices With Cells Comprising Routing Resources - A cell comprising at least one diffusion region and a plurality of interconnection conductive patterns located over the at least one diffusion layer and comprising a first outer interconnection conductive pattern and a second outer interconnection conductive pattern. The cell further includes at least one different conductive pattern located above the at least one diffusion region and interspersed between the plurality of interconnection conductive patterns. The at least one diffusion region extends in a first direction and the plurality of interconnection conductive patterns and at least one different conductive pattern extend in a second direction substantially perpendicular to the first direction. At least one of the interconnection conductive patterns extends in the second direction substantially perpendicular to the first direction and is long enough to connect to another interconnection conductive pattern on a second cell when the cell abuts the second cell vertically to create at least one routing resource. | 2017-11-30 |
20170345811 | METHOD FOR MANUFACTURING ESD PROTECTION DEVICE - Disclosed is a method for manufacturing an ESD protection device. The method comprises: forming a first buried layer on the semiconductor substrate; forming a first epitaxial layer on the semiconductor substrate; forming a first doped region in the first epitaxial layer and forming a second doped region surrounding the first doped region in the first epitaxial layer, wherein the semiconductor substrate and the first doped region are both of a first doping type, the buried layer and the first epitaxial layer are both of a second doping type, the first doping type is opposite to the second doping type, the first doped region and the second doped region are formed using a same first mask. The method uses the same mask to form an emitter region of the open-base bipolar transistor, and to form a barrier doped region at the periphery of the emitter region, so that the manufacture cost is reduced and the parasitic capacitance of the ESD protection device is decreased. | 2017-11-30 |
20170345812 | THROUGH VIA EXTENDING THROUGH A GROUP III-V LAYER - A process for manufacturing an integrated circuit (IC) with a through via extending through a group III-V layer to a diode is provided. An etch is performed through the group III-V layer, into a semiconductor substrate underlying the group III-V layer, to form a via opening. A doped region is formed in the semiconductor substrate, through the via opening. Further, the doped region is formed with an opposite doping type as a surrounding region of the semiconductor substrate. The through via is formed in the via opening and in electrical communication with the doped region. | 2017-11-30 |
20170345813 | LOW DYNAMIC RESISTANCE LOW CAPACITANCE DIODES - A low dynamic resistance, low capacitance diode of a semiconductor device includes a heavily-doped n-type substrate. A lightly-doped n-type layer 1 micron to 5 microns thick is disposed on the n-type substrate. A lightly-doped p-type layer 3 microns to 8 microns thick is disposed on the n-type layer. The low dynamic resistance, low capacitance diode, of the semiconductor device includes a p-type buried layer, with a peak dopant density above 1×10 | 2017-11-30 |
20170345814 | SEMICONDUCTOR DEVICE - According to one embodiment, an electrostatic discharge semiconductor device includes one or more wiring layers first disposed over a substrate, including: a wiring electrically connected at a first connecting point of a pad, a second wiring electrically connected at a second connecting point of a ground wiring, and a third wiring electrically connected at a third connecting point of the ground wiring; a first transistor formed in the substrate comprising a first diffusion region electrically connected to the first wiring, a second diffusion region electrically connected to the second wiring, and a gate electrically connected to the ground wiring; and a second transistor formed in the substrate comprising the first diffusion region electrically connected to the first wiring, a third diffusion region electrically connected to the third wiring, and a gate electrically connected to the ground wiring, wherein, a first resistance value of a first current pathway leading from the first connecting point to the second connecting point via the first transistor is different from a second resistance value of a second current pathway leading from the first connecting point to the third connecting point via the second transistor. | 2017-11-30 |
20170345815 | THIN-FILM DEVICE - A thin-film device is provided with high reliability that prevents breakage of a thin-film resistance element due to stress caused by expansion of a resin layer. Thin-film resistance elements can be pressed against a substrate with a first constraint thin film that is formed on a resin layer arranged on a resin layer at the opposite side to the substrate so as to overlap with the thin-film resistance elements when seen in the plan view of the device. Therefore, bending stress that is applied to the thin-film resistance elements due to expansion of the resin layers in a high-temperature state can be moderated to thereby prevent breakage of the thin-film resistance elements due to stress caused by the expansion of the resin layers. | 2017-11-30 |
20170345816 | DECOUPLING CAPACITOR - A device includes a plurality of active areas, a plurality of gates, and a plurality of conductors. The active areas are elongated in a first direction. The gates are elongated in a second direction. The conductors are disposed between the active areas and elongated in the second direction. Each one of the conductors has an overlap with at least one corresponding gate of the gates to form at least one capacitor. | 2017-11-30 |
20170345817 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREFOR AND SEMICONDUCTOR MODULE - A semiconductor device of the present invention achieves improved avoidance of a parasitic operation in a circuit region while achieving miniaturization of the semiconductor device and a reduction in the amount of time for manufacturing the semiconductor device. The semiconductor device according to the present invention includes an IGBT disposed on a first main surface of a semiconductor substrate provided with a drift layer of a first conductivity type; a thyristor disposed on the first main surface of the semiconductor substrate; a circuit region; a hole-current retrieval region separating the IGBT and the circuit region in a plan view; and a diffusion layer of a second conductivity type, the diffusion layer being disposed on a second main surface of the semiconductor substrate. The IGBT has an effective area equal to or less than an effective area of the thyristor in a plan view. | 2017-11-30 |
20170345818 | Semiconductor Devices with Trench Gate Structures in a Semiconductor Body with Hexagonal Crystal Lattice - A semiconductor device includes trench gate structures in a semiconductor body with hexagonal crystal lattice. A mean surface plane of a first surface is tilted to a <1-100> crystal direction by an off-axis angle, wherein an absolute value of the off-axis angle is in a range from 2 degree to 12 degree. The trench gate structures extend oriented along the <1-100> crystal direction. Portions of the semiconductor body between neighboring trench gate structures form transistor mesas. Sidewalls of the transistor mesas deviate from a normal to the mean surface plane by not more than 5 degree. | 2017-11-30 |
20170345819 | SEMICONDUCTOR DEVICE HAVING GATE STRUCTURE WITH REDUCED THRESHOLD VOLTAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device is provided, including: a substrate having a first area and a second area; several first gate structures formed at the first area, and at least one of the first gate structures including a first hardmask on a first gate, and the first gate structure having a first gate length; several second gate structures formed at the second area, and at least one of the second gate structures including a second hardmask on a second gate, and the second gate structure having a second gate length. The first gate length is smaller than the second gate length, and the first hardmask contains at least a portion of nitrogen (N | 2017-11-30 |
20170345820 | Metal Gate Isolation Structure and Method Forming Same - A device includes a gate isolation plug, which further includes a U-shaped layer having a bottom portion and two sidewall portions, and an inner region overlapping the bottom portion. The inner region contacts the two sidewall portions. A first transistor has a first gate stack, and a first end of the first gate stack is in contact with both the inner region and the U-shaped layer of the gate isolation plug. A second transistor has a second gate stack, and a second end of the second gate stack is in contact with both the inner region and the U-shaped layer of the gate isolation plug. The first gate stack and the second gate stack are on opposite sides of the gate isolation plug. | 2017-11-30 |
20170345821 | HIGH SPEED SEMICONDUCTOR DEVICE - A semiconductor device includes a fin extending from a substrate, a first source/drain feature, a second source/drain feature, and a gate structure on the fin. A distance between the gate structure and the first source/drain feature is different from a distance between the gate structure and the second source/drain feature. | 2017-11-30 |
20170345822 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - Semiconductor devices may include a substrate, gate electrodes on the substrate, and source/drain regions at both sides of each of the gate electrodes. Each of the gate electrodes may include a gate insulating pattern on the substrate, a lower work-function electrode pattern that is on the gate insulating pattern and has a recessed upper surface, and an upper work-function electrode pattern that conformally extends on the recessed upper surface of the lower work function electrode pattern. Topmost surfaces of the lower work-function electrode patterns may be disposed at an equal level, and the upper work-function electrode patterns may have different thicknesses from each other. | 2017-11-30 |
20170345823 | ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME - An electronic device includes a semiconductor memory. The semiconductor memory may include a semiconductor substrate having an isolation trench in a first region and a capacitor trench in a second region, an isolation layer filling the isolation trench, an insulation layer pattern disposed along the capacitor trench, and a conductive layer pattern filling the capacitor trench over the insulation layer pattern. A capacitor includes a first portion of the semiconductor substrate in the second region, the insulation layer pattern, and the conductive pattern. A sidewall of the capacitor trench has a first angle with respect to a surface of the semiconductor substrate and a sidewall of the isolation trench has a second angle with respect to the surface of the semiconductor substrate. The first angle is more proximate to 90 degrees than the second angle. | 2017-11-30 |