48th week of 2017 patent applcation highlights part 67 |
Patent application number | Title | Published |
20170346424 | SUPPLY CURRENT LIMITING OF DC MACHINES - An embodiment of a control system includes a current command module configured to receive a torque command and output a current command for controlling a direct current (DC) motor, and a supply current limiting module configured to receive a supply current limit as an input and actively compute a motor current limit based on the supply current limit, the supply current limiting module configured to limit the current command based on the motor current limit. | 2017-11-30 |
20170346425 | CURRENT REGULATION IN MOTORS - A motor controller that includes a processing device and a drive circuit. The drive circuit may include a plurality of switches, a motor winding, and a current sensor coupled together in an H-bridge configuration. The processing device is configured to cause a drive current to drive through the motor winding for a minimum amount of time. The processing device is also configured to compare the current through the current sensor to a threshold value at the minimum amount of time. The processing device is also configured to, based on the current being at or above the threshold value at the minimum amount of time, stop the drive current for an off period of time and cause a first decay of the current for a first percentage of the off period of time and a first slow decay for a second percentage of the off period of time. | 2017-11-30 |
20170346426 | APPARATUS AND METHOD TO DETECT STALL CONDITION OF A STEPPER MOTOR - A method for detecting a stall condition in a stepper motor includes measuring stepper motor current, computing load angle of the motor, and detecting a stall condition if the load angle is more than 90 degrees. | 2017-11-30 |
20170346427 | Gas Turbine Power Generation System and Control System Used in the Same - A gas turbine power generation system having an improved function to stabilize the power system is disclosed. The gas turbine power generation system has a dual-shaft gas turbine, an electric generator mechanically connected to a low pressure turbine of the dual-shaft gas turbine and electrically connected to an electric power system, a rotary electric machine mechanically connected to a high pressure turbine through a compressor of the dual-shaft gas turbine and electrically connected to the electric power system, wherein a power oscillation is suppressed by operation of the rotary electric machine as a motor or as a generator. | 2017-11-30 |
20170346428 | METHOD OF CONTROLLING A DEVICE FOR REGULATING AN AUTOMOTIVE VEHICLE ALTERNATOR, CORRESPONDING REGULATING DEVICE AND ALTERNATOR - The method of control according to the invention slaves a DC voltage generated by the alternator to a predetermined setpoint value by controlling an excitation current flowing in an excitation circuit comprising an excitation winding of a rotor of the alternator. The excitation current is controlled by means of a semiconductor switch, in turn controlled by a control signal having a predetermined period. The method comprises a detection of a failure of the excitation circuit. At least one short-circuit of the excitation winding is detected. According to another characteristic of the method, the control signal is generated on the basis of a combination of a setpoint signal formed by pulses of the predetermined period exhibiting a duty ratio representative of the setpoint value and of a detection signal indicative of the short-circuit. | 2017-11-30 |
20170346429 | CONTROLLER-INTEGRATED ROTATING ELECTRICAL MACHINE - A controller-integrated rotating electrical machine incudes a rotating electrical machine and a control device. The rotating electrical machine is equipped with a stator and a rotor. The control device is equipped with a control circuit for an inverter circuit and an angle position sensing device which works to measure an angular position of the rotor. The control device has first substrate on which the control circuit is mounted and a second substrate on which the angle position sensing device is mounted. The first substrate is located closer to the rotating electrical machine than the angle position sensing device is in an axial direction of the controller-integrated rotating electrical machine. This minimizes adverse effects of magnetic flux, as generated by the rotating electrical machine, on operation of the angle position sensing device, thereby enhancing a measurement accuracy of the angle positon sensing device. | 2017-11-30 |
20170346430 | SYSTEMS AND METHODS FOR ADJUSTING OPERATIONS OF A GAS TURBINE FOLLOWING A TRANSIENT EVENT - A method may involve monitoring a first set of electrical properties associated with an electrical grid configured to couple to a generator and determining whether a transient event is present on the electrical grid based on the first set of electrical properties. The method may also involve determining a mechanical power present on a shaft of the generator based on a second set of electrical properties associated with the generator, the electrical grid, or both when the transient event is present and sending the mechanical power to a controller associated with a turbine configured to couple to the generator, wherein the controller is configured to adjust one or more operations of the turbine based on the mechanical power. | 2017-11-30 |
20170346431 | EXCITATION CURRENT-LIMITED POWER GENERATOR - An excitation current-limited power generator includes a digital interface configured to be coupled to an engine control unit (ECU), a regulator coupled configured to be coupled to an excitation current input of an alternator, the excitation current controlling current generated by the alternator, a frequency sensor configured to measuring rotation speed of the alternator, and memory storing a communicated limit received by the digital interface and a first permanent limit, the regulator configured to limit the excitation current to the lesser of the first permanent limit and the communicated limit. | 2017-11-30 |
20170346432 | MOTOR - A motor includes a magnet and a coil. α2=[{(Br2−Br1)/Br1}/(T2−T1)]×100≧−0.10 and α3=[{(Br3−Br1)/Br1}/(T3−T1)]×100≦−0.12 are satisfied. In the magnet, Br1 (mT) is a residual magnetic flux density at T1 (° C.), Br2 (mT) is a residual magnetic flux density at T2 (° C.), and Br3 (mT) is a residual magnetic flux density at T3 (° C.), and α2 (%/° C.) is a temperature coefficient at a target temperature of T2 (° C.) with respect to a reference temperature of T1 (° C.), and α3 (%/° C.) is a temperature coefficient at a target temperature of T3 (° C.) with respect to a reference temperature of T1 (° C.) in conditions of T1=23, T2=60, and T3=180. | 2017-11-30 |
20170346433 | SYSTEMS AND METHODS OF OPTIMIZING OPERATION EFFICIENCY OF A MOTOR DRIVE - Methods and systems of optimizing efficiency of a motor drive or generator are provided. The methods include measuring data corresponding to input power and output power of a motor drive or generator at a control parameter and different load values. The methods include generating a three-dimensional surface model based on the measured data. The three-dimensional surface model can estimate an efficiency of the motor drive or generator at the control parameter and at unmeasured load values. The methods can include determining optimal efficiency of the motor drive or generator at the different load values and the unmeasured load values based on the three-dimensional surface model. | 2017-11-30 |
20170346434 | CONTROL OF LONG-STATOR LINEAR MOTOR COILS OF LONG-STATOR LINEAR MOTOR STATOR - The present invention provides a method and device for controlling the n LLM coils (L | 2017-11-30 |
20170346435 | MOTOR APPARATUS COMPRISING AT LEAST TWELVE COILS - The invention is based on a motor apparatus, in particular on an EC motor apparatus, comprising at least one stator ( | 2017-11-30 |
20170346436 | CONTROL APPARATUS OF ROTARY ELECTRIC MACHINE AND ELECTRIC POWER STEERING APPARATUS USING THE SAME - An apparatus for controlling a rotary electric machine includes: first and second inverters corresponding to first and second winding groups; first and second voltage detectors; and first and second control units. Each of the first and second inverters includes plurality of switching elements. The first and second voltage detectors each detects input voltage of corresponding inverter. The first control unit limits a first current command value of the first winding group, when both of the first and second inverter input voltages are in normal, and a first differential value is larger than a determination threshold, and the second control unit limits a second current command value of the second winding group, when both of the first and second inverter input voltages are normal, and a second differential value is larger than the determination threshold. | 2017-11-30 |
20170346437 | BRACKET FOR CLAMPING A PHOTOVOLTAIC MODULE TO A TORQUE TUBE - A bracket for clamping a photovoltaic module to a torque tube includes a planar base having a pair of aligned holes, a pair of bolts each extending through one of the pair of holes, and a plurality of securing tabs. Each of the securing tabs can be formed by bending a corner portion of the planar base downwardly to a desired angle. The pair of bolts extend to a sufficient length so as to permit a threaded portion of each bolt to be threaded into a complementary threaded hole of the photovoltaic module assembly (e.g., a rail supporting the photovoltaic module). The supporting tabs are structured and arranged to grip lateral sides of the torque tube. Advantageously, the dimensions allow the clamp to stay on the torque tube through a friction fit for ease of installation prior to threading the hardware into the photovoltaic module assembly. | 2017-11-30 |
20170346438 | Mounting Clips for Panel Installation - A photovoltaic panel mounting clip comprising a base, central indexing tabs, flanges, lateral indexing tabs, and vertical indexing tabs. The mounting clip removably attaches one or more panels to a beam or the like structure, both mechanically and electrically. It provides secure locking of the panels in all directions, while providing guidance in all directions for accurate installation of the panels to the beam or the like structure. | 2017-11-30 |
20170346439 | Apparatus for Mounting Conduit to Solar Panel Arrays - In various representative aspects, an apparatus for securing conduit to solar panel arrays that are typically installed on roof structures. More specifically, the assembly comprises a mount that is coupled to a solar panel module or a rail-less wire conduit structure for securing wire conduit alongside the perimeter of an array of solar panel modules. | 2017-11-30 |
20170346440 | Bracket Mounting Assembly for Securing Junction Boxes to Solar Panel Arrays - In various representative aspects, an assembly for connecting and electrically bonding electronic equipment to solar panel frames is provided. The present invention relates generally to an assembly for supporting junction box structures used in a solar panel frame array. More specifically, the apparatus comprises an adjustable bracket assembly that can mount most sizes and shapes of junction boxes that are then secured virtually to any solar panel frame while being electrically bonded by way of a surface layer penetrating means. | 2017-11-30 |
20170346441 | Bracket Mount for Securing Micro-Inverters and Power Optimizers to Solar Panel Arrays - In various representative aspects, an assembly for connecting and electrically bonding electronic equipment to solar panel frames is provided. More specifically, the present invention relates generally to an assembly for securing and installing micro inverter and power optimizer units for use with solar panel arrays that are typically installed on roof structures. The assembly comprises a bracket assembly that couples micro invertors and power optimizers to solar panel frames. | 2017-11-30 |
20170346442 | OSCILLATOR, ELECTRONIC APPARATUS, VEHICLE, AND METHOD OF MANUFACTURING OSCILLATOR - An oscillator includes an external terminal, a resonator, and an oscillation circuit that oscillates the resonator. The oscillation circuit includes an amplification circuit and a current source that supplies a current to the amplification circuit, and the current is variably set according to a control signal input from the external terminal. | 2017-11-30 |
20170346443 | SERIES OF COUPLED SYNCHRONOUS OSCILLATORS - An integrated circuit includes at least two identical, synchronous and independent oscillator circuits that are coupled one to one in parallel with each other at homologous oscillating nodes of the respective oscillator circuits. The coupling in parallel is made using at least one coupling track that is configured so as to not introduce any phase shift or to introduce a very small phase shift. | 2017-11-30 |
20170346444 | Semiconductor Device and Method - A circuit includes a first digital controlled oscillator and a second digital controlled oscillator coupled to the first digital controlled oscillator. A skew detector is connected to determine a skew between outputs of the first digital controlled oscillator and the second digital controlled oscillator, and a decoder is utilized to output a control signal, based on the skew, to modify a frequency of the first digital controlled oscillator using a switched capacitor array to reduce or eliminate the skew. A differential pulse injection oscillator circuit and a pulse injection signal generator circuit are also provided, | 2017-11-30 |
20170346445 | Dense Wavelength-Division Multiplexing (DWDM) Network and Method - A dense wavelength-division multiplexing (DWDM) optical network comprises an optical bus, which includes an optical source configured to generate a plurality of unmodulated optical signals each having a different wavelength; an optical multiplexer configured to multiplex the unmodulated optical signals to produce a combined, unmodulated optical signal, and to transmit the combined, unmodulated optical signal through an optical fiber; a plurality of nodes connected in sequence to the output of the optical multiplexer. The plurality of nodes are connected by the optical fiber. A DWDM optical network and a method of operation of the DWDM optical network are also disclosed therein. | 2017-11-30 |
20170346446 | MULTI-PHASE POWER CONVERTER SYSTEM USING MULTIPLE AMPLIFIER INTEGRATED CIRCUITS - In accordance with embodiments of the present disclosure, a system may include a circuit having a power converter and an amplifier, wherein the power converter is configured to generate an intermediate voltage, provide the intermediate voltage as an amplifier supply voltage to the amplifier, and share the intermediate voltage with one or more additional circuits external to the circuit, wherein at least one of the one or more additional circuits is configured to generate the intermediate voltage. | 2017-11-30 |
20170346447 | Method for Load Measurement in Switching Amplifiers, Corresponding Device and Amplifier - A method can be used to measure a load driven by a switching amplifier having a differential input, an LC output demodulator filter and a feedback network between the amplifier output and the differential input. The amplifier is AC driven in a differential and in a common mode by applying a common. The feedback network provides feedback towards the differential input from downstream the LC demodulator filter by computing the impedance of the load as a function of the differential mode output current and the common mode output current. The feedback network provides feedback towards the differential input from upstream the LC demodulator filter by measuring the impedance value of the inductor of the LC demodulator filter, and computing the impedance of the load as a function of the differential mode output current, the common mode output current and the impedance value of the inductor of the LC demodulator filter. | 2017-11-30 |
20170346448 | VARIABLE GAIN LOW NOISE AMPLIFIER - LNA circuitry includes an input node, and output node, a primary amplifier stage, a first ancillary amplifier stage, and an input gain selection switch. The primary amplifier stage is configured to provide a first gain response between a primary amplifier stage input node and a primary amplifier stage output node, wherein the primary amplifier stage input node is coupled to the input node and the primary amplifier stage output node is coupled to the output node. The first ancillary amplifier stage is configured to provide a second gain response between a first ancillary amplifier stage input node and a first ancillary amplifier stage output node, wherein the first ancillary amplifier stage output node is coupled to the primary amplifier stage output node. The input gain selection switch is coupled between the input node and the first ancillary amplifier stage input node. | 2017-11-30 |
20170346449 | Low Noise Amplifier - A low noise amplifier includes an amplifier transistor having a source, a gate, and a drain. An input node is coupled to the gate. An output node is coupled to the drain. An inductor is coupled between the gate and the drain. | 2017-11-30 |
20170346450 | PRE-AMPLIFIER CIRCUIT INCLUDING MICROPHONE PRE-AMPLIFIER STAGE - A pre-amplifier circuit including a microphone pre-amplifier stage with a direct injection (DI) unit that provides a high impedance source signal and a low impedance XLR connection operable without a line or mic switch. | 2017-11-30 |
20170346451 | SWITCHLESS LINE-DI/MIC PRE-AMPLIFIER INPUT - A switchless pre-amplifier input circuit includes an audio input connector that receives a first audio device operable at a first impedance and a second audio device operable at a second impedance less than the first impedance. A preamplifier circuit outputs a preamplified audio signal in response to amplifying a first audio signal generated by the first audio device or a second audio signal generated by the second audio device. The switchless pre-amplifier input circuit further includes a impedance selector circuit that adjusts an impedance at the output to reach the second impedance in response to connecting the second audio device to the audio input connector and to adjust the impedance at the output to reach the first impedance in response to connecting the first audio device to the audio input. | 2017-11-30 |
20170346452 | RADIO FREQUENCY FILTER, RADIO FREQUENCY FRONT-END CIRCUIT, COMMUNICATION DEVICE, AND DESIGN METHOD FOR RADIO FREQUENCY FILTER - A radio frequency filter includes communication bandpass filters disposed corresponding respectively to a plurality of communication bands, a switch, and a matching circuit. The switch includes a common terminal and a plurality of optionally selectable terminals, the plurality of optionally selectable terminals being individually connected to the plurality of bandpass filters in a one-to-one relation. The matching circuit is connected to the common terminal and is a common matching circuit to the plurality of communication bandpass filters. The plurality of communication bandpass filters are set such that filter characteristics of a serial circuit in combination of one of the plurality of communication bandpass filters, the one being selected by the switch, and the common matching circuit are improved in comparison with filter characteristics of the selected communication bandpass filter with respect to the communication band corresponding to the selected communication bandpass filter. | 2017-11-30 |
20170346453 | MULTIDRIVER BASED CANALPHONE SYSTEM - A canalphone system may include a pair of high audio drivers carried by a canalphone housing, and a pair of low audio drivers carried by the canalphone housing adjacent to the high audio driver. The system may also include an amplifier that amplifies an audio signal and delivers that amplified audio signal to the pair of high audio drivers and the pair of low audio drivers, the amplifier being non-destructively removable by a user. The system may further include a passive audio crossover carried by the canalphone housing, the passive audio crossover receives the amplified audio signal from the amplifier and then delivers the amplified audio signal in a suitable frequency range to at least one of the pair of high audio drivers and the pair of low audio drivers, the passive audio crossover filtering the amplified audio signal within the canalphone housing rather than attenuating the amplified audio signal. | 2017-11-30 |
20170346454 | TRANSCONDUCTANCE AMPLIFIER HAVING LOW DISTORTION - A low distortion transconductance amplifier provides current to a grounded load using a virtual ground input stage, a pair of current mirrors, and a bias current source. The virtual ground input stage may include transistors arranged as a Darlington pair. The low distortion transconductance amplifier can function as a voltage-controlled AC current source that is operable at high frequencies. | 2017-11-30 |
20170346455 | CIRCUIT FOR AND METHOD OF RECEIVING AN INPUT SIGNAL - A circuit for receiving an input signal is described. The receiver comprises a first receiver input configured to receive a first input of a differential input signal; a second receiver input configured to receive a second input of a differential input signal; a differential pair having an inverting input and a non-inverting input; a first impedance matching element coupled to the differential pair, wherein the first impedance matching element provides DC impedance matching from the inverting input and non-inverting input of the differential pair; and a second impedance matching element coupled to the differential pair, wherein the second impedance matching element provides AC impedance matching from the inverting input and non-inverting input of the differential pair. | 2017-11-30 |
20170346456 | ACTIVE RC FILTERS - An operational amplifier comprises:
| 2017-11-30 |
20170346457 | AMPLIFIER CIRCUIT INCLUDING FIRST INPUT BRANCH CIRCUIT, SECOND INPUT BRANCH CIRCUIT, FEEDBACK CAPACITOR, AND OPERATIONAL AMPLIFIER AND PULSE-WAVE MEASURING DEVICE - An amplifier circuit includes a first input branch circuit including a first sampling capacitor, a second input branch circuit including a second sampling capacitor, an averaging capacitor, and a subtraction capacitor, a feedback capacitor, and an operational amplifier. The first sampling capacitor samples an input voltage in a first time period and outputs a first voltage. The second sampling capacitor samples the input voltage in the first time period and outputs a second voltage. The averaging capacitor takes an average of the second voltage in the second time period and outputs a third voltage. The subtraction capacitor receives the third voltage in the first time period. The subtraction capacitor subtracts the first voltage from the third voltage and outputs a fourth voltage in the second time period. The operational amplifier is connected to the feedback capacitor and amplifies the fourth voltage. The first and second time periods are repeated alternately. | 2017-11-30 |
20170346458 | POWER AMPLIFIER CIRCUIT - An RF power amplifier circuit includes a power divider, multiple power amplification circuits and a power combiner that cooperatively perform power amplification on an RF input signal so as to output an RF output signal, and an impedance conversion circuit that has a circuit terminal coupled to one of the power divider and the power combiner which has a microstrip structure, and that is configured such that a conversion impedance, which is an impedance seen into the impedance conversion circuit from the circuit terminal, matches an impedance seen into the power divider or the power combiner from the circuit terminal. The microstrip structure has a physical length associated with the conversion impedance. | 2017-11-30 |
20170346459 | INTELLIGENTLY MODIFYING THE GAIN PARAMETER OF A PLAYBACK DEVICE - Techniques for optimizing a player based on the addition of a second player are disclosed. In an embodiment, when a first player no longer needs to play certain audio frequencies due to the addition of a second player, the gain of the first player is automatically increased as part of the setup process. In another embodiment, when a first player needs to play certain audio frequencies, for example due to the removal of a second player, the gain of the first player is automatically decreased. Many other embodiments are disclosed. | 2017-11-30 |
20170346460 | ADJUSTING DYNAMIC RANGE OF AN AUDIO SIGNAL BASED ON ONE OR MORE DYNAMIC EQUALIZATION AND/OR DYNAMIC RANGE CONTROL PARAMETERS - The invention relates to the measurement and control of the perceived sound loudness and/or the perceived spectral balance of an audio signal. An audio signal is modified in response to calculations performed at least in part in the perceptual (psychoacoustic) loudness domain. The invention is useful, for example, in one or more of: loudness-compensating volume control, automatic gain control, dynamic range control (including, for example, limiters, compressors, expanders, etc.), dynamic equalization, and compensating for background noise interference in an audio playback environment. The invention includes not only methods but also corresponding computer programs and apparatus. | 2017-11-30 |
20170346461 | PACKET-BASED RADIO RECEIVER WITH AUTOMATIC GAIN CONTROL - A packet-based radio receiver ( | 2017-11-30 |
20170346462 | BULK ACOUSTIC RESONATOR DEVICES AND PROCESSES FOR FABRICATING BULK ACOUSTIC RESONATOR DEVICES - In a bulk acoustic resonator device, at least one additional metal feature is formed on a top surface of the bottom electrode at a location at which the bottom electrode electrical contact will subsequently be formed, thereby thickening the metal at the location below where the piezoelectric material layer will be etched to form the opening for the bottom electrode electrical contact. Consequently, even though some of the metal of the additional metal feature and/or of the bottom electrode will be removed during the process of etching the opening in the piezoelectric material layer, the bottom electrode will always retain sufficient thickness after the piezoelectric material layer is etched. | 2017-11-30 |
20170346463 | ACOUSTIC WAVE DEVICE - An acoustic wave device includes: a first substrate that includes a first acoustic wave filter located on an upper surface of the first substrate; a second substrate that is flip-chip mounted on the upper surface of the first substrate through a bump, and includes a second acoustic wave filter on a lower surface of the second substrate, the lower surface of the second substrate facing the upper surface of the first substrate across an air gap; and a shield electrode that is supported by the upper surface of the first substrate, and is located between at least a part of the first acoustic wave filter and at least a part of the second acoustic wave filter through the air gap. | 2017-11-30 |
20170346464 | BIASED IMPEDANCE CIRCUIT, IMPEDANCE ADJUSTMENT CIRCUIT, AND ASSOCIATED SIGNAL GENERATOR - A biased impedance circuit, an impedance adjustment circuit, and an associated signal generator are provided. The biased impedance circuit is coupled to a summation node and applies a biased impedance to the summation node. A periodic input signal is received at the summation node. The biased impedance circuit includes a switching circuit for receiving an output window signal, wherein a period of the output window signal is shorter than a period of the periodic input signal. The switching circuit includes a low impedance path and a high impedance path. The low impedance sets the biased impedance to a first impedance when the output window signal is at a first voltage level. The high impedance path sets the biased impedance to a second impedance when the output window signal is at a second voltage level. The first impedance is less than the second impedance. | 2017-11-30 |
20170346465 | NON LINEAR FILTER WITH GROUP DELAY AT PRE-RESPONSE FREQUENCY FOR HIGH RES RADIO - Methods and devices are described for reducing the audible effect of pre-responses in an audio signal. The pre-responses are effectively delayed by employing a digital non-minimum-phase filter, which includes a zero lying outside the unit circle in its z-transform response. This zero is not paired with another zero at a reciprocal position inside the unit circle, as this would linearise the phase modification. The filtering can introduce a greater group delay at the pre-response frequency than at a low frequency, such as 500 Hz or even 0 Hz. The technique can be used to reduce pre-responses in an existing audio signal and also to pre-empt pre-responses that would be introduced to the audio signal by subsequent processing. | 2017-11-30 |
20170346466 | IMPEDANCE CALIBRATION DEVICE FOR SEMICONDUCTOR DEVICE - An impedance calibration device for a semiconductor device includes a process sensor that detects a process condition for the semiconductor device and outputs a process signal, a temperature monitoring sensor that detects a temperature of the semiconductor device and outputs a temperature signal, a converter that converts the process signal and the temperature signal into a digital signal, and a code generation circuit that generates and outputs a driving code for controlling a level of a voltage at an output node according to the digital signal of the converter and a data signal. The impedance calibration device further includes an output driver that pulls up or pulls down the voltage at the output node according to the driving code. | 2017-11-30 |
20170346467 | DELAY LINE WITH SHORT RECOVERY TIME - A delay circuit includes a plurality of cascaded delay elements responsive to control signals. Each delay element is configurable to receive an input signal on a forward path and return the input signal on two return paths. A control unit is connected to the plurality of cascaded delay elements and configured to generate a first set of control signals for defining a first configuration of the plurality of cascaded delay elements, a second set of control signals for causing a delay element of the plurality of cascaded delay elements to change from a powered off status to a powered on status while configured in an initialization mode, and a third set of control signals for defining a second configuration of the plurality of cascaded delay elements. | 2017-11-30 |
20170346468 | RADAR APPARATUS AND STARTUP TIMING DETERMINATION METHOD - A radar apparatus includes a transmitter including a plurality of circuits that intermittently transmit one or more radar signals, the plurality of circuits being suspended power supplying during a period in which the one or more radar signals are not transmitted, variation detection circuitry that detects process variations of the plurality of circuits, and determination circuitry that determines a startup timing of each of the plurality of circuits in response to the process variations and outputs startup commands in response to the determined startup timings to the plurality of circuits. | 2017-11-30 |
20170346469 | CIRCUIT AND METHOD FOR LOW POWER CHIP ENABLE CIRCUITRY - A novel low power enable circuit is less sensitive to power supply variations while consuming less than 50 nA of supply current. The enable circuit includes a voltage clamp circuit which limits the supply level for a first inverter. The clamp circuit having a first input connected to a supply, a second input connected to chip enable, and a first output. The enable circuit further includes a first inverter having a third input connected to the chip enable, a fourth input connected to the first output of the clamp circuit, and a second output; a second inverter having a fifth input connected to the second output of the first inverter, a sixth input connected to the supply, and a third output; a memory element having a seventh input connected to the third output of the second inverter, an eighth input, and a fourth output; and a comparator having a ninth input connected to the chip enable, a tenth input connected to a reference signal, an eleventh input connected to the fourth output of the memory element, and a fifth output connected to the eighth input of the memory element. | 2017-11-30 |
20170346470 | FOLDED DIVIDER ARCHITECTURE - A circuit includes a counter circuit, a logic circuit, and a clock divider. The counter circuit includes a clock divider counter to be loaded with most significant bits of a divider value, and decremented at a same edge of each pulse of a clock signal. The logic circuit compares a value contained in the divider counter to a reference value and generates an end count signal as a function of the value contained in the divider counter matching the reference value, and transitions a toggle signal at a same edge of each pulse of the end count signal. The clock divider counter is reloaded with the most significant bits of the divider value as a function of the end count signal. The clock divider generates a divided version of the clock signal as a function of the toggle signal. | 2017-11-30 |
20170346471 | SYNCHRONIZED SEMICONDUCTOR DEVICE WITH PHASE ADJUSTMENT CIRCUIT - According to one embodiment, a synchronous semiconductor device is disclosed. According to this embodiment, the synchronous semiconductor device includes a pulse width detection circuit to provide detection information responsive to a plurality of delay amounts being different from one another and at least one of a high pulse width and a low pulse width of a first clock signal. The detection information representing relationships in size between each of the plurality of delay amounts and the at least one of the high pulse width and the tow pulse width of the first clock signal. A delay line control circuit coupled to the pulse width detection circuit and the delay line. The delay line control circuit configured to change a delay amount of the delay line by a step size determined responsive, at least in part, to the detection information. | 2017-11-30 |
20170346472 | LOW POWER COMPARATOR - A comparator includes an input stage having a differential input and an output, wherein the voltage at the output is in response to the voltage at the input. The comparator further includes a current limiter for limiting the current flow through the input stage, wherein the current flow through the input stage is in response to the voltage at the input. | 2017-11-30 |
20170346473 | DIFFERENTIAL COMPARATOR - A differential comparator has a first input and a second input comprises:
| 2017-11-30 |
20170346474 | Reconfigurable Direct Mapping for RF Switch Control - A circuit architecture and process that provides for a dual-mode methodology for an RF integrated circuit (IC) switch circuit that allows switching between a direct mapping configuration and a fully decoded mapping configuration, and further provides for changing either mapping configuration after fabrication. A control word is selectively compared to a programmed map register value so that, in a first mode, only one bit position of a control word matches a decoded programmed map bit pattern, and in a second mode, all bits of a control word match a corresponding programmed map bit pattern. Because the map registers can be programmed at least once after IC fabrication, the exact mapping required for a particular application can be determined post fabrication. Further, the first mode of operation is often beneficial during testing because multiple RF signal paths can be turned on at the same time and thus tested in parallel. | 2017-11-30 |
20170346475 | ENHANCEMENT MODE FET GATE DRIVER IC - A fully integrated GaN driver comprising a digital logic signal inverter, a level shifter circuit, a UVLO circuit, an output buffer stage, and (optionally) a FET to be driven, all integrated in a single package. The level shifter circuit converts a ground reference 0-5 V digital signal at the input to a 0-10 V digital signal at the output. The output drive circuitry includes a high side GaN FET that is inverted compared to the low side GaN FET. The inverted high side GaN FET allows switch operation, rather than a source follower topology, thus providing a digital voltage to control the main FET being driven by the circuit. | 2017-11-30 |
20170346476 | LDMOS Transistors And Associated Systems And Methods - A lateral double-diffused metal-oxide-semiconductor field effect transistor includes a silicon semiconductor structure, first and second gate structures, and a trench dielectric layer. The first and second gate structures are disposed on the silicon semiconductor structure and separated from each other in a lateral direction. The trench dielectric layer is disposed in a trench in the silicon semiconductor structure and extends at least partially under each of the first and second gate structures in a thickness direction orthogonal to the lateral direction. | 2017-11-30 |
20170346477 | LDMOS Transistors And Associated Systems And Methods - A lateral double-diffused metal-oxide-semiconductor field effect (LDMOS) transistor includes a silicon semiconductor structure, a dielectric layer at least partially disposed in a trench of the silicon semiconductor structure in a thickness direction, and a gate conductor embedded in the dielectric layer and extending into the trench in the thickness direction. The dielectric layer and the gate conductor are at least substantially symmetric with respect to a center axis of the trench extending in the thickness direction, as seen when the LDMOS transistor is viewed cross-sectionally in a direction orthogonal to the lateral and thickness directions. | 2017-11-30 |
20170346478 | DC SWITCHING DEVICE AND METHOD OF CONTROL - A DC switching device has at least one switching unit which is arranged between two terminals. Further, the DC switching device has a control unit for controlling the at least one switching unit. The switching unit has a first and a second semiconductor switching element, which are arranged in parallel with one another, the first switching element being a high-voltage switching element and the second switching element being a low-power-loss switching element. The switching unit is controllable by the control unit in such a way that, when the switching unit is switched off, initially the second switching element is switched to be non-conductive, and subsequently the first switching unit is switched to be non-conductive, and when the switching unit is switched on, initially the first switching element is switched to be conductive and subsequently the second switching element is switched to be conductive. | 2017-11-30 |
20170346479 | VOLTAGE DETECTOR CIRCUITS AND METHODS - A voltage detector includes a first node configured to have a first supply voltage, a second node configured to have a second supply voltage, and an output node. The voltage detector is configured to drive the output node to the first supply voltage in response to a difference between the first supply voltage and the second supply voltage exceeding a predetermined threshold voltage value. | 2017-11-30 |
20170346480 | High-Voltage Stacked Transistor Circuit - A High-Voltage Stacked Transistor Circuit (HVSTC) includes a stack of power transistors coupled in series between a first terminal and a second terminal. The HVSTC also has a control terminal for turning on an off the power transistors of the stack. All of the power transistors of the stack turn on together, and turn off together, so that the overall stack operates like a single transistor having a higher breakdown voltage. Each power transistor, other than the one most directly coupled to the first terminal, has an associated bipolar transistor. In a static on state of the HVSTC, the bipolar transistors are off. The associated power transistors can therefore be turned on. In a static off state of the HVSTC, the bipolar transistors are conductive (in one example, in the reverse active mode) in such a way that they keep their associated power transistors off. | 2017-11-30 |
20170346481 | THERMALLY CONTROLLED ELECTRONIC DEVICE - An electronic device includes at least one electronic component, a gradient heat-flux sensor GHFS based on thermoelectric anisotropy and conducting heat generated by the electronic component, and a controller adapted to manage electrical current of the electronic component at least partly on the basis of an electrical control signal generated by the gradient heat-flux sensor and proportional to a heat-flux through the gradient heat-flux sensor. Therefore, the electrical current and thereby also the heat generation of the electronic component are managed directly on the basis of the heat-flux generated by the electronic component. Thus, the electrical current can be managed without a need for voltage and current measurements which may be challenging to be carried out with a sufficient bandwidth especially when the switching frequency of the electronic component is on a range from hundreds of kHz to few MHz. | 2017-11-30 |
20170346482 | RADIO-FREQUENCY SWITCH HAVING DYNAMIC GATE BIAS RESISTANCE, BODY CONTACT, AND COMPENSATION CIRCUIT - Radio-frequency (RF) switch circuits having switchable transistor coupling for improved switching performance. An RF switch system includes at least one field-effect transistor (FET) disposed between first and second nodes, each FET having a gate and body. A switchable resistive coupling circuit is connected to each of the respective gates. A switchable resistive grounding circuit is connected to each of the respective bodies. The RF switch system also includes a compensation circuit to compensate a non-linearity effect generated by at least one of the field-effect transistors. | 2017-11-30 |
20170346483 | SEMICONDUCTOR DEVICE DRIVE CIRCUIT - A semiconductor device drive circuit includes a first drive circuit and a second drive circuit. The first drive circuit generates a control signal for controlling a voltage-controlled switching element. The first drive circuit generates a control signal in synchronization with a voltage signal input to the first drive signal. The first drive circuit has an output current capability corresponding to a magnitude of the voltage signal. The second drive circuit outputs a voltage signal to the first drive circuit. The second drive circuit includes an output adjustment circuit that adjusts the magnitude of the voltage signal. | 2017-11-30 |
20170346484 | ELECTRIC POWER CONVERSION CIRCUIT INCLUDING SWITCHES AND BOOTSTRAP CIRCUITS, AND ELECTRIC POWER TRANSMISSION SYSTEM INCLUDING ELECTRIC POWER CONVERSION CIRCUIT - An electric power conversion circuit includes: first through fourth port terminals; a first diode having an anode connected to the first port terminal; a second diode having a cathode connected to the second port terminal; a third diode having a cathode connected to the first port terminal; a fourth diode having an anode connected to the second port terminal; first through fourth switches that are bridge-connected between a cathode of the first diode and an anode of the second diode; fifth through eighth switches that are bridge-connected between an anode of the third diode and a cathode of the fourth diode; a first bootstrap circuit that is connected to control terminals of the first through fourth switches; and a second bootstrap circuit that is connected to control terminals of the fifth through eighth switches. | 2017-11-30 |
20170346485 | Switch Cell Structure and Method - A switch cell structure includes a switch cell of a first type, which includes a master switch cell and a plurality of slave switch cells. The master switch cell includes a buffer having an input and an output and a transistor having a gate coupled to the output of the buffer. The slave switch cell includes a respective signal line having an input and output and a transistor having a gate coupled to the signal line, the signal lines of the slave switch cells are coupled to one another, with the output of one coupled to the input of another of the signal lines. The output of the buffer of the master switch cell is coupled to an input of one of the signal lines of slave switch cells to drive the plurality of slave switch cells. | 2017-11-30 |
20170346486 | Independent Control of Branch FETs for RF Performance Improvement - A FET-based RF switch architecture and method that provides for independent control of FETs within component branches of a switching circuit. With independent control of branch FETs, every RF FET in an inactive branch that is in an “open” (capacitive) state can be shunted to RF ground and thus mitigate impedance mismatch effects. Providing a sufficiently low impedance to RF ground diminishes such negative effects and reduces the sensitivity of the switch circuit to non-matched impedances. | 2017-11-30 |
20170346487 | SYSTEM FOR ALLOWING A USER TO WIRELESSLY MANAGE SOFTWARE APPLICATIONS OF A COMPUTING DEVICE AND PLURALITY OF VEHICLES SENSORS - Disclosed is a beacon for allowing a user to wirelessly manage software applications of a computing device and plurality of vehicle's sensors. The beacon includes a housing, a touch sensor to identify tap from the user, a bi-directional communication unit to wirelessly bi-directionally communicate with the computing device and the vehicle's sensors on receiving tap from the user, a memory unit to store plurality of modules and plurality of instructions, wherein each instruction corresponding to each tap and a processor coupled to the memory unit and configured in the housing to process the plurality of modules. The plurality of modules includes a computing device module opens the specific software application based upon specific number of taps received from the user; a vehicle sensor module operates a specific vehicle sensor based upon a specific number of taps receive from the user; and a vehicle sensor and computing device module opens the status of the vehicle sensor on the computing device depending upon the specific number of taps received from the user. | 2017-11-30 |
20170346488 | CAPACITIVE KEYBOARD - A capacitive keyboard that can detect a key that has been depressed and the depressed amount thereof with high accuracy is provided. The capacitive keyboard includes a drive circuit 11 that alternatively switches the voltage of each of drive lines M from an L-level to an H-level, a sensing circuit 12 that is connected to each of sensing lines N and that selects one of the sensing lines N to detect the voltage generated in the selected sensing line, and a control circuit 15. The control circuit 15 includes a storage unit 44 including storage areas corresponding to keys, a storage control unit 42 that acquires the voltage generated in the sensing line and that stores the acquired voltage in a storage area corresponding to a key, and a correction unit 43 that corrects, if one of the keys is operated, the voltage generated as a result of an operation of the one of the keys by using voltages stored in storage areas corresponding to other keys. Thus, even if a plurality of keys are depressed at the same time, detection with high accuracy can be realized. | 2017-11-30 |
20170346489 | LOGIC CIRCUIT, SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE - A drive capability of a dynamic logic circuit is improved. A logic circuit includes a dynamic logic circuit, a first output node, a first transistor that is diode-connected, and a capacitor. The dynamic logic circuit includes a second output node. The first transistor and transistors in the dynamic logic circuit have an n-type conductivity or a p-type conductivity. The first output node is electrically connected to a first terminal of the capacitor, and the second output node is electrically connected to a second terminal of the capacitor. A first terminal of the first transistor is electrically connected to the first output node, and a first voltage is input to a second terminal of the first transistor. | 2017-11-30 |
20170346490 | Semiconductor Device Layout - A semiconductor device, comprising at least one active region; at least one MD region formed over a portion of the at least one active region; and at least one gate electrode formed over a portion of the at least one active region different than the portion of the active region where the MD region is formed. The semiconductor device further comprises at least one metal layer over at least a portion of the at least one active region, the at least one metal layer being located on a layer of the semiconductor device, different than the layers on which the at least one MD region and at least one gate electrode are formed. A via is formed over the at least one active region and configured to connect one of the at least one gate electrodes to one of the at least one metal layers. The at least one metal layer is configured to enable the at least one gate electrode to be connected to another at least one electrode and/or at least one MD region. | 2017-11-30 |
20170346491 | PROGRAMMING SYSTEM AND METHOD - A programming method includes an upper computer, a calculation module, and a first signal conversion module. The calculation module includes a second signal conversion module and a programming interface. The upper computer is configured to convert programming data into first bus signals. When the calculation module is in a normal programming state, the second signal conversion module converts the first bus signals into first clock signals and first data signals to program the calculation module. When the calculation module is in a non-normal programming state, the first signal conversion module converts the first bus signals into second clock signals and second data signals to program the calculation module. A programming method is also provided. | 2017-11-30 |
20170346492 | TEST CIRCUIT TO ISOLATE HCI DEGRADATION - Embodiments are directed to a system for synchronizing switching events. The system includes a controller, a clock generator communicatively coupled to the controller and a delay chain communicatively coupled to the controller. The delay chain is configured to perform a plurality of delay chain switching events in response to an input to the delay chain. The controller is configured to initiate a synchronization phase that includes enabling the clock generator to provide as an input to the delay chain a clock generator output at a synchronization frequency, wherein the clock generator output passing through the delay chain synchronizes the plurality of delay chain switching events to occur at the synchronization frequency resulting in a frequency of an output of the delay chain being synchronized to the synchronization frequency of the clock generator output. | 2017-11-30 |
20170346493 | DTC-Based PLL and Method for Operating the DTC-Based PLL - The disclosure provides a phase locked loop, PLL, for phase locking an output signal to a reference signal. The PLL comprises a reference path providing the reference signal to a first input of a phase detector, a feedback loop providing the output signal of the PLL as a feedback signal to a second input of the phase detector, a controllable oscillator generating the output signal based on at least a phase difference between reference and feedback signal, a digital-to-time converter, DTC, delaying a signal that is provided at one of the first and second input, a delay calculation path for calculating a DTC delay value. The PLL further comprises a randomization unit for generating and adding a random offset, i.e. a pseudo-random integer, to the delay value. The offset is such that a target output of the phase detector remains substantially unchanged. | 2017-11-30 |
20170346494 | METHOD OF SPEEDING UP OUTPUT ALIGNMENT IN A DIGITAL PHASE LOCKED LOOP - To speed up output clock alignment in a digital phase locked loop wherein a controlled oscillator generates synthesizer pulses that are divided to produce output pulses at a predetermined normal spacing and time location, and wherein during an alignment procedure the output pulses are moved in time in response to a delay value obtained by comparing a phase of the output pulses with a phase applied to the controlled oscillator averaged over a number of synthesizer pulses in a feedback circuit to align said output pulses with a reference clock taking into account hardware delay, a group of the output pulses is advanced during the alignment procedure to reduce the spacing between them. After determining the delay value averaged over the group of output pulses subsequent output pulses are restored to their normal spacing and time locations. | 2017-11-30 |
20170346495 | FREQUENCY DIVIDER - A variable frequency divider arrangement is arranged to divide a frequency of an incoming signal by a variable number D to provide a resultant signal. The arrangement comprises:
| 2017-11-30 |
20170346496 | OSCILLATOR CALIBRATION - A phase locked loop comprises:
| 2017-11-30 |
20170346497 | OVERSAMPLING NOISE-SHAPING SUCCESSIVE APPROXIMATION ADC - A successive approximation Analogue to Digital Converter (ADC), comprising: a sample and hold device arranged to sample and hold an input signal at the beginning of a conversion cycle; a successive approximation register that sequentially builds up a digital output from its most significant bit to its least significant bit; a digital to analogue converter that outputs a signal based on the output of the successive approximation register; a comparator that compares the output of the digital to analogue converter with an output of the sample and hold device and supplies its output to the successive approximation register; and a residual signal storage device arranged to store the residual signal at the end of a conversion cycle; and wherein the successive approximation ADC is arranged to add the stored residual signal from the residual signal storage device to the input signal stored on the sample and hold device at the start of each conversion cycle. After each ADC full conversion by the SAR, the analogue conversion of the digital output is as close to the original input signal as the resolution will allow. However there remains the residual part of the input signal that is smaller than what can be represented by the least significant bit of the digital output of the SAR. In normal operation, successive outputs of a SAR for the same input will result in the same digital value output and the same residual. By storing the residual at the end of each conversion and adding the residual onto the input signal of the next conversion the residuals are accumulated over time so that they may affect the output digital value. After a number of conversions, the accumulated residuals add up to more than the value represented by the LSB of the register and the digital value will be one higher than if a conversion had been performed on the input signal alone. In this way, the residual signal affects the output value in time and thus can be taken into account by processing the digital output in the time domain. | 2017-11-30 |
20170346498 | CHARGE COMPENSATION CIRCUIT AND ANALOG-TO-DIGITAL CONVERTER WITH THE SAME - A charge compensation circuit for use in an analog-to-digital converter (ADC) includes at least one capacitor and at least one logic circuit. A first terminal of the capacitor is coupled to a reference voltage of the analog-to-digital converter. The logic circuit is configured to adjust a voltage at a second terminal of the capacitor according to a control signal. The control signal is determined according to at least one output bit from the analog-to-digital converter. | 2017-11-30 |
20170346499 | ANALOGUE TO DIGITAL CONVERTER - A SAR ADC is disclosed. The SAR ADC includes a plurality of SAR-capacitors. For each of the SAR-capacitors, a sampling-switching-block is configured to connect a first plate of the associated SAR-capacitor to either: v-ref-low, v-ref-high or an input-voltage. The SAR ADC also includes an offset-capacitor and an offset-switching-block configured to connect a first plate of the offset-capacitor to either: v-ref-low, or v-ref-high. The SAR ADC further includes a SAR machine configured to provide signals to the sampling-switching-blocks and the offset-switching-block in order to define a calibration-sampling-mode-of-operation, a calibration-conversion-mode-of-operation, a sampling-mode-of-operation and a conversion-mode-of-operation. A code converter is also includes and is configured to subtract the offset-value from the raw-digital-word in order to provide a digital-output-signal. | 2017-11-30 |
20170346500 | METHOD AND SYSTEM FOR ASYNCHRONOUS SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTOR (ADC) ARCHITECTURE - A system for processing signals may be configured to detect occurrence of particular errors, comprising meta-stability events, during digital conversion to analog signals, and to handle any detected meta-stability event, such as by adjusting at least a portion of a corresponding digital output based on detection of the meta-stability event. The adjusting of the digital output may comprise setting at least the portion of the digital output, such as to one of a plurality of predefined digital values or patterns. The system may comprise a code generator for generating and/or outputting the predefined digital values or patterns. The system may comprise a selector for adaptively selecting, for portions of the digital output, between output of normal processing path and between predefined values or patterns. | 2017-11-30 |
20170346501 | ANALOGUE-TO-DIGITAL CONVERTER - This application relates to analogue-to-digital converters (ADCs). An ADC | 2017-11-30 |
20170346502 | GENERATING A CODE ALPHABET OF SYMBOLS TO GENERATE CODEWORDS FOR WORDS USED WITH A PROGRAM - Provided are a computer program product, system, and method for generating a code alphabet for use by a deployed program to determine codewords for words. A first code alphabet has a first number of symbols that provide variable length codings of the words. A second code alphabet is generated having a second number of symbols formed by merging the symbols in the first code alphabet, wherein the second code alphabet comprises the code alphabet used by the deployed program. | 2017-11-30 |
20170346503 | Lossless Compression Method for Graph Traversal - To enable lossless compression, an auxiliary bitmap is used to provide side information about the graph bitmap. Each bit in the auxiliary bitmap represents a word in the graph bitmap. A zero bit in the auxiliary bitmap means that the corresponding word in the graph bitmap is not transmitted. Therefore, it is set to the default value, λ, during decompression. This default value could be either an all-zeros word, or all-ones word depending on the BFS step. A one bit in the auxiliary bitmap means that the corresponding word in the graph bitmap is transmitted. | 2017-11-30 |
20170346504 | APPARATUS AND METHOD FOR GENERATING AN ERROR CODE FOR A BLOCK COMPRISING A PLURALITY OF DATA BITS AND A PLURALITY OF ADDRESS BITS - An apparatus and method are provided for generating an error code for a block comprising a plurality of data bits and a plurality of address bits. The apparatus has block generation circuitry to generate a block comprising a plurality of data bits and a plurality of address bits, and error code generation circuitry for receiving that block and a mask array comprising a plurality of mask rows, and for then applying an error code generation algorithm to generate an error code for the block. The error code comprises a plurality of check bits, where each check bit is determined using the block and a corresponding mask row of the mask array. Each mask row comprises a plurality of mask bits, each mask bit being associated with a corresponding bit of the block. At least one mask row has its mask bit values constrained so as to ensure that when all of the data bits of the block have the same value, the error code generated by the error code generation circuitry has at least one check bit having a different value to the value of the data bits irrespective of the value of the address bits. In addition to supporting detection and/or correction of errors in the data bits, such an approach also allows memory address decode errors to be detected whilst in addition allowing detection of stuck at zero or stuck at one errors in a memory's output. | 2017-11-30 |
20170346505 | CIRCUITS AND METHODS FOR WRITING AND READING DATA - A writing circuit for writing write data into a memory comprises an evaluator configured for providing an error handling code on the basis of the write data. A modifier reversibly modifies extended write data comprising both the write data and the error handling code in dependence on address information related to a writing address in order to provide modified extended write data. A writer writes the modified extended write data in a position of the memory defined by a writing address. A reading circuit for reading extended read data from a memory comprises a reader configured for reading the extended read data from a position of the memory defined by a reading address. A de-modifier modifies the extended read data in dependence on address information related to a reading address in order to provide extracted read data and an extracted error handling code. An error-detector detects based on the extracted error handling code whether the extracted read data comprises an error. | 2017-11-30 |
20170346506 | MULTI-CHIP MILLIMETER-WAVE INTERFACE - Systems and methods are provided for millimeter-wave (MMW) communication, the system includes a transceiver chip to generate and to receive signals. An interface is used to communicate the signals between the transceiver chip and one or more active antenna modules. The signals include modulated MMW signals and control signals. The transceiver chip includes baseband circuitry, up and down conversion mixers, and RF front-end circuitry. An active antenna module receives a first modulated MMW signal from the interface for transmission via antennas and to receive a second modulated MMW signal from the antennas for transmission through the interface to the transceiver chip. | 2017-11-30 |
20170346507 | APPARATUS AND METHOD FOR REDUCED COMPUTATION AMPLIFIER GAIN CONTROL - Signals are received that include a channel band and an adjacent band. The channel band is demodulated to obtain recovered symbols. Cross-correlation between the recovered symbols and the adjacent band is estimated. Adjacent channel interference is estimated, using the estimated cross-correlation of the recovered symbols and the adjacent band. Upon the estimated adjacent channel interference meeting a condition, a back-off command is sent to a transmitter power amplifier. | 2017-11-30 |
20170346508 | DIRECT COMPENSATION OF IQ SAMPLES FOR UNDESIRED FREQUENCY DEVIATION IN PHASE LOCKED LOOPS - A transmitter includes estimation circuitry and correction circuitry. The estimation circuitry is configured to estimate, based at least on a phase error between a local oscillator and a reference frequency, values for parameters that describe a frequency deviation experienced by a phase locked loop (PLL) during transmission of the data sample, wherein the PLL includes a local oscillator. The correction circuitry is configured to generate a correction term based at least on the estimated parameters; adjust the data sample with the correction term to generate a compensated data sample; and provide the compensated data sample for modulation of a carrier wave generated by the local oscillator. | 2017-11-30 |
20170346509 | DIGITAL PRE-EMPHASIS QUADRATURE IMBALANCE COMPENSATING FILTER - A transmitter includes a pre-emphasis digital filter configured to filter a series of respective digital input data samples according to a plurality of coefficients to generate a series of respective corresponding pre-emphasized data samples. The transmitter also includes a digital-to-analog converter (DAC) configured to sample the series of pre-emphasized data samples to generate an analog signal and an analog filter configured to filter the analog signal to generate a filtered signal. Estimator circuitry is configured to input a pre-emphasized data sample; input a corresponding sample of the filtered signal; and calculate the plurality of coefficients based on the sample of the filtered signal and the pre-emphasized data sample. | 2017-11-30 |
20170346510 | QUADRATURE TRANSMITTER, WIRELESS COMMUNICATION UNIT, AND METHOD FOR SPUR SUPPRESSION - A quadrature transmitter is described that comprises: a first transmitter path and a second transmitter path that are matched. Each transmitter path comprises: at least one input arranged to receive respective first or second sets of quadrature baseband signals; at least one local oscillator, LO, port configured to receive respective first and second sets of quadrature LO signals; at least one mixer stage coupled to the at least one input and configured to respectively multiply the sets of quadrature baseband signals with the respective first or second sets of quadrature LO signals to produce a respective output radio frequency, RF, signal; and a combiner configured to combine the output radio frequency signals of the first transmitter path and the second transmitter path. The first set of quadrature signals is a substantially 45° phase shifted version of the second set of quadrature signals; and the first set of quadrature LO signals is a reverse substantially 45° phase shifted version of the second set of quadrature LO signals. | 2017-11-30 |
20170346511 | REMOVING RF INTERFERENCE THROUGH SCAN RATE LOCKING - This relates to methods and apparatus for mitigating effects of the presence of RF communication signals. In some examples, non-linearity and rectification of the RF communication signals can become rectified in sensor circuitry such that spectral components of a frame or sub-frame timing of the RF communication signals can be aliased into the sensor circuitry output within a bandwidth of interest. In some examples, a notch filter can be employed to remove the aliased RF communication signals from the sensor output. In some examples, a sampling rate used for sampling the user's physiological signals can be generated such that the sampling of the sensor is synchronous with the RF communication signals. In some examples, the sampling rate for the sensor can be generated as an integer multiple or integer submultiple of the frame or sub-frame timing of the RF communication signals. | 2017-11-30 |
20170346512 | METHOD FOR RECEIVING DATA IN MIMO MOLECULAR COMMUNICATION SYSTEM - Disclosed is a method for receiving data that can reduce intersymbol interference (ISI) and interlink interference (ILI) occurring in a MIMO molecular communication system. An embodiment of the present invention provides a method for receiving data at a receiver in a MIMO molecular communication system, where the method includes: determining an enzyme inhibitor discharge stopping timepoint by using the distance between the antennas of the transmitter and the distance between the transmitter and the receiver; discharging an enzyme inhibitor, which is configured to deactivate an enzyme that is distributed around the receiver, and receiving a molecule transmitted from the transmitter; and stopping the discharge of the enzyme inhibitor according to the enzyme inhibitor discharge stopping timepoint, and where the enzyme is reactive to the molecule. | 2017-11-30 |
20170346513 | EFFICIENT CLOSED LOOP TUNING USING SIGNAL STRENGH - A wireless communication system, in some embodiments, comprises: a receiver; one or more tunable elements, coupled to the receiver, to adjust an impedance of the system; and a processor, coupled to the one or more tunable elements, to tune said one or more tunable elements based on the strength of a received signal. | 2017-11-30 |
20170346514 | LOW-POWER RECEIVER - A low-power scouting receiver is presented that provides an ability perform low-power scouting functions at a relatively low power. The low-power scouting functions determine context information for the receiver and enable fine-tuning of other receiver operations based on the context information. The low-power scouting functions include receiver control and switching, jammer detection, self-interference detection, or other context-dependent radio parameters. | 2017-11-30 |
20170346515 | COMMUNICATION TERMINALS AND A METHOD FOR EXCHANGING INFORMATION BETWEEN COMMUNICATION TERMINALS IN A NOISY ENVIRONMENT - A method, system and computer readable medium for transmitting data and feedback over a noisy feedforward channel and a noisy feedback channel. | 2017-11-30 |
20170346516 | CONTOUR TUNING CIRCUIT AND RELATED SYSTEMS AND METHODS - Aspects of this disclosure relate tuning an impedance presented to a common port of a multi-throw switch and a tunable notch filter coupled to the common port. The impedance presented to the common port can be tuned based on an impedance associated with a throw of the multi-throw switch that is activated. According to embodiments of this disclosure, a shunt inductor in parallel with a tunable capacitance circuit can tune the impedance presented to the common port of the multi-throw switch. In certain embodiments, the tunable notch filter includes a series LC circuit in parallel with a tunable impedance circuit. | 2017-11-30 |
20170346517 | ADJUSTING AN ANTENNA CONFIGURATION OF A TERMINAL DEVICE IN A CELLULAR COMMUNICATION SYSTEM - A method for adjusting an antenna configuration of the terminal device ( | 2017-11-30 |
20170346518 | Noise and Interference Estimation for Colliding Neighbor Reference Signals - This disclosure relates to techniques for estimating noise and interference in a wireless communication system in which neighbor and serving cell reference signals are colliding. A wireless device and a base station may establish a wireless communication link such that the base station acts as a serving cell to the wireless device. It may be determined that one or more neighboring cells have colliding reference signals with the serving cell. Neighbor load conditions may be determined. A neighbor reference signal interference cancellation policy may be selected based at least in part on the determined neighbor load conditions and the one or more neighboring cells having colliding reference signals with the serving cell. | 2017-11-30 |
20170346519 | Signal Distribution System Cascadable AGC Device and Method - A cascadable AGC amplifier in a signal distribution system includes a low noise cascadable amplifier having a through path and a cascadable output. The cascadable amplifier is also configured to provide AGC over a predetermined input power range. The cascadable AGC amplifier can be configured to provide gain or attenuation. When the cascadable AGC amplifier is implemented in a signal distribution system, typically as part of a signal distribution device, an input signal can be gain controlled and supplied to multiple signal paths without distortion due to degradation of signal to noise ratio or distortion due to higher order amplifier products. The distributed signal is not significantly degraded by distortion regardless of the number of cascadable AGC amplifiers connected in series or the position of the cascadable AGC amplifier in the signal distribution system. | 2017-11-30 |
20170346520 | Multi-Standard, Multi-Channel Expandable TV/Satellite Receiver - In one example, a semiconductor die includes multi-standard, multi-channel expandable television/satellite receiver that can be flexibly implemented in a number of different configurations to enable incorporation into a plurality of different systems. The semiconductor die may include multiple tuners to receive and tune a terrestrial radio frequency (RF) signal and a satellite RF signal. These tuners may include different frequency synthesizers including voltage controlled oscillators (VCOs) to generate VCO signals at different frequencies, mixers to downconvert the RF signals to baseband signals using the VCO signals. In an implementation, the semiconductor die may further include shared circuitry coupled to the tuners to digitize, process and demodulate the baseband signals. | 2017-11-30 |
20170346521 | ELECTRONIC DEVICE WITH ANTENNA CONTROL FUNCTION AND ANTENNA CONTROL METHOD - An antenna control method selects as required one of two inbuilt antenna paths for optimal communication and includes a first transmission power of the antenna being acquired from one antenna path when a first and a second switch device are connected, and a second transmission power from a second antenna path when so connected. A determination is made on events or on a periodic basis as to whether the second transmission power is greater than or equal to the first transmission power, and the antenna path with greater power is selected for communication. | 2017-11-30 |
20170346522 | QUICK RELEASE MOUNT FOR HOLDING HANDHELD ELECTRONIC DEVICE - The present invention is to provide a quick release mount for holding handheld electronic device, comprises a mount base having an accommodating space inside, and a base hole on topside thereof; a constraint sliding plate movablely installed inside the accommodating space, having an upper side provided with a plate hole, a push button disposed on one end thereof, and having a free end exposed outside the mount base, when the push button is pushed, the stud element protruding on rear side of the handheld electronic device can pass through base and plate holes and freely access the accommodating space; and an resilient element abutted against the mount base and the constraint sliding plate, so that, when the push button is released, the resilient element can force the constraint sliding plate to move to a lock state not allowing the stud element to escape from the plate hole. | 2017-11-30 |
20170346523 | CASE FOR A TABLET SHAPED DEVICE, A METHOD FOR REMOVING A STYLUS THEREFROM AND A METHOD FOR MAKING A CASE FOR A TABLET SHAPED DEVICE - Disclosed herein is a case for a tablet shaped device, a method for removing a stylus therefrom, and a method for making a case for a tablet shaped device. | 2017-11-30 |