48th week of 2011 patent applcation highlights part 16 |
Patent application number | Title | Published |
20110291141 | SEMICONDUCTOR LIGHT-EMITTING ELEMENT - The present invention is directed to the provision of a semiconductor light-emitting element that has an electrode formed with a desired thickness using a plated metal layer. A semiconductor light-emitting element for flip-chip mounting on a circuit substrate includes a semiconductor layer including a light-emitting layer, an N-side bump electrode for connecting the semiconductor layer to the circuit substrate, and a P-type bump electrode for connecting the semiconductor layer to the circuit substrate, wherein the N-side bump electrode and the P-type bump electrode each include an under-bump metal layer and a plated metal layer, the under-bump metal layer includes a high-reflectivity metal layer disposed on a side that faces the semiconductor layer and a metal layer disposed on a side opposite from the semiconductor layer, and the plated metal layer has a thickness not less than 3 μm but not greater than 30 μm. | 2011-12-01 |
20110291142 | OXYNITRIDE PHOSPHOR, METHOD FOR PREPARING THE SAME, AND LIGHT-EMITTING DEVICE - The present invention relates to an oxynitride phosphor, a method for preparing the same, and a light-emitting device. More specifically, the present invention provides the oxynitride phosphor including crystals represented by the following Chemical Formula, a method for preparing the same, and a light-emitting device including the oxynitride phosphor. The invention includes the crystals' represented by the following Chemical Formula to obtain high light-emitting efficiency. [Chemical Formula] (A | 2011-12-01 |
20110291143 | LIGHT-EMITTING-DEVICE PACKAGE AND A METHOD FOR PRODUCING THE SAME - A light emitting device package includes: a substrate with a mounting surface; a light emitting device bonded to the mounting surface of the substrate; a light reflecting resin part containing a high reflective material, filled on the substrate around the light emitting device so as to extend in a space between the light emitting device and the substrate; and a packing resin part hermetically sealed to cover the light emitting device and the light reflection resin part. | 2011-12-01 |
20110291144 | OPTICAL SEMICONDUCTOR DEVICE - A semiconductor optical module M is disclosed, where it includes a stem | 2011-12-01 |
20110291145 | OPTOELECTRONIC ELEMENT AND MANUFACTURING METHOD THEREOF - An optoelectronic element includes an optoelectronic unit having a first top surface, a first bottom surface opposite to the first top surface, and a lateral surface between the first top surface and the first bottom surface; a first transparent structure covering the lateral surface and exposing the first top surface of the optoelectronic unit; a first insulating layer on the first top surface and the first transparent structure; a second insulating layer on the first insulating layer; a first opening through the first insulating layer and the second insulating layer; and a first conductive layer on the second insulating layer and electrically connecting to the optoelectronic unit via the first opening. | 2011-12-01 |
20110291146 | DRY FLUX BONDING DEVICE AND METHOD - Methods of forming devices, including LED devices, are described. The devices may include fluorinated compound layers. The methods described may utilize a plasma treatment to form the fluorinated compound layers. The methods described may operate to produce an intermetallic layer that bonds two substrates such as semiconductor wafers together in a relatively efficient and inexpensive manner. | 2011-12-01 |
20110291147 | OHMIC CONTACTS FOR SEMICONDUCTOR STRUCTURES - A composition and method for formation of ohmic contacts on a semiconductor structure are provided. The composition includes a TiAl | 2011-12-01 |
20110291148 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a first electrode, a second electrode, an insulating layer, a first interconnection layer, a second interconnection layer, a first metal pillar, a second metal pillar, a resin layer and a conductive material. The conductive material is provided on a surface of the resin layer between the first metal pillar and the second metal pillar, and electrically connects the first metal pillar and the second metal pillar. | 2011-12-01 |
20110291149 | LIGHT EMITTING DEVICE - According to one embodiment, a light emitting device includes a light emitting chip, an external terminal made of a metal material, and a circuit board. The light emitting chip is mounted on the circuit board via the external terminal. The light emitting chip includes a semiconductor layer, a first electrode, a second electrode, an insulating layer, a first interconnection layer, a second interconnection layer, a first metal pillar, a second metal pillar and a resin layer. The circuit board includes an interconnection bonded to the first metal pillar and the second metal pillar via the external terminal, and a heat radiation material provided on an opposite side of the interconnection and connected to the interconnection. | 2011-12-01 |
20110291150 | LED ILLUMINATION DEVICE - The invention disclose a light emitting diode (LED) illustration device, comprising a platform, a substrate and a light emitting diode die. The said platform comprises an upper surface and a bottom surface. A first concave portion is formed on the upper surface of the platform, and a second concave portion is formed on the bottom surface of the platform. The first concave portion is connected with the second concave portion. The substrate is embedded in the second concave portion, wherein the said substrate comprises an electrostatic discharge protection structure. The said light emitting diode die is disposed on the said substrate. | 2011-12-01 |
20110291151 | LIGHT EMITTING DEVICE AND LIGHTING APPARATUS - According to one embodiment, a light emitting device includes a ceramics substrate, a metallic thermally-conductive layer formed on the substrate in which the substrate involves no electric connection, a light emitting element mounted on the metallic thermally-conductive layer, and a metallic bonding layer interposed between the metallic thermally-conductive layer and the light emitting element to bond the light emitting element to the metallic thermally-conductive layer. | 2011-12-01 |
20110291152 | LED LEAD FRAME WITH WATER-REPELLENT LAYER - An LED lead frame includes a housing having a cavity for receiving an LED chip, and a pair of conductive leads mounted with the housing. Each lead includes an embedded section retained in the housing. The embedded section is plated with a silver layer thereon and a water-repellent layer disposed on the silver layer. | 2011-12-01 |
20110291153 | CHIP SUBMOUNT, CHIP PACKAGE, AND FABRICATION METHOD THEREOF - A light-emitting diode submount includes a base, a through silicon via and a sealing layer. The base has a die side and a back side. The through silicon via penetrates the base to connect the die side and the back side. The through silicon via includes a conoidal-shaped portion converging from the back side toward the die side, and a vertical via portion connects with the conoidal-shaped portion. A sealing layer seals the vertical via portion. | 2011-12-01 |
20110291154 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device, has a package constituted by the lamination of a first insulating layer having a pair of positive and negative conductive wires formed on its upper face, an inner-layer wire below the first insulating layer, and a second insulating layer below the inner-layer wire; a semiconductor light emitting element that has a pair of positive and negative electrodes on the same face side and that is disposed with these electrodes opposite the conductive wires; and a sealing member that covers the semiconductor light emitting element, wherein part of the conductive wires is formed extending in the outer edge direction of the sealing member from directly beneath the semiconductor light emitting element, on the upper face of the first insulating layer, and is connected to the inner-layer wire via a conductive wire disposed in the thickness direction of the package, and the inner-layer wire is disposed so as to be spaced apart from the outer periphery of the semiconductor light emitting element in a see-through view of the package from the upper face side of the first insulating layer. | 2011-12-01 |
20110291155 | Light-Emitting Diode Chip Package Body and Method for Manufacturing Same - A light-emitting diode chip package body with an excellent heat dissipation performance and a low manufacturing cost, and a packaging method of the same are disclosed. A LED chip package body is provided, the LED chip package body comprising: a LED chip having an electrode-side surface and at least two electrodes mounted on said electrode-side surface; an electrode-side insulating layer formed on said electrode-side surface of said LED chip and formed with a plurality of through-holes registered with corresponding said electrodes; a highly heat-dissipating layer formed in each of said through-holes of said insulating layer on said electrode-side surface; and a highly heat-conducting metal layer formed on said highly heat-dissipating layer in each of said through-holes. | 2011-12-01 |
20110291156 | ORGANIC ELECTROLUMINESCENT ELEMENT - An organic compound layer includes a fluorescent light-emitting sub-layer, a phosphorescent light-emitting sub-layer, and an exciton generation sub-layer which is disposed therebetween and which generates excitons. The interface between the fluorescent light-emitting sub-layer and the exciton generation sub-layer serves as an energy barrier for carriers. Excitons are generated on the exciton generation sub-layer side of the interface therebetween. | 2011-12-01 |
20110291157 | LATERAL INSULATED GATE BIPOLAR TRANSISTOR - A lateral insulated gate bipolar transistor includes a semiconductor substrate including a drift layer, a collector region, a channel layer, an emitter region, a gate insulating layer, a gate electrode, a collector electrode, an emitter electrode, and a barrier layer. The barrier layer is disposed along either side of the collector region and is located to a depth deeper than a bottom of the channel layer. The barrier layer has an impurity concentration that is higher than an impurity concentration of the drift layer. The barrier layer has a first end close to the collector region and a second end far from the collector region. The first end is located between the channel layer and the collector region, and the second end is located on the bottom of the channel layer. | 2011-12-01 |
20110291158 | HETERO-JUNCTION BIPOLAR PHOTOTRANSISTOR - The present invention provides a HPT having high sensitivity and extensive wavelength band characteristics. The collector and barrier layer ( | 2011-12-01 |
20110291159 | Stress release structures for metal electrodes of semiconductor devices - This invention teaches stress release metal electrodes for gate, drain and source in a field effect transistor and stress release metal electrodes for emitter, base and collector in a bipolar transistor. Due to the large difference in the thermal expansion coefficients between semiconductor materials and metal electrodes, significant strain and stresses can be induced in the devices during the fabrication and operation. The present invention provides metal electrode with stress release structures to reduce the strain and stresses in these devices. | 2011-12-01 |
20110291160 | FIELD EFFECT TRANSISTOR - A field effect transistor includes a nitride-based semiconductor multi-layer structure, a source electrode ( | 2011-12-01 |
20110291161 | PHYSICAL QUANTITY DETECTING DEVICE AND IMAGING APPARATUS - A physical quality detecting device including: a detecting unit that detects a physical quantity supplied from the outside with photo-converting pixels which are two-dimensionally arranged, each of which has a selecting transistor for outputting a signal from the detecting unit to a signal line. In the physical quality detecting device, the selecting transistor is a depletion-type transistor. The signal line is selectively coupled to a reference voltage. | 2011-12-01 |
20110291162 | SOLID STATE IMAGING DEVICE - Each of pixels | 2011-12-01 |
20110291163 | Reduction of Defect Rates in PFET Transistors Comprising a Si/Ge Semiconductor Material Formed by Epitaxial Growth - In sophisticated semiconductor devices, the defect rate that may typically be associated with the provision of a silicon/germanium material in the active region of P-channel transistors may be significantly decreased by incorporating a carbon species prior to or during the selective epitaxial growth of the silicon/germanium material. In some embodiments, the carbon species may be incorporated during the selective growth process, while in other cases an ion implantation process may be used. In this case, superior strain conditions may also be obtained in N-channel transistors. | 2011-12-01 |
20110291164 | CMOS three-dimensional image sensor detectors with assured non collection of late arriving charge, more rapid collection of other charge, and with improved modulation contrast - A CMOS-implementable TOF detector promptly collects charge whose creation time can be precisely known, while rejecting collection of potentially late arriving charge whose creation time may not be precisely known. Charges created in upper regions of the detector structure are ensured to be rapidly collected, while charges created in the lower regions of the detector structure, potentially late arriving charges, are inhibiting from being collected. | 2011-12-01 |
20110291165 | DETECTOR MODULE - A detector module, in particular for super-resolution satellites, contains a multi-chip carrier. At least one TDI-CCD detector and at least one CMOS chip are arranged on the multi-chip carrier, and are electrically connected to one another. The CMOS chip contains at least the digital output electronics for the TDI-CCD detector. | 2011-12-01 |
20110291166 | INTEGRATED CIRCUIT WITH FINFETS AND MIM FIN CAPACITOR - An integrated circuit having finFETs and a metal-insulator-metal (MIM) fin capacitor and methods of manufacture are disclosed. A method includes forming a first finFET comprising a first dielectric and a first conductor; forming a second finFET comprising a second dielectric and a second conductor; and forming a fin capacitor comprising the first conductor, the second dielectric, and the second conductor. | 2011-12-01 |
20110291167 | SEMICONDUCTOR DEVICE - In one embodiment, a semiconductor device includes a substrate having a through hole, and a MEMS capacitor provided above the substrate. The device further includes an integrated circuit configured to control the MEMS capacitor, the circuit including transistors on the substrate and being provided under the MEMS capacitor and on the substrate. Further, an area on the substrate immediately under the MEMS capacitor overlaps at least partially with the through hole. | 2011-12-01 |
20110291168 | SEMICONDUCTOR DEVICE HAVING ESD STRUCTURE - Semiconductor layers on active areas for transistors in a memory cell region (region A) and a peripheral circuit region (region B) are simultaneously epitaxially grown in the same thickness in which the adjacent semiconductor layers in region A do not come into contact with each other. Only semiconductor layer ( | 2011-12-01 |
20110291169 | REDUCED CORNER LEAKAGE IN SOI STRUCTURE AND METHOD - A structural alternative to retro doping to reduce transistor leakage is provided by providing a liner in a trench, undercutting a conduction channel region in an active semiconductor layer, etching a side, corner and/or bottom of the conduction channel where the undercut exposes semiconductor material in the active layer and replacing the removed portion of the conduction channel with insulator. This shaping of the conduction channel increases the distance to adjacent circuit elements which, if charged, could otherwise induce a voltage and cause a change in back-channel threshold in regions of the conduction channel and narrows and reduces cross-sectional area of the channel where the conduction in the channel is not well-controlled; both of which effects significantly reduce leakage of the transistor. | 2011-12-01 |
20110291170 | Semiconductor Device Comprising a Buried Capacitor Formed in the Contact Level - In a semiconductor device, capacitors may be formed so as to be in direct contact with a transistor by using a shared transistor region, such as a drain region or a source region of closely spaced transistors, as one capacitor electrode, while the other capacitor electrode is provided in the form of a buried electrode in the dielectric material of the contact level. To this end, dielectric material may be deposited so as to reliably form a void, wherein, at any appropriate manufacturing stage, a capacitor dielectric material may be provided so as to separate the capacitor electrodes. | 2011-12-01 |
20110291171 | VARACTOR - A variable capacitance device including a plurality of FETs, the sources and drains of each FET being coupled to a first terminal, the gates of each FET being coupled to a second terminal, the capacitance of said device between said first and second terminals varying as a function of the voltage across said terminals, the device further including a biasing providing a respective backgate bias voltage to each the FETs setting a respective gate threshold voltage thereof. The aggregate V-C characteristic can be tuned as desired, either at design time or dynamically. The greater the number of FETs forming the varactor, the greater the number of possible Vt values that can be individually set, so that arbitrary V-C characteristics can be more closely approximated. | 2011-12-01 |
20110291172 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes a substrate doped with a first conductive type dopant, a plurality of stacked structures arranged side by side on the substrate and extending in a first direction, each of the stacked structures including gate electrodes spaced apart from each other, the plurality of stacked structures including a pair of stacked structures spaced apart from each other at a first interval in a second direction perpendicular to the first direction, and a pick-up region extending in the first direction in the substrate between the pair of stacked structures and doped with the first conductive type dopant. | 2011-12-01 |
20110291173 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The invention provides a semiconductor device and its manufacturing method in which a memory transistor and a plurality of thin film transistors that have gate insulating films with different thicknesses are fabricated over a substrate. The invention is characterized by the structural difference between the memory transistor and the plurality of thin film transistors. Specifically, the memory transistor and some of the plurality of thin film transistors are provided to have a bottom gate structure while the other thin film transistors are provided to have a top gate structure, which enables the reduction of characteristic defects of the transistor and simplification of its manufacturing process. | 2011-12-01 |
20110291174 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a nonvolatile semiconductor memory device includes a substrate, and a well region formed in the substrate. The device further includes device regions formed in the well region and defined by isolation trenches formed in the well region, the device regions extending in a first direction parallel to a principal surface of the substrate, and being adjacent to one another in a second direction that is perpendicular to the first direction. The device further includes isolation insulators buried in the isolation trenches to isolate the device regions from one another. The device further includes floating gates disposed on the device regions via gate insulators, and a control gate disposed on the floating gates via an intergate insulator. The device further includes first diffusion suppressing layers formed inside the respective device regions to divide each of the device regions into an upper device region and a lower device region. The device further includes second diffusion suppressing layers formed on side surfaces of the respective upper device regions, the side surfaces being perpendicular to the second direction. | 2011-12-01 |
20110291175 | Non-Volatile Memory Devices and Methods of Manufacturing the Same - A non-volatile memory device includes a field region that defines an active region in a semiconductor substrate, a floating gate pattern on the active region, a dielectric layer on the floating gate pattern and a control gate on the dielectric layer. The control gate includes a first conductive pattern that has a first composition that crystallizes in a first temperature range, and a second conductive pattern that has a second composition that is different from the first composition and that crystallizes in a second temperature range that is lower than the first temperature range, the first conductive pattern being between the dielectric layer and the second conductive pattern. | 2011-12-01 |
20110291176 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device includes a pair of columnar cell channels vertically extending from a substrate, a doped pipe channel arranged to couple lower ends of the pair of columnar cell channels, insulation layers over the substrate in which the doped pipe channel is buried, memory layers arranged to surround side surfaces of the columnar cell channels, and control gate electrodes arranged to surround the memory layers. | 2011-12-01 |
20110291177 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a pipe insulation layer having a pipe channel hole, a pipe gate disposed over the pipe insulation layer, a pair of cell strings each having a columnar cell channel, and a pipe channel coupling the columnar cell channels and surrounding inner sidewalls and a bottom of the pipe channel hole. | 2011-12-01 |
20110291178 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes a substrate, a lower gate layer, a stacked body, a dummy electrode layer, an insulating film, and a channel body. The lower gate layer is provided above the substrate. The stacked body includes a plurality of insulating layers and a plurality of electrode layers alternately stacked above the lower gate layer. The dummy electrode layer is provided between the lower gate layer and the stacked body, made of the same material as the electrode layer, and thicker than each of the electrode layers. The insulating film includes a charge storage film provided on a side wall of a hole formed to penetrate through the stacked body and the dummy electrode layer. The channel body is provided on an inside of the insulating film in the hole. | 2011-12-01 |
20110291179 | Scalable Interpoly Dielectric Stacks With Improved Immunity to Program Saturation - A method for manufacturing a non-volatile memory device is described. The method comprises growing a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored. A non-volatile memory device is also described. In the non-volatile memory device, the interpoly/blocking dielectric comprises a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored, the siliconoxide consuming material having consumed at least part of the upper layer. | 2011-12-01 |
20110291180 | ANGLED ION IMPLANTATION IN A SEMICONDUCTOR DEVICE - Angled ion implants are utilized to form doped regions in a semiconductor pillar formed in an opening of a mask. The pillar is formed to a height less than the height of the mask. Angled ion implantation can be used to form regions of a semiconductor device such as a body tie region, a halo region, or current terminal extension region of a semiconductor device implemented with the semiconductor pillar. | 2011-12-01 |
20110291181 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device including a cell region and a terminal region includes a first semiconductor region of a first conductivity type, semiconductor pillars of the first and a second conductivity type, a second semiconductor region of the second conductivity type, and a third semiconductor region of the first conductivity type. The semiconductor pillars of the first and second conductivity type are and arranged alternately on the first semiconductor region. The second semiconductor region is provided on the semiconductor pillar of the second conductivity type. The third semiconductor region is provided on the second semiconductor region. A semiconductor pillar other than a semiconductor pillar most proximal to the terminal region is provided in a stripe configuration. The semiconductor pillar most proximal to the terminal region includes regions having a high and a low impurity concentration. The regions are provided alternately. | 2011-12-01 |
20110291182 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes vertical pillars formed by etching a semiconductor substrate and junction regions which are located among the neighboring vertical pillars and spaced apart from one another in a zigzag pattern. As a result, the semiconductor device easily guarantees an electrical passage between the semiconductor substrate and the vertical pillars, such that it substantially prevents the floating phenomenon from being generated, resulting in the prevention of deterioration of the semiconductor device. | 2011-12-01 |
20110291183 | POWER SEMICONDUCTOR DEVICE HAVING LOW GATE INPUT RESISTANCE AND MANUFACTURING METHOD THEREOF - A power semiconductor device having low gate input resistance and a manufacturing method thereof are provided. The power semiconductor device includes a substrate, at least a trench transistor, a conductive layer, a metal contact plug, an insulating layer, an interlayer dielectric, a gate metal layer, and a source metal layer. The metal contact plug can serve as a buried gate metal bus line, and the metal contact plug can pass under the source metal layer and keeps the area of the source metal layer complete. Accordingly, the present invention can provide a lower gate input resistance without dividing the source metal layer, so the source metal layer can have a larger and complete area for the following packaging and bonding process. | 2011-12-01 |
20110291184 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The present application discloses a semiconductor structure and a method for manufacturing the same. The semiconductor structure comprises a semiconductor substrate; an epitaxial semiconductor layer formed on two side portions of the semiconductor substrate; a gate stack formed at a central position on the semiconductor substrate and abutting the epitaxial semiconductor layer, the gate comprising a gate conductor layer and a gate dielectric layer which is sandwiched between the gate conductor layer and the semiconductor substrate and surrounding the lateral surfaces of the gate conductor layer; and a sidewall spacer formed on the epitaxial semiconductor layer and surrounding the gate. The method for manufacturing the above semiconductor structure comprises forming raised source/drain regions in the epitaxial semiconductor layer utilizing the sacrificial gate. The semiconductor structure and the method for manufacturing the same can simplify the fabrication process for an ultra-thin SOI transistor and reduce the ON-state resistance and power consumption of the transistor. | 2011-12-01 |
20110291185 | Semiconductor Device Having an Edge Termination Structure and Method of Manufacture Thereof - A semiconductor device having a semiconductor body ( | 2011-12-01 |
20110291186 | Semiconductor power devices manufactured with self-aligned processes and more reliable electrical contacts - This invention discloses semiconductor power device that includes a plurality of top electrical terminals disposed near a top surface of a semiconductor substrate. Each and every one of the top electrical terminals comprises a terminal contact layer formed as a silicide contact layer near the top surface of the semiconductor substrate. The trench gates of the semiconductor power device are opened from the top surface of the semiconductor substrate and each and every one of the trench gates comprises the silicide layer configured as a recessed silicide contact layer disposed on top of every on of the trench gates slightly below a top surface of the semiconductor substrate surround the trench gate. | 2011-12-01 |
20110291187 | Double Diffused Drain Metal-Oxide-Semiconductor Devices with Floating Poly Thereon and Methods of Manufacturing The Same - A metal-oxide-semiconductor (MOS) device is disclosed. The MOS device includes a substrate of a first impurity type, a diffused region of a second impurity type in the substrate, a patterned first dielectric layer including a first dielectric portion over the diffused region, a patterned first conductive layer on the patterned first dielectric layer, the patterned first conductive layer including a first conductive portion on the first dielectric portion, a patterned second dielectric layer including a second dielectric portion that extends on a first portion of an upper surface of the first conductive portion and along a sidewall of the first conductive portion to the substrate; and a patterned second conductive layer on the patterned second dielectric layer, the patterned second conductive layer including a second conductive portion on the second dielectric portion. | 2011-12-01 |
20110291188 | STRAINED FINFET - A FinFET is described incorporating at least two fins extending from a common Si containing layer and epitaxial material grown from the common layer and from sidewalls of the fins to introduce strain to the common layer and the fins to increase carrier mobility. | 2011-12-01 |
20110291189 | THIN CHANNEL DEVICE AND FABRICATION METHOD WITH A REVERSE EMBEDDED STRESSOR - A device and method for inducing stress in a semiconductor layer includes providing a substrate having a dielectric layer formed between a first semiconductor layer and a second semiconductor layer. A removable buried layer is provided on or in the second semiconductor layer. A gate structure with side spacers is formed on the first semiconductor layer. Recesses are formed down to the removable buried layer in areas for source and drain regions. The removable buried layer is etched away to form an undercut below the dielectric layer below the gate structure. A stressor layer is formed in the undercut, and source and drain regions are formed. | 2011-12-01 |
20110291190 | System and method for integrated circuits with cylindrical gate structures - A system and method for integrated circuits with surrounding gate structures are disclosed. The integrated circuits system includes a transistor having a gate all around cylindrical (GAAC) nanowire channel with an interposed dielectric layer. The cylindrical nanowire channel being in a middle section of a semiconductor wire pattern connects the source and drain region positioned at the two opposite end sections of the same wire pattern. A method is provided for manufacturing the integrate circuits system with a GAAC transistor including forming an SOI layer wire pattern on the buried oxide layer of an SOI wafer; forming a cavity underneath the middle section of the wire pattern and shaping the middle section to cylindrically shaped channel; forming a gate electrode surrounding the cylindrical channel region with an interposed gate dielectric layer, the gate electrode being positioned on the buried oxide layer vertically towards the wire pattern; forming the source/drain regions at the two opposite end sections of the wire pattern on either sides of the gate electrode and channel. | 2011-12-01 |
20110291191 | MOS Structure with Suppressed SOI Floating Body Effect and Manufacturing Method thereof - The present invention discloses a MOS structure with suppressed floating body effect including a substrate, a buried insulation layer provided on the substrate, and an active area provided on the buried insulation layer comprising a body region, a first conductive type source region and a first conductive type drain region provided on both sides of the body region respectively and a gate region provide on top of the body region, wherein the active area further comprises a highly doped second conductive type region between the first conductive type source region and the buried insulation layer. For manufacturing this structure, implant ions into a first conductive type source region via a mask having an opening thereon forming a highly doped second conductive type region under the first conductive type source region and above the buried insulation layer. The present invention will not increase chip area and is compatible with conventional CMOS process. | 2011-12-01 |
20110291192 | INCREASING BODY DOPANT UNIFORMITY IN MULTI-GATE TRANSISTOR DEVICES - Techniques and structures for increasing body dopant uniformity in multi-gate transistor devices are generally described. In one example, an electronic device includes a semiconductor substrate, a multi-gate fin coupled with the semiconductor substrate, the multi-gate fin comprising a source region, a drain region, and a gate region wherein the gate region is disposed between the source region and the drain region, the gate region being body-doped after a sacrificial gate structure is removed from the multi-gate fin and before a subsequent gate structure is formed, a dielectric material coupled with the source region and the drain region of the multi-gate fin, and the subsequent gate structure coupled to the gate region of the multi-gate fin. | 2011-12-01 |
20110291193 | HIGH DENSITY BUTTED JUNCTION CMOS INVERTER, AND MAKING AND LAYOUT OF SAME - A high density, asymmetric, butted junction CMOS inverter, formed on an SOI substrate, may include: an asymmetric p-FET that includes a halo implant on only a source side of the p-FET; an asymmetric n-FET that includes a halo implant on only a source side of the n-FET; and a butted junction comprising an area of said SOI substrate where a drain region of the asymmetric n-FET and a drain region of the asymmetric p-FET are in direct physical contact. Asymmetric halo implants may be formed by a sequential process of covering a first FET of the CMOS inverter with an ion-absorbing structure and applying angled ion radiation to only the source side of the second FET, removing the ion-absorbing structure, covering the first FET with a second ion-absorbing structure, and applying angled ion radiation to only the source side of the second FET. A layout display of CMOS integrated circuit may require one ground rule for the high density, asymmetric butted junction CMOS inverter and another ground rule for other CMOS circuits. | 2011-12-01 |
20110291194 | PROTECTION CIRCUIT FOR SEMICONDUCTOR DEVICE - A protection circuit for a semiconductor device includes a first gate electrode formed on a substrate of a first conductivity type, and a source and a drain of a second conductivity type having an opposite polarity to the first conductivity type. The source and the drain are commonly coupled to a ground voltage terminal, and the first gate electrode is coupled to a power supply voltage terminal. | 2011-12-01 |
20110291195 | Depletion-Mode MOSFET Circuit and Applications - Positive logic circuits, systems and methods using MOSFETs operated in a depletion-mode, including electrostatic discharge protection circuits (ESD), non-inverting latches and buffers, and one-to-three transistor static random access memory cells. These novel circuits supplement enhancement-mode MOSFET technology and are also intended to improve the reliability of the complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) products. | 2011-12-01 |
20110291196 | Self-Aligned Multiple Gate Transistor Formed on a Bulk Substrate - Three-dimensional transistors in a bulk configuration may be formed on the basis of gate openings or gate trenches provided in a mask material. Hence, self-aligned semiconductor fins may be efficiently patterned in the underlying active region in a portion defined by the gate opening, while other gate openings may be efficiently masked, in which planar transistors are to be provided. After patterning the semiconductor fins and adjusting the effective height thereof, the further processing may be continued on the basis of process techniques that may be commonly applied to the planar transistors and the three-dimensional transistors. | 2011-12-01 |
20110291197 | INTEGRATED CIRCUITS AND MANUFACTURING METHODS THEREOF - An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is spaced from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. The first metallic layer is electrically coupled with the first source region. The first metallic layer and the first diffusion area overlap with a first distance. A second metallic layer is electrically coupled with the first drain region and the second drain region. The second metallic layer and the first diffusion area overlap with a second distance. The first distance is larger than the second distance. | 2011-12-01 |
20110291198 | Scaled Equivalent Oxide Thickness for Field Effect Transistor Devices - A method for forming a field effect transistor device includes forming an oxide layer on a substrate, forming a dielectric layer on the oxide layer, forming a first TiN layer on the dielectric layer, forming a metallic layer on the first layer, forming a second TiN layer on the metallic layer, removing a portion of the first TiN layer, the metallic layer, and the second TiN layer to expose a portion of the dielectric layer, forming a layer of stoichiometric TiN on the exposed portion of the dielectric layer and the second TiN layer, heating the device, and forming a polysilicon layer on the device. | 2011-12-01 |
20110291199 | SRAM MEMORY CELL WITH FOUR TRANSISTORS PROVIDED WITH A COUNTER-ELECTRODE - The memory cell is of SRAM type with four transistors provided with a counter-electrode. It comprises a first area made from semiconductor material with a first transfer transistor and a first driver transistor connected in series, their common terminal defining a first electric node. A second transfer transistor and a second driver transistor are connected in series on a second area made from semiconductor material and their common terminal defines a second electric node. The support substrate comprises first and second counter-electrodes. The first and second counter-electrodes are located respectively facing the first and second semiconductor material areas. The first transfer transistor and second driver transistor are on a first side of a plane passing through the first and second electric nodes whereas the first driver transistor and second transfer transistor are on the other side of the plane. | 2011-12-01 |
20110291200 | INTEGRATED CIRCUITS AND MANUFACTURING METHODS THEREOF - An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure. | 2011-12-01 |
20110291201 | MULTI-STRAINED SOURCE/DRAIN STRUCTURES - The present disclosure provides a semiconductor device. The semiconductor device includes a silicon substrate. The semiconductor device includes first and second regions that are disposed in the substrate. The first and second regions have a silicon compound material. The semiconductor device includes first and second source/drain structures that are partially disposed in the first and second regions, respectively. The semiconductor device includes a first gate that is disposed over the substrate. The first gate has a first proximity to the first region. The semiconductor device includes a second gate that is disposed over the substrate. The second gate has a second proximity to the second region. The second proximity is different from the first proximity. The first source/drain structure and the first gate are portions of a first transistor, and the second source/drain structure and the second gate are portions of a second transistor. | 2011-12-01 |
20110291202 | DEVICE AND METHOD OF REDUCING JUNCTION LEAKAGE - A device and method for reducing junction leakage in a semiconductor junction includes forming a faceted raised structure in a source/drain region of the device. Dopants are diffused from the faceted raised structure into a substrate below the faceted raised structure to form source/drain regions. A sprinkle implantation is applied on the faceted raised structure to produce a multi-depth dopant profile in the substrate for the source/drain regions. | 2011-12-01 |
20110291203 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device according to an embodiment of the present invention includes a active region, a drain electrode, a source electrode, a gate electrode, a passivation layer, a source field plate, and a electrical connection. The active region is formed on a semiconductor substrate. The drain electrode, the source electrode, and the gate electrode are formed on a surface of the active region to be separated from each other. The passivation layer is formed on a surface of the active region between the drain electrode and the source electrode to cover the gate electrode. The source field plate is formed at least at a position including an upper portion of the drain-side end portion of the gate electrode on a surface of the passivation layer. The electrical connection is formed on the passivation layer to connect the source field plate and the source electrode. The electrical connection has a width of the electrical connection smaller than electrode widths of the source field plate and the source electrode. | 2011-12-01 |
20110291204 | SEMICONDUCTOR DEVICE HAVING STI WITH NITRIDE LINER AND UV LIGHT SHIELDING FILM - A semiconductor device has: a silicon substrate; trench formed downward from the surface of the silicon substrate, the trench defining active regions on the surface of the silicon substrate; a first liner layer of a silicon nitride film covering an inner wall of the trench; a second liner layer of a silicon nitride layer formed on the first liner layer; an element isolation region of an insulator formed on the second liner layer; a p-channel MOS transistor formed in and on one of the active regions; a contact etch stopper layer of a silicon nitride layer not having a ultraviolet shielding ability, formed above the silicon substrate, and covering the p-channel MOS transistor; and a light shielding film of a silicon nitride layer having the ultraviolet shielding ability and formed above the contact etch stopper layer. | 2011-12-01 |
20110291205 | HIGH-K GATE DIELECTRIC AND METHOD OF MANUFACTURE - A device and method of formation are provided for a high-k gate dielectric and gate electrode. The high-k dielectric material is formed, and a silicon-rich film is formed over the high-k dielectric material. The silicon-rich film is then treated through either oxidation or nitridation to reduce the Fermi-level pinning that results from both the bonding of the high-k material to the subsequent gate conductor and also from a lack of oxygen along the interface of the high-k dielectric material and the gate conductor. A conductive material is then formed over the film through a controlled process to create the gate conductor. | 2011-12-01 |
20110291206 | Semiconductor Device and Method of Manufacturing a Semiconductor Device - A semiconductor device and a method of manufacturing a gate stack for such a semiconductor device. The device includes a gate stack that has a gate insulation layer provided over a channel region of the device, and a metal layer that is insulated from the channel region by the gate insulation layer. The metal layer contains work function modulating impurities which have a concentration profile that varies along a length of the metal layer from the source region to the drain region. The gate stack has a first effective work function in the vicinity of a source region and/or the drain region of the device and a second, different effective work function toward a centre of the channel region. | 2011-12-01 |
20110291207 | TRANSDUCER DEVICES HAVING DIFFERENT FREQUENCIES BASED ON LAYER THICKNESSES AND METHOD OF FABRICATING THE SAME - A transducer array on a common substrate includes a membrane and first and second transducer devices. The membrane is formed on the common substrate, and includes a lower layer and an upper layer. The first transducer device includes a first resonator stack formed on at least the lower layer in a first portion of the membrane, the upper layer having a first thickness in the first portion of the membrane. The second transducer device includes a second resonator stack formed on at least the lower layer in a second portion of the membrane, the upper layer having a second thickness in the second portion of the membrane, where the second thickness is different from the first thickness, such that a first resonant frequency of the first transducer device is different from a second resonant frequency of the second transducer device. | 2011-12-01 |
20110291208 | ELEMENT STRUCTURE, INERTIA SENSOR, AND ELECTRONIC DEVICE - Manufacturing of an element structure including a capacitor is to be facilitated. An element structure includes a first substrate that has a first support layer and a first movable beam having one end supported side the first support layer and the other end having a void part provided therearound and a second substrate that has a second support layer and a first fixing electrode formed side the second support layer wherein the second substrate is disposed to face above the first substrate, the first movable beam is provided with a first movable electrode and the first fixing electrode and the first movable electrode are disposed to face each other, with a gap therebetween. | 2011-12-01 |
20110291209 | MAGNETIC MEMORY DEVICE - To provide a magnetic memory device having an increased write current and improved reliability in writing. The magnetic memory device of the invention has a substrate, a write line provided over the substrate, a bit line placed with a space from the write line in a thickness direction of the substrate and extending in a direction crossing with an extending direction of the write line, and a magnetic memory element positioned between the write line and the bit line. The magnetic memory element has a pinned layer whose magnetization direction has been fixed and a recording layer whose magnetization direction changes, depending on an external magnetic field. The recording layer contains an alloy film. The alloy film contains cobalt, iron, and boron and its boron content exceeds 21 at %. | 2011-12-01 |
20110291210 | BETAVOLTAIC POWER CONVERTER DIE STACKING - A power converter comprises a first die and a second die. Each die comprises a semiconductor substrate comprising a junction for converting nuclear radiation particles to electrical energy, the junction of each semiconductor substrate comprising a first side and a second side, a first electrode comprising a nuclear radiation-emitting radioisotope deposited on the semiconductor substrate, the first electrode being electrically connected to the first side of the junction, and a second electrode deposited on the semiconductor substrate, the second electrode being electrically connected to the second side. A bond is formed between one of the first electrode or the second electrode of the first die and one of the first electrode or the second electrode of the second die, wherein the bond forms an electrical contact between the bonded electrodes. | 2011-12-01 |
20110291211 | IMAGE SENSOR AND RELATED FABRICATING METHOD THEREOF - A fabricating method of an image sensor includes the steps of: providing a substrate; forming sensing elements on the substrate; forming microlenses on the sensing elements; filling a stuffed material on the microlenses, and air regions are formed in the stuffed material; and forming optical filters on the stuffed material. | 2011-12-01 |
20110291212 | IMAGING APPARATUS HAVING PHOTOSENSOR AND MANUFACTURING METHOD OF THE SAME - A photosensor comprises a photoelectric conversion device region and a connection pad on the lower surface of a semiconductor substrate, and also comprises a wiring line connected to the connection pad via insulating film under the semiconductor substrate, and a columnar electrode as an external connection electrode connected to the wiring line. As a result, as compared with the case where the photoelectric conversion device region and the connection pad connected to the photoelectric conversion device region are formed on the upper surface of the semiconductor substrate, a piercing electrode for connecting the connection pad and the wiring line does not have to be formed in the semiconductor substrate. Thus, the number of steps can be smaller, and a fabrication process can be less restricted. | 2011-12-01 |
20110291213 | PHOTODIODE MANUFACTURING METHOD AND PHOTODIODES - A semiconductor substrate | 2011-12-01 |
20110291214 | PHOTO MASK AND METHOD FOR FABRICATING IMAGE SENSORS - A method for fabricating an image sensor includes forming an insulation layer over a substrate in a logic circuit region and a pixel region, forming a photoresist over the insulation layer, patterning the photoresist to form a photoresist pattern where the insulation layer in the pixel region is exposed and the insulation layer in the logic circuit region is not exposed, wherein a thickness of the photoresist pattern is gradually decreased in an interfacial region between the pixel region and the logic circuit region in a direction of the logic circuit region to the pixel region, and performing an etch back process over the insulation layer and the photoresist pattern in conditions that an etch rate of the photoresist pattern are substantially the same as that of the insulation layer. | 2011-12-01 |
20110291215 | WAFER LEVEL IMAGE SENSOR PACKAGING STRUCTURE AND MANUFACTURING METHOD FOR THE SAME - The present invention discloses a wafer level image sensor packaging structure and a manufacturing method for the same. The manufacturing method includes the following steps: providing a silicon wafer with image sensor chips, providing a plurality of transparent lids, allotting one said transparent lid on top of the corresponding image sensor chip, and carrying out a packaging process. The manufacturing method of the invention has the advantage of having a simpler process, lower cost, and higher production yield rate. The encapsulation compound arranges on the first surface of the image sensor chip and covers the circumference of the transparent lid to avoid the side light leakage as traditional chip scale package (CSP). Thus, the sensing performance of the wafer level image sensor packaging structure can be enhanced. | 2011-12-01 |
20110291216 | IMAGE SENSOR - In an image sensor | 2011-12-01 |
20110291217 | PHOTOELECTRIC CONVERTER AND IMAGING SYSTEM INCLUDING THE SAME - A photoelectric converter includes a substrate, photoelectric converting elements formed in the substrate and each having a light-receiving surface, an antireflection film arranged above at least a part of the light-receiving surface of each photoelectric converting element, an element isolation region including an insulator, a plurality of transistors including read transistors configured to read electric charges of the photoelectric converting elements, an interlayer insulating film arranged above the photoelectric conversion elements and the read transistors, and contacts electrically connected to active regions of the transistors. The antireflection film is arranged above the element isolation region and the active region connected to each contact. The antireflection film serves as an etch stop film when the interlayer insulating film is etched. | 2011-12-01 |
20110291218 | PHOTODIODE AND PHOTODIODE ARRAY - A photodiode array PDA | 2011-12-01 |
20110291219 | BACKSIDE ILLUMINATION IMAGE SENSOR, METHOD OF FABRICATING THE SAME, AND ELECTRONIC SYSTEM INCLUDING THE BACKSIDE ILLUMINATION IMAGE SENSOR - A backside illumination image sensor, a method of fabricating the same, and an electronic system including the backside illumination image sensor, the backside illumination image sensor including a semiconductor substrate, the semiconductor substrate having an upper surface and a lower surface; photodiodes in the semiconductor substrate; and metal interconnections below the semiconductor substrate, wherein each of the photodiodes includes a N-type region, a lower P-type region below the N-type region, and an upper P-type region on the N-type region. | 2011-12-01 |
20110291220 | SOLID-STATE IMAGING DEVICE - According to one embodiment, a solid-state imaging device includes a first diffusion layer for accumulating carriers generated by a photoelectric effect; a second diffusion layer adjoining the first diffusion layer, the second diffusion layer having a polarity opposite to that of the first diffusion layer; and a reference voltage setting unit that applies a changing voltage that temporally changes to the first diffusion layer through the second diffusion layer and sets a voltage based on an amplitude of the applied changing voltage as a reference voltage of the first diffusion layer. | 2011-12-01 |
20110291221 | SEMICONDUCTOR LIGHT RECEIVING DEVICE - A semiconductor light receiving device includes: a substrate having a rectangular shape with first through fourth corners, a multilayer structure formed on the substrate, a light receiving part having a mesa structure positioned at a first corner side from a center part of the rectangular shape of the substrate, a first electrode pad provided on the semiconductor substrate, and a second electrode pad provided on the semiconductor substrate so as to be close to a second corner diagonally opposite to the first corner, a first minimum distance between the second electrode pad and an edge of the substrate being longer than a second minimum distance between the first electrode pad and the edge of the substrate. | 2011-12-01 |
20110291222 | SILICON DIOXIDE CANTILEVER SUPPORT AND METHOD FOR SILICON ETCHED STRUCTURES - An apparatus includes a semiconductor layer ( | 2011-12-01 |
20110291223 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate having a diode active region and an edge termination region adjacent to each other, a first region of a first conductivity type in the diode active region, a second region of a second conductivity type, a third region of the first conductivity type in the edge termination region, and a fourth region of the second conductivity type. The first region and the third region share a drift region of the first conductivity type. The first region and the third region share a fifth region of the first conductivity type. The drift region in the third region is greater in number of crystal defects per unit volume than the drift region in the first region in order that the drift region in the third region is shorter in carrier lifetime than the drift region in the first region. | 2011-12-01 |
20110291224 | EFFICIENT PITCH MULTIPLICATION PROCESS - Pitch multiplied and non-pitch multiplied features of an integrated circuit, e.g., features in the array, interface and periphery areas of the integrated circuit, are formed by processing a substrate through a mask. The mask is formed by patterning a photoresist layer which simultaneously defines mask elements corresponding to features in the array, interface and periphery areas of the integrated circuit. The pattern is transferred to an amorphous carbon layer. Sidewall spacers are formed on the sidewalls of the patterned amorphous carbon layer. A layer of protective material is deposited and then patterned to expose mask elements in the array region and in selected parts of the interface or periphery areas. Amorphous carbon in the array region or other exposed parts is removed, thereby leaving a pattern including free-standing, pitch multiplied spacers in the array region. The protective material is removed, leaving a pattern of pitch multiplied spacers in the array region and non-pitch multiplied mask elements in the interface and periphery areas. The pattern is transferred to a hard mask layer, through which an underlying substrate is etched. | 2011-12-01 |
20110291225 | Semiconducture Structure and Method of Forming the Semiconductor Structure that Provides Two Individual Resistors or a Capacitor - A semiconductor structure is formed in the metal interconnect structure of an integrated circuit in a method that provides either two individual resistors that are vertically isolated from each other, or a metal-insulator-metal (MIM) capacitor. As a result, both semiconductor resistors and MIM capacitors can be formed in the same process flow. | 2011-12-01 |
20110291226 | Compound Semiconductor Device and Method for Fabricating the Same - A compound semiconductor device is provided, including a gallium arsenide (GaAs) substrate having a first protrusion portion and a second protrusion portion, wherein the first protrusion portion is formed over a first portion of the GaAs substrate and the second protrusion is formed over a second portion of the GaAs substrate. A first element is disposed over the first protrusion portion, and a second element is disposed over the second protrusion portion. | 2011-12-01 |
20110291227 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING - A method for manufacturing a semiconductor device is disclosed. The method includes forming a shallow trench isolation (STI) region extending in a first direction on a semiconductor substrate, forming a mask layer extending in a second direction that intersects with the first direction on the semiconductor substrate and forming a trench on the semiconductor substrate by using the STI region and the mask layer as masks. In addition, the method includes forming a charge storage layer so as to cover the trench and forming a conductive layer on side surfaces of the trench and the mask layer. Word lines are formed from the conductive layer on side surfaces of the trench that oppose in the first direction by etching. The word lines are separated from each other and extend in the second direction. | 2011-12-01 |
20110291228 | PACKAGE STRUCTURE AND METHOD FOR MAKING THE SAME - A package structure which includes a non-conductive substrate, a conductive element, a passivation, a jointed side, a conductive layer, a solder and a solder mask is disclosed. The conductive element is disposed on a surface of the non-conductive substrate and consists of a passive element and a corresponding circuit. The passivation completely covers the conductive element and the non-conductive substrate so that the conductive element is sandwiched between the passivation and the non-conductive substrate. The conductive layer covers the jointed side which exposes part of the corresponding circuit, extends beyond the jointed side and is electrically connected to the corresponding circuit. The solder mask which completely covers the jointed side and the conductive layer selectively exposes the solder which is disposed outside the jointed side and electrically connected to the conductive layer. | 2011-12-01 |
20110291229 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR FABRICATING THE SAME - A semiconductor integrated circuit includes: a semiconductor chip; a through-chip via passing through a conductive pattern disposed in the semiconductor chip and cutting the conductive pattern; and an insulation pattern disposed on an outer circumference surface of the through-chip via to insulate the conductive pattern from the through-chip via. | 2011-12-01 |
20110291230 | Fuse of a Semiconductor Device - A method for forming a fuse of a semiconductor device includes performing an ion-implanting process at sides of a fuse blowing region of a metal fuse, thereby increasing the concentration of impurity ions of a thermal transmission path region. In a subsequent laser blowing process, as a result of the increased resistance of metal fuse the electric and thermal conductivity is reduced, thereby increasing the thermal condensation efficiency of the fuse blowing region and improving the efficiency of the laser blowing process. | 2011-12-01 |
20110291231 | METHOD OF MANUFACTURING A SEMICONDUCTOR COMPONENT AND STRUCTURE - A semiconductor component and methods for manufacturing the semiconductor component that includes a monolithically integrated common mode choke. In accordance with embodiments, a transient voltage suppression device may be coupled to the monolithically integrated common mode choke. | 2011-12-01 |
20110291232 | 3D Inductor and Transformer - In accordance with an embodiment, a semiconductor device comprises a semiconductor die, an interposer, and conductive bumps bonding the semiconductor die to the interposer. The semiconductor die comprises a first metallization layer, and the first metallization layer comprises a first conductive pattern. The interposer comprises a second metallization layer, and the second metallization layer comprises a second conductive pattern. Some of the conductive bumps electrically couple the first conductive pattern to the second conductive pattern to form a coil. Other embodiments contemplate other configurations of coils, inductors, and/or transformers, and contemplate methods of manufacture. | 2011-12-01 |
20110291233 | SEMICONDUCTOR DEVICE WITH INTEGRATED ANTENNA AND MANUFACTURING METHOD THEREFOR - There is disclosed a package comprising at least an integrated circuit embedded in an electrically non-conductive moulded material. The moulded material includes at least one moulded pattern on at least one surface thereof, and at least one electrically conductive track in the pattern. There is further provided at least one capacitive, inductive or galvanic component electrically connecting between at least two parts of the at least one electrically conductive track. The conductive track can be configured as an antenna, and the capacitive, inductive or galvanic component is used to adjust tuning and other characteristics of the antenna. | 2011-12-01 |
20110291234 | SEMICONDUCTOR CIRCUIT STRUCTURE AND METHOD OF MAKING THE SAME - A semiconductor circuit structure includes an interconnect region, and a material transfer region. The semiconductor circuit structure includes a conductive bonding region which couples the material transfer region to the interconnect region through a bonding interface. The conductive bonding region includes a barrier layer between a conductive layer and bonding layer. The bonding layer is positioned towards the material transfer region, and the conductive layer is positioned towards the interconnect region. | 2011-12-01 |
20110291235 | COPPER INTERCONNECTION STRUCTURE WITH MIM CAPACITOR AND A MANUFACTURING METHOD THEREOF - The present invention discloses a copper interconnection structure with MIM capacitor and a manufacturing method thereof. The method firstly makes a copper conductive pattern in a copper interconnection structure and a copper through hole bolt connected with the copper conductive pattern; etch away an insulation layer around the copper through hole bolt and deposit a etch stop layer, so as to expose the top and side surface of the copper through hole bolt and part of the top surface of the copper conductive pattern; deposit a dielectric layer on the obtained structure and fill a protection material in the recession area of the obtained structure; etch a trench for receiving other copper conductive patterns; remove the protection material; plate copper in the recession area, and plate copper in the trench, so as to obtain a copper interconnection structure with MIM capacitor. | 2011-12-01 |
20110291236 | SEMICONDUCTOR MODULE WITH ELECTRICAL SWITCHING ELEMENTS - A semiconductor module is provided which is capable of lowering surges caused when switching elements are switched on and off. The module has a plurality of lead frames, switching elements, electronic components, and a sealing member. The switching elements are electrically connected to the lead fames respectively. Part of the lead frames, the switching elements, and the electronic components are sealed by the sealing member. The electronic components are mounted on primary surfaces of the lead frames respectively. | 2011-12-01 |
20110291237 | LANTHANIDE DIELECTRIC WITH CONTROLLED INTERFACES - Methods and devices for a dielectric are provided. One method embodiment includes forming a passivation layer on a substrate, wherein the passivation layer contains a composition of silicon, oxygen, and nitrogen. The method also includes forming a lanthanide dielectric film on the passivation layer, and forming an encapsulation layer on the lanthanide dielectric film. | 2011-12-01 |
20110291238 | BIAS-CONTROLLED DEEP TRENCH SUBSTRATE NOISE ISOLATION INTEGRATED CIRCUIT DEVICE STRUCTURES - A novel and useful apparatus for and method of providing noise isolation between integrated circuit devices on a semiconductor chip. The invention addresses the problem of noise generated by digital switching devices in an integrated circuit chip that may couple through the silicon substrate into sensitive analog circuits (e.g., PLLs, transceivers, ADCs, etc.) causing a significant degradation in performance of the sensitive analog circuits. The invention utilizes a deep trench capacitor (DTCAP) device connected to ground to isolate victim circuits from aggressor noise sources on the same integrated circuit chip. The deep penetration of the capacitor creates a grounded shield deep in the substrate as compared with other prior art shielding techniques | 2011-12-01 |
20110291239 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a first interlayer insulating film; a first conductive member provided lower than the first interlayer insulating film; a contact plug that penetrates through the first interlayer insulating film, and is electrically connected to the first conductive member, the contact plug including a small-diameter part, and a large-diameter part arranged on the small-diameter part, an outer diameter of the large-diameter part being larger than an outer diameter of the small-diameter part, and the outer diameter of the large-diameter part being larger than an outer diameter of a connection face between the second conductive member and the large-diameter part; and a second conductive member that is provided on the first interlayer insulating film, and is electrically connected to the contact plug. | 2011-12-01 |
20110291240 | POWER STORAGE DEVICE AND METHOD FOR MANUFACTURING THE SAME - To provide a power storage device with improved cycle characteristics and a method for manufacturing the power storage device, a power storage device is provided with a conductive layer in contact with a surface of an active material layer including a silicon layer after an oxide film, such as a natural oxide film, which is formed on the surface of the active material layer is removed. The conductive layer is thus provided in contact with the surface of the active material layer including a silicon layer, whereby the conductivity of the electrode surface of the power storage device is improved; therefore, cycle characteristics of the power storage device can be improved. | 2011-12-01 |