48th week of 2010 patent applcation highlights part 67 |
Patent application number | Title | Published |
20100306406 | SYSTEM AND METHOD FOR ACCESSING A REMOTE DESKTOP VIA A DOCUMENT PROCESSING DEVICE INTERFACE - The subject application is directed to a system and method for accessing a remote desktop via a document processing device interface. A thin client interface is generated on a graphical display associated with a document processing device, and data communication is established between the thin client interface and an associated remote frame buffer server disposed on a workstation via a document processing device network interface associated with a document processing device. A user interface associated with the workstation is generated on the graphical display via the thin client in accordance with an established data communication, user input is received via the thin client, and remote operation of the workstation is enabled via received user input. | 2010-12-02 |
20100306407 | METHOD AND SYSTEM FOR MANAGING TRANSMISSION OF FRAGMENTED DATA PACKETS - A method of managing transmission of a fragmented datagram in a network having end devices and intermediate routing or switching devices in which fragmentation of the datagram takes place at an upstream intermediate device. The method includes receiving and temporarily storing a first datagram fragment at a downstream intermediate device, the fragment including data allowing classification of the fragments of the datagram; and receiving and temporarily storing subsequent fragments of the same datagram at the downstream device. Once all datagram fragments are received, all of the fragments are classified and transmitted on based on the classification data of the first fragment. However, if a predetermined time period has elapsed and at least one fragment is missing, an action other than transmission on to a subsequent device is initiated. | 2010-12-02 |
20100306408 | AGILE DATA CENTER NETWORK ARCHITECTURE - This patent application relates to an agile network architecture that can be employed in data centers, among others. One implementation provides a virtual layer-2 network connecting machines of a layer-3 infrastructure. | 2010-12-02 |
20100306409 | SYSTEM AND METHOD FOR LOCATION DISCOVERY BASED ON DNS - A system and method for enabling a client to query a DNS server for location information that is associated with the client's IP address. The client receives the location information which identifies a list of sub-locations and a location IP address space encompassing the sub-locations listed. The client selects a network service located nearest to the client based on the location information, and then accesses the network service. | 2010-12-02 |
20100306410 | CREATING A TREE TO FACILITATE EFFICIENT ACCESS TO INFORMATION - A system and method for allocating an interval to each of multiple locations within a network topology, where each interval indicates a range of Internet Protocol (IP) addresses associated with the corresponding location. Each allocated interval is associated with a computing service that provides information about network services near the location associated with the allocated interval. The intervals are allocated into intermediate nodes, where each intermediate node includes at least two of the intervals. The intervals, associated computing services, and intermediate nodes are then organized into a modified B+ tree structure that facilitates the discovery of one of the network services near the allocated interval. | 2010-12-02 |
20100306411 | METHOD OF TRANSCODING CONTENT, TRANSCODER UNIT, AND UPNP NETWORK SYSTEM - A method of transcoding a content stored on a first server (OS) is provided. The first server (OS) is arranged within an UPnP network comprising at least one first server (OS), at least one UPnP renderer (UR) and at least one UPnP control point (CP). The content directoryservices (CDS) of the at least one first server (OS) are browsed to determine the available content and the available encodings of the content. The rendering capabilities of the at least one renderer (UR) are determined. The rendering capabilities of the at least one renderer (UR) are compared with the available content and the available encoding of the content according to the content directory service of the at least one server (OS). The content directoryservice (CDS) of the at least one server (OS) is updated. | 2010-12-02 |
20100306412 | Method and apparatus for content-aware and adaptive deduplication - A method, a system, an apparatus, and a computer readable medium for transmission of data across a network are disclosed. The method includes receiving a data stream, analyzing the received data stream to determine a starting location and an ending location of each zone within the received data stream, based on the starting and ending locations, generating a zone stamp identifying the zone, the zone stamp includes a sequence of contiguous characters representing at least a portion of data in the zone, wherein the order of characters in the zone stamp corresponds to the order of data in the zone, comparing the zone stamp with another zone stamp of another zone in any data stream received, determining whether the zone is substantially similar to another zone by detecting that the zone stamp is substantially similar to another zone stamp, delta-compressing zones within any data stream received that have been determined to have substantially similar zone stamps, thereby deduplicating zones having substantially similar zone stamps within any data stream received, and transmitting the deduplicated zones across the network from one storage location to another storage location. | 2010-12-02 |
20100306413 | METHODS FOR DETECTING AND HANDLING VIDEO AND VIDEO-LIKE CONTENT IN REMOTE DISPLAY SYSTEM - Method and apparatus for improving streaming data of graphics remoting applications are described herein. According to one embodiment, a stream of data objects is generated, each data object representing graphics data associated with an image to be rendered at a client over a network. For each data object, it is detected whether the associated image includes a first region and a second region having content with different types of contents based on a changing rate of display output regions. The first region is compressed using a first compression method and the second region is compressed using a second compression method different than the first compression method. The graphics data associated with the compressed first region and second region is transmitted to the client over the network to be rendered at the client. Other methods and apparatuses are also described. | 2010-12-02 |
20100306414 | Transferring of SNMP Messages Over UDP with Compression of Periodically Repeating Sequences - The transfer of messages using an UDP transport is provided. A typical example is offered by the SNMP messages, used to perform the communication (C | 2010-12-02 |
20100306415 | Using Provider Backbone Bridged Network to Reduce the Number of Media Access Control Addresses Visible to Core Bridges in the Data Center - A system comprising a backbone core bridge (BCB) in a provider backbone bridged network (PBBN), and a backbone edge bridge (BEB) coupled to the BCB via a provider network port (PNP) and to a customer bridge in a customer bridged network via a C-tagged service interface, wherein the C-tagged service interface maps a service instance from the customer bridged network that is identified by a customer-virtual local area network identifier (C-VID) to a backbone service instance on the PBBN that is identified by a service instance identifier (I-SID). | 2010-12-02 |
20100306416 | SYSTEM AND METHOD FOR DISCOVERING AND PROTECTING SHARED ALLOCATED RESOURCES IN A SHARED VIRTUALIZED I/O DEVICE - A system includes a virtualized I/O device coupled to one or more processing units. The virtualized I/O device includes programmed I/O (PIO) configuration registers corresponding to hardware resources, and a storage for storing a resource table that includes a plurality of entries. Each entry corresponds to a respective hardware resource. A system processor may allocate the hardware resources to functions that may include physical and virtual functions, and may program each entry of the resource discovery table for each function with an encoded value that indicates whether a requested hardware resource has been allocated to a requesting process, and whether the requested hardware resource is shared with another function. Processing units may execute a device driver instance associated with a given process to discover allocated resources by requesting access to the resource discovery table. The virtualized I/O device protects the resources by checking access requests against the resource discovery table. | 2010-12-02 |
20100306417 | Transfer of Commands And Storage Data To A Data Storage Device - A controller controls transfer of commands and storage data over a databus to a data storage device. The controller comprises a memory arranged to store a queue of commands prior to the commands being transferred over the databus. The controller identifies data access commands in the queue that specify the same type of data access and contiguous ranges of addresses. A concatenated data access command is transferred in place of so identified data access commands, the concatenated data access command specifying the same type of data access and the overall range of addresses. This improves the rate of data transfers. | 2010-12-02 |
20100306418 | Methods and System for Configuring a Peripheral Device with an Information Handling System - A method for configuring a peripheral device in communication with an information handling system (IHS) is disclosed, wherein the method includes receiving visual data associated with the peripheral device and mapping configuration data to the peripheral device based on the visual data. The method further includes utilizing the configuration data to configure the peripheral device in communication with the IHS. An information handling system (IHS) in communication with an image capturing device is further disclosed including a storage device operable to store a database, the database configured to store a standard image of a peripheral device, wherein the standard image is associated with configuration data for the peripheral device. The system further includes a memory coupled to the storage device and a processor to receive visual data associated with the peripheral device from the image capturing device. The processor is operable to execute a software application configured to match the visual data with the standard image to configure the peripheral device based on the configuration data. | 2010-12-02 |
20100306419 | COMPUTER SYSTEM, MANAGEMENT SERVER, AND MISMATCHED CONNECTION CONFIGURATION DETECTION METHOD - The management of computers connected with I/O switch devices is simplified. A computer system S includes one or several computers (server devices), one or several I/O devices, one or several I/O switch devices, and a management server | 2010-12-02 |
20100306420 | FAST PATH SCSI IO - A hardware automated IO path, comprising a message transport unit for transporting an IO request to a local memory via a DMA operation and determining a LMID for associating with a request descriptor of the IO request; a fastpath engine for validating the request descriptor and creating a fastpath descriptor based on the request descriptor; a data access module for performing an IO operation based on the fastpath descriptor and posting a completion message into the fastpath completion queue upon a successful completion of the IO operation. The fastpath engine is further configured for: receiving the completion message, releasing the IO request stored in the local memory, and providing a reply message based on the completion message. The message transport unit is further configured for providing the reply message in response to the IO request. | 2010-12-02 |
20100306421 | DMA TRANSFER DEVICE - A source address setting detector acquires a DMA source address from a transfer start address setting for a DMA source area of a plurality of register settings for a DMAC which are made by a master. A read-ahead processor reads ahead data in a resource which is specified by the DMA source address before the DMAC starts DMA transfer, and further, increments the DMA source address to repeat read-ahead operation. The DMAC starts DMA transfer if the master completes the register settings, reads data in the DMA source area which has already been read ahead in the read-ahead processor, and transfers the data to a DMA destination area in the resource. | 2010-12-02 |
20100306422 | COMMUNICATION APPARATUS - The present invention provides, as one aspect, a communication apparatus which is connected with a communication bus and performs communication using Carrier Sense Multiple Access with Collision Avoidance (CSMA/CA). The apparatus includes an edge detection section which detects an edge of data on the communication bus, and a data obtaining section which obtains data from the communication bus to determine a collision of data on the communication bus after a predetermined delay time period has passed from the time at which the edge detection section detects the edge. | 2010-12-02 |
20100306423 | INFORMATION PROCESSING SYSTEM AND DATA TRANSFER METHOD - An information processing system includes a master module for outputting a transfer state signal in correspondence to a data read instruction when the data read instruction is successively output plural times, the transfer state signal indicating that at least one data read instruction succeeds some one of the data read instructions; and a memory controller for, when receiving the some one of the data read instructions and the corresponding transfer state signal from the master module, supplying data corresponding to the some one of the data read instructions to the master module, while reading data corresponding to the at least one data read instruction, which succeeds the some one of the data read instructions, from a memory and holding the read data in accordance with the received transfer state signal. | 2010-12-02 |
20100306424 | CONNECTION BETWEEN A CLIENT DEVICE AND MULTIPLE HOST DEVICES - A method of handling a connection between a client device and a plurality of host devices comprises connecting the client device to a host device of the plurality of host devices, transmitting a message from the client device to the connected host device, the message requesting transferring the connection to a different host device, the connected host device disconnecting the connection to the client device, and the different host device connecting to the client device. | 2010-12-02 |
20100306425 | Switching Device Configured to Couple a First Computer to a First Peripheral Device and One or More Second Peripheral Devices and Method of Manufacturing Same - In some embodiments, a switching device is configured to couple a first computer to a first peripheral device and one or more second peripheral devices. The switching device includes: (a) a switch configured to couple to the one or more second peripheral devices; (b) a first hub including: (1) a first upstream port configured to couple to the first computer; (2) a first downstream port configured to couple to the first peripheral device; and (3) at least one second downstream port coupled to the switch. Other embodiments are also disclosed herein. | 2010-12-02 |
20100306426 | FIFO BUFFER - A FIFO memory circuit is for interfacing between circuits with different clock domains. The circuit has a FIFO memory ( | 2010-12-02 |
20100306427 | PS/2 TO USB KEYBOARD ADAPTOR SUPPORTING N-KEY ROLLOVER - A USB converter circuit for converting electrical signals from a key scan circuit (in PS/2 or other formats) into USB signals for a computer while supporting N-key rollover (NKRO) functions. The converter circuit can be implemented as a stand-alone PS/2 to USB keyboard converter or as an integral component of a USB keyboard or KVM switch. The converter circuit includes a converter module that generates keyboard data packets in the USB format having a 16-byte, 64-byte, etc. format representing key press information for up to 8 modifier keys and 14, 62, etc. non-modifier keys, respectively. The converter circuit also includes a USB device controller module which transmits the 16-byte etc. USB keyboard data as one or multiple USB data packets to the host computer. When multiple USB data packets are needed to transmit each keyboard data packet (depending on the USB speed), they are transmitted in consecutive polling periods. | 2010-12-02 |
20100306428 | Consumer Media Player - A consumer media player is configured to be electronically coupled to various different types of media source devices, extract media files from those media source devices, and play the extracted media files to a consumer. The consumer media player is also configured to physically hold all or part of one or more media source devices in a manner that facilitates electronic coupling of the media source device to the consumer media player and that provides an aesthetically pleasing appearance to the consumer. In particular, the consumer media player includes a cavity that can hold at least a portion of the media source device. In one of the embodiments described herein, at least some types of media source devices can be entirely physically stored within the cavity in the consumer media player. | 2010-12-02 |
20100306429 | System and Method of Signal Processing Engines With Programmable Logic Fabric - A bus structure providing pipelined busing of data between logic circuits and special-purpose circuits of an integrated circuit, the bus structure including a network of pipelined conductors, and connectors selectively joining the pipelined conductors between the special-purpose circuits, other pipelined connectors, and the logic circuits. | 2010-12-02 |
20100306430 | BUS CONTROL SYSTEM AND SEMICONDUCTOR INTEGRATED CIRCUIT - A bus control circuit includes a first bus to which a first circuit is connected, a second bus to which a second circuit is connected and a control circuit that transfers data between the first circuit and the second circuit, wherein the control circuit monitors completion of the processing of an access request that is resident in the control circuit. | 2010-12-02 |
20100306431 | Dynamic Address Change for Slave Devices on a Shared Bus - A master/slave data communication system in which a master device communicates with the slave devices by uniquely addressing each of the slave devices. In order to enhance the security of the data communication system, each slave device includes an address generator for generating unique addresses. Periodically, the master device requests that one or more slave device change its address. In response to the request, the addressed slave device increments its address generating algorithm to provide a new slave address. The master device also includes an algorithm that is synchronized with the slave address generating algorithm, whereby when the slave changes its address, it need not transmit the new slave address to the master device over the bus. | 2010-12-02 |
20100306432 | COMPUTER-IMPLEMENTED MULTI-RESOURCE SHARED LOCK - In one embodiment of a computer-implemented system, comprising a plurality of computer entities and multiple resources, one of the computer entities may request a multi-resource lock to one of the multiple resources; the one resource determines whether a resource lock is available at the one resource and, if so, the one resource communicates with all peer resources to determine whether a resource lock is available; if the peer resources indicate a resource lock is available, lock all of the resources to the requesting computer entity, and the one resource communicates the lock of the resources to the requesting computer entity; and if any the resource indicates contention for the multi-resource lock, the one resource communicates the contention to the requesting computer entity, and the requesting computer entity backs off the multi-resource lock request and, after a random time interval, repeats the request. | 2010-12-02 |
20100306433 | INTERRUPT-NOTIFICATION CONTROL UNIT, SEMICONDUCTOR INTEGRATED CIRCUIT AND METHODS THEREFOR - An interrupt-notification control unit that receives interrupt requests from a plurality of interrupt dispatchers and sends the received interrupt requests together to a processor, where the interrupt-notification control unit determines a correlation among the interrupt requests to control a time to send the interrupt requests together to the processor. | 2010-12-02 |
20100306434 | SYSTEMS AND METHODS FOR SCALABLE STORAGE MANAGEMENT - Systems and methods for management of scalable storage architectures are disclosed. The system includes one or more storage backplanes, each storage backplane configured to interface with one or more hard disk drives. The system includes a baseboard management controller, which includes an interface to communicate with one or more of the storage backplanes and programmable logic configured to detect the presence of one or more hard disk drives in an interfaced storage backplane and control one or more status indicators, wherein each status indicator is related to at least one of the hard disk drives in the interfaced storage backplane. | 2010-12-02 |
20100306435 | RECONFIGURABLE VIRTUAL BACKPLANE SYSTEMS AND METHODS - Reconfigurable virtual backplane systems and methods are provided. One virtual backplane system includes a bus, and first and second line cards coupled to the bus. Each line card includes a processor including a memory storing an array of configuration tables. Each configuration table stores a listing of processes to be transmitted to or received from the communication bus, wherein a first configuration table is selected from the first line card upon the occurrence of a first event and a second configuration table is selected from the second line card upon the occurrence of a second event. One method includes connecting first and second buses in first and second systems, respectively, to form a bus for a new system. The method further includes detecting the connection of the first and second buses, and reconfiguring the first and second systems to operate as the new system in response to detecting the connection. | 2010-12-02 |
20100306436 | MODULARLY CONSTRUCTED FIELD DEVICE OF PROCESS AUTOMATION TECHNOLOGY - The present invention relates to a modularly constructed field device ( | 2010-12-02 |
20100306437 | METHOD AND APPARATUS TO SELECTIVELY EXTEND AN EMBEDDED MICROPROCESSOR BUS THROUGH A DIFFERENT EXTERNAL BUS - A method and apparatus to selectively extend an embedded microprocessor bus through a different external bus are generally presented. In this regard, an apparatus is introduced comprising a first high speed serializer/deserializer (SERDES) bus internal to an integrated circuit device to couple an embedded microprocessor with an embedded component, a second high speed SERDES bus different from the first bus to couple the embedded component with an external interface of the integrated circuit device, and extension circuitry to selectively bypass the embedded component and extend the first bus to function at the external interface over a physical layer of the second bus. Other embodiments are also described and claimed. | 2010-12-02 |
20100306438 | BUS SYSTEM FOR USE WITH INFORMATION PROCESSING APPARATUS - A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal. | 2010-12-02 |
20100306439 | DATA CHECK CIRCUIT - A data check circuit comprising: a request signal output circuit configured to output a request signal for requesting occupation of a bus to an arbitration circuit configured to arbitrate the occupation of the bus, when a CPU connected, as a bus master, with the bus for accessing a memory outputs an instruction signal for providing an instruction for starting detection of whether or not data stored in the memory is correct; a data acquisition circuit configured to acquire data stored in the memory through the bus, when the arbitration circuit outputs a permission signal for permitting the occupation of the bus based on the request signal; and a data processing circuit configured to perform processing for detecting whether or not the acquired data is correct, the acquired data acquired by the data acquisition circuit. | 2010-12-02 |
20100306440 | SYSTEM AND METHOD FOR SERIAL INTERFACE TOPOLOGIES - A system and method for serial interface topologies is disclosed. A serial interface topology includes a replication device configured to receive control information from a controller interface. The replication device is configured to transmit two or more copies of substantially replicated control information to a device control interface. A data interface is configured to provide differential, point-to-point communication of data with the device controller interface. | 2010-12-02 |
20100306441 | DATA TRANSFER APPARATUS AND DATA TRANSFER METHOD - A data transfer apparatus for transferring data between a system bus and a local bus at a high speed is provided. A bus bridge | 2010-12-02 |
20100306442 | DETECTING LOST AND OUT OF ORDER POSTED WRITE PACKETS IN A PERIPHERAL COMPONENT INTERCONNECT (PCI) EXPRESS NETWORK - An article of manufacture, an apparatus, and a method for processing packets in a peripheral component interconnect express (PCIe) network. An article of manufacture includes a computer program product that includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes receiving a PCIe posted write packet at a receiving device, the PCIe posted write packet including a received tag identifier and a requesting device identifier identifying a requesting device. An expected tag identifier is determined for the requesting device. The received tag identifier is compared to the expected tag identifier. An error flag is set if the received tag identifier does not match the expected tag identifier. | 2010-12-02 |
20100306443 | SIGNAL TRANSMISSION INTERFACE AND DIGITAL BROADCAST RECEIVING DEVICE - A signal transmission interface includes: a USB audio format encoding unit adapted to be coupled to a digital broadcast receiving end, for converting a digital audio signal that originates from the digital broadcast receiving end into a USB audio signal; a USB hub coupled to the USB audio format encoding unit and adapted to be coupled to a host end, for transmitting the USB audio signal to the host end and receiving a USB control signal that originates from the host end; and a USB/serial transmission bus bridge unit coupled to the USB hub and adapted to be coupled to the digital broadcast receiving end, for converting the USB control signal that is transmitted from the USB hub into a serial transmission bus control signal, and transmitting the serial transmission bus control signal to the digital broadcast receiving end. | 2010-12-02 |
20100306444 | Free-Space Reduction in Cached Database Pages - A computing system stores a database comprising pages. Each of the pages is the same size. When a page is requested, a block of virtual memory addresses is associated with the page and a set of physical data storage locations is committed to the block of virtual memory addresses. A copy of the page is then stored into the set of physical data storage locations. Physical data storage locations committed to the virtual memory addresses associated with available free space in the copy of the page are deallocated, thereby allowing reuse of these physical data storage locations. A reference to the copy of the page is then returned. | 2010-12-02 |
20100306445 | Mechanism for Virtual Logical Volume Management - In one embodiment, a mechanism for virtual logical volume management is disclosed. In one embodiment, a method for virtual logical volume management includes writing, by a virtual machine (VM) host server computing device, a control block to each of a plurality of network-capable physical storage devices and mapping, by the VM host server computing device, physical storage blocks of the plurality of network-capable physical storage devices to virtual storage blocks of a virtual storage pool by associating the physical storage blocks with the virtual storage blocks in the control block of the network-capable physical storage device housing the physical storage blocks being mapped. Furthermore, the method includes assigning, by the VM host server computing device, a block range of the virtual storage blocks to a VM allocated by the VM host server computing device by writing a unique identifier (ID) of the VM to one or more entries in the control block having the physical storage blocks associated with the block range of the virtual storage blocks assigned to the VM. | 2010-12-02 |
20100306446 | METHOD AND DEVICES FOR CONTROLLING POWER LOSS - Described herein are methods and devices for controlling power loss. For one embodiment, a method includes issuing a controlled power off command with a controller. The method includes determining whether a memory device is performing a background operation. The method includes safely suspending the background operation or completing the background operation if the memory device is performing the background operation. The method includes safely removing a supply power. | 2010-12-02 |
20100306447 | DATA UPDATING AND RECOVERING METHODS FOR A NON-VOLATILE MEMORY ARRAY - Methods for updating and recovering user data of a non-volatile memory array such as a flash memory are disclosed. An indication for indicating a mapping relationship for a logical address is established when original user data of the logical addresses is updated into new user data. The indication records new pointers, which record the mapping relationships between logical addresses and physical addresses storing the new user data of the logical addresses. Alternatively, the indication records memory positions of the non-volatile memory array which are defined as designated memory positions and a sequence for using these designated memory positions. | 2010-12-02 |
20100306448 | CACHE AUTO-FLUSH IN A SOLID STATE MEMORY DEVICE - A device, system and method in which data in a write cache, that must at some point be written to non-volatile memory, is written to non-volatile memory after expiration of a threshold time period during which no new host commands are received. If either the last dirty entry is written back or a host command is received during the write-back process, the time threshold time period and auto-flush process is restarted. | 2010-12-02 |
20100306449 | Transportable Cache Module for a Host-Based Raid Controller - In accordance with the present disclosure, a system and method for an information handling system having transportable cache module is disclosed herein. The information handling system has a memory controller coupled to a central processing unit and a plurality of memory modules. The transportable cache module has a protected memory module, a nonvolatile memory module, a module controller, and an independent power source. The module controller is operative to copy a protected memory region from the protected memory module to a nonvolatile memory region on the nonvolatile memory module. The independent power source is operative to supply power to the protected memory module, the nonvolatile memory module, and the module controller. | 2010-12-02 |
20100306450 | SECURE DELIVERY OF DIGITAL MEDIA VIA FLASH DEVICE - A flash device for secure delivery of media content is provided. The flash device can include a controller module and a memory module. The controller module can include at least one local central processing unit, at least one register having factory initialized data written therein, and at least one memory module interface. The factory initialized data can include: a vendor identification (“VID”) string, a product identification (“PID”) string, and a manufacturer identification string. The memory module can include at least one read-only partition having digital data disposed therein, where at least a portion of the digital data comprises at least one machine executable instruction set. | 2010-12-02 |
20100306451 | ARCHITECTURE FOR NAND FLASH CONSTRAINT ENFORCEMENT - Described embodiments provide for constraint checking for constraints imposed on NAND flash devices. An exemplary implementation of a computing environment comprises at least one NAND data storage device. In the illustrative implementation, the data processing and storage management paradigm allows for the storage of data according using a selected constraint enforcement algorithm. A NAND data storage constraint checking module can be operable to enforce one or more selected device constraints with one or more co-operating components to the NAND data store. | 2010-12-02 |
20100306452 | MULTI-MAPPED FLASH RAID - Disclosed is a storage system. The storage system includes a redundant array of inexpensive disks (RAID) controller. The RAID controller includes a flash memory controller coupled to a flash memory. The flash memory controller may perform background management tasks. These include logging and error reporting, address translation, cache table management, bad block management, defect management, wear leveling, and garbage collection. The array controller also allows the flash memory to be divided into multiple mappings. | 2010-12-02 |
20100306453 | METHOD FOR OPERATING A PORTION OF AN EXECUTABLE PROGRAM IN AN EXECUTABLE NON-VOLATILE MEMORY - A method for operating at least a portion of an executable program in an executable non-volatile memory is described. The method includes determining, by a user input, at least a portion of an executable program for pinning in the executable non-volatile memory. The portion of the executable program is pinned to the executable non-volatile memory. The portion of the executable program is then executed from the executable non-volatile memory. | 2010-12-02 |
20100306454 | ELECTRONIC DEVICES AND OPERATION METHODS OF A FILE SYSTEM - An operation method of file system includes retrieving the first header of the first file, adding the auxiliary data to the first header to generate the second header, writing the dummy data into the second header to adjust the data length of the second header, thereby serving as the third header, and modifying the link relation of clusters recorded in the file allocation table such that the third header and the second data segment are linked together, thereby generating the second file. | 2010-12-02 |
20100306455 | METHOD FOR MANAGING A PLURALITY OF BLOCKS OF A FLASH MEMORY, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for managing a plurality of blocks of a Flash memory includes: sieving out at least one first block having invalid pages from the plurality of blocks; and moving data of a portion of valid pages of the first block to a second block, where data of all valid pages of the first block is not moved to the second block at a time. An associated memory device and a controller thereof are also provided, where the controller includes: a ROM arranged to store a program code; and a microprocessor arranged to execute the program code to control the access to the Flash memory and manage the plurality of blocks. The controller that executes the program code by utilizing the microprocessor sieves out the first block from the plurality of blocks, and moves the data of the portion of valid pages of the first block to the second block. | 2010-12-02 |
20100306456 | METHOD FOR EVEN UTILIZATION OF A PLURALITY OF FLASH MEMORY CHIPS - A method for addressing a memory having a plurality of flash memory chips organized in erasable blocks, which in turn contain writable sectors, and where an erase counter is associated with each memory block. The overwriting of the sectors occurs by way of alternative memory blocks searched in the same chip for low erase counter values, as long as a threshold value of the erase counter is not exceeded. The copying operations are conducted efficiently using a copy command internal to the memory chip. As soon as the threshold value is exceeded, alternative memory blocks are searched in other memory chips as well. | 2010-12-02 |
20100306457 | Microcontroller with CAN Module - A microcontroller has a random access memory, and a Controller Area Network (CAN) controller with a control unit receiving an assembled CAN message. The control unit generates a buffer descriptor table entry using the assembled CAN message and stores the buffer descriptor table entry in the random access memory, and the buffer descriptor table entry has at least a message identifier and load data from the CAN message and information of a following buffer descriptor table entry. | 2010-12-02 |
20100306458 | Memory device having integral instruction buffer - A dynamic random access memory integrated circuit includes an interface to a serial interconnect, where the interface is configured to receive a plurality of memory access instructions over the serial interconnect, and a buffer configured to store the plurality of memory access instructions prior to execution of the buffered memory access instructions by the dynamic random access memory integrated circuit. The memory access instructions are received over at least one serial link that forms the serial interconnect, and the at least one serial link may be a shared bi-directional serial link or a uni-directional serial link. | 2010-12-02 |
20100306459 | Memory Controllers - Techniques pertaining the designs of memory controller are disclosed. According to one aspect of the present invention, a memory controller reduces delays in a data strobe signal of a DDR memory relative to a clock signal of a memory controller thereof. In one embodiment, the memory controller employs four IO ports, two inverters, six edge triggers and a multiplexer. By feeding back an inverted clock signal and utilizing the rising and filing edges of the clock signal, the delays in a data strobe signal of a DDR memory relative to a clock signal of a memory controller are considerably reduced or minimized. | 2010-12-02 |
20100306460 | MEMORY CONTROLLER, SYSTEM, AND METHOD FOR ACCESSING SEMICONDUCTOR MEMORY - A memory controller includes a sorting determination circuit which activates a sorting signal when an access request address for wrapping access to at least one memory block of a semiconductor memory is different from a first leading address of the at least one memory block, an address conversion circuit which sets the first leading address to an access starting address when the sorting signal is activated, a first data sorting circuit which sorts, when the sorting signal is activated, data sequentially read from the semiconductor memory in accordance with the access starting address starting from data corresponding to the access request address and a first output circuit which outputs the sorted data to an external bus. | 2010-12-02 |
20100306461 | MEMORY SYSTEM AND METHOD HAVING VOLATILE AND NON-VOLATILE MEMORY DEVICES AT SAME HIERARCHICAL LEVEL - A processor-based system includes a processor coupled to core logic through a processor bus. This includes a dynamic random access memory (“DRAM”) memory buffer controller. The DRAM memory buffer controller is coupled through a memory bus to a plurality of a dynamic random access memory (“DRAM”) modules and a flash memory module, which are at the same hierarchical level from the processor. Each of the DRAM modules includes a memory buffer to the memory bus and to a plurality of dynamic random access memory devices. The flash memory module includes a flash memory buffer coupled to the memory bus and to at least one flash memory device. The flash memory buffer includes a DRAM-to-flash memory converter operable to convert the DRAM memory requests to flash memory requests, which are then applied to the flash memory device. | 2010-12-02 |
20100306462 | VIRTUAL TAPE APPARATUS, CONTROL METHOD OF VIRTUAL TAPE APPARATUS, AND CONTROL SECTION OF ELECTRONIC DEVICE - A virtual tape apparatus is interposed between a host and a tape device so as to store data transmitted from the host to a logical tape volume. The virtual tape apparatus includes: a data communication unit that receives data transmitted from the host; a RAID device having a logical tape volume for storing the data; a management table that manages attribute information of data stored in the physical tape volume; a position determination section that determines the write starting position of the data stored in the logical tape volume on the physical tape volume based on the management table; and a drive control unit that writes data in the logical tape volume to the physical tape volume based on a result of the determination. | 2010-12-02 |
20100306463 | STORAGE SYSTEM AND ITS CONTROLLING METHOD - This invention, in the interface coupled to the server, the disk interface coupled to the second memory to store final data, the cache to store data temporarily, and in the storage system with the MP which controls them, specifies the area by referring to the stored data, and makes the virtual memory area resident in the cache by using the storage system where the specified area is made resident in the cache. | 2010-12-02 |
20100306464 | System and Method for Managing Devices in an Information Handling System - A method can include associating a bin access value with each data storage bin of a plurality of data storage bins after a current time window ends; mapping each data storage bin of the plurality of data storage bins to a storage tier of a hierarchy of storage tiers, based on the bin access value associated with the data storage bin, such that a bin access value associated with each data storage bin mapped to a storage tier is greater than or equal to a bin access value associated with each data storage bin mapped to a next highest-performing storage tier; causing data associated with each data storage bin of the plurality of data storage bins to be migrated to the storage tier to which the data storage bin is mapped; and, when a data storage bin was not mapped to a current storage tier after a previous time window ended, automatically determining a time weighting factor to be applied to an access frequency associated with a time window. | 2010-12-02 |
20100306465 | STORAGE SYSTEM COMPRISING PLURALITY OF PROCESSOR UNITS - The present invention allows load balancing between processor units without impacting the I/O performance of the storage system. An LDEV owner right is changed on the basis of static information that does not dynamically change in accordance with the number of I/O commands relating to a LDEV. This information is a load index determined for each LDEV. Any of a plurality of processor units selects a processor unit that is to be an assignment destination of the owner right of a target LDEV, based on the load index that has been assigned to each processor unit and the load index of the target LDEV, and assigns this owner right to the selected processor unit. The load index assigned to the processor unit is a value based on the load index of one or more LDEV respectively corresponding to one or more owner rights assigned to this processor unit. | 2010-12-02 |
20100306466 | METHOD FOR IMPROVING DISK AVAILABILITY AND DISK ARRAY CONTROLLER - The present invention discloses a method for improving disk availability and a disk array controller. The method includes: determining, when detecting that part of tracks of a disk in a disk array is damaged, a first master data storage space in a damaged track; selecting an idle first backup data storage space from at least one back data storage space, establishing a corresponding relation between an address of a strip contained in the first master data storage space and an address of a strip contained in the first backup data storage space; and receiving an instruction for accessing the strip contained in the first master data storage space, finding the strip contained in the first backup data storage space according to an address of the strip in the instruction and the corresponding relation, and accessing the strip contained in the first backup data storage space. | 2010-12-02 |
20100306467 | Metadata Management For Virtual Volumes - Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, manage metadata for virtual volumes. In some implementations, a method and system include defining multiple metadata blocks in a persistent storage, including information that links a virtual address space to the storage system, where the defining includes, for at least one of the multiple metadata blocks, determining multiple output addresses corresponding to the storage system, and writing the multiple output addresses and an identifier corresponding to the multiple metadata blocks in a metadata block in the persistent storage. In some implementations, a method and system include reading the multiple metadata blocks into the memory from the persistent storage, including identifying the metadata block based on the identifier; receiving an input address of the virtual address space; and obtaining a corresponding output address to the storage system using the multiple metadata blocks in the memory. | 2010-12-02 |
20100306468 | DISK ARRAY, AND DISK ARRAY CONTROL METHOD AND PROGRAM - A data management section manages source data from a host apparatus by dividing the source data into a plurality of stripe structure data, and distributes and stores the plurality of stripe structure data in a plurality of storage devices having different capacity. Then, the data management section performs control for determining the length of the stripe structure data according to the capacity of each of the plurality of storage devices, and stores the stripe structure data of the same length in each of the storage devices. Further, the data management section manages, as a chunk structure, a data set configured by each one of the stripe structure data respectively stored in the plurality of storage devices. At this time, the source data is configured by a set of the chunk structures. The above contents are the same in RAID 0 and RAID 5. | 2010-12-02 |
20100306469 | PROCESSING METHOD AND APPARATUS - A processing apparatus externally receives a processing request and executes the requested processing. The processing apparatus transmits the result of the processing to a processing request source if a connection to the processing request source is maintained until the requested processing is executed. The processing apparatus stores the result of executing the processing in a memory if the connection to the processing request source is disconnected before the end of the requested processing. The processing apparatus transmits the processing result stored in the memory to the processing request source if the processing requested when the processing request is received is executed but is stored in the memory. | 2010-12-02 |
20100306470 | Methods and Apparatus for Issuing Memory Barrier Commands in a Weakly Ordered Storage System - Efficient techniques are described for enforcing order of memory accesses. A memory access request is received from a device which is not configured to generate memory barrier commands. A surrogate barrier is generated in response to the memory access request. A memory access request may be a read request. In the case of a memory write request, the surrogate barrier is generated before the write request is processed. The surrogate barrier may also be generated in response to a memory read request conditional on a preceding write request to the same address as the read request. Coherency is enforced within a hierarchical memory system as if a memory barrier command was received from the device which does not produce memory barrier commands. | 2010-12-02 |
20100306471 | D-CACHE LINE USE HISTORY BASED DONE BIT BASED ON SUCCESSFUL PREFETCHABLE COUNTER - A method of providing history based done logic for a D-cache includes receiving a D-cache line in an L2 cache; determining if the D-cache line is unprefetchable; aging the D-cache line without a delay if the D-cache line is prefetchable; and aging the D-cache line with a delay if the D-cache line is unprefetchable. | 2010-12-02 |
20100306472 | I-CACHE LINE USE HISTORY BASED DONE BIT BASED ON SUCCESSFUL PREFETCHABLE COUNTER - A method of providing history based done logic for a I-cache includes receiving an I-cache line in an L2 cache; determining if the I-cache line is unprefetchable; aging the I-cache line without a delay if the I-cache line is prefetchable; and aging the I-cache line with a delay is the I-cache line is unprefetchable. | 2010-12-02 |
20100306473 | CACHE LINE USE HISTORY BASED DONE BIT MODIFICATION TO D-CACHE REPLACEMENT SCHEME - A method of providing history based done logic includes receiving a cache line in a L2 cache; determining if the cache line has a history of access at least three times on a previous call into the L2 cache; providing the cache line directly to a processor if the history of access was less then the at least three times; and loading the cache line into an L1 cache if the history of access was the at least three times. | 2010-12-02 |
20100306474 | CACHE LINE USE HISTORY BASED DONE BIT MODIFICATION TO I-CACHE REPLACEMENT SCHEME - A method of providing history based done logic for instructions includes receiving an instruction in a cache line in a L2 cache; and loading the cache line into an L1 cache with a history count that indicates the number of read references of the previous access. | 2010-12-02 |
20100306475 | DATA CACHE WITH MODIFIED BIT ARRAY - A cache memory system includes a first array of storage elements each configured to store a cache line, a second array of storage elements corresponding to the first array of storage elements each configured to store a first partial status of the cache line in the corresponding storage element of the first array, and a third array of storage elements corresponding to the first array of storage elements each configured to store a second partial status of the cache line in the corresponding storage element of the first array. The second partial status indicates whether or not the cache line has been modified. When the cache memory system modifies the cache line within a storage element of the first array, it writes only the second partial status in the corresponding storage element of the third array to indicate that the cache line has been modified but refrains from writing the first partial status in the corresponding storage element of the second array. The cache memory system reads both the first partial status and the second partial status to determine the full status. | 2010-12-02 |
20100306476 | CONTROLLING SIMULATION OF A MICROPROCESSOR INSTRUCTION FETCH UNIT THROUGH MANIPULATION OF INSTRUCTION ADDRESSES - Instruction fetch unit (IFU) verification is improved by dynamically monitoring the current state of the IFU model and detecting any predetermined states of interest. The instruction address sequence is automatically modified to force a selected address to be fetched next by the IFU model. The instruction address sequence may be modified by inserting one or more new instruction addresses, or by jumping to a non-sequential address in the instruction address sequence. In exemplary implementations, the selected address is a corresponding address for an existing instruction already loaded in the IFU cache, or differs only in a specific field from such an address. The instruction address control is preferably accomplished without violating any rules of the processor architecture by sending a flush signal to the IFU model and overwriting an address register corresponding to a next address to be fetched. | 2010-12-02 |
20100306477 | STORE PREFETCHING VIA STORE QUEUE LOOKAHEAD - Systems and methods for efficient handling of store misses. A processor comprises a store queue that stores data for committed store instructions. Coupled to the store queue is a cache responsible for ensuring consistent ordering of store operations for all consumers, which may be accomplished by maintaining a corresponding cache line be in an exclusive state before executing a store operation. In response to a first committed store instruction missing in the cache, the store queue is configured to convey to the cache a second entry of the plurality of queue entries as a speculative prefetch instruction. This second entry corresponds to a committed store instruction that follows in program order the first committed store instruction of a given thread. If the prefetch instruction misses in the cache, the latency for acquiring a corresponding cache line overlaps with the latency of the first store instruction. | 2010-12-02 |
20100306478 | DATA CACHE WITH MODIFIED BIT ARRAY - A microprocessor includes first and second functional units and a data cache having a data array having a write port, a modified bit array having a read port and a write port, and a tag array having a read port, each array having the corresponding predetermined organization. The first functional unit writes data to a cache line of the data array. The first functional unit sets a modified bit in the modified bit array to indicate that the corresponding cache line in the data array has been modified. The second functional unit reads the modified bit from the modified bit array to determine whether or not the cache line has been modified. The second functional unit reads a partial status of the corresponding cache line from the tag array. The partial status does not indicate whether the cache line has been modified. The tag array does not include a port by which the first functional unit may update the partial status of the corresponding cache line. | 2010-12-02 |
20100306479 | PROVIDING SHARED MEMORY IN A DISTRIBUTED COMPUTING SYSTEM - A distributed computing system includes a plurality of processors and shared memory service entities executable on the processors. Each of the shared memory service entities is associated with a local shared memory buffer. A producer is associated with a particular shared memory service entity, and the producer provides data that is stored in the local shared memory buffer associated with the particular shared memory service entity. The shared memory service entities propagate content of the local shared memory buffers into a global shared memory, wherein propagation of content of the local shared memory buffers to the global shared memory is performed using a procedure that relaxes guarantees of consistency between the global shared memory and the local shared memory buffers. | 2010-12-02 |
20100306480 | Shared Memory - The present invention relates to a shared memory ( | 2010-12-02 |
20100306481 | DECENTRALIZED PROCESSING NETWORK - A free-space, decentralized, distributed computing network may comprise at least one free-space dynamic memory unit, at least one free-space processing unit, at least one free-space static memory unit, and at least one free-space communications link. The free-space dynamic memory unit may store data. The free-space processing unit may process the data, stored by the free-space dynamic memory unit, into information. The free-space static memory unit may provide operational instructions to the free-space dynamic memory unit and to the free-space processing unit. The free-space communications link may connect in the free-space the free-space dynamic memory unit, the free-space processing unit, and the free-space static memory unit. The free-space dynamic memory unit, the free-space processing unit, and the free-space static memory unit may each comprise at least one tracking device, and a transducer, transmitter, and/or receiver. | 2010-12-02 |
20100306482 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile memory having a non-power of two memory capacity is disclosed. The nonvolatile memory device includes at least one plane. The plane includes a plurality of blocks with each of the blocks divided into a number of pages and each of the blocks defined along a first dimension by a first number of memory cells for storing data, and along a second dimension of by a second number of memory cells for storing data. The nonvolatile memory has a non-power of two capacity proportionally related to a total number of memory cells in said plane. The nonvolatile memory also includes a plurality of row decoders. An at least substantially one-to-one relationship exists, in the memory device, for number of row decoders to number of pages. Each of the row decoders is configured to facilitate a read operation on an associated page of the memory device. | 2010-12-02 |
20100306483 | Data Processor with Efficient Scalable Queuing and Method Therefor - A data processor includes a single-token-record memory, a sequence circuit, and a memory controller. The single-token-record memory has a plurality of first storage locations. The sequencer circuit is coupled to the single-token-record memory. The sequencer circuit, responsive to a request to place a token in a tail-end of a queue, either stores said token into one of the plurality of first storage locations if the single-token-record memory stores no greater than a predetermined number of tokens associated with the tail-end of the queue, or stores the token with at least one additional token and a pointer to a next storage location into one of a plurality of second storage locations otherwise. The memory controller is coupled to the sequencer circuit to store the token with the at least one additional token and the pointer in a location of a multi-token-record memory having the plurality of second storage locations. | 2010-12-02 |
20100306484 | HETEROGENEOUS STORAGE ARRAY OPTIMIZATION THROUGH EVICTION - A storage system can comprise storage devices having storage media with differing characteristics. An eviction handler can receive information regarding the state of storage media or of data stored thereon, as well as information regarding application or operating system usage, or expected usage, of data, or information regarding policy, including user-selected policy. Such information can be utilized by the eviction handler to optimize the use of the storage system by evicting data from storage media, including evicting data in order to perform maintenance on, or replace, such storage media, and evicting data to make room for other data, such as data copied to such storage media to facilitate pre-fetching or implement policy. The eviction handler can be implemented by any one or more of processes executing on a computing device, control circuitry of any one or more of the storage devices, or intermediate storage-centric devices. | 2010-12-02 |
20100306485 | CONTENT LONGEVITY WITH USER DEVICE DOMAINS - A system is disclosed for providing trusted third-party management of user device domains in a digital rights management environment. The system includes a plurality of content providers that distribute digital content items via user accounts having associated user device domains. The user device domains are managed by an independent domain manager. The domain manager includes a device registrar which is operative, for a given user device domain, to receive a request to add a device to the user device domain. If the request is grantable, a domain controller of the domain manager is operative to cause a domain private key to be transmitted to the device being added to the user device domain. The domain private key is usable at the device to decrypt a content key which was previously released to the user device domain for decrypting protected digital content. | 2010-12-02 |
20100306486 | POLICY-BASED APPLICATION AWARE STORAGE ARRAY SNAPSHOT BACKUP AND RESTORE TECHNIQUE - A method and system for performing a policy-based backup and recovery operation in a storage network is disclosed. In one embodiment, a method of performing a backup and restore operation in a storage network includes detecting each application entity in the storage network and configuring a backup and restore policy associated with the storage network for said each application entity. The storage network includes at least one host server and at least one storage array. The method also includes performing a backup operation of data associated with said each application entity based on the backup and restore policy using application utilities and operating system (OS) utilities configured to interface with said each application entity and a corresponding operating system of the at least one host server respectively, and using a storage array interface configured to directly interface with the at least one storage array. | 2010-12-02 |
20100306487 | INFORMATION STORAGE MEDIUM, AND RECORDING/REPRODUCING METHOD AND APPARATUS - An information storage medium includes: a user data area for recording user data; a spare area including spare blocks each for replacing a defective block occurring in the user data area; and a defect management area in which information about the defective block occurring in the user data area is recorded, wherein the spare blocks of the spare area include usable spare blocks with replacement blocks existing in forward parts of the usable spare blocks in a usage order, and usable spare blocks without replacement blocks existing in forward parts of the usable spare blocks in the usage order, wherein a next available position pointer of the spare area is recorded in the defect management area, and the next available position pointer of the spare area indicates a first usable spare block from among the usable spare blocks without the replacement blocks existing in the forward parts of the usable spare blocks in the usage order. | 2010-12-02 |
20100306488 | PERFORMING MIRRORING OF A LOGICAL STORAGE UNIT - Mirroring of a logical storage unit initially associated with a first controller is performed, where the first log segment associated with the first controller is maintained of writes by the first controller to the logical storage unit. The first log segment is for use in mirroring writes to a mirror system. Control of the logical storage unit is transferred from the first controller to at least a second controller, and in response to the transfer, a first marker is provided in the first log segment to enable the mirror system to synchronize mirrored writes corresponding to writes to the logical storage units by the first controller and at least a second controller. | 2010-12-02 |
20100306489 | ERROR MANAGEMENT FIREWALL IN A MULTIPROCESSOR COMPUTER - A multiprocessor computer system comprises a plurality of processors and a plurality of nodes, each node comprising one or more processors. A local memory in each of the plurality of nodes is coupled to the processors in each node, and a hardware firewall comprising a part of one or more of the nodes is operable to prevent a write from an unauthorized processor from writing to the local memory. | 2010-12-02 |
20100306490 | TRANSACTIONAL OBJECT CONTAINER - A computing device receives an object at runtime of a compiled application, wherein the object is a component of the application. The computing device generates a transactional proxy for the object, the transactional proxy including transactional logic, a transactional marker and a pointer to the object. The transactional proxy is passed to the application, wherein the application to make calls on the transactional proxy instead of on the object. | 2010-12-02 |
20100306491 | Data storage device - A data storage device capable of improving reading and writing performance includes at least one memory chip comprising a control unit and a plurality of blocks for storing data, and communicating with a host through a channel; and memory storing data output from the at least one memory chip. The control unit may sequentially read data having continuous logic addresses and discontinuous physical addresses from the plurality of blocks and store the data in the memory to have continuous physical addresses. | 2010-12-02 |
20100306492 | Relay device and relay program - Relay devices each include a port connected to a communication channel that is used to transfer and receive an access request to and from another relay device; a first virtual area section that is set as a virtual memory area that receives an access request; and a second virtual area section set as a virtual memory area for receiving an access request transferred from another relay device. The relay device sends, if a channel to a storage device is in operation, the access request that is sent to the first virtual area section and the access request that is sent to the second virtual area section, to the storage device via the channel. The relay device transfers, if the channel is not in operation, the access request sent to the first virtual area section, to another relay device via the communication channel connected to the port. | 2010-12-02 |
20100306493 | SYSTEM, METHOD, AND COMPUTER-READABLE MEDIUM FOR OPTIMIZED DATA STORAGE AND MIGRATION IN A DATABASE SYSTEM - A system, method, and computer-readable medium that facilitate optimized data storage and migration are provided. Storage device zones are tested and assigned respective speed quality ratings. The frequency with which data is accessed within the system may be periodically monitored and a corresponding access frequency quantifier assigned to the data is updated accordingly. The data access frequency quantifier may be associated with a storage device zone speed quality rating. The association between data access frequency quantifiers and the storage device zone speed quality ratings may be made in a hierarchical association such that quantifiable differentials may be ascertained between a particular access frequency quantifier and a storage device zone speed quality rating. In this manner, when no storage zone having a speed quality rating that is associated with data having a particular access frequency quantifier is available for storage of the data, a storage zone having a speed quality rating more proximate the speed quality rating associated with the access frequency quantifier may be identified for migration of the data for storage thereby. | 2010-12-02 |
20100306494 | DYNAMICALLY ALLOCATING LIMITED SYSTEM MEMORY FOR DMA AMONG MULTIPLE ADAPTERS - A method, apparatus, and computer program product dynamically allocate limited system memory for direct memory access (DMA) among a plurality of input/output (I/O) adapters in a system partition. Initially a minimum entitlement of I/O entitled memory capacity is allocated to each of the respective multiple I/O adapters. The minimum entitlement enables operation of an I/O adapter driver. Additional entitlement of I/O entitled memory capacity is selectively allocated based upon I/O demands of each I/O adapter. | 2010-12-02 |
20100306495 | RECORDING MEDIUM STORING MANAGEMENT PROGRAM, MANAGEMENT DEVICE AND MANAGEMENT METHOD - A management device obtains, from the plurality of storage nodes, information of accesses which are made to the actual storage areas included in the storage nodes, generating load information of the actual storage areas based on the access information, and storing the generated load information in a load information storage unit. The device changes, based on the load information stored in the load information storage unit, the assignment relations of the actual storage areas with respect to the virtual storage areas such that loads of the storage nodes are leveled. The device instructs the plurality of storage nodes to move the data in the actual storage areas depending on change in the assignment of the actual storage areas to the virtual storage areas. | 2010-12-02 |
20100306496 | APPARATUS AND METHOD FOR ADDRESS GENERATION FOR ARRAY PROCESSOR AND ARRAY PROCESSOR - In address generation processors, the start and the end of the processing for address generation need to be controlled in addition to controlling the processing for base address generation. A timing control unit manages control for address conversion on a clock cycle basis. The difference between the processing speed in the address generation processors and the processing speed in the address conversion circuit is absorbed by buffers. | 2010-12-02 |
20100306497 | Computer implemented masked representation of data tables - In the computer software field, method and apparatus to obfuscate (mask or hide) computer data which is part of or accessed by a computer program. The method protects (hides) accesses to tables of data in terms of the place or position of each element in the table. It does this by providing an intermediate table which describes the positions of the elements of the first table or tables, but in a transformed (modified) fashion. | 2010-12-02 |
20100306498 | STORAGE SYSTEM AND STORAGE CONTROL METHOD THAT COMPRESS AND STORE DATA ELEMENTS - A pool is formed based on a plurality of storage devices. This pool is constituted by a plurality of real pages. Real pages of different lengths are included in this plurality of real pages. Among a plurality of virtual pages which make up a virtual volume, a controller compresses a write data element for a write destination virtual page, selects a real page of a real page length based on the data length of a data unit including the compressed write data element, and allocates the selected real page to the write destination virtual page. | 2010-12-02 |
20100306499 | Translation Lookaside Buffer (TLB) with Reserved Areas for Specific Sources - In an embodiment, a TLB is partitioned into regions. The TLB may be set associative, and each section may include a portion of the locations in each way of the set associative memory. The TLB may reserve at least one of the sections for access by a subset of the request sources that use the TLB. For requests from the subset, the reserved section may be used and a location in the reserved section may be allocated to store a translation for a request from the subset that misses in the TLB. For requests for other request sources, the non-reserved section or sections may be used. In one embodiment, each way of the reserved section may be assigned to a different one of the request sources in the subset. | 2010-12-02 |
20100306500 | METHOD AND APPARATUS FOR MANAGING THIN PROVISIONING VOLUME BY USING FILE STORAGE SYSTEM - In one embodiment, a method of operating block-based thin provisioning disk volumes in a system including a first storage system which is connected via a network to a second storage system comprises, in response to a volume creation request to create a thin provisioning disk volume in the first storage system, recording in the first storage system attribute information of the block-based thin provisioning disk volume; specifying a directory path for the block-based thin provisioning disk volume in a file system in the second storage system; and creating a directory for the block-based thin provisioning disk volume under the specified directory path. | 2010-12-02 |
20100306501 | Hybrid Computer Systems - A hybrid computer system is provided, including first and second computer devices. The first computer device is configured with the second computer device via a connection unit. Each of the first computer device and the second computer device is capable of operating independently when the first computer device and the second computer device are separated. The first computer device and the second computer device communicate with each other in a master-slave structure and combined with each other into a single system. The peripheral devices of the first and second computer devices are shared, wherein the first and second computer devices are master/slave systems or slave/master systems. | 2010-12-02 |
20100306502 | DIGITAL SIGNAL PROCESSOR HAVING A PLURALITY OF INDEPENDENT DEDICATED PROCESSORS - A digital signal processor uses a number of independent sub-processors that may be controlled by a master programmable controller. For example, a specialized input processor may process input signals while a specialized output processor may process output signals. Each of these processors may also accomplish math functions when input and output processing is not necessary. The various processors may communicate with one another through general purpose registers which receive data and provide data to any of the processors in the system. Math processors may be added as needed to accomplish desired mathematical functions. In addition, a RAM processor may be utilized to hold the results of intermediate calculations in one embodiment of the present invention. In this way, an adaptable and scaleable design may be implemented that accommodates a variety of different operations without requiring redesign of all the components. | 2010-12-02 |
20100306503 | GUARANTEED PREFETCH INSTRUCTION - A microprocessor includes a cache memory, an instruction set having first and second prefetch instructions each configured to instruct the microprocessor to prefetch a cache line of data from a system memory into the cache memory, and a memory subsystem configured to execute the first and second prefetch instructions. For the first prefetch instruction the memory subsystem is configured to forego prefetching the cache line of data from the system memory into the cache memory in response to a predetermined set of conditions. For the second prefetch instruction the memory subsystem is configured to complete prefetching the cache line of data from the system memory into the cache memory in response to the predetermined set of conditions. | 2010-12-02 |
20100306504 | Controlling issue and execution of instructions having multiple outcomes - At least one instruction of a sequence of program instructions has a plurality of alternative outcomes including at least a first outcome that is independent of at least one operand and a second outcome that is dependent on the at least one operand. The at least one operand is a value generated by a preceding instruction in the sequence. The instruction is issued for execution independently of when the at least one operand is generated by the preceding instruction. Recovery circuitry is provided to perform a recovery operation in the event that the second outcome is executed for the at least one instruction and the at least one operand has not been generated by the preceding instruction when the at least one instruction is to be executed by said instruction execution circuitry. | 2010-12-02 |
20100306505 | Result path sharing between a plurality of execution units within a processor - A processor | 2010-12-02 |