48th week of 2021 patent applcation highlights part 82 |
Patent application number | Title | Published |
20210376770 | ELECTROSTATIC ENERGY HARVESTER - An electrostatic energy harvester broadly comprises an electrical energy storage component, an electrical energy transfer stage, first and second variable capacitors, and a switching control module. The electrical energy transfer stage includes diode-connected transistors and dictates electrical energy transfer between the electrical energy storage component and the variable capacitors. The switching control module timely switches between the first and second variable capacitors according to a state machine. Subsequent electrical energy investments from the electrical energy storage component are less than an initial electrical energy investment due to remnant electrical energy remaining at the previously active one of the first and second variable capacitors from previous electrical energy harvesting. | 2021-12-02 |
20210376771 | DRIVING DEVICE, TACTILE SENSATION PROVIDING APPARATUS, AND DRIVING METHOD - A driving device generates a driving signal and outputs the driving signal to a piezoelectric element, the driving signal having a waveform obtained by using, as a first modulated wave, a first low-frequency wave having a frequency of 1 Hz or more and less than 100 Hz, using, as a second modulated wave, a waveform obtained by modulating an amplitude of a second low-frequency wave having a frequency of 100 Hz or more and 300 Hz or less with the first modulated wave, and modulating a high-frequency wave having a frequency of 20 kHz or more and 100 kHz or less with the second modulated wave. | 2021-12-02 |
20210376772 | THIN FILM ACTUATOR HAVING TRANSVERSELY ORIENTED STRUCTURAL STIFFENERS TO INCREASE ACTUATOR STROKE - A thin film actuator having transversely oriented structural stiffeners that serve to increase actuation stroke that results from longitudinal curvature. The thin film actuator may be deployed within electromechanical devices such that an actuatable deflection of a tip of the actuator plate produces the actuation stroke. The thin film actuator may include an actuator plate affixed to a substantially rigid frame structure. The actuator plate protrudes along a longitudinal axis away from the frame structure such that the actuator plate is cantilevered from the frame structure by some distance along this longitudinal axis. The thin film actuator includes a piezoelectric film on a surface of the actuator plate. Activation of the piezoelectric film generates tensile stress or compressive stress at the surface, thereby inducing a bending moment that causes the actuator plate to undergo longitudinal curvature and some lesser degree of transverse curvature. | 2021-12-02 |
20210376773 | SYSTEM AND METHOD FOR COMBINED HEAT AND ELECTRIC POWER GENERATION - A system for combined heat and electric power generation, preferably including a heat reservoir and one or more electric generators, each preferably including a heat source and an energy converter. A method for combined heat and electric power generation, preferably including activating an electric generator, deactivating the electric generator, and/or providing heat from a heat reservoir. | 2021-12-02 |
20210376774 | DEVICE FOR CONVERTING ELECTROMAGNETIC MOMENTUM TO MECHANICAL MOMENTUM - Described hereafter is a device for the conversion of electromagnetic momentum into mechanical momentum to be used in airless environment. The device is built from rotating disk, made of non-magnetic material, on the circumference of which plurality of bar magnets are mounted. The bar magnets are in a plane which is perpendicular to the plane of the disk and in a plane, which is perpendicular to the radius of the disk that meets the centre of the bar magnet. The disk is driven by a motor that causes it to rotate. The magnets are positioned in an angle relative to the rotation axis of the disk. When the disk rotates, mechanical momentum, perpendicular to the plane of the rotating disk is generated. This momentum acts on the disk and causes it to move along the axis of rotation of the disk. | 2021-12-02 |
20210376775 | DISPLACEMENT CORRECTION APPARATUS, MAGNETIC LEVITATION BEARING SYSTEM AND DISPLACEMENT CORRECTION METHOD THEREOF - Disclosed is a displacement correction apparatus. The apparatus comprises: a reference circuit and a correction circuit; the reference circuit is configured to provide a reference signal; the correction circuit is configured to perform a logarithm operation on a nonlinear displacement signal to be corrected based on the reference signal, to obtain a corrected linear displacement signal. The displacement correction apparatus can solve the problem of poor detection accuracy resulting from a position signal output by an eddy current sensor being not in a linear relationship with a displacement signal of a shaft, thereby achieving the effect of improving detection accuracy. A magnetic levitation bearing system and a displacement correction method therefor which use the above displacement correction apparatus are also disclosed. | 2021-12-02 |
20210376776 | ELECTRIC MOTOR DRIVE SYSTEM FOR A VEHICLE - An electrical drive system for a vehicle. The system includes a plurality of electric propulsion motors and a plurality of corresponding inverter circuits. The system also includes an auxiliary motor for driving an auxiliary device located in the vehicle. The auxiliary motor is connected to the propulsion motors and is driven by the inverter circuits. The system does not include a separate inverter for driving the auxiliary motor. | 2021-12-02 |
20210376777 | SYSTEMS AND METHODS FOR IDENTIFYING A MAGNETIC MOVER - A system is described in which a magnetic mover includes at least one mover identification device. The system also includes a stator defining a work surface and including an actuation coil assembly and at least one stator identification device operable to interact with the at least one mover identification device. One or more sensors are used to sense a position of the first magnetic mover. One or more stator driving circuits are used to drive the actuation coil assembly to thereby move the first magnetic mover over the work surface. The first magnetic mover includes one or more magnetic components positioned such that interaction of one or more magnetic fields emitted by the one or more magnetic components with one or more magnetic fields generated by the actuation coil assembly when driven by the one or more stator driving circuits enables movement of the first magnetic mover in at least two degrees of freedom. | 2021-12-02 |
20210376778 | CONTROLLER FOR AC ROTARY ELECTRIC MACHINE - To provide a controller for AC rotary electric machine which can reduce an electromagnetic exciting force in the execution region of the magnetic flux weakening control. A controller for AC rotary electric machine, in a specific operating region which is set in an operating region of the magnetic flux weakening control, increases a maximum value of amplitude of fundamental wave components of applied voltages applied to windings more than a normal operating region other than the specific operating region; and calculates dq-axis current command values by the magnetic flux weakening control, in a condition in which the maximum value of amplitude of the fundamental wave components of the applied voltages is increased. | 2021-12-02 |
20210376779 | BRUSHLESS DC MOTOR CONTROL DEVICE FOR CEILING FAN - A brushless DC motor control device for a ceiling fan is electrically connected to a brushless DC motor and includes at least one switch, a processor, and a driving module. The processor includes at least one detection module and a processing module. The switch transmits a switch signal to the detection module for detection. After the detection module detects an operating electric potential and a normal electric potential of the switch signal, the detection module outputs a detection signal to the processing module. The processing module outputs a control signal to the driving module, so that the driving module transmits a driving signal to the brushless DC motor to control the rotational speed, stop and rotational direction of the brushless DC motor. | 2021-12-02 |
20210376780 | CONTROL DEVICE - A control device includes a processor configured to control operation of an inverter by a synchronous pulse width modulation control using a pulse width modulation signal. The inverter is coupled to a motor. The pulse width modulation signal is generated by comparison of a carrier signal and a voltage command. In the synchronous pulse width modulation control, on the condition that resonance is caused, in a circuit including the inverter, by a particular harmonic component out of harmonic components to be generated in accordance with the pulse width modulation signal, the processor is configured to change the number of pulses of the carrier signal in one cycle of the voltage command, from the main number of pulses to the sub-number of pulses. | 2021-12-02 |
20210376781 | HEIGHT ADJUSTMENT BRACKET FOR ROOF APPLICATIONS - A roof mount system supports a solar panel above a roof and includes a base positioned on the roof and a first fastener connected to the base and extending away from the roof and moveable along the base in a direction generally parallel to the roof. A first clamp supports a bottom surface of a solar panel frame and adjusts the height of the solar panel above the roof by moving the first clamp along a first fastener in a direction perpendicular to the roof. A second clamp is connected to a second fastener and moves with respect to the first clamp perpendicular to the roof. The solar panel is clamped between the first clamp and the second clamp portion. A protrusion extends from the first or second clamp to form an electrical bond between the solar panel frame and the respective first or second clamp. | 2021-12-02 |
20210376782 | ROOF MOUNTING SYSTEM - In various embodiments, the mounting systems described herein may be configured to mount a solar panel array to a flat concrete roof like those found throughout the Caribbean and Central and South America. Other systems described herein may be configured to facilitate mounting structures on standing seam metals roofs. Still other systems described herein may be configured to facilitate mounting structures on composite shingle, slate, or tile roofs. The mounting systems described herein may be configured as rail-less or rails free roof mounting systems. | 2021-12-02 |
20210376783 | Mount For An Energizer - A mount for an energizer includes a base body, a pivot element attachable to the energizer, and a pivot assembly connecting the pivot element to the base body. The pivot assembly is movable between a first position and a second position in which the pivot assembly is biased toward the first position. The pivot element is held at a fixed pivot angle by the base body with the pivot assembly in the first position. The pivot element is pivotable with respect to the base body with the pivot assembly in the second position. | 2021-12-02 |
20210376784 | SYSTEM AND METHOD FOR CONTROLLING A SOLAR PHOTOVOLTAIC INSTALLATION - System and method for controlling a photovoltaic installation ( | 2021-12-02 |
20210376785 | MAGNETICALLY LINKABLE MODULAR SOLAR PANEL SYSTEM - A modular solar charging system includes a base unit and at least one secondary unit. The base unit has a solar panel, within a base frame, electrically connected to a controller on a first lateral surface of the base frame and has conductive magnetic connectors on a second lateral surface of the base frame electrically connected to the controller. The secondary unit has a solar panel, within a secondary frame, electrically connected to conductive magnetic connectors on a first lateral surface of the secondary frame magnetically linkable to the conductive magnetic connectors on the base unit. The modular solar charging system includes solar panels with affixed electrically conductive magnetic connectors. Each of the solar panels is electrically connected to at least two electrically conductive magnetic connectors. Adjacent electrically conductive magnetic connectors are couplable to form a conductive connection. | 2021-12-02 |
20210376786 | PHOTOVOLTAIC-CLAD MASONRY UNIT - A masonry unit including a photovoltaic cell for generation of electricity is described herein. More particularly a photovoltaic-clad concrete block that combines the structural attributes of concrete block (or other masonry unit) and the energy production of solar photovoltaics is described herein. Methods for manufacturing, installing, and electrically connecting such photovoltaic-clad concrete blocks are also described herein. | 2021-12-02 |
20210376787 | Improvements To Solar Panels and Harvesting of Solar Derived Energy - Photovoltaic thermal (PVT) apparatus | 2021-12-02 |
20210376788 | SELF-POWERED VOLTAGE RAMP FOR PHOTOVOLTAIC MODULE TESTING - A self-powered voltage ramp for photovoltaic module testing provides a robust circuit for the measurement of current-voltage curves. A resistor and capacitor form a timer circuit to control a gate of a power transistor and give a linear voltage sweep from a short circuit (e.g., zero volts) to an open circuit voltage V | 2021-12-02 |
20210376789 | SOLAR CELL OR SOLAR PANEL ENERGY EXTRACTION SYSTEM - A photovoltaic system having at least one solar cell and a secondary direct current power supply connected to the at least one solar cell. The secondary power supply is configured for constant voltage operation to input power to the photovoltaic cell to maintain operation of the solar cell at or near an optimum voltage working level for the solar cell. | 2021-12-02 |
20210376790 | OPTIMIZER, PHOTOVOLTAIC POWER GENERATION SYSTEM, AND IV CURVE SCANNING METHOD FOR PHOTOVOLTAIC MODULE - A photovoltaic power generation system includes a plurality of photovoltaic modules, a plurality of optimizers, and an inverter. Each optimizer is connected to at least one photovoltaic module, and output ends of the plurality of optimizers are connected in series to form a string and then connected to the inverter. The optimizer includes a conversion unit, and a control unit configured to control the conversion unit. The optimizer further includes an auxiliary power source, an energy storage unit, and a first unidirectional conduction unit that are connected between the conversion unit and the control unit. The control unit is configured to perform IV curve scanning for each voltage segment, where the voltage segments are obtained by segmenting a range of an output voltage of a photovoltaic module corresponding to the optimizer from an open-circuit voltage to a preset minimum voltage, and at least two voltage segments are obtained through division. | 2021-12-02 |
20210376791 | Integrated Circuit, Oscillator, Electronic Apparatus, And Vehicle - An integrated circuit includes a first coupling terminal and a second coupling terminal disposed along a first side, an oscillation circuit which is electrically coupled to a resonator element via the first coupling terminal and the second coupling terminal, a temperature sensor, a temperature compensation circuit configured to compensate a temperature characteristic of the resonator element based on an output signal of the temperature sensor, and an output circuit to which a signal output from the oscillation circuit is input, and which is configured to output an oscillation signal, wherein d | 2021-12-02 |
20210376792 | OSCILLATOR WAFER-LEVEL-PACKAGE STRUCTURE - An oscillator wafer-level-package structure is provided, comprising a bottom layer, an oscillator crystal and a capping layer. The bottom layer includes an upper plane, the capping layer includes a lower plane, and the oscillator crystal is disposed between the bottom layer and the capping layer and includes at least one cavity. An upper seal ring and a lower seal ring are respectively surrounding the oscillator crystal such that the oscillator crystal is sealed in between the capping layer and the bottom layer by employing the upper and lower seal rings. In addition, a diffusion barrier is further disposed in the upper seal ring and in the lower seal ring for avoiding interface diffusion. Moreover, the present invention adopts the same material for fabricating the capping layer, the oscillator crystal and the bottom layer to achieve an optimal thermal stress result when realizing the packaging structure. | 2021-12-02 |
20210376793 | SPIN TORQUE OSCILLATOR WITH AN ANTIFERROMAGNETICALLY COUPLED ASSIST LAYER AND METHODS OF OPERATING THE SAME - A spin torque oscillator includes a first electrode, a second electrode and a device layer stack located between the first electrode and the second electrode. The device layer stack includes a spin polarization layer including a first ferromagnetic material, an assist layer including a third ferromagnetic material, a ferromagnetic oscillation layer including a second ferromagnetic material located between the spin polarization layer and the assist layer, a nonmagnetic spacer layer located between the spin polarization layer and the ferromagnetic oscillation, and a nonmagnetic coupling layer located between the ferromagnetic oscillation layer and the assist layer. The assist layer is antiferromagnetically coupled to the ferromagnetic oscillation layer through the non-magnetic coupling layer, and the assist layer has a magnetization that is coupled to a magnetization of the ferromagnetic oscillation layer. | 2021-12-02 |
20210376794 | METHOD AND CIRCUIT FOR POWER CONSUMPTION REDUCTION IN ACTIVE PHASE SHIFTERS - An electronic circuit and method are provided. The electronic circuit includes an in-phase(I)-quadrature(Q) amplifier including an I cascode branch and a Q cascode branch, the IQ amplifier configured to receive a differential input and control signals, control, based on the control signals, gate voltages in the I cascode branch and gate voltages in the Q cascode branch, generate an I output signal with the I cascode branch, and generate a Q output signal with the Q cascode branch, and a quadrature coupler configured to perform quadrature summation of the I output signal and the Q output signal and generate a final phase shifted output. | 2021-12-02 |
20210376795 | DIGITAL ENVELOP TRACKER FOR POWER AMPLIFIER - A digital envelop tracker for a power amplifier. The digital envelop tracker includes a supply filter for filtering a supply voltage to a power amplifier, a level selection circuitry configured to determine a level of supply voltage based on an instantaneous power of an input data stream, schedule a series of switching events based on the determined level of supply voltage, and generate a level select signal based on the scheduled series of switching events, and a switch for connecting one of supply voltages to the supply filter based on the level select signal. The level selection circuitry schedules a primary switching event of the switch based on the determined level of supply voltage and secondary switching events of the switch delayed with respect to the primary switching event based on the determined level of supply voltage to generate a filter response of the supply filter with smaller peaking. | 2021-12-02 |
20210376796 | METHOD AND SYSTEM FOR POWERING AN AUDIO AMPLIFIER - A method for powering an audio amplifier includes receiving an input audio signal in an audio signal processor, delaying the input audio signal in the audio signal processor to generate a delayed audio signal, predicting a power demand estimate by analyzing the input audio signal to calculate the power demand estimate in the audio signal processer, and selecting, by the audio signal processor, power conversion settings for a DC to DC converter on the basis of the power demand estimate. The method further includes supplying power input to the DC to DC converter, converting the power input in accordance with the power conversion settings to provide a power output, powering the audio amplifier using the power output, and supplying the delayed audio signal to the audio amplifier from the audio signal processor to generate an amplified audio signal. | 2021-12-02 |
20210376797 | LOW-NOISE AMPLIFIER SUPPORTING MULTI CARRIER OPERATIONS - A radio-frequency (RF) amplifier circuit facilites carrier-aggregation (CA) operation in a wireless communication network. A first amplifier subcircuit is coupled to an input node, and a second amplifier subcircuit is coupled to the input node. An amplifier subcircuit selector is to selectively enable operation of the first amplifier subcircuit, the second amplifier subcircuit, or the first and the second amplifier subcircuits together, in response to a selection indication. A reactive coupling network is arranged to selectively adjust the input impedance at the input node in response to the selection indication to reduce the input impedance variation. | 2021-12-02 |
20210376798 | DOHERTY AMPLIFIER INCORPORATING OUTPUT MATCHING NETWORK WITH INTEGRATED PASSIVE DEVICES - An amplifier includes a package that includes a carrier amplifier having a carrier amplifier input and output, a peaking amplifier having a peaking amplifier input and output, and corresponding input and output leads. The package includes a first integrated passive device including a first capacitor structure. The first integrated passive device includes a first contact pad coupled to the peaking amplifier output and a second contact pad coupled to the peaking output lead. The package includes a second integrated passive device including a second capacitor structure. The second integrated passive device includes a third contact pad coupled to the carrier amplifier output and a fourth contact pad coupled to the carrier output lead. The amplifier includes input circuitry a combining node configured to combine a carrier output signal and a peaking output signal. | 2021-12-02 |
20210376799 | CONTROL CIRCUIT - A control circuit is configured to control a Doherty amplifier including a carrier amplifier and a peak amplifier. The control circuit includes a resistor having a resistance value that is irreversibly adjustable. The resistor is configured to determine, based on the resistance value, a bias of the peak amplifier. The control circuit controls a Doherty amplifier. | 2021-12-02 |
20210376800 | PHASED ARRAY AMPLIFIER LINEARIZATION - Apparatus and methods provide predistortion for a phased array. Radio frequency (RF) sample signals from phased array elements are provided along return paths and are combined by a hardware RF combiner. Phase shifters are adjusted such that the RF sample signals are phase-aligned when combined. Adaptive adjustment of predistortion for the amplifiers of the phased array can be based on a signal derived from the combined RF sample signals. | 2021-12-02 |
20210376801 | AMPLIFIER HAVING INPUT POWER PROTECTION - Amplifier having input power protection. In some embodiments, an amplifier circuit can include an input node and an output node, and an amplifier implemented between the input node and the output node. The amplifier circuit can further include a bias circuit configured to provide a bias signal to the amplifier. The amplifier circuit can further include a protection circuit configured to generate a detected voltage representative of a peak of a radio-frequency signal present at the input node. The protection circuit can be further configured to enable a protection mode when the detected voltage is greater than a first threshold value and to disable the protection mode when the detected voltage is less than a second threshold value that is less than the first threshold value. | 2021-12-02 |
20210376802 | BALANCED AMPLIFIER ARRANGEMENT FOR POWER CONTROL AND IMPROVED DEEP BACK-OFF EFFICIENCY - Methods and apparatuses for providing a reduction in output power of a balanced amplifier configuration are presented. According to one aspect, reduction of the output power is provided by deactivating one of the two amplification paths of the balanced amplifier. According to another aspect, impedances seen at ports of input and output couplers of the balanced amplifier configuration part of a deactivated amplification path are selectively switched in dependence of operation according to the reduced output power or according to normal output power. In addition, or in the alternative, impedance seen at an isolated/terminated port of the input and/or the output coupler is selectively switched in dependence of the operation. When operating according to the reduced output power, values of the switched impedances can be adjusted to tune a frequency response of the balanced amplifier. | 2021-12-02 |
20210376803 | RADIO FREQUENCY POWER AMPLIFIER AND METHOD OF ASSEMBLY THEREOF - Radio frequency amplifier ( | 2021-12-02 |
20210376804 | RADIO FREQUENCY (RF) DEVICE HAVING TUNABLE RF POWER AMPLIFIER AND ASSOCIATED METHODS - A radio frequency (RF) device may include an RF signal source having a selectable frequency, an RF antenna, and an RF power amplifier module coupled between the RF signal source and the RF antenna. The RF power amplifier module may include at least one input tunable cavity impedance matching device, at least one output tunable cavity impedance matching device, and a power amplifier device connected therebetween. A controller may select the selectable frequency of the RF signal source, tune the at least one input tunable cavity impedance matching device based upon the selected frequency, and tune the at least one output tunable cavity impedance matching device based upon the selected frequency. | 2021-12-02 |
20210376805 | ADJUSTABLE CAPACITORS TO IMPROVE LINEARITY OF LOW NOISE AMPLIFIER - An amplifier includes an input transistor pair connected to amplifier input nodes, a complementary transistor pair connected to a common bias, amplifier output nodes connected to the input transistor pair and the complementary transistor pair, and variable capacitors connected between the complementary transistor pair and the amplifier output nodes. | 2021-12-02 |
20210376806 | INTERNAL POWER SUPPLY FOR AMPLIFIERS - An internal power supply for an amplifier is disclosed. The internal power supply floats according to a common mode voltage at the input to the amplifier and according to an input voltage at an input stage of the amplifier. Powering the input stage of the amplifier using the floating supply allows for the use of low voltage devices even when the range of possible common mode voltages includes high voltages. The use of low voltage devices can correspond to performance improvement for the amplifier and can help reduce the size of the amplifier. The internal supply can accommodate both positive and negative common mode voltages and can be used for current sense amplifiers of any gain. | 2021-12-02 |
20210376807 | RF AMPLIFIERS HAVING SHIELDED TRANSMISSION LINE STRUCTURES - RF transistor amplifiers include an RF transistor amplifier die having a semiconductor layer structure, a coupling element on an upper surface of the semiconductor layer structure, and an interconnect structure on an upper surface of the coupling element so that the RF transistor amplifier die and the interconnect structure are in a stacked arrangement. The coupling element includes a first shielded transmission line structure. | 2021-12-02 |
20210376808 | CIRCUITS, EQUALIZERS AND RELATED METHODS - A circuit is disclosed, in accordance with some embodiments. The circuit includes a transistor stage, a resistive element, a first tunable capacitive element and a second tunable capacitive element. The transistor stage includes a first input/output terminal and a second input/output terminal. The resistive element is connected to the transistor stage. The first tunable capacitive element is connected in parallel with the resistive element. The second tunable capacitive element is connected to the second input/output terminal of the transistor stage. | 2021-12-02 |
20210376809 | FILTER INDUCTOR AND ON-BOARD-CHARGER - A filter inductor, which includes: an outer magnetic core with a window, an inner magnetic core, and a winding. The inner magnetic core includes a first inner magnetic core and a second inner magnetic core which are located at least partially in the window. The winding includes a first winding, a second winding, a third winding and a fourth winding which are wound around the outer magnetic core at intervals. The first inner magnetic core and the second inner magnetic core are stacked. For the first inner magnetic core, a first end is located between the first winding and the second winding, and a second end is located between the third winding and the fourth winding. For the second inner magnetic core, a first end is located between the second winding and the third winding, and a second end is located between the fourth winding and the first winding. | 2021-12-02 |
20210376810 | PACKAGE COMPRISING STACKED FILTERS WITH A SHARED SUBSTRATE CAP - A package that includes a first filter comprising a first polymer, a substrate cap, a second filter comprising a second polymer frame, at least one interconnect, an encapsulation layer and a plurality of through encapsulation vias. The substrate cap is coupled to the first polymer frame such that a first void is formed between the substrate cap and the first filter. The second polymer frame is coupled to the substrate cap such that a second void is formed between the substrate cap and the second filter. The at least one interconnect is coupled to the first filter and the second filter. The encapsulation layer encapsulates the first filter, the substrate cap, the second filter, and the at least one interconnect. The plurality of through encapsulation vias coupled to the first filter. | 2021-12-02 |
20210376811 | ACOUSTIC WAVE DEVICE AND COMPOSITE FILTER DEVICE - An acoustic wave device includes a mounting substrate, and an acoustic wave element chip. The mounting substrate includes a first major surface with an electrode land thereon, and a second major surface facing the first major surface. The acoustic wave element chip includes a piezoelectric substrate including a major surface, and a functional electrode and a bump located over the major surface of the piezoelectric substrate. The bump is joined to the electrode land. A heat radiation pattern is located over the first major surface of the mounting substrate and located within a region facing the functional electrode of the acoustic wave element chip. The heat radiation pattern is connected to an internal layer portion of the mounting substrate between the first and second major surfaces, and not electrically connected to the electrode land on the first major surface. | 2021-12-02 |
20210376812 | SURFACE ACOUSTIC WAVE ELECTROACOUSTIC DEVICE FOR REDUCED TRANSVERSAL MODES - Aspects of the disclosure relate to an electroacoustic device that includes a piezoelectric material and an electrode structure that includes a first busbar and a second busbar along with electrode fingers arranged in an interdigitated manner and including a first plurality of fingers connected to the first busbar and a second plurality of fingers connected to the second busbar. The electrode structure further includes a first conductive structure disposed between each of the first plurality of fingers and disposed between the first busbar and the second plurality of fingers. The electrode structure further includes a second conductive structure disposed between each of the second plurality of fingers and disposed between the second busbar and the first plurality of fingers. The first conductive structure and the second conductive structure each have a height that is less than a height of the second plurality of fingers. | 2021-12-02 |
20210376813 | SLANTED APODIZATION FOR ACOUSTIC WAVE DEVICES - A device includes a die and an interdigital transducer on the die. The interdigital transducer includes a first bus bar, a second bus bar, and a number of electrode fingers. The first bus bar is parallel to the second bus bar. The electrode fingers are divided into a first set of electrode fingers and a second set of electrode fingers. The first set of electrode fingers extend obliquely from the first bus bar towards the second bus bar. The second set of electrode fingers extend obliquely from the second bus bar towards the first bus bar, and are parallel to and interleaved with the first set of electrode fingers. By providing the electrode fingers oblique to the bus bars, spurious transverse modes may be suppressed while maintaining the quality factor, electromechanical coupling coefficient, and capacitance of the device. | 2021-12-02 |
20210376814 | TRANSVERSELY-EXCITED FILM BULK ACOUSTIC RESONATORS WITH TWO-LAYER ELECTRODES - Acoustic resonators and filter devices, and methods of making acoustic resonators and filter devices. An acoustic resonator includes a substrate having a surface and a single-crystal piezoelectric plate having front and back surfaces, the back surface attached to the surface of the substrate except for a portion of the plate forming a diaphragm that spans a cavity in the substrate. An interdigital transducer (IDT) is formed on the front surface with interleaved fingers of the IDT on the diaphragm. The plate and the IDT are configured such that a radio frequency signal applied to the IDT excites a primary shear acoustic mode in the diaphragm. The fingers include a first layer proximate the diaphragm, and a second layer over the first layer. The first and second layers are different metals. A transverse acoustic impedance of the second layer is higher than a transverse acoustic impedance of the first layer. | 2021-12-02 |
20210376815 | MICRO-TRANSFER-PRINTED ACOUSTIC WAVE FILTER DEVICE - A compound acoustic wave filter device comprises a support substrate having an including two or more circuit connection pads. An acoustic wave filter includes a piezoelectric filter element and two or more electrodes. The acoustic wave filter is micro-transfer printed onto the support substrate. An electrical conductor electrically connects one or more of the circuit connection pads to one or more of the electrodes. | 2021-12-02 |
20210376816 | PACKAGE COMPRISING STACKED FILTERS - A package that includes a first filter device and a second filter device coupled to the first filter device. The first filter device includes a first substrate comprising a first piezoelectric material, and a first metal layer coupled to a first surface of the first substrate. The second filter device includes a second substrate comprising a second piezoelectric material, and a second metal layer coupled to a first surface of the first substrate. The package includes a first pillar interconnect configured to be electrically coupled to the first metal layer of the first filter device, where the first pillar interconnect extends through the second filter device. The package further includes a second pillar interconnect configured to be electrically coupled to the second metal layer of the second filter device. | 2021-12-02 |
20210376817 | PHASE-VARIABLE FREQUENCY MULTIPLIER AND ANTENNA DEVICE - A phase-variable frequency multiplier includes: a 90-degree divider for dividing an input signal into an I-signal and a Q-signal; an amplitude setting circuit for distributing each of the I-signal and the Q-signal to two paths, setting amplitudes of two of four signals including the two distributed I-signals and the two distributed Q-signals depending on a phase shift amount of the input signal, and outputting as set signals, the four signals including the signals with the set amplitudes; a first mixer for multiplying one of the two I-signals included in the set signals by one of the two Q-signals included in the set signals to generate a first signal having a frequency being twice the frequency of the input signal; a second mixer for multiplying the other of the two I-signals included in the set signals by the other of the two Q-signals included in the set signals to generate a second signal with an amplitude ratio with respect to the first signal, being a tangent or a reciprocal of a tangent of the phase shift amount and with a frequency being twice the frequency of the input signal; and a 90-degree combiner for applying a phase difference of 90 degrees between the first signal and the second signal, and combining the first signal having the phase difference of 90 degrees from the second signal with the second signal. | 2021-12-02 |
20210376818 | RECONFIGURABLE GALLIUM NITRIDE (GAN) ROTATING COEFFICIENTS FIR FILTER FOR CO-SITE INTERFERENCE MITIGATION - A finite impulse response (FIR) filter including an input of the FIR filter that receives an RF input signal, a clock input configured to receive a clock signal, an output of the FIR filter that provides a filtered output signal, a plurality of signal paths including a plurality of sample-and-hold circuits and a plurality of multipliers arranged in parallel, each signal path including a respective sample-and-hold circuit and a respective multiplier being configured to receive the RF input signal and the clock signal to provide a modulated output signal, an adder configured to receive n modulated output signals from the plurality of signal paths and combine the n modulated output signals to produce the filtered output signal, and a controller. | 2021-12-02 |
20210376819 | FLIP-FLOP CELL - An integrated circuit includes a semiconductor substrate and a plurality of circuit elements in or on the substrate. The circuit elements are defined by standard layout cells selected from a cell library. The circuit elements including a plurality of flip-flops. Each flip-flop has a data input terminal, a data output terminal, a clock input terminal, and a clock output terminal. A first one of the flip-flops directly abuts a second flip-flop such that the clock output terminal of the first flip-flop electrically connects with the clock input terminal of the second flip-flop. | 2021-12-02 |
20210376820 | OSCILLATION CIRCUIT, SEMICONDUCTOR DEVICE FOR OSCILLATION CIRCUIT AND METHOD FOR MANUFACTURING THE SAME - An oscillation circuit is provided. The oscillation circuit includes a first inverting circuit. The first inverting circuit comprises a first transistor of a first type and a second transistor of the first type, wherein a gate terminal of the first transistor is connected to a gate terminal of the second transistor, and a source terminal of the first transistor is connected to a drain terminal of the second transistor. | 2021-12-02 |
20210376821 | DIGITAL CIRCUIT DEVICE AND VOLTAGE DROP DETECTOR CIRCUITRY - A digital circuit device includes a power supply circuitry, a digital circuitry, a digital circuitry, and a protection circuitry. The power supply circuitry is configured to output a supply voltage. The digital circuitry is configured to be driven by the supply voltage, and is configured to perform at least one operation according to a first clock signal. The protection circuitry is configured to generate the first clock signal according to at least one of a voltage drop of the supply voltage and a load signal sent from the digital circuitry. | 2021-12-02 |
20210376822 | Galvanically Isolated Driver Package for Switch Drive Circuit with Power Transfer - The present application provides a packaged gate drive circuit having a transformer. The transformer which is used to transfer both signals and power from a primary side to a secondary side. The windings of the transformer are formed using a combination of tracks and wirebond wires. The transformer is positioned in a well formed using a first insulating material and covered with a second insulating material. | 2021-12-02 |
20210376823 | SWITCHING CIRCUIT - A switching circuit includes a first transmission terminal, a second transmission terminal, a third transmission terminal, and a variable impedance circuit. The first and the second transmission terminals coupled to a common node form a first transmission path. The third transmission terminal coupled to the common node forms a second transmission path with the first transmission terminal. The variable impedance circuit has a first terminal coupled between the common node and the third transmission terminal, and a second terminal coupled to a first reference potential terminal. When the first transmission path transmits a first signal, a first frequency bandwidth range provided by the variable impedance circuit is determined according to a first frequency of the first signal so that the variable impedance circuit provides low impedance in the first frequency bandwidth range, and the first frequency bandwidth range covers the first frequency. | 2021-12-02 |
20210376824 | METHOD AND APPARATUS FOR AVOIDING PARASITIC OSCILLATION IN A PARALLEL SEMICONDUCTOR SWITCH - A method for avoiding parasitic oscillation in a parallel semiconductor switch includes allowing only one of the plurality of power components to control a turn-on transition of the semiconductor switch and allowing only one of the plurality of power components to control a turn-off transition of the semiconductor switch, by setting unbalanced driving impedances for the plurality of power components coupled in parallel. Parasitic oscillation in a switch transition may be avoided without impedance matching, and the switch transition may provide a relatively small impact on switch characteristics. | 2021-12-02 |
20210376825 | SiC GATE DRIVE CONTROL WITH TRENCH FETS FROM HIGH dV\dT AT DRAIN SOURCE - A switching circuit can help reduce electrical feedback ringing at a gate terminal of a transistor. The switching circuit can include a transistor circuit to switch an electrical signal and a control circuit to provide an actuation signal to the gate terminal of the transistor device. The switching circuit can also include a booster circuit that is disposed between the control circuit and the gate terminal of the transistor device. The booster circuit can be configured to detect a signal from the control circuit to turn off the transistor device and, responsive to the detected signal, drive a current into the gate terminal of the transistor device for a specified span of time before the transistor device turns off. | 2021-12-02 |
20210376826 | GATE DRIVING APPARATUS, SWITCHING APPARATUS AND GATE DRIVING METHOD - Provided is a gate driving apparatus, including: a gate driving unit for driving a gate of a switching device; a switching unit for switching a gate current of the switching device during, within a turn-on period of the switching device, at least a part of the period, which is after timing when a current starts to flow in the switching device, to a smaller current when compared to the gate current before at least a part of the period. | 2021-12-02 |
20210376827 | LOW EMISSION ELECTRONIC SWITCH FOR SIGNALS WITH LONG TRANSITION TIMES - A switch including multiple current branches and slope circuitry. The slope circuitry activates or deactivates the current branches one at a time according to a corresponding one of multiple slope functions in response to a transition of the input signal. Each current branch develops a current so that the output node follows a predetermined voltage-current function. Each slope function is other than a step function and may be linear or non-linear. A slope function may be configured as a current-starved inverter charging or discharging a capacitor with a fixed current. Delay circuitry may be included to delay the inputs or the outputs of the slope circuitry configured as multiple slope control circuits. The slope control circuits may be daisy-chained from first to last to effectuate the delay. Each current branch may include an electronic switch and may further include a resistor to determine the current level. | 2021-12-02 |
20210376828 | FEEDBACK-BASED TRANSISTOR DRIVER - A device for driving a control terminal of a transistor includes an input terminal, a transformer including an input winding and an output winding, the input winding being coupled to the input terminal, an n-stage buffer circuit configured to generate a drive signal for the control terminal of the transistor, the n-stage buffer circuit being coupled to a first end of the output winding, and a positive feedback path coupled to an output of a stage of the n-stage buffer circuit to provide a DC offset to an input of the n-stage buffer circuit. | 2021-12-02 |
20210376829 | SIMULTANEOUS TIME DOMAIN DIFFERENTIAL SENSING AND ELECTRIC FIELD SENSING - Systems and methods for determining a touch input are provided. The systems and methods generally include measuring the peak voltage at an electrode over a measurement period and determining a touch input based on the peak voltage. The systems and methods can conserve computing resources by deferring digital signal processing until after a peak electrode capacitance has been sampled. The systems and methods are suitable for capacitive sensors using self-capacitance and capacitive sensors using mutual capacitance. The systems and methods are also suitable for capacitive buttons, track pads, and touch screens, among other implementations. | 2021-12-02 |
20210376830 | SIMULTANEOUS TIME DOMAIN DIFFERENTIAL SENSING AND ELECTRIC FIELD SENSING - Systems and methods for determining a touch input are provided. The systems and methods generally include measuring the peak voltage at an electrode over a measurement period and determining a touch input based on the peak voltage. The systems and methods can conserve computing resources by deferring digital signal processing until after a peak electrode capacitance has been sampled. The systems and methods are suitable for capacitive sensors using self-capacitance and capacitive sensors using mutual capacitance. The systems and methods are also suitable for capacitive buttons, track pads, and touch screens, among other implementations. | 2021-12-02 |
20210376831 | Method for Multiplexing Between Power Supply Signals for Voltage Limited Circuits - In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and to generate a plurality of adjustable power signals. One adjustable power signal may be coupled to a particular functional circuit of the functional circuits. The power management circuit may a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit may couple a respective power node for a sub-circuit of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit may also be configured to maintain an operational voltage level on the power node. | 2021-12-02 |
20210376832 | APPARATUS AND CONTROL OF A SINGLE OR MULTIPLE SOURCES TO FIRE COUNTERMEASURE EXPENDABLES ON AN AIRCRAFT - A sequencer for use with a countermeasure defense system includes an input signal indicative of firing an expendable, a circuit card that receives the input signal indicative of firing the expendable and an output analog signal from the circuit card that fires the expendable. The parameters of the output analog signal correspond to parameters of a digital waveform. | 2021-12-02 |
20210376833 | METHOD AND APPARATUS FOR PROVIDING FIELD-PROGRAMMABLE GATE ARRAY (FPGA) INTEGRATED CIRCUIT (IC) PACKAGE - An integrated circuit (“IC”) module includes a substrate, multiple field-programmable gate array (“FPGA”) dies, and pads capable of being selectively configured to perform one or more user defined logic functions. The substrate is configured to house multiple FPGA dies side-by-side in an array formation facilitating transmission of signals between the FPGA dies or chips. The FPGA dies are placed on the substrate functioning as a single FPGA device. The periphery dies of the FPGA dies are configured for external connectivity and the interior dies which are interconnected to perform user defined logic functions. The pads, in one aspect, coupling to the FPGA dies, are configured to provide connections between at least some of the FPGA dies. | 2021-12-02 |
20210376834 | METHOD AND APPARATUS FOR PROVIDING MULTIPLE POWER DOMAINS A PROGRAMMABLE SEMICONDUCTOR DEVICE - A semiconductor device, able to be selectively configured to perform one or more user defined logic functions, includes a semiconductor die and a selectable power regulator. The semiconductor die, in one aspect, includes a first region and a second region. The first region is operatable to perform a first set of logic functions based on a first power domain having a first voltage. The second region is configured to perform a second set of logic functions based on a second power domain having a second voltage. The selectable power regulator, in one embodiment, provides the second voltage for facilitating the second power domain in the second region of the semiconductor die in response to at least one enabling input from the first region of the semiconductor die. | 2021-12-02 |
20210376835 | SCHEDULING OF TASKS FOR EXECUTION IN PARALLEL BASED ON GEOMETRIC REACH - Systems and methods related to scheduling of tasks for execution in parallel based on geometric reach are described. An example method includes processing information pertaining to connectivity among superconducting components and nodes included in a shared floor plan to generate a plurality of areas of reach, where each of the plurality of areas of reach corresponds to a portion of the shared floor plan. The method further includes generating a plurality of inflated areas of reach by inflating each of the plurality of areas of reach based on a target inductance of wires for routing signals among the superconducting components and the nodes included in the shared floor plan. The method further includes scheduling parallel execution of tasks for routing wires among a subset of the superconducting components and the nodes within any of the plurality of inflated areas of reach satisfying a geometric constraint. | 2021-12-02 |
20210376836 | SIGNAL PROCESSING CIRCUIT, SIGNAL PROCESSING DEVICE, AND SIGNAL PROCESSING METHOD - A signal processing circuit ( | 2021-12-02 |
20210376837 | PHASE LOCK LOOP (PLL) SYNCHRONIZATION - In an embodiment, an apparatus includes a first integrated circuit (IC) chip configured to receive a timing signal and a reference clock signal; and a second IC chip configured to receive the timing signal and the reference clock signal. The first and second IC chips are configured to generate respective first and second reference time signals based on the timing signal and the reference clock signal. The first and second IC chips include a respective first phase lock loop (PLL) and second PLL. The first PLL and the second PLL are synchronized to each other based on the first reference time signal and the second reference time signal. | 2021-12-02 |
20210376838 | CHARGE PUMP - In described examples, a method of operating a charge pump includes a first control signal deactivating a first transistor, and the first control signal's logical complement activating a second transistor to reset the first transistor's DC bias voltage. The first control signal's logical complement deactivates the second transistor, and the first control signal provides a bias voltage to the first transistor to activate it, causing current to be transmitted from an input voltage to an output terminal. A second control signal deactivates a third transistor, and the second control signal's logical complement activates a fourth transistor to reset the second transistor's DC bias voltage. The second control signal's logical complement deactivates the fourth transistor, and the second control signal provides a bias voltage to the third transistor to activate it, causing current to be transmitted from the output terminal to a ground. | 2021-12-02 |
20210376839 | Closed-Loop Oscillator Based Sensor Interface Circuit - An oscillator-based sensor interface circuit includes first and second input nodes arranged to receive first and second electrical signals representative of an electrical quantity, respectively; an analog filter; a first oscillator arranged to receive a first oscillator input signal and a second oscillator different from the first oscillator and arranged to receive a second oscillator input signal; a comparator arranged to compare signals coming from the first and second oscillators; a first feedback element arranged to receive a representation of the digital comparator output signal and to convert the representation into a first feedback signal to be applied to the oscillation means; a digital filter arranged to yield an output signal, being an filtered version of the digital comparator output signal; a second feedback element arranged to receive the output signal and to convert the output signal into a second feedback signal. | 2021-12-02 |
20210376840 | Oscillator, Electronic Apparatus, And Vehicle - In the oscillator, a quartz crystal resonator and an oscillation circuit formed in an IC incorporating an inductor are electrically coupled to each other with a resonator interconnection disposed on a surface of a substrate to form an oscillation loop. A conductor layer disposed as an intermediate layer of the substrate is disposed so as to overlap the resonator interconnection and not to overlap the inductor incorporated in the IC in a plan view. | 2021-12-02 |
20210376841 | DIGITAL PHASE LOCKED LOOP CIRCUIT, DIGITALLY-CONTROLLED OSCILLATOR, AND DIGITAL-TO-TIME CONVERTER - With respect to a phase locked loop (PLL) circuit that receives a first reference clock and generates an output clock, the PLL circuit includes a delay circuit that delays the first reference clock to generate a second reference clock, a feedback circuit that generates a control signal based on a phase difference between the second reference clock and a feedback clock, an oscillator that oscillates at a frequency determined based on the control signal to generate the output clock, and a divider that divides the output clock in the on state. The PLL circuit switches between a first mode and a second mode, the feedback clock in the first mode is a signal obtained by retiming an output of the divider with the output clock, and the feedback clock in the second mode is a signal obtained by retiming the first reference clock with the output clock. | 2021-12-02 |
20210376842 | Open loop fractional frequency divider - Disclosed is an open loop fractional frequency divider including an integer divider, a control circuit, and a phase interpolator. The integer divider processes an input clock according to the setting of a target frequency to generate a first frequency-divided clock and a second frequency-divided clock. The control circuit generates a coarse-tune control signal and a fine-tune control signal according to the setting. The phase interpolator generates an output clock according to the first frequency-divided clock, the second frequency-divided clock, and the two control signals. The two control signals are used for determining a first current, and their reversed signals are used for determining a second current. The phase interpolator controls a contribution of the first (second) frequency-divided clock to the generation of the output clock according to the first (second) frequency-divided clock, the reversed signal of the first (second) frequency-divided clock, and the first (second) current. | 2021-12-02 |
20210376843 | Atomic Oscillator And Frequency Signal Generation System - An atomic oscillator including an oscillator that outputs an oscillation signal, a light emitter to which a signal based on the oscillation signal is inputted, an atomic cell, a light receiver that detects the light passing through the atomic cell and outputs a detection signal, a first temperature controller, and a control circuit, and the control circuit has a first mode including the process of operating the light emitter and the first temperature controller and the process of causing the oscillator to output the oscillation signal, a second mode including the process of causing the light emitter and the first temperature controller to stop operating and the process of causing the oscillator to stop outputting the oscillation signal, and a third mode including the process of causing the light emitter to stop operating, the process of operating the first temperature controller, and the process of causing the oscillator to stop outputting the oscillation signal. | 2021-12-02 |
20210376844 | Event Driven Quasi-Level Crossing Delta Modulator Analog To Digital Converter With Adaptive Resolution - A novel and useful digitally intensive event-driven quasi-level crossing (quasi-LC) delta modulator analog to digital converter (ADC) with adaptive resolution (AR) for Internet of Things (IoT) wireless networks. Minimizing the average sampling rate for sparse input signals significantly reduces the power consumed in data transmission, processing, and storage. The AR quasi-LC delta modulator quantizes the residue voltage signal with a 4-bit asynchronous successive approximation register (SAR) sub-ADC, which enables a straightforward implementation of LC and AR algorithms in the digital domain. The modulator achieves data compression by means of a globally signal dependent average sampling rate and achieves AR through a digital multilevel comparison window that overcomes the tradeoff between the dynamic range and the input bandwidth in conventional LC ADCs. Engaging the AR algorithm reduces the average sampling rate by a factor of three at the edge of the modulator's signal bandwidth. | 2021-12-02 |
20210376845 | ADC HAVING ADJUSTABLE THRESHOLD LEVELS FOR PAM SIGNAL PROCESSING - An ADC system dynamically adjusts threshold levels used to resolve PAM signal amplitudes into digital values. The ADC circuitry includes an analog front end to receive and condition the PAM signal, a low-resolution ADC to digitize the conditioned signal according to a first set of threshold values, and a high-resolution ADC to subsample the conditioned signal to generate subsampled signals. A microprocessor in communication with the low-resolution ADC and the high-resolution ADC derives a statistical value from the subsampled signals, determines an updated set of threshold values, and dynamically replaces the first set of threshold values for the low-resolution ADC with the updated set of threshold values. | 2021-12-02 |
20210376846 | ANALOG-TO-DIGITAL CONVERTER CAPABLE OF CANCELLING SAMPLING NOISE - The present application discloses an analog-to-digital converter capable of cancelling sampling noise, which comprises: a sampling circuit configured to acquire an analog input signal; a sampling noise cancelling circuit has an input end connected with an output end of the sampling circuit, and is configured to cancel noise generated by the sampling circuit; a comparator has an input end connected with an output end of the sampling noise cancelling circuit, and an output end connected with an input end of a logic circuit, and is configured to compare magnitudes of output signals of the sampling noise cancelling circuit and output a comparison result to the logic circuit; and the logic circuit has an output end connected with the sampling circuit, and is configured to output a digital output signal, and process the comparison result to obtain a control signal by which an output voltage of the sampling circuit is controlled. | 2021-12-02 |
20210376847 | COMPARATOR CIRCUIT APPLICABLE TO HIGH-SPEED PIPELINE ADC - The present invention provides a comparator circuit applicable to a high-speed pipeline ADC. The comparator circuit includes a switch capacitor circuit, a pre-amplification circuit, and a latch circuit. The pre-amplification circuit includes a pre-amplifier, a resistance-adjustable device, two switches. The latch circuit includes a differential static latch, a first capacitor, a second capacitor, and a third switch. The transmission rates of a sampling phase and a setup phase can be increased. | 2021-12-02 |
20210376848 | SEMICONDUCTOR DEVICE - A semiconductor device with a novel structure is provided. The semiconductor device includes a sensor, an amplifier circuit to which a sensor signal of the sensor is input, a sample-and-hold circuit that retains a voltage corresponding to an output signal of an amplifier input to the sample-and-hold circuit, an analog-to-digital converter circuit to which an output signal of the sample-and-hold circuit corresponding to the voltage is input, and an interface circuit. The interface circuit has a function of switching and controlling a first control period in which the sensor signal is input to the amplifier circuit and an output signal of the amplifier circuit is retained in the sample-and-hold circuit and a second control period in which a digital signal obtained by output of the voltage retained in the sample-and-hold circuit to the analog-to-digital converter circuit is output to the interface circuit. In the first control period, the analog-to-digital converter circuit is switched to stop output of the digital signal. The first control period is longer than the second control period. | 2021-12-02 |
20210376849 | ANALOGUE-TO-DIGITAL CONVERSION METHOD OF PIPELINED ANALOGUE-TO-DIGITAL CONVERTER AND PIPELINED ANALOGUE-TO-DIGITAL CONVERTER - The disclosure belongs to the field of integrated circuits, and is used for reducing an area overhead and a power consumption of a pipelined analog-to-digital converter. Each stage of the pipelined analog-to-digital converter according to the disclosure comprises an analogue-to-digital converter, a digital-to-analog converter, a subtractor and an amplifier. According to the disclosure, an amplification time of the pipelined ADC is used for extra quantization, and a number of bits of each ADC is reduced on the premise of not increasing a number of stages of the pipelined ADC, so that a scale of each circuit is greatly reduced, and the power consumption and the area overhead are reduced. | 2021-12-02 |
20210376850 | HIGH-SPEED SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER WITH IMPROVED MISMATCH TOLERANCE - An image sensor may contain an array of imaging pixels. Each pixel column outputs signals that are read out using a successive approximation register (SAR) analog-to-digital converter (ADC). The SAR ADC may include at least first and second input sampling capacitors, a comparator, a capacitive digital-to-analog converter (CDAC), and associated control circuitry. If desired, the SAR ADC may include a bank of more than two input sampling capacitors alternating between sampling and conversion. The first capacitor may be used to sample an input signal while conversion for the second capacitor is taking place. Prior to conversion, an input voltage of the comparator and an output voltage of the CDAC may be initialized. During conversion of the signal on the first capacitor, the first capacitor is embedded within the SAR ADC feedback loop to prevent charge sharing between the input sampling capacitor and the CDAC, thereby mitigating potential capacitor mismatch issues. | 2021-12-02 |
20210376851 | LOOP DELAY COMPENSATION IN A SIGMA-DELTA MODULATOR - A circuit includes a transconductance stage having first and second outputs. The circuit also includes a comparator having first and second inputs. The first input is coupled to the first output, and the second input is coupled to the second output. The comparator includes first through fifth transistors and a pair of cross-coupled transistors. The pair of cross-coupled transistors is coupled to the second current terminals of the first and second transistors. The second current terminal of the third transistor is coupled to the second current terminal of the first transistor, and the first current terminals of the first, second, and third transistors are coupled together. The second current terminals of the fourth and fifth transistors are coupled together and to the control input of the third transistor. | 2021-12-02 |
20210376852 | METHOD FOR COMPRESSING DIGITAL SIGNAL DATA AND SIGNAL COMPRESSOR MODULE - A method of compressing digital signal data obtained from a signal is described. The method includes: receiving digital signal data associated with a signal and/or generating digital signal data based on a signal; transforming the digital signal data into a transform domain, thereby generating transformed digital signal data; determining at least one characteristic parameter based on the transformed digital signal data by an artificial intelligence circuit; detecting and/or classifying at least one wanted signal portion based on the at least one characteristic parameter by the artificial intelligence circuit; and storing only a subset of the digital signal data that is associated with the at least one wanted signal portion. Further, a signal compressor circuit for compressing digital signal data obtained from a signal and a computer program are described. | 2021-12-02 |
20210376853 | MULTIVARIATE DATA COMPRESSION SYSTEM AND METHOD THEREOF - A smart sensing architecture ( | 2021-12-02 |
20210376854 | READ THRESHOLD CALIBRATION USING MULTIPLE DECODERS - A memory controller includes, in one embodiment, a memory interface, a plurality of decoders, and a controller circuit. The memory interface is configured to interface with a memory having a plurality of wordlines. Each decoder of the plurality of decoders is configured to determine a bit error rate (BER). The controller circuit configured to generate a plurality of bit-error-rate estimation scan (BES) hypotheses for one wordline of the plurality of wordlines, divide the plurality of BES hypotheses among the plurality of decoders, receive BER results from the plurality of decoders based on the plurality of BES hypotheses, and adjust one or more read locations of the one wordline based on the BER results from the plurality of decoders. | 2021-12-02 |
20210376855 | STORAGE ERROR CORRECTION USING CYCLIC-CODE BASED LDPC CODES - Techniques are described for joint encoding and decoding of information symbols. In one embodiment, a method for joint encoding includes, in part, obtaining a sequence of information symbols, generating a plurality of cyclic codewords each corresponding to a portion of the sequence of information symbols, jointly encoding the plurality of cyclic codewords to generate at least one combined codeword, and providing the combined codeword to a device. The at least one combined codeword may be generated through Galois Fourier Transform (GFT). In one embodiment, a method for joint decoding includes, in part, obtaining a sequence of encoded symbols, wherein the sequence of encoded symbols is generated through GFT, jointly decoding the sequence of encoded symbols using an iterative soft decision decoding algorithm to generate a decoded sequence, transforming the decoded sequence to generate a plurality of cyclic codewords, and decoding the plurality of cyclic codewords to generate a plurality of decoded information symbols. | 2021-12-02 |
20210376856 | APPARATUS AND METHOD FOR CHANNEL ENCODING/DECODING IN COMMUNICATION OR BROADCASTING SYSTEM - The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). An apparatus and a method for channel encoding and decoding in a communication or broadcasting system is provided. According to the present disclosure, the method for channel encoding in a communication or broadcasting system includes determining a block size Z, and performing encoding based on the block size and a parity check matrix corresponding to the block size, in which the block size is included in any one of the plurality of block size groups and the parity check matrix is different for each block size group. | 2021-12-02 |
20210376857 | HIGH-RATE LONG LDPC CODES - Methods and devices are disclosed for encoding source words and decoding codewords with LDPC matrices, comprising: receiving a 1×K source word row vector ū; and generating a 1×N codeword vector | 2021-12-02 |
20210376858 | METHOD FOR OPTIMIZING PROTOGRAPH-BASED LDPC CODE OVER UNDERWATER ACOUSTIC CHANNEL - The present disclosure provides a method for optimizing a protograph-based LDPC code over an underwater acoustic (UAW) channel. The traditional protograph-based LDPC code over an UAW channel does not consider performance in an error floor region. The method first determines parameters such as a protograph-based LDPC code length, a basic protograph, a target decoding threshold, a threshold adjustment factor, and an ACE check parameter. The protograph is optimized, and the method constructs a parity check matrix by using a UAW channel-based PEG/ACE hybrid algorithm, performs ACE check on the parity check matrix, and calculates a decoding threshold for the matrix passing the check. If the decoding threshold is within a range of an iterative decoding threshold, the parity check matrix is a final optimized matrix. Otherwise, the method continues to optimize the protograph until a parity check matrix passing the check is obtained. | 2021-12-02 |
20210376859 | LOW POWER ECC FOR EUFS - Systems and methods are described for low power error correction coding (ECC) for embedded universal flash storage (eUFS) are described. The systems and methods may include identifying a first element of an algebraic field; generating a plurality of lookup tables for multiplying the first element; multiplying the first element by a plurality of additional elements of the algebraic field, wherein the multiplication for each of the additional elements is performed using an element from each of the lookup tables; and encoding information according to an ECC scheme based on the multiplication. | 2021-12-02 |
20210376860 | ERROR CORRECTION CIRCUIT AND ERROR CORRECTION ENCODING METHOD - The present technology relates to an error correction circuit. According to the present technology, an error correction circuit performing error correction encoding on a plurality of messages to be stored in a memory device includes a first error correction encoder and a second error correction encoder. The first error correction encoder generates a plurality of codewords by performing first error correcting encoding on each of the plurality of messages. The second error correction encoder performs a second error correction encoding operation by performing an exclusive OR operation on symbols of an identical column layer within the codewords. The second error correction encoder determines a data unit as a target of the second error correction encoding operation based on a use period of the memory device. | 2021-12-02 |
20210376861 | METHOD, DEVICE AND COMPUTER READABLE STORAGE MEDIUM FOR INTERLEAVING DATA IN WIRELESS COMMUNICATION SYSTEM - Embodiments of the present disclosure relate to a method, device and computer readable medium for interleaving data in a wireless communication system. The method described herein comprises determining, based on a first number of bits in a bit sequence to be interleaved, a second number of rows in a triangular interleaver for interleaving the bits. The method also comprises dividing the bit subsequence into the second number of subsequences associated with the rows, a difference between numbers of bits in any two successive subsequences of the subsequences being a predetermined value. The method further comprises writing the second number of subsequences into the triangular interleaver in an order of the rows, the writing comprising, for a given row in the triangular interleaver, determining, based on an index of the given row, a writing order of bits having odd indexes and bits having even indexes in a subsequence associated with the given row. | 2021-12-02 |
20210376862 | METHOD FOR PERFORMING BELIEFS PROPAGATION, COMPUTER PROGRAM PRODUCT, NON-TRANSITORY INFORMATION STORAGE MEDIUM, AND POLAR CODE DECODER - A decoder performs: computing (S | 2021-12-02 |
20210376863 | METHOD OF DECODING POLAR CODES BASED ON BELIEF PROPAGATION - A method of decoding polar codes based on belief propagation includes conventional belief propagation to decode the polar codes first; when a number of iterations exceeds a predefined upper limit and a cyclic redundancy check fails, the method selects log-likelihood ratio vectors of a plurality of R or L messages from a plurality of log-likelihood ratio vectors generated in each of the iterations and generates another set of log-likelihood ratio vectors (referred to as candidate vector group) to be used as initial values of the R or L messages for a subsequent belief propagation to perform belief propagation decoding iterations and cyclic redundancy check again. Whenever a decoding result passes the cyclic redundancy check, the method exits; otherwise, the method iterates the above procedure until a maximum number of candidate vector groups has been reached. | 2021-12-02 |
20210376864 | MESH-NETWORK MULTIMODE SYSTEM WITH A SOFTWARE DEFINABLE RADIO - A communication system that may be used in room and building automation. A mesh network may be associated with a room of a building, or the like. Connectivity may be provided for devices with servers and a cloud in one mode. Connectivity may be provided for devices to mobile devices and a room-level information module in another mode. These modes of connectivities of various modes may be effected with a software definable radio or radios. Other modes of connectivity may be implemented. Examples of modes may incorporate Bluetooth low energy (BLE) and non-BLE formats. The modes may be multiplexed to operate one at a time and be switched back and forth as needed. | 2021-12-02 |
20210376865 | APPARATUSES AND METHODS FOR GENERATING AD-HOC NETWORKS TO EXTEND COVERAGE - Aspects of the subject disclosure may include, for example, connecting to network infrastructure to extend a scope of coverage associated with a service provided by the network infrastructure to a communication device, transmitting a first signal at a first frequency included within a frequency band that is detectable by the communication device, subsequent to the transmitting of the first signal, receiving a second signal from the communication device, and establishing, in accordance with the receiving of the second signal, a connection between the network infrastructure and the communication device via a processing system to facilitate the service. Other embodiments are disclosed. | 2021-12-02 |
20210376866 | ELECTRONIC DEVICE FOR CONTROLLING OUTPUT OF ANTENNA BY USING APC OF COMMUNICATION MODULE, AND METHOD FOR OPERATION OF ELECTRONIC DEVICE - In an electronic device and a method for operation of the electronic device according to various embodiments, the electronic device may comprise: a sensor module for sensing whether an external object approaches the electronic device; a communication module for cellular communication; a first antenna for the cellular communication; a short-range wireless communication module for short-range wireless communication; a second antenna for the short-range wireless communication; and a processor, wherein the processor is configured to: check by means of the sensor module whether the external object approaches so as to be within a specified range, while transmitting a cellular signal with specified power through the first antenna; output a specified signal through the second antenna at least on the basis of determining that the external object has approached so as to be within the specified range; acquire, by means of the second antenna, a signal returning after the specified signal is reflected by the external object; transmit a cellular signal having been adjusted to have lower power than the specified power, when the phase difference between the specified signal and the reflected signal falls within a specified range; and refrain from adjusting the specified power, when the phase difference falls outside the specified range. Various other embodiments are also possible. | 2021-12-02 |
20210376867 | RADIO-FREQUENCY MODULE AND COMMUNICATION DEVICE - A radio-frequency module includes a module substrate having a first principal surface and a second principal surface on opposite sides of the module substrate, a power amplifier capable of amplifying a transmission signal, a low-noise amplifier capable of amplifying a reception signal, a first switch connected to an input terminal of the power amplifier and disposed on the second principal surface, a second switch connected to an output terminal of the low-noise amplifier and disposed on the second principal surface, and a first ground terminal disposed in a region that is on the second principal surface and that is between the first switch and the second switch in plan view of the module substrate. | 2021-12-02 |
20210376868 | Radio Frequency Receiver for Carrier Aggregation - A Radio Frequency (RF) receiver is provided. The RF receiver is configured to simultaneously receive at least two radio frequency bands with a single receiver path. The RF receiver comprises a single local oscillator (LO), and the RF receiver is configured to filter a received signal using a complex filter having a variable center frequency. in accordance with another aspect, many RF receivers are combined to form an aggregate carrier receiver. | 2021-12-02 |
20210376869 | ELECTRONIC DEVICE AND COMMUNICATION DEVICE CALIBRATION METHOD OF ELECTRONIC DEVICE - An electronic device according to various embodiments of the present invention comprises: a housing; a plurality of antennas arranged on or inside the housing; a second communication circuit located inside the housing and electrically connected to the plurality of antennas; a first communication circuit, which is electrically connected to the second communication circuit, and generates a radio frequency (RF) signal or an intermediate frequency (IF) signal so as to transmit the RF or IF signal to the second communication circuit; a memory for storing at least one parameter set to correspond to the characteristic of the second communication circuit; and a control circuit electrically connected to the first communication circuit, wherein the control circuit can be set to transmit a control signal for controlling at least one amplifier included in the second communication circuit to the second communication circuit on the basis of the at least one parameter stored in the memory. Various embodiments of the present invention can be other embodiments. | 2021-12-02 |