49th week of 2009 patent applcation highlights part 73 |
Patent application number | Title | Published |
20090300379 | SENSOR SYSTEM - A sensor node for use in a sensor system includes a core component a sensor component and a power component. The core component includes processing and transmission/receiving components. Additionally, the core component includes interfaces for selectively connecting sensor and power components of any one of a plurality of types. In this manner, the core component enables the corresponding power and sensor components to be matched according to a particular application to generate the desired sensor node. | 2009-12-03 |
20090300380 | Remote power save service for imaging device - A remote power save service for an imaging device is provided. When the imaging device is awake, a power save controller on the imaging device causes the imaging device to enter a reduced power mode in response to a valid power save request received from a remote power save client. Entry into a reduced power mode by the imaging device is thereby achieved without waiting for timeout and without a need for action on the imaging device front panel. Moreover, where an imaging device supports multiple reduced power modes, a power save controller on the imaging device causes the imaging device to enter the particular one of the reduced power modes indicated in the power save request received from the remote power save client. | 2009-12-03 |
20090300381 | THIN CLIENT AND POWER MANAGEMENT METHOD THEREOF - Thin client-server architecture networks have a server and a thin client electrically connecting each. The server receives command signals from the thin client, produces respond signals respectively, and sends the respond signals back to the thin client. The server has a counter for counting a residual number, the number of the respond signals not being transmitted yet, and a power management application module. When the residual number turns zero, the power management application module sends a standby signal to a power management module of the thin client to selectively close or maintain the power of the thin client. | 2009-12-03 |
20090300382 | Controlling Power Consumption in a Data Processing Apparatus - A data processing apparatus, bus logic and method are provided for controlling power consumption within a data processing apparatus. The data processing apparatus has a plurality of logic elements, at least one of the logic elements being an initiator logic element for initiating transfers, and at least one of the logic elements being a recipient logic element for receiving transfers. A communication path is provided between an initiator logic element and a recipient logic element to enable payload data the subject of a transfer to be passed from the initiator logic element to the recipient logic element. The communication path has at least one buffer circuit provided therein for propagating at least the payload data along the communication path. Further, a power control circuit is associated with the at least one buffer circuit, which is responsive to a control signal indicating whether the payload data on the communication path is valid. If the control signal indicates that the payload data is not valid, the power control circuit causes the associated at least one buffer circuit to enter a power saving state. The control signal is derived from at least one pre-existing signal associated with the transfer. This has been found to provide a particularly efficient and flexible technique for reducing leakage current in buffer circuits within the data processing apparatus. | 2009-12-03 |
20090300383 | ENERGY CONSERVATION CONTROL DEVICE FOR A NETWORK SYSTEM - In order to accomplish the aforementioned task, there is characterized an electric power consumption control method, for a plurality of network connection devices connected with the network, which groups a plurality of network connection devices and, on the basis of the traffic level of the grouped network connection devices, controls the grouped network connection devices in group units. | 2009-12-03 |
20090300384 | Reducing Power Consumption While Performing Collective Operations On A Plurality Of Compute Nodes - Methods, apparatus, and products are disclosed for reducing power consumption while performing collective operations on a plurality of compute nodes that include: receiving, by each compute node, instructions to perform a type of collective operation; selecting, by each compute node from a plurality of collective operations for the collective operation type, a particular collective operation in dependence upon power consumption characteristics for each of the plurality of collective operations; and executing, by each compute node, the selected collective operation. | 2009-12-03 |
20090300385 | Reducing Power Consumption While Synchronizing A Plurality Of Compute Nodes During Execution Of A Parallel Application - Methods, apparatus, and products are disclosed for reducing power consumption while synchronizing a plurality of compute nodes during execution of a parallel application that include: beginning, by each compute node, performance of a blocking operation specified by the parallel application, each compute node beginning the blocking operation asynchronously with respect to the other compute nodes; reducing, for each compute node, power to one or more hardware components of that compute node in response to that compute node beginning the performance of the blocking operation; and restoring, for each compute node, the power to the hardware components having power reduced in response to all of the compute nodes beginning the performance of the blocking operation. | 2009-12-03 |
20090300386 | Reducing power consumption during execution of an application on a plurality of compute nodes - Methods, apparatus, and products are disclosed for reducing power consumption during execution of an application on a plurality of compute nodes that include: powering up, during compute node initialization, only a portion of computer memory of the compute node, including configuring an operating system for the compute node in the powered up portion of computer memory; receiving, by the operating system, an instruction to load an application for execution; allocating, by the operating system, additional portions of computer memory to the application for use during execution; powering up the additional portions of computer memory allocated for use by the application during execution; and loading, by the operating system, the application into the powered up additional portions of computer memory. | 2009-12-03 |
20090300387 | OPERATION METHOD OF STORAGE APPARATUS, STORAGE APPARATUS AND STORAGE SUBSYSTEM - Proposed is an operation method for seeking a power interruption operation target in which MTBF will become longest. When a target value regarding a power interruption time and a target value regarding a power interruption count per 24 hours is input from an administrator to a management computer, the management computer calculates the MTBF after one year and the annual power consumption for each of the input target values, and, as a power interruption operation target in which the MTBF will become longest in one year, a target value regarding a power interruption time and a target value regarding a power interruption count are respectively selected among multiple target values in which the MTBF will become longest based on each of the calculation results, and displayed on a screen of an output unit. | 2009-12-03 |
20090300388 | Distributed Clock Gating with Centralized State Machine Control - A method, computer program product, and system are provided for controlling a clock distribution network. For example, an embodiment of the method can include programming a predetermined delay time into a plurality of processing elements and controlling an activation and de-activation of these processing elements in a sequence based on the predetermined delay time. The processing elements are located in a system incorporating the clock distribution network, where the predetermined delay time can be programmed in a control register of a clock gate control circuit residing in the processing element. Further, when controlling the activation and de-activation of the processing elements, this activity can be controlled with a state machine based on the system's mode of operation. In controlling the activation and de-activation of the processing elements, the method described above can not only control the effects of di/dt in the system but also shut off clock signals in the clock distribution network when idle, thus reducing dynamic power consumption. | 2009-12-03 |
20090300389 | POWER SUPPLY HAVING MULTIPLE SETS OF OUTPUT POWER - A power supply having multiple sets of output power includes a primary power system to transform AC power to DC power when a computer host is power on and a standby power system linking and transforming the AC power to the DC power when the computer host is shut down. The power supply has a power output port located outside. The power output port has a primary power terminal dock linking to the primary power system and a standby power terminal dock linking to the standby power system. A transmission line is provided that has one end electrically connected to the power output port and other end forming at least a first coupling end and a second coupling end to output respectively primary power and standby power to a linking and corresponding computer equipment and an external electronic device. Thus the power supply can provide electric power to the computer equipment and external electronic device through the transmission line when the computer host is power on, and continuously provide the electric power to the external electronic device when the machine is shut down. It solves the problem of the conventional power supply that can provide power only when the machine is power on. | 2009-12-03 |
20090300390 | Imaging device with adaptive power saving behavior and method for use thereon - An imaging device with an adaptive power saving behavior conserves power by establishing reduced power mode entry and/or exit timeout values based on device usage statistics. Such an imaging device in some embodiments comprises at least one interface and a processor communicatively coupled with the interface, wherein under control of the processor the imaging device determines usage statistics for the imaging device based on jobs received on the interface and selects a power save entry timeout value for the imaging device based on the usage statistics. | 2009-12-03 |
20090300391 | Self-Powered Devices and Methods - A system includes a computing device that selectively communicates with a self-powered device. The self-powered device has several modes of operation, including a first low-power mode of operation and a second high-power mode of operation. The self-powered device is to communicate with the computing device when the self-powered device is in the second mode of operation. The self-powered device may conserve power by alternating between the first mode of operation and the second mode of operation such that the self-powered device is in the second mode of operation during pre-determined or adaptively-determined time intervals. A duty-cycle of the second mode of operation relative to the first mode of operation may be in accordance with a power budget for the self-powered device. | 2009-12-03 |
20090300392 | HIGH SPEED NETWORK INTERFACE WITH AUTOMATIC POWER MANAGEMENT WITH AUTO-NEGOTIATION - A computer system comprises host processor and a network interface, wherein the host processor includes resources supporting a full power mode, a lower power mode and a power down mode, as seen in standard system bus specifications such as PCI and InfiniBand. The network interface includes a medium interface unit coupled to network media supporting a least high speed protocol, such as a Gigabit Ethernet or high-speed InfiniBand, and a lower speed protocol, such as one of 10 Mb and 100 Mb Ethernet or a lower speed InfiniBand. Power management circuitry forces the medium interface unit to the lower speed protocol in response to an event signaling entry of the lower power mode. In the lower power mode, the network interface consumes less than the specified power when executing the lower speed protocol, and consumes greater than the specified power when executing the high speed protocol. Logic in the network interface operates in the lower power mode, and uses the lower speed protocol to detect a pattern in incoming packets. In response to the detection of said pattern, the logic issues a reset signal to the host processor. Thus, the network interface operates as a wake-up device in the lower power mode, using the lower speed protocol. | 2009-12-03 |
20090300393 | DYNAMIC POWER CONTROL FOR REDUCED VOLTAGE LEVEL OF GRAPHICS CONTROLLER COMPONENT OF MEMORY CONTROLLER BASED ON ITS DEGREE OF IDLENESS - A method includes detecting a trigger condition, and in response to detecting the trigger condition, reducing a voltage applied to a graphics controller component of a memory controller. The reduction in voltage may cause the voltage to be reduced below a voltage level required to maintain context information in the graphics controller component. | 2009-12-03 |
20090300394 | Reducing Power Consumption During Execution Of An Application On A Plurality Of Compute Nodes - Methods, apparatus, and products are disclosed for reducing power consumption during execution of an application on a plurality of compute nodes that include: executing, by each compute node, an application, the application including power consumption directives corresponding to one or more portions of the application; identifying, by each compute node, the power consumption directives included within the application during execution of the portions of the application corresponding to those identified power consumption directives; and reducing power, by each compute node, to one or more components of that compute node according to the identified power consumption directives during execution of the portions of the application corresponding to those identified power consumption directives. | 2009-12-03 |
20090300395 | POWER SAVING SYSTEM AND METHOD - A power saving system is provided, comprising a system chip, at least one controller and at least one corresponding switch. The system chip is coupled to the controller. The controller is coupled between the system chip and a connector. The switch is coupled between the controller and a power and is turned on or off according to a GPIO signal. When the switch is turned on, the controller is active. When there is no device through the connector and the controller coupled to the system chip, the controller is turned off for power saving. | 2009-12-03 |
20090300396 | INFORMATION PROCESSING APPARATUS - According to one embodiment, an information processing apparatus includes a power supply module, a connection bus, a processor connected to the connection bus and including a power supply control circuit module supplied with power from the power supply module and a arithmetic circuit module connected to the power supply control circuit module, a power supply control module configured to control supply of power from the power supply module to the arithmetic circuit module of the processor, and control module for sending, when the power supply control circuit module of the processor receives a predetermined notification, the predetermined notification to the power supply control module from the power supply control circuit module, and controlling, by the power supply control module which has received the predetermined notification, to stop power supply from the power supply module to the arithmetic circuit module. | 2009-12-03 |
20090300397 | METHOD, APPARATUS AND SYSTEM FOR REDUCING POWER CONSUMPTION INVOLVING DATA STORAGE DEVICES - The invention provides a method, apparatus and system for reducing power consumption involving data storage devices. One embodiment involves storing data in a first memory; in response to the first memory exceeding a first threshold, migrating the data from the first memory to a second memory; in response to the second memory exceeding a second threshold, then activating a third memory if the third memory is in active; and in response to the second memory exceeding a third threshold greater than the second threshold, migrating the data from the second memory to a third memory; wherein the second memory is sized and configured to store data targeted for the third memory to intelligently maintain a portion of the third memory in an inactive state. | 2009-12-03 |
20090300398 | CONTROL STRUCTURE FOR A POWER SUPPLY CLUSTER - A control structure for a power supply cluster which has a primary power supply and a secondary power supply that are independently linked to AC power and transform the AC power to DC power to supply electric power required by an electronic device in a computer equipment. A switch unit is provided to be linked to the primary power supply and the secondary power supply to get a start signal from the primary power supply and transfer to the secondary power supply. Electric power of the primary power supply also is transferred to the electronic device to present a first power supply status. A judgment unit also is provided to be linked to the primary power supply and the switch unit to get the start signal and defer sending a switch signal to the switch unit so that the electronic device can get electric power from the secondary power supply and present a second power supply status. Thereby the electronic device can continuously get the electric power after the primary power supply is started to improve the shortcoming of a conventional power supply cluster that is not started concurrently and results in poor system matching, and requires an additional transmission line even if concurrent start can be accomplished. | 2009-12-03 |
20090300399 | Profiling power consumption of a plurality of compute nodes while processing an application - Methods, apparatus, and products are disclosed for profiling power consumption of a plurality of compute nodes while processing an application that include: executing the application on the plurality of compute nodes; monitoring performance characteristics for components of the plurality of compute nodes during execution of the application; and recording, in a power profile for the application, power consumption during execution of the application in dependence upon the performance characteristics for components of the plurality of compute nodes. | 2009-12-03 |
20090300400 | PRIMARY SIDE CONTROL CIRCUIT AND METHOD FOR ULTRA-LOW IDLE POWER OPERATION - A method and circuit for reducing power consumption during idle mode to ultra-low levels, such as about 1/10 | 2009-12-03 |
20090300401 | PERFORMING A PERFORM TIMING FACILITY FUNCTION INSTRUCTION FOR SYCHRONIZING TOD CLOCKS - A system, method and computer program product for performing a Perform Timing Facility (PTFF) instruction for steering a Time of Day (TOD) clock of the computer system for synchronizing the TOD clock with TOD clocks of other computer systems. The computer system comprises a memory; and, a processor in communications with the computer memory. The processor is capable of performing a PTFF instruction comprising: obtaining a function code specified in a first general register, the function code for identifying any one of a query function or a control function to be performed; obtaining, from a second general register, a memory address of a parameter block; responsive to the function code specifying a query function, storing timing information of the computer system in the parameter block according to the specified query function; responsive to the function code specifying a control function, using timing information obtained from the parameter block to perform the specified control function; and setting a condition code value indicating an outcome of the specified function. | 2009-12-03 |
20090300402 | EMBEDDED SOFTWARE TESTING USING A SINGLE OUTPUT - An integrated circuit includes a processor and a circuit. The processor is configured to execute software. The software includes a plurality of software events. The circuit is configured to output a pulse on a single pin or pad of the integrated circuit in response to executing each software event. A pulse width of each pulse identifies a software event. | 2009-12-03 |
20090300403 | FINE GRAINED FAILURE DETECTION IN DISTRIBUTED COMPUTING - A client sends a request message to a process hosted by a remote server via a middleware service, wherein the request message specifies a procedure for the process to execute. The client waits a predetermined time period to receive a response message from the process. If no response message is received within the predetermined time period, the client probes the process to determine why no response message has been received, wherein said probing reveals thread level information about the process. | 2009-12-03 |
20090300404 | Managing Execution Stability Of An Application Carried Out Using A Plurality Of Pluggable Processing Components - Methods, apparatus, and products are disclosed for managing execution stability of an application carried out using a plurality of pluggable processing components. Managing execution stability of an application includes: receiving, by an application manager, component stability metrics for a particular pluggable processing component; determining, by the application manager, that the particular pluggable processing component is unstable in dependence upon the component stability metrics for the particular pluggable processing component; and notifying, by the application manager, a system administrator that the particular pluggable processing component is unstable. | 2009-12-03 |
20090300405 | BACKUP COORDINATOR FOR DISTRIBUTED TRANSACTIONS - A primary coordinator generates a prepare message for a two-phase commit distributed transaction, the prepare message including an address of a backup coordinator. The primary coordinator maintains a transaction log of the distributed transaction, wherein the transaction log is accessible to both the primary coordinator and the backup coordinator. The prepare message is sent to a plurality of participants. The primary coordinator fails over to the backup coordinator without interrupting the distributed transaction. | 2009-12-03 |
20090300406 | INFORMATION PROCESSING SYSTEM AND INFORMATION PROCESSING DEVICE - An information processing system includes a plurality of server devices including a main server device and at a standby server device, and a client device coupled to said server devices via a network. The client device includes a monitor unit to asynchronously monitor an operation state of each of the plurality of server devices, and a display control unit to acquire a content from the main server device and display the content in a display area on a screen once the monitor unit detects an operation state of the main server device is active, and to acquire from the standby server device a content for a process that the standby server device has taken over from the main server device and displays the content on the screen once the monitor unit detects an operation state of the standby server device is switched from standby state to active state. | 2009-12-03 |
20090300407 | SYSTEMS AND METHODS FOR LOAD BALANCING VIA A PLURALITY OF VIRTUAL SERVERS UPON FAILOVER USING METRICS FROM A BACKUP VIRTUAL SERVER - The present invention provides methods and systems for performing load balancing via a plurality of virtual servers upon a failover using metrics from a backup virtual server. The methods and systems described herein provide systems and methods for an appliance detecting that a first virtual server of a plurality of virtual servers having one or more backup virtual servers load balanced by an appliance is not available, identifying at least a first backup virtual server of a one or more backup virtual servers of the first virtual server is available, maintaining a status of the first virtual server as available in response to the identification, obtaining one or more metrics from the first backup virtual server of a one or more backup virtual servers, and determining the load across the plurality of virtual servers using the metrics obtained from the first backup virtual server associated with the first virtual server. | 2009-12-03 |
20090300408 | MEMORY PRESERVED CACHE FAILSAFE REBOOT MECHANISM - A method, system and computer program product for preserving data in a storage subsystem having dual cache and dual nonvolatile storage (NVS) through a failover from a failed cluster to a surviving cluster, the surviving cluster undergoing a rebooting process, is provided. A memory preserved indicator associated with a cache of the surviving cluster is detected. The memory preserved indicator designates marked tracks having an image in an NVS of the failed cluster to be preserved through the rebooting process. A counter in a data structure of the surviving cache is incremented. If a value of the counter exceeds a predetermined value, a cache memory is initialized, and the marked tracks are removed from the cache to prevent an instance of repetitive reboots caused by a corrupted structure in the cache memory. | 2009-12-03 |
20090300409 | METHOD FOR DATA DISASTER RECOVERY ASSESSMENT AND PLANNING - A method for assessing the risk and cost for data loss and disaster recovery (DR) plans includes providing an application having a graphical user interface (GUI) comprising first and second windows arranged adjacent to each other. The first window comprises a catalog of components used to generate data disaster recovery (DR) configurations and the second window displays the generated DR configurations. A first DR configuration is generated in the second window and components are added to the first DR configuration by dragging and dropping components from the catalog into appropriate locations of the second window. Metrics for the first DR configuration are calculated and reported in the second window. A second configuration is also similarly generated in the second window and the metrics results are graphically compared to each other. | 2009-12-03 |
20090300410 | SEMICONDUCTOR INTEGRATED CIRCUIT, CONTROL METHOD, AND INFORMATION PROCESSING APPARATUS - A semiconductor integrated circuit includes a circuit block connected to an arithmetic processing unit via a bus, a power supply noise data generator which is configured to generate a power supply noise data signal by converting power supply noise generated in power supply voltage of power supply operates the circuit block, an error detector which is configured to detect an error of data outputted from the circuit block to the bus, and a write controller which is configured to associate power supply noise information based on the power supply noise data signal with data on the bus and write the data in a storage unit, and to stop to write the data in response to the detection of the error by the error detector. | 2009-12-03 |
20090300411 | Implementing Redundant Memory Access Using Multiple Controllers for Memory System - A method and apparatus implement redundant memory access using multiple controllers for a memory system, and a design structure on which the subject circuit resides are provided. A first memory controller uses a first memory and a second memory controller uses the second memory as its respective primary address space, for storage and fetches. The second memory controller is also connected to the first memory. The first memory controller is also connected to the second memory. The first memory controller and the second memory controller, for example, are connected together by a processor communications bus. When one of the first memory controller or the second memory controller fails, then the other memory controller is notified. The other memory controller takes control of the memory for the failed controller, using the direct connection to that memory, and maintains coherence of both the first memory and second memory. | 2009-12-03 |
20090300412 | VIRTUAL DISK DRIVE SYSTEM AND METHOD - A disk drive system and method capable of dynamically allocating data is provided. The disk drive system may include a RAID subsystem having a pool of storage, for example a page pool of storage that maintains a free list of RAIDs, or a matrix of disk storage blocks that maintain a null list of RAIDs, and a disk manager having at least one disk storage system controller. The RAID subsystem and disk manager dynamically allocate data across the pool of storage and a plurality of disk drives based on RAID-to-disk mapping. The RAID subsystem and disk manager determine whether additional disk drives are required, and a notification is sent if the additional disk drives are required. Dynamic data allocation and data progression allow a user to acquire a disk drive later in time when it is needed. Dynamic data allocation also allows efficient data storage of snapshots/point-in-time copies of virtual volume pool of storage, instant data replay and data instant fusion for data backup, recovery etc., remote data storage, and data progression, etc. | 2009-12-03 |
20090300413 | DISABLING PORTIONS OF MEMORY WITH DEFECTS - An apparatus and methods are disclosed herein for identifying and avoiding attempts to access a defective portion of memory. Errors associated with portions of memory, such as a cache memory, are tracked over time enabling detection of both hard and erratic errors. Based on the number of errors tracked over time for a portion of memory, it is determined if the portion of memory is defective. In response to determining portion of memory is defective, the portion of memory is disabled. The portion of memory may be flushed and moved before being disable. Additionally, disabling the portion of memory may be conditioned upon determining if it is allowable to disable the portion of memory. | 2009-12-03 |
20090300414 | METHOD AND COMPUTER SYSTEM FOR MAKING A COMPUTER HAVE HIGH AVAILABILITY - A method and a computer system for making a computer achieve high availability. The method includes running a host virtual machine on a host virtual machine container; running a servant virtual machine on the servant virtual machine container; and synchronizing the host virtual machine and the servant virtual machine by using an I/O instruction. The system includes at least two computers including a host computer and a servant computer, each computer including a virtual machine container; a virtual machine running on the virtual machine container; and a communication channel making the virtual machine container execute a virtual machine synchronization operation. The virtual machine synchronization operation of the virtual machine container is triggered by the virtual machine executing I/O instructions. | 2009-12-03 |
20090300415 | Computer System and Method for Performing Integrity Detection on the Same - The present invention proposes a computer system and a method capable of performing integrity detection, comprising: a running mode unit which comprises an integrity detection boot variable to determine whether or not to initiate an integrity detection boot mode by judging said running mode unit; an EFI integrity detection unit ( | 2009-12-03 |
20090300416 | REMEDYING METHOD FOR TROUBLES IN VIRTUAL SERVER SYSTEM AND SYSTEM THEREOF - According to the invention, a managing server, using a snapshot-appended information table which stores management information for identifying snapshots of a virtual server, a setting change table which stores setting change information on the virtual server, and a policy table which stores policies to be met by the virtual server, acquires the setting change information from the setting change table, selects the setting change information items from the acquired setting change information matching policies stored in the policy table, acquires management information on the snapshots of the virtual server from the snapshot-appended information table, identifies a snapshot of the virtual server with reference to the acquired management information, changes the identified snapshot of the virtual server based on the selected setting change information items, and rolls back the virtual server according to the changed snapshot. | 2009-12-03 |
20090300417 | SYSTEM AND METHOD FOR ADVANCED CONDITION MONITORING OF AN ASSET SYSTEM - A method for advanced condition monitoring of an asset system includes using a plurality of auto-associative neural networks to determine estimates of actual values sensed by at least one sensor in at least one of the plurality of operating regimes; determining a residual between the estimated sensed values and the actual values sensed by the at least one sensor from each of the plurality of auto-associative neural networks; and combining the residuals by using a fuzzy supervisory model blender; performing a fault diagnostic on the combined residuals; and determining a change of the operation of the asset system by analysis of the combined residuals. An alert is provided if necessary. A smart sensor system includes an on-board processing unit for performing the method of the invention. | 2009-12-03 |
20090300418 | Method for Error Tree Analysis - A technical system is broken down into a plurality of subsystems, each of which is allocated a time-dependent distribution function which describes the probability of failure of the respective subsystem. The distribution functions are linked to one another to form a time-dependent system distribution function which describes the probability of failure of the technical system. | 2009-12-03 |
20090300419 | REALTIME TEST RESULT PROMULGATION FROM NETWORK COMPONENT TEST DEVICE - The technology disclosed relates to real-time collection and flexible reporting of test data. In particular, it is useful when collecting packet counts during tests of network devices that simulate thousands or even millions of data sessions conducted through a device under test (“DUT”). | 2009-12-03 |
20090300420 | Method for Testing at Least One Arithmetic Unit Installed in a Control Unit - A method for testing at least two arithmetic units installed in a control unit includes: loading of first test data for testing a first arithmetic unit; saving the loaded first test data in a second memory unit of a second arithmetic unit; switching the first arithmetic unit to a test mode, in which a first scan chain of the first arithmetic unit is accessible; reading the first test data from the second memory unit; shifting the first test data which have been read through the first scan chain of the first arithmetic unit switched to the test mode for providing test result data for the first arithmetic unit; checking the provided test result data for plausibility for providing a test result for the first arithmetic unit. | 2009-12-03 |
20090300421 | METHOD AND APPARATUS FOR CHANGING BIOS PARAMETER VIA AN EXCHANGE FILE - An apparatus for changing BIOS parameters via an exchange file, including a control unit, a microprocessor, a first memory, a second memory, a third memory and a keyboard. The method includes the steps of saving N parameter banks of BIOS in the third memory, forming the exchange file and performing a operation process via parameter banks, which including the steps of forming, writing, reading, revising and opening the exchange file, selecting one of parameter banks and performing corresponding operations according to the selected parameter bank. | 2009-12-03 |
20090300422 | Analysis method and system using virtual sensors - A method for analyzing operations of a plurality of machines communicating with a server computer. The method may include establishing a plurality of virtual sensors corresponding to a plurality of engine systems of the respective plurality of machines. Each virtual sensor may be indicative of interrelationships between a plurality of input parameters and a plurality of output parameters of an engine system. The method may also include determining an operational accuracy of each virtual sensor, and calculating a score of each machine based on the operational accuracy of a virtual sensor of the machine. Further, the method may include ranking the plurality of machines based upon the score of each machine, scheduling maintenance for a certain number of machines based on the ranking of the plurality of machines, and providing automatic notification of the scheduled maintenance. | 2009-12-03 |
20090300423 | SYSTEMS AND METHODS FOR SOFTWARE TEST MANAGEMENT IN CLOUD-BASED NETWORK - Embodiments relate to systems and methods for testing and evaluating software in the network cloud. A developer or other operator may wish to debug, modify, or update a set of test software based on testing of that software. The developer can instantiate a set of virtual servers or other test beds in the cloud, and install the subject software to the virtual test beds. A test management module can monitor the execution of the set of test software on the set of virtual test beds, to detect execution faults, measure processing performance, stress-test the software with predetermined data inputs, and manage other aspects of software life cycle development. The test management module can provide or access a set of application programming interfaces to a set of software tools external to the cloud, so that the set of test software can be tested and optimized using external programming development tools. | 2009-12-03 |
20090300424 | FAULT DETECTING METHOD AND INFORMATION PROCESSING APPARATUS - An information processing apparatus including a storage area separated into a user space and a kernel space executes, generating a core file of a process existing in the user space, retaining the process with the core file which starts being generated in the user space, and notifying a monitor unit of an identification number of the process with the core file which starts being generated, wherein the monitor unit detects a fault in the process by receiving the identification number allocated to the process. | 2009-12-03 |
20090300425 | Resilience to Memory Errors with Firmware Assistance - Embodiments of the invention provide an interrupt handler configured to distinguish between critical and non-critical unrecoverable memory errors, yielding different actions for each. Doing so may allow a system to recover from certain memory errors without having to terminate a running process. In addition, when an operating system critical task experiences an unrecoverable error, such a task may be acting on behalf of a non-critical process (e.g., when swapping out a virtual memory page). When this occurs, an interrupt handler may respond to a memory error with the same response that would result had the process itself performed the memory operation. Further, firmware may be configured to perform diagnostics to identify potential memory errors and alert the operating system before a memory region state change occurs, such that the memory error would become critical. | 2009-12-03 |
20090300426 | TESTING A VIRTUALISED STORAGE SYSTEM IN RESPONSE TO DISK EXERCISING COMMANDS - Provided are a method, apparatus, and computer program product for testing a virtualised storage system. Data defining one or more configuration features of the virtualised storage system is received. Also received is a set of one or more predetermined rules defining interpretation of the disk exercising commands, the interpretation being dependent on one or more of the configuration features. A first disk exercising command is received. The first disk exercising command is interpreted in accordance with one of the predetermined rules to produce a second disk exercising command. The second disk exercising command is sent to the virtualised storage system. | 2009-12-03 |
20090300427 | METHOD OF LOGGING STACK TRACE INFORMATION - A computer system comprises a memory configured to store software instructions; a set of registers; and a processing unit configured to temporarily store passed parameters in the set of registers during execution of the software instructions, the processing unit further configured to skip save and restore operations when executing a logging function to log the passed parameters. | 2009-12-03 |
20090300428 | METHOD OF COLLECTING INFORMATION IN SYSTEM NETWORK - To quickly establish an inferring result when a problem is detected in an operation management system equipped with a rule-based inference processing function, there is provided a method of collecting information for managing a computer system equipped with a plurality of devices. The computer system holds rule for associating a plurality of events with a conclusion output when all of the plurality of events have been detected. The method includes: executing, at a first interval, polling to obtain information indicating whether each of the plurality of events has been detected; judging whether the plurality of events have been detected; and executing, upon judgment that at least one of the plurality of events has been detected and none of the remaining events have been detected, before execution of next polling at the first interval, polling to obtain information indicating whether at least one of the undetected remaining events has been detected. | 2009-12-03 |
20090300429 | SYSTEMS AND METHODS FOR DIAGNOSING FAULTS IN ELECTRONIC SYSTEMS - Apparatus, systems, and methods for identifying a fault in an electronic system are provided. One apparatus includes memory storing a model of the electronic system, a processor, and a fault module. The processor is configured to pass system inputs through the model to generate corresponding simulated outputs, and the fault module is configured to determine the fault based on a comparison of the system outputs and the simulated outputs. A system includes an electronic system including multiple components generating system outputs based on system inputs and the apparatus for identifying a fault in the electronic system discussed above. One method includes generating a model of the electronic system, passing one or more inputs to the electronic system through the model to generate corresponding simulated outputs, and determining the fault based on a comparison of the one or more simulated outputs and one or more electronic system outputs. | 2009-12-03 |
20090300430 | HISTORY-BASED PRIORITIZING OF SUSPECTED COMPONENTS - A method for servicing a computerized system includes detecting a failure of a given type in the computerized system, and generating a list of corrective actions in response to the failure, using an automated maintenance program. A record of one or more previous failures of the given type in the computerized system is retrieved, indicating at least one previous corrective action taken in response to the previous failures. The method prioritizes the list of corrective actions responsively to the record, using the automated maintenance program, so as to adjust a priority of the at least one previous corrective action in the list. The prioritized list from the automated maintenance program is provided to a repair function for use in servicing the computerized system. | 2009-12-03 |
20090300431 | METHOD AND SYSTEM FOR CONTROLLING MOVEMENT OF USER SETTING INFORMATION REGISTERED IN SERVER - A method and system to utilize an Extensible Markup Language (XML) Configuration Access Protocol (XCAP) in which a MOVE command is newly defined, and a user setting information movement request is processed in one operation, are disclosed. A method of controlling movement of particular user setting information registered in a server includes, at a client, transmitting a movement request message including a movement command to set user information, and at the server, processing movement of the particular user setting information as commanded by the movement request message and transmitting a response message. | 2009-12-03 |
20090300432 | INFORMATION PROCESSING APPARATUS AND INFORMATION NOTIFICATION METHOD THEREFOR, AND CONTROL PROGRAM - To enable the host server side to be aware of the recovery of an error when the error is recovered by the user's power off/on operation, the most recent state regarding occurrences of errors at printer | 2009-12-03 |
20090300433 | INFORMATION PROCESSING APPARATUS, MEDIUM RECORDING ERROR NOTIFICATION PROGRAM, AND ERROR NOTIFICATION METHOD - There is provided an information processing apparatus that includes a CPU board | 2009-12-03 |
20090300434 | Clearing Interrupts Raised While Performing Operating System Critical Tasks - Embodiments of the invention provide an interrupt handler configured to distinguish between critical and non-critical unrecoverable memory errors, yielding different actions for each. Doing so may allow a system to recover from certain memory errors without having to terminate a running process. In addition, when an operating system critical task experiences an unrecoverable error, such a task may be acting on behalf of a non-critical process (e.g., when swapping out a virtual memory page). When this occurs, an interrupt handler may respond to a memory error with the same response that would result had the process itself performed the memory operation. Further, firmware may be configured to perform diagnostics to identify potential memory errors and alert the operating system before a memory region state change occurs, such that the memory error would become critical. | 2009-12-03 |
20090300435 | Method and Device for Monitoring a Process Execution - A method for monitoring a process execution of a plurality of sequentially executed processes starts one of a plurality of timers in cyclic permutation when one of the processes is started, and outputs a first error signal when a period of time recorded by one of the timers exceeds a predefined maximum period of time. | 2009-12-03 |
20090300436 | SYNCHRONIZING DEVICE ERROR INFORMATION AMONG NODES - Provided are a method, system, and article of manufacture for synchronizing device error information among nodes. A first node performs an action with respect to a first node error counter for a device in communication with the first node and a second node. The first node transmits a message to the second node indicating the device and the action performed with respect to the first node error counter for the device. The second node performs the action indicated in the message with respect to a second node error counter for the device indicated in the message, wherein the second node error counter corresponds to the first node error counter for the device. | 2009-12-03 |
20090300437 | DATA REPOSITORY AND ANALYSIS SYSTEM FOR REMOTELY MANAGED TEST AND MONITORING DEVICES - A data repository and analysis system manages test and monitoring end devices through hub/routing functionality implemented on custom or generic platform devices and wired and/or wireless communication with a backbone infrastructure. Hub/routing devices manage test and monitoring end devices locally collecting data, configuring the end devices, etc. Data collected by the hub/routing devices is gathered at the data repository and analysis system, which also manages the hub/routing devices by sending them instructions, monitoring their operations, updating operational parameters, and the like. In addition to analyzing gathered data and providing reports to designated third parties, the data repository and analysis system may monitor alert conditions based on gathered data and provide alerts to designated recipients if such a condition is detected. | 2009-12-03 |
20090300438 | Connection monitoring method, connection monitoring apparatus, and connection monitoring system - A connection monitoring apparatus determines whether the connection monitoring apparatus is communicatively connected to the customer apparatus at a regular connection time. When the connection monitoring apparatus is not communicatively connected to the customer apparatus at the regular connection time and the present time falls within the support contract time of a customer, the connection monitoring apparatus issues a connection fault notification. When the connection monitoring apparatus is not communicatively connected to the customer apparatus at the regular connection time and the present time does not fall within the support contract time of the customer, the connection monitoring apparatus suppresses the connection fault notification from being issued and issues the connection fault notification at the next support contract time of the customer. | 2009-12-03 |
20090300439 | Method and Apparatus for Testing Write-Only Registers - There is disclosed a test circuit for testing an integrated circuit containing at least one write-only register and providing at least one output signal through at least one output pin. The test circuit may include a test mode decoder circuit to enable a test mode and a data selector circuit to select at least a portion of data stored in the at least one write-only register as test data. The test data may be output from the integrated circuit through the at least one output pin. | 2009-12-03 |
20090300440 | DATA CONTROLLING IN THE MBIST CHAIN ARCHITECTURE - A memory collar including a first circuit and a second circuit. The first circuit may be configured to generate one or more data sequences in response to one or more test commands. The one or more data sequences may be presented to a memory during a test mode. The second circuit may be configured to pre-process one or more outputs generated by the memory in response to the one or more data sequences. | 2009-12-03 |
20090300441 | ADDRESS CONTROLLING IN THE MBIST CHAIN ARCHITECTURE - A memory collar includes a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a first control signal, a second control signal and a third control signal in response to one or more test commands. The second circuit may be configured to generate a fourth control signal in response to said third control signal and the fourth control signal. The third circuit may be configured to generate one or more address sequences. The one or more address sequences are presented to a memory during a test mode. | 2009-12-03 |
20090300442 | Field mounting-type test apparatus and method for testing memory component or module in actual PC environment - Provided are a field mounting-type test apparatus and method, which can enhance competitiveness of a product by simulating various test conditions including a mounting environment so as to improve quality reliability of a memory device and by minimizing overall loss due to change in a mounting environment so as to reduce testing time and cost. In accordance with example embodiments, the field mounting-type test apparatus may include a mass storage device configured to store logic data simulating a mounting environment of a device under test (DUT) and a tester main frame configured to test the DUT by using the logic data. | 2009-12-03 |
20090300443 | Test apparatus, test method, and integrated circuit - A test apparatus includes an up counter, a down counter, a selector that selects either an up counter output from the up counter or a down counter output from the down counter, an inversion circuit that inverts either the counter output selected by the selector or the counter output nonselected by the selector, and a comparison circuit that compares the counter output inverted by the inversion circuit and the other counter output. | 2009-12-03 |
20090300444 | METHOD AND APPARATUS FOR TESTING HIGH CAPACITY/HIGH BANDWIDTH MEMORY DEVICES - A plurality of stacked memory device die and a logic circuit are connected to each other through a plurality of conductors. The stacked memory device die are arranged in a plurality of vaults. The logic circuit die serves as a memory interface device to a memory access device, such as a processor. The logic circuit die includes a plurality of link interfaces and downstream targets for transmitting received data to the vaults. The logic circuit die includes a packet builder and broadcaster configured to receive command, address and data signals over separate interfaces from a conventional tester, format the signals into a packet and broadcast the signals to a plurality of vaults. | 2009-12-03 |
20090300445 | METHOD AND SYSTEM FOR ALTERNATING BETWEEN PROGRAMS FOR EXECUTION BY CELLS OF AN INTEGRATED CIRCUIT - A method and device for data processing in an integrated circuit having cells, the cells adapted for executing programs. A first program is run. In response to a waiting condition during which no program execution is able to take place, saving data from the cells to a memory. A second program, e.g., a test program, is run after the data is saved. The saved data is then reloaded into the cells after running the second program. | 2009-12-03 |
20090300446 | Selective Per-Cycle Masking Of Scan Chains For System Level Test - Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. The presence of the specialized scan chain selector increases the efficiency in masking X states. Also disclosed are: (1) an architecture of a selector that works with multiple scan chains and time compactors, (2) a method for determining and encoding per cycle scan chain selection masks used subsequently to suppress X states, and (3) a method to handle an over-masking phenomenon. | 2009-12-03 |
20090300447 | SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS - Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan frame input shift register contain a test stimulus data section and a test command section. Scan frames output from the scan frame output shift register contain a test response data section and, optionally, a section for outputting other data. The command section of the input scan frame controls the test architecture to execute a desired test operation. | 2009-12-03 |
20090300448 | SCAN FLIP-FLOP DEVICE - A scan flip-flop device has a scan flip-flop, a Nch insulated gate field effect transistor and a Pch insulated gate field effect transistor. The Nch insulated gate field effect transistor is located on an output side the scan flip-flop. The Nch insulated gate field effect transistor turns off and dose not output a signal when a test enable signal is in a disable mode. The Pch insulated gate field effect transistor is located between a higher voltage source and an output side of the Nch insulated gate field effect transistor. The Pch insulated gate field effect transistor turns on when a test enable signal is in a disable mode. The Pch insulated gate field effect transistor sets a SO port at a high level voltage. | 2009-12-03 |
20090300449 | Method and System for Message Retransmission and Intersystem Message Delivery - The present invention discloses a method and a system for resending messages with a minimized number of retries and maximized timeliness of delivering the message to the receiving party. The method sets a retry period for a message that needs to be resent, determines a retry time according to the retry period, and sends the message after the retry time is reached. The retry period increases as the number of retries increases. The method and the system can ensure reliable delivery of notification messages and support many transmission protocols between different systems, does not require the receiving party to implement complicated interaction protocols to reliably receive a notification message, and is suitable for widespread use in the Internet. Moreover, the disclosure supports multiple transaction processing, can be used as a common business transaction application platform, and allows flexible expansion of multiple transactions and multiple protocols. | 2009-12-03 |
20090300450 | PACKET RETRANSMISSION AND MEMORY SHARING - Through the identification of different packet-types, packets can be handled based on an assigned packet handling identifier. This identifier can, for example, enable forwarding of latency-sensitive packets without delay and allow error-sensitive packets to be stored for possible retransmission. In another embodiment, and optionally in conjunction with retransmission protocols including a packet handling identifier, a memory used for retransmission of packets can be shared with other transceiver functionality such as, coding, decoding, interleaving, deinterleaving, error correction, and the like. | 2009-12-03 |
20090300451 | Frame transferring apparatus and frame transferring system - A frame transferring apparatus includes a check-frame storage unit that has temporarily stored therein a reception check frame; a check-frame transmitting unit that transmits a transmission check frame to another frame transferring apparatus; a check-frame discarding unit that, when a storage space for storing the reception check frame is left in the check-frame storage unit, stores the reception check frame in the check-frame storage unit and, when no storage space is left, discards the reception check frame; a transferring-apparatus-information obtaining unit that obtains frame-transferring-apparatus information; a checking unit that checks a non-arrival of a frame based on the frame-transferring-apparatus information; a retransmission requesting unit that, when the reception check frame is discarded, requests the frame transferring apparatus of a transmission source of the discarded check frame to retransmit a check frame; and a check-frame retransmitting unit that, when accepting a request for retransmitting the transmission check, retransmits the check frame. | 2009-12-03 |
20090300452 | ERROR IDENTIFYING METHOD, DATA PROCESSING DEVICE, AND SEMICONDUCTOR DEVICE - A data processing device which performs a data transmission between semiconductor devices using a plurality of signal lines. In the data processing device, when there occurs an error in a data transmission from a transmitting device to a receiving device using a plurality of signal lines, data in which the error has occurred is stored. The stored data is compared bit by bit with non-erroneous data, thereby designating a bit in which error has occurred in the stored data. | 2009-12-03 |
20090300453 | TRANSMITTING APPARATUS AND WIRELESS COMMUNICATION METHOD - A transmitting apparatus and a wireless communication method are provided. The transmitting apparatus is capable of transmitting, together with transmission data, retransmission data in response to an HARQ from a receiving apparatus, according to an MCS determined based on a request from the receiving apparatus and includes a storage portion which stores information indicating a transition of an FER with respect to a communication quality for each MCS in both cases in which an HARQ response is enabled and disabled, an HARQ switching portion which switches whether to enable or disable the HARQ response in accordance with a QoS class of data to be transmitted, and an MCS switching portion which switches an MCS in accordance with the switching of whether to enable or disable the HARQ response, while referring to the information stored in the storage portion. | 2009-12-03 |
20090300454 | TRANSMISSION APPARATUS, ACCESS POINT AND SYMBOL TRANSMISSION METHOD - In a transmission apparatus in a MIMO-OFDM communication system employing a cyclic diversity, a cyclic delay controller sets plural delay magnitudes different for respective antennas, in cyclic delayers for each predetermined timing. The cyclic delayers receive symbols subjected to orthogonal frequency division multiplexing, for the respective ones of plural allotted antennas. Besides, the cyclic delayers bestow cyclic delays on the individual symbols of the respective antennas in accordance with plural set delay magnitudes. The symbols cyclically delayed are outputted from the antennas. As the delay magnitudes, a first delay magnitude at a first transmission timing and a second delay magnitude at a second transmission timing are different for one antenna, and the delay magnitudes differ in the respective antennas for one transmission timing. Thus, in a MIMO-OFDM transmission scheme, a frequency diversity and a time diversity are enhanced to heighten a retransmission efficiency in a data retransmission mode. | 2009-12-03 |
20090300455 | DATA TRANSMITTING DEVICE, CONTROL METHOD THEREFOR, AND PROGRAM - A data transmitting device determines a coding rate used to perform error correction coding processing for data transmitted to a data receiving device based on information relating to the function of concealing an error occurring in data transmitted from the data transmitting device, the function being provided in the data receiving device. Then, the data transmitting device performs the error correction coding processing for data transmitted to the data receiving device based on the determined coding rate, and transmits the data subjected to the error correction coding processing to the data receiving device. | 2009-12-03 |
20090300456 | HARQ PROCESS UTILIZATION IN MULTIPLE CARRIER WIRELESS COMMUNICATIONS - Methods and apparatus utilize hybrid automatic repeat request (HARQ) transmissions and retransmissions that are usable on multiple carriers, i.e. joint HARQ processes. For example, a downlink (DL) shared channel transmission of a joint HARQ process is received on one of the carriers. A first part of an identity of the joint HARQ process is determined by using HARQ process identity data received on a shared control channel. A second part of the joint HARQ process identity is determined using additional information. The joint HARQ process identity is then determined by combining the first part and the second part. A WTRU is provided that is configured to receive the DL shared channel and to make the aforementioned determinations. A variety of other methods and apparatus configurations are disclosed for utilizing joint HARQ processes, in particular in the context of DC-HSDPA. | 2009-12-03 |
20090300457 | Method and Apparatus for Improving HARQ Uplink Transmission - The present invention provides a method for improving Hybrid Automatic Repeat Request (HARQ) uplink transmission in a user equipment (UE) of a wireless communication system. The method includes the HARQ entity of the UE instructing an HARQ process to perform transmission or retransmission of a transport block according to an uplink (UL) grant allocated to the UE, and flushing all HARQ buffers for uplink transmission in the HARQ entity when a Time Alignment Timer of the UE expires. | 2009-12-03 |
20090300458 | REVERSE LINK AUTOMATIC REPEAT REQUEST - An Access Network (AN) can send an acknowledge message (ACK) to an Access Terminal (AT) to indicate that the AN has successfully decoded the data received in the first set of slots of the first data packet. The AN can send a negative acknowledge message (NAK) to the AT to indicate that the AN has not successfully decoded the data received in the first set of slots of a first data packet. Based upon receipt of the NAK, the AT can resend the data by sending a second set of slots of the first data packet containing redundant data. Based upon receipt of the ACK, the AT can send a first set of slots of another packet. The AT can gate off for a predetermined period of time after sending the first set of slots of a first packet and before sending a next set of slots. | 2009-12-03 |
20090300459 | DATA TRANSMISSION APPARATUS AND DATA RECEPTION APPARATUS - A transmission apparatus receives information used to identify data unsuccessfully received by a reception apparatus. Then, the transmission apparatus determines whether the data corresponding to the received identification information should be retransmitted based on whether the reception apparatus has a function of displaying the display area of the data corresponding to the identification information by using data having the display area corresponding to the data corresponding to the identification information. | 2009-12-03 |
20090300460 | Optical transmitter and receiver and optical transmission and reception system - An optical transmitter and receiver has stored in advance therein FEC techniques and applicable conditions for applying the FEC techniques to a counterpart optical transmitter and receiver. The optical transmitter and receiver measures a state of receiving data transmitted from the counterpart optical transmitter and receiver, determines an applicable condition satisfying the measured data reception state from among the stored applicable conditions, and selects a FEC technique stored in association with the applicable condition determined as satisfying. The optical transmitter and receiver then notifies the counterpart optical transmitter and receiver of the selected FEC technique. | 2009-12-03 |
20090300461 | DEVICE, METHOD AND COMPUTER PROGRAM PRODUCT FOR COMMUNICATION - A transmitter may include an encoder configured to encode a data bit vector to provide an codeword that includes a first codeword portion and a second codeword portion; wherein the first codeword portion is decodable by a first parity check process to yield the data bit vector; wherein the codeword is decodable by a second parity check process to yield the data bit vector; and a communication module, for transmitting the codeword. | 2009-12-03 |
20090300462 | Coding Apparatus, Coding Method and Coding Program - Disclosed herein is an encoding apparatus which combines an RLL code word and an error correction code word, with an interleaving technique when encoding, including: an error correction encoding section; an interleaving section; and an RLL encoding section, wherein, if an address i (i is an integer satisfying relations 0≦i2009-12-03 | |
20090300463 | SYSTEM AND METHOD FOR DETERMINING PARITY BIT SOFT INFORMATION AT A TURBO DECODER OUTPUT - A decoding circuit, is provided, comprising: a turbo decoder configured to receive a input systematic bit soft information values and input parity bit information values, and to generate output systematic bit soft information values and hard decoded bits according to a turbo decoding operation; and a parity bit soft information generation circuit configured to receive the input systematic bit soft information values, the input parity bit soft information values, and the output systematic bit soft information values; to determine initial forward metrics, initial backward metrics, and branch metrics as a function of the input parity bit soft information values and the output systematic bit soft information values; to determine output parity bit soft information values based on the branch metrics, the initial forward metrics, and the initial backward metrics; and to provide the output parity bit soft information values as a signal output. | 2009-12-03 |
20090300464 | RADIO COMMUNICATION SYSTEM - A base station creates a dummy pattern added with an error correction code, during occurring of a control channel not allocated for transmission of control information, transmits the dummy pattern instead of control information at a power level lower than a normal power level. A mobile station decodes control information transmitted through the control channel, examines whether or not a value specified by the decoded control information is within a suitable range, and performs error detection of the decoded control information. The mobile station stops decoding of data transmitted through a data channel, upon judging that the value is not within the suitable range or detecting an error in the error detection. | 2009-12-03 |
20090300465 | STATISTICAL TRACKING FOR FLASH MEMORY - A system includes a read module, a statistical data generating module, and a storing module. The read module reads charge levels of nonvolatile memory cells and generates read signals. The statistical data generating module generates statistical data based on the read signals. The storing module stores the statistical data. The read module generates the read signals based on the charge levels of the nonvolatile memory cells and the statistical data. | 2009-12-03 |
20090300466 | ERROR CORRECTION METHOD AND ERROR CORRECTION CIRCUIT - In an error correction method, an error correction of data can be completed readily in a short period of time. In this method, actual data are written together with additional data to a magnetic disk having sectors. The actual data have a first length. The additional data are produced from source data. The source data are formed by predetermined data or the actual data. The sectors of the magnetic disk have a read/write unit of a second length that is longer than the first length. One of the sectors to which actual data to be read have been written is specified, and actual data and additional data are read from the specified sector. The read additional data are verified with the source data. A first error correction is performed on the read additional data based on a result of the verification. | 2009-12-03 |
20090300467 | Using a Phase Change Memory as a High Volume Memory - A phase change memory may be utilized in place of more conventional, higher volume memories such as static random access memory, flash memory, or dynamic random access memory. To account for the fact that the phase change memory is not yet a high volume technology, an error correcting code may be incorporated. The error correcting code may be utilized in ways which do not severely negatively impact read access times, in some embodiments. | 2009-12-03 |
20090300468 | FORWARD ERROR CORRECTION - A receiver is arranged to start receiving a data frame | 2009-12-03 |
20090300469 | System and method for inter-packet channel coding and decoding - A system and method for inter-packet channel encoding/decoding for recovering lost packets, while minimizing network latency and delay. The novel inter-packet channel encoding/decoding scheme described herein operates on a running-basis. This running-basis scheme advantageously allows for a large number of packet losses to be corrected at a receiving node. | 2009-12-03 |
20090300470 | MEMORY ARCHITECTURE FOR HIGH THROUGHPUT RS DECODING FOR MEDIAFLO RECEIVERS - A system and method for increasing the throughput of a RS decoder in MediaFLO™ receivers. A MAC de-interleaver RAM architecture allowing operation of parallel RS decoders comprises of four equal portioned memory banks, a codeword buffer for data correction, and a higher bit width RAM. The method of increasing throughput of RS decoder by minimizing RAM access and clock frequency includes increasing the bit width of the de-interleaver RAM, using parallel RS decoder cores for decoding received data, partitioning a 4-bank RAM and ECB allocation scheme, and correcting the data using intermediate buffers. The architecture enables on-chip implementation of the MAC de-interleaver RAM and RS decoders with reduced power consumption and provide higher RS decoder throughput. | 2009-12-03 |
20090300471 | Processing Publishing Rules by Routing Documents Based on Document Conceptual Understanding - Embodiments of the invention may be used to improve enforcement and compliance with publishing rules in an automated and provable manner. Prior to publication, documents may be processed using publishing rules (workflows) based on conceptual analysis of document content. Additionally, embodiments of the invention include a content creation system configured to provide prompt feedback on content coverage. Such a system enables the creator of information to better understand what approval requirements apply to content they create and intend to publish, as the content is being created. | 2009-12-03 |
20090300472 | METHOD OF AUTHORING, DEPLOYING AND USING INTERACTIVE, DATA-DRIVEN TWO OR MORE DIMENSIONAL CONTENT - A method whereby dynamic, interactive, two or more dimensional media can be assembled and delivered where the need for pre-packaged binary content files and pre-compiled content is eliminated by using a markup language, a standard URI to identify local and/or remote media resources within a markup text, a standard protocol to retrieve the resource, a parser to load resources from the native format and a markup language to define behavior and where dynamic, interactive, n-dimensional media is achieved by using a markup language, connecting or embedding content into a local or remote data source, dragging-and-dropping markup text into a content provider application, updating content using a form, establishing a two-way connection between content and one or more data sources such that changing to the data source(s) and seeing the results propagate to the scene changing the content and seeing the results propagate to the data source(s) and using a markup language to issue commands, configure interaction, and create behavior. | 2009-12-03 |
20090300473 | Systems and Methods for Displaying Albums Having Links to Documents - Under one aspect, a method of displaying information includes: obtaining, responsive to a user query, an album from a remote computer, wherein the album comprises a plurality of links. Each link is to a static graphic representation, and each static graphic representation is stored in a document repository in a remote location. Each static graphic representation is a static graphic representation of a document retrieved from the Internet at a time before the obtaining. The method also includes getting, responsive to said user query, a subset or all of the static graphic representations using a corresponding subset or all of the links. The subset or all of the static graphic representations in the album is at least two static graphic representations in the album. The method also includes displaying the subset of static representations on a graphic output device. | 2009-12-03 |
20090300474 | Computer-based architecture using remotely-controlled electronic grid-based calculators - The present invention comprises a centrally-maintained electronic grid-based calculator and requisite service-oriented architecture to expose the calculator's computational facilities as a service to remote users. Furthermore, the present invention provides a server-side automation architecture of the electronic grid-based calculator which facilitates the distribution of intellectual capital throughout the business enterprise while providing real-time collection, analysis, and reporting of each distributed calculator while facilitating data production, data concurrency, data validation, data security, version control, audit trail, centralized reporting, internal control, quality control, computation, editing and communication. | 2009-12-03 |
20090300475 | WEB-BASED SYSTEM FOR COLLABORATIVE GENERATION OF INTERACTIVE VIDEOS - Systems and methods are provided for adding and displaying interactive annotations for existing online hosted videos. A graphical annotation interface allows the creation of annotations and association of the annotations with a video. Annotations may be of different types and have different functionality, such as altering the appearance and/or behavior of an existing video, e.g. by supplementing it with text, allowing linking to other videos or web pages, or pausing playback of the video. Authentication of a user desiring to perform annotation of a video may be performed in various manners, such as by checking a uniform resource locator (URL) against an existing list, checking a user identifier against an access list, and the like. As a result of authentication, a user is accorded the appropriate annotation abilities, such as full annotation, no annotation, or annotation restricted to a particular temporal or spatial portion of the video. | 2009-12-03 |
20090300476 | Internet Guide Link Matching System - A method of identifying relevant information while a user views an application user interface is provided. A keyword(s) is identified from an application user interface presented at a first computer, wherein the identification is performed transparent to a user viewing the application user interface. The identified keyword is compared with information associated with a plurality of guide links. A guide link is associated with a categorized collection of information about a topic. A relevant guide link of the plurality of guide links is identified based on the comparison. If a relevant guide link is identified, a match between the identified keyword and the identified guide link is indicated at the first computer. If a relevant guide link is identified, a user may view the identified guide link at the first computer. | 2009-12-03 |
20090300477 | Information processing apparatus, information processing method, and computer-readable recording medium storing an information processing program - An information processing apparatus parses document data described in a structured language to extract necessary information from the data. At least a part of the document data is stored in a storage unit, and the stored document data is parsed in order to extract information contained in the document data using. The parsing proceeds from a group of nodes having a high importance to another group of nodes having a lower importance in a network structure represented by the document data. | 2009-12-03 |
20090300478 | IMAGE FORMING APPARATUS, INFORMATION PROCESSING METHOD AND PROGRAM - An image forming apparatus includes multiple executing units; multiple Webpage generating units each corresponding to an executing unit and configured to execute a process corresponding to an HTTP request and generate a Web page for displaying information indicating the process result; multiple menu-information integrating units, each corresponding to an executing unit and configured to obtain, from each Webpage generating unit corresponding to the executing unit, a URL of the Webpage generating unit and menu-item display information provided for allowing use of the Webpage generating unit, integrate and store the menu-item display information in a first file specific to the executing unit, and merge, with the first file, information obtained from another first file specific to another executing unit; and a menu-page generating unit configured to generate, based on information stored in the merged first file, a Web page including menu items provided for allowing use of the Webpage generating units. | 2009-12-03 |