49th week of 2015 patent applcation highlights part 70 |
Patent application number | Title | Published |
20150349016 | IMAGE SENSOR FOR X-RAY AND METHOD OF MANUFACTURING THE SAME - Provided are an image sensor for an X-ray and a method of manufacturing the same, the image sensor for the X-ray, including: a semiconductor active layer formed on an insulating substrate; a gate insulating film on the semiconductor active layer; a gate electrode formed on the gate insulating film; an interlayer insulating film which is formed on the gate electrode and in which a first via hole is formed; a source electrode formed on the first via hole; a drain electrode formed on the first via hole; a first electrode formed to be connected to the source electrode or the drain electrode; and a photo diode formed on the first electrode. | 2015-12-03 |
20150349017 | METHOD OF FABRICATING SEMICONDUCTOR STRUCTURE - A method of fabricating a semiconductor structure is disclosed, in which a pad above a connecting section and metal structures above a functional section are formed from the same metal layer. This design enables the simultaneous formation of the pad and the metal structures by forming a single metal layer and performing thereon a selective etching process, thereby leading to the advantages of process simplification, throughput improvement and cost reduction. | 2015-12-03 |
20150349018 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - A method for producing a semiconductor device includes preparing a wafer having plural portions and having an insulator having plural openings thereon, forming an embedding member in each of the plural openings and on the insulator, removing at least a part of the embedding member, and planarizing the embedding member. The plural portions have a first portion and a second portion and each of the first portion and the second portion has a first region and a second region. The density of the openings in the first region is higher than that in the second region. The process of removing at least a part of the embedding member includes removing the embedding member positioned in the second region of the first portion, and removing the embedding member positioned in the second region of the second portion. A first removal amount and a second removal amount in the processes are different. | 2015-12-03 |
20150349019 | METHOD FOR MANUFACTURING SOLID-STATE IMAGE SENSING DEVICE - A method for manufacturing a solid-state image sensing device includes forming a first insulating film on a semiconductor substrate, planarizing the first insulating film, forming a second insulating film after the planarization, forming an opening in the first and the second insulating film, and forming an optical waveguide by forming a filling member in the opening. The thickness of the first insulating film is measured before the formation of the second insulating film, and the second insulating film is formed to a thickness according to the thickness of the first insulating film. | 2015-12-03 |
20150349020 | MECHANISMS FOR FORMING IMAGE-SENSOR DEVICE WITH DEEP-TRENCH ISOLATION STRUCTURE - A method for fabricating an image-sensor device is provided. The method includes forming a radiation-sensing region and a doped isolation region in a semiconductor substrate. The doped isolation region is adjacent to the radiation-sensing region. The method also includes thinning the semiconductor substrate such that the radiation-sensing region and the doped isolation region are exposed. The method further includes partially removing the doped isolation region to form a recess. In addition, the method includes forming a negatively charged film over an interior surface of the recess and a surface of the radiation-sensing exposed after the thinning of the semiconductor substrate. | 2015-12-03 |
20150349021 | CMOS-BASED THERMOELECTRIC DEVICE WITH REDUCED ELECTRICAL RESISTANCE - An integrated circuit containing CMOS transistors and an embedded thermoelectric device may be formed by forming field oxide in isolation trenches to isolate the CMOS transistors and thermoelectric elements of the embedded thermoelectric device. N-type dopants are implanted into the substrate to provide at least 1×10 | 2015-12-03 |
20150349022 | CMOS-BASED THERMOPILE WITH REDUCED THERMAL CONDUCTANCE - An integrated circuit containing CMOS transistors and an embedded thermoelectric device is formed by forming isolation trenches in a substrate, concurrently between the CMOS transistors and between thermoelectric elements of the embedded thermoelectric device. Dielectric material is formed in the isolation trenches to provide field oxide which laterally isolates the CMOS transistors and the thermoelectric elements. Germanium is implanted into the substrate in areas for the thermoelectric elements, and the substrate is subsequently annealed, to provide a germanium density of at least 0.10 atomic percent in the thermoelectric elements between the isolation trenches. The germanium may be implanted before the isolation trenches are formed, after the isolation trenches are formed and before the dielectric material is formed in the isolation trenches, and/or after the dielectric material is formed in the isolation trenches. | 2015-12-03 |
20150349023 | CMOS COMPATIBLE THERMOPILE WITH LOW IMPEDANCE CONTACT - An integrated circuit containing CMOS transistors and an embedded thermoelectric device may be formed by forming active areas which provide transistor active areas for an NMOS transistor and a PMOS transistor of the CMOS transistors and provide n-type thermoelectric elements and p-type thermoelectric elements of the embedded thermoelectric device. Stretch contacts with lateral aspect ratios greater than 4:1 are formed over the n-type thermoelectric elements and p-type thermoelectric elements to provide electrical and thermal connections through metal interconnects to a thermal node of the embedded thermoelectric device. The stretch contacts are formed by forming contact trenches in a dielectric layer, filling the contact trenches with contact metal and subsequently removing the contact metal from over the dielectric layer. The stretch contacts are formed concurrently with contacts to the NMOS and PMOS transistors. | 2015-12-03 |
20150349024 | RESISTOR MEMORY BIT-CELL AND CIRCUITRY AND METHOD OF MAKING THE SAME - A resistive memory cell control unit, integrated circuit, and method are described herein. The resistive memory cell control unit includes a switching transistor and a resistive memory cell. The switching transistor includes a gate disposed on a first surface of a semiconductor substrate, a source, and a drain each disposed in the semiconductor substrate, a gate terminal disposed on the first surface and connected to the gate, a source terminal disposed on the first surface and connected to the source, and a drain terminal connected to the drain and disposed on a second surface opposite the first surface. The resistive memory cell is disposed on the second surface and has a first end connected to the drain terminal. The structure provides a small area and simple manufacturing process for a resistive memory cell integrated circuit. | 2015-12-03 |
20150349025 | MEMORY DEVICE AND MEMORY UNIT - There are provided a memory device and a memory unit that make it possible to improve retention property of a resistance value in low-current writing. The memory device of the technology includes a first electrode, a memory layer, and a second electrode in order, in which the memory layer includes an ion source layer containing one or more transition metal elements selected from group 4, group 5, and group 6 in periodic table, one or more chalcogen elements selected from tellurium (Te), sulfur (S), and selenium (Se), and one or both of boron (B) and carbon (C), and a resistance change layer having resistance that is varied by voltage application to the first electrode and the second electrode. | 2015-12-03 |
20150349026 | ELECTRONIC MEMORY USING MEMRISTORS AND CROSSBARS - A memory system comprising a plurality of layers of spaced-apart row electrodes, each having a dorsal and a ventral side, a plurality of layers of spaced-apart column electrodes, each having a dorsal and a ventral side is, and a plurality of layers of spaced-apart memristors arranged so that each of the row electrodes and each of the column electrodes is in contact with at least one memristor on the dorsal side thereof and with at least one memristor on the ventral side thereof. | 2015-12-03 |
20150349027 | Organic Optoelectronic Component - An organic optoelectronic component includes a substrate embodied in a light-transmissive fashion, an organic light-emitting element having an organic light-emitting layer between two electrodes, and an organic light-detecting element having an organic light-detecting layer. The organic light-emitting element and the organic light-detecting element are arranged on the substrate. Part of the light generated by the organic light-emitting element during operation enters into the substrate, emerges from the substrate and is detected by the organic light-detecting element. | 2015-12-03 |
20150349028 | LIGHT SHIELDING APPARATUS, METHOD OF FABRICATING THE SAME, AND TRANSPARENT DISPLAY DEVICE INCLUDING THE SAME - A light shielding apparatus that may transmit or shield light by using a plurality of PDLC layers, a method of fabricating the light shielding apparatus, and a transparent display device including the light shielding apparatus are discussed. The light shielding apparatus can include first and second substrates facing each other; a first electrode on the first substrate; a second electrode on the second substrate; and first and second polymer dispersed liquid crystal layers between the first electrode and the second electrode, wherein the first polymer dispersed liquid crystal layer includes first droplets having first liquid crystals, and the second polymer dispersed liquid crystal layer includes second droplets having second liquid crystals and first dichroic dyes. | 2015-12-03 |
20150349029 | DISPLAY PANEL AND METHOD FOR MANUFACTURING THEREOF - A display panel includes a substrate with a plurality of color sub pixel regions and a white sub pixel region constituting a unit pixel; a color filter layer with a color filter provided in each of the plurality of color sub pixel regions; and a reflection reduction layer provided in the white sub pixel region. The reflection reduction layer includes at least one color filter selected from the color filter layer, and a thickness of the reflection reduction layer is smaller than a thickness of the selected color filter. | 2015-12-03 |
20150349030 | COLOR FILTER FORMING SUBSTRATE AND ORGANIC EL DISPLAY DEVICE - Provided is an organic EL display device capable of preventing or restraining color shift or color mixing in an image displayed in each of its pixels, this inconvenience being caused by the entry of light into the pixel from an organic EL element of a pixel adjacent to the pixel; and provided is a color filter forming substrate making it possible to produce such an organic EL display device. The color filter forming substrate is a substrate for an organic EL display device, in which: a pixel-dividing light-shielding region is arranged over one surface of a base material comprising a transparent substrate to make plural pixel regions into a region-divided form; and plural color-filter-forming coloring layers for multiple colors are arranged to the predetermined pixel regions in accordance with the respective colors, characterized in that a light-shielding layer is arranged in the pixel-dividing light-shielding region, and a surface of the light-shielding layer farthest from the one surface of the base material is positioned farther from the one surface of the base material than respective surfaces of the color-filter-forming coloring layers in the respective colors, these surfaces not being respective base material side surfaces of the coloring layers, are positioned. | 2015-12-03 |
20150349031 | 3-D Displaying Panel Having Depth-Of-Field Effect And Displaying Method Thereof - The present invention provides a 3-D display panel having depth-of-field effect, and which includes a substrate ( | 2015-12-03 |
20150349032 | Low Power Consumption OLED Display - This disclosure relates to reduced power consumption OLED displays at reduced cost for reduced information content applications, such as wearable displays. Image quality for wearable displays can be different than for high information content smart phone displays and TVs, where the wearable display has an architecture that in includes, for example, an all phosphorescent device and/or material system that may be fabricated at reduced cost. The reduced power consumption can facilitate wireless and solar charging. | 2015-12-03 |
20150349033 | DISPLAY PANEL - A display panel is provided. The display panel includes a substrate and a plurality of sub-pixels. The substrate includes a plurality of unit regions. One first sub-pixel, one second sub-pixel, one third sub-pixel and one fourth sub-pixel are disposed in each unit region. Each sub-pixel includes a first electrode layer, a light-emitting layer and a second electrode layer. The light-emitting layer is disposed on the first electrode layer, and the second electrode layer is disposed on the light-emitting layer. The light-emitting layer of each first sub-pixel and the light-emitting layer of each second sub-pixel include a same light-emitting material capable of emitting a first color light and a second color light. A difference between a main peak of the first color light and a main peak of the second color light is within 50 nm in the wavelength range. | 2015-12-03 |
20150349034 | HIGH RESOLUTION LOW POWER CONSUMPTION OLED DISPLAY WITH EXTENDED LIFETIME - Systems and techniques are provided that allow for fabrication of full-color OLED displays that include only two colors of emissive regions and four or more sub-pixels within pixels of the device. Mask arrangements for fabricating such devices are also provided. | 2015-12-03 |
20150349035 | ELECTRONIC APPARATUS HAVING AN OXYGEN ION PUMP - The present invention relates to an electronic apparatus which contains an electronically active material and an oxygen ion pump for removing oxygen from the apparatus. Furthermore, the present invention also relates to the use of an oxygen ion pump for removing oxygen from an electronic apparatus. | 2015-12-03 |
20150349036 | Organic Optoelectronic Component - An organic optoelectronic component includes an organic light-emitting element and an organic protective diode element. The organic light-emitting element includes an organic functional layer stack having at least one organic light-emitting layer between two electrodes. The organic protective diode element includes an organic functional layer stack having an organic pn-junction between two electrodes and is arranged on a shared substrate in laterally adjacent area regions with the organic light-emitting element. | 2015-12-03 |
20150349037 | ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - Provided is a method of manufacturing an organic light-emitting display apparatus which may reduce white angular dependency (WAD). The method includes forming a common layer on each of subpixel areas at the same time without discretion within one pixel area, the common layer not being formed on connection areas between pixel areas. | 2015-12-03 |
20150349038 | LIGHT EMITTING DEVICE, METHOD OF MANUFACTURING LIGHT EMITTING DEVICE, AND ELECTRONIC EQUIPMENT - A light emitting device includes a transistor, a light reflection layer, a first insulation layer that includes a first layer thickness part, a second layer thickness part, and a third layer thickness part, a pixel electrode that is provided on the first insulation layer, a second insulation layer that covers a peripheral section of the pixel electrode, a light emission functional layer, a facing electrode, and a conductive layer that is provided on the first layer thickness part. The pixel electrode includes a first pixel electrode which is provided in the first layer thickness part, a second pixel electrode which is provided in the second layer thickness part, and a third pixel electrode which is provided in the third layer thickness part. The first pixel electrode, the second pixel electrode, and the third pixel electrode are connected to the transistor through the conductive layer. | 2015-12-03 |
20150349039 | DISPLAY DEVICE - In one example embodiment, a display device for suppressing reflected light includes a driving circuit and a display region which includes a plurality of pixels. In one example embodiment, the plurality of pixels includes a first pixel having a first light emitting element which includes a first light emitting portion having a first layer surface. In one example embodiment, first pixel includes a second light emitting element which includes a second light emitting portion having a second, different layer surface. In one example embodiment, the first pixel includes a third light emitting element which includes a third light emitting portion having a third, different layer surface. | 2015-12-03 |
20150349040 | Organic Electroluminescence Device and Fabrication Method Thereof - An organic electroluminescence device is disclosed which includes: a substrate; a thin film transistor formed on the substrate; a first electrode formed on the substrate provided with the thin film transistor; an organic light emission layer and a second electrode sequentially formed on the first electrode; and a first light absorption layer formed over the thin film transistor and configured to shield light emitted from the organic light emission layer. As such, the organic electroluminescence device employing the oxide thin film transistor can secure reliability against light. | 2015-12-03 |
20150349041 | Input Device - To provide a novel input device that can be manufactured at low cost or has high reliability. The input device includes a first flexible base material, a second flexible base material, and a sensor circuit that can sense an object such as a finger that is close to or in contact with a surface of the second flexible base material. The sensor circuit includes a transistor portion including a first transistor and a light-emitting element including a second transistor. The first transistor and the second transistor are provided on the first flexible base material side. Connection defects can be less likely to occur, which leads to an increase in the reliability of the input device. | 2015-12-03 |
20150349042 | FLEXIBLE CIRCUIT FILM AND DISPLAY APPARATUS HAVING THE SAME - A flexible circuit film includes a first flexible film, a second flexible film facing the first flexible film, a plurality of wirings arranged between the first flexible film and the second flexible film and extending in a first direction, then bending to extend in a second direction crossing the first direction, and then bending a second time to extend in an opposing direction to the first direction, and a guide film including a material more rigid than the first and second flexible films and arranged on an ends of the first flexible film. The guide film includes a tear-preventing portion overlapping with a bending portion of a shortest one of the wirings while covering portions of an inner edge near inner corners of a U-shaped flexible circuit film. | 2015-12-03 |
20150349043 | EL DISPLAY PANEL, POWER SUPPLY LINE DRIVE APPARATUS, AND ELECTRONIC DEVICE - Disclosed herein is an electroluminescence display panel including a pixel circuit, a signal line, a scan line, a drive power supply line, a common power supply line, a power supply line drive circuit, a high-potential power supply line, and a low-potential power supply line. | 2015-12-03 |
20150349044 | PIXEL CIRCUIT AND DISPLAY DEVICE, AND A METHOD OF MANUFACTURING PIXEL CIRCUIT - The display device including a pixel circuit has a first line, a transistor, a light emitting element, and a second line. The transistor is located between the second line and an electrode of the light emitting element. Either the first line or the second line is wired in a region that overlaps a light emitting region of the light emitting element in a lamination direction of layers. The second line intersects the first line outside of the light emitting region and overlaps a non-light emitting region of the light emitting element. | 2015-12-03 |
20150349045 | INTEGRATED CIRCUIT AND METHOD OF FABRICATING THE SAME - An integrated circuit and a method of fabricating the integrated circuit are provided. In various embodiments, the integrated circuit includes a substrate and a polysilicon resistor. The polysilicon resistor is disposed on the substrate. The polysilicon resistor has at least one positive TCR portion and at least one negative TCR portion. The positive TCR portion is adjacent to the negative TCR portion, and the positive TCR portion is in direct contact with the negative TCR portion. | 2015-12-03 |
20150349046 | WELL RESISTORS AND POLYSILICON RESISTORS - An integrated circuit containing a well resistor has STI field oxide and resistor dummy active areas in the well resistor. STI trenches are etched and filled with trench fill dielectric material. The trench fill dielectric material is removed from over the active areas by a CMP process, leaving STI field oxide in the STI trenches. Subsequently, dopants are implanted into a substrate in the well resistor area to form the well resistor. An integrated circuit containing a polysilicon resistor has STI field oxide and resistor dummy active areas in an area for the polysilicon resistor. A layer of polysilicon is formed and planarized by a CMP process. A polysilicon etch mask is formed over the CMP-planarized polysilicon layer to define the polysilicon resistor. A polysilicon etch process removes polysilicon in areas exposed by the polysilicon etch mask, leaving the polysilicon resistor. | 2015-12-03 |
20150349047 | MIM CAPACITOR AND METHOD OF FORMING THE SAME - According to an exemplary embodiment, a method of forming a MIM capacitor is provided. The method includes the following operations: providing a first metal layer; providing a dielectric layer over the first metal layer; providing a second metal layer over the dielectric layer; etching the second metal layer to define the metal-insulator-metal capacitor; and oxidizing a sidewall of the second metal layer. According to an exemplary embodiment, a MIM capacitor is provided. The MIM capacitor includes a first metal layer; a dielectric layer over the first metal layer; a second metal layer over the dielectric layer; and an oxidized portion in proximity to the second metal layer and made of oxidized second metal layer. | 2015-12-03 |
20150349048 | SEMICONDUCTOR DEVICE AND PROCESS OF MAKING THE SAME - A semiconductor device includes a substrate, a seed layer, a first patterned metal layer, a dielectric layer and a second metal layer. The seed layer is disposed on a surface of the substrate. The first patterned metal layer is disposed on the seed layer and has a first thickness. The first patterned metal layer includes a first part and a second part. The dielectric layer is disposed on the first part of the first patterned metal layer. The second metal layer is disposed on the dielectric layer and has a second thickness, where the first thickness is greater than the second thickness. The first part of the first patterned metal layer, the dielectric layer and the second metal layer form a capacitor. The first part of the first patterned metal layer is a lower electrode of the capacitor, and the second part of the first patterned metal layer is an inductor. | 2015-12-03 |
20150349049 | STRUCTURE OF CAPACITOR - A capacitor including a substrate, a conductive layer, a middle dielectric material layer, a first dielectric material layer, and a second dielectric material layer is provided. The conductive layer includes a first electrode and a second electrode, and the conductive layer is located over the substrate. The middle dielectric material layer is located between the first electrode and the second electrode. The first dielectric material layer is located between the middle dielectric material layer and the first electrode. The second dielectric material layer is located between the middle dielectric material layer and the second electrode. The dielectric constant of the middle dielectric material layer is different from the dielectric constants of the first dielectric material layer and the second dielectric material layer. | 2015-12-03 |
20150349050 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device is provided. The semiconductor device includes a semiconductor substrate, a P-well and an N-well disposed in the semiconductor substrate, a source disposed in the N-well and a drain disposed in the P-well, a shallow trench isolation (STI) structure disposed in the P-well, a gate structure disposed on the semiconductor substrate, wherein a portion of the gate structure extends into the semiconductor substrate and is disposed in a location corresponding to the STI structure. | 2015-12-03 |
20150349051 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first silicon carbide semiconductor layer of a first conductive type that is positioned on a front surface of a substrate of the first conductive type, a transistor region that includes transistor cells, a Schottky region, and a boundary region. The boundary region includes a second body region and a gate connector that is arranged on the second body region via an insulating film and electrically connected with a gate electrode. The Schottky region includes a Schottky electrode that is arranged on the first silicon carbide semiconductor layer. | 2015-12-03 |
20150349052 | STRUCTURE FOR HIGH VOLTAGE DEVICE AND CORRESPONDING INTEGRATION PROCESS - An embodiment of a structure for a high voltage device of the type which comprises at least a semiconductor substrate being covered by an epitaxial layer of a first type of conductivity, wherein a plurality of column structures are realized, which column structures comprises high aspect ratio deep trenches, said epitaxial layer being in turn covered by an active surface area wherein said high voltage device is realized, each of the column structures comprising at least an external portion being in turn realized by a silicon epitaxial layer of a second type of conductivity, opposed than said first type of conductivity and having a dopant charge which counterbalances the dopant charge being in said epitaxial layer outside said column structures, as well as a dielectric filling portion which is realized inside said external portion in order to completely fill said deep trench. | 2015-12-03 |
20150349053 | SEMICONDUCTOR DEVICES WITH A LAYER OF MATERIAL HAVING A PLURALITY OF SOURCE/DRAIN TRENCHES - One device disclosed herein includes an active region defined in a semiconductor substrate, a layer of material positioned above the semiconductor substrate, first and second laterally spaced-apart source/drain trenches defined in the layer of material above the active region, first and second conductive source/drain contact structures positioned within the first and second laterally spaced-apart source/drain trenches, respectively, a gate trench formed at least partially in the layer of material between the first and second laterally spaced-apart source/drain trenches in the layer of material, wherein portions of the layer of material remain positioned between the first and second laterally spaced-apart source/drain trenches and the gate trench, a gate structure positioned within the gate trench, and a gate cap layer positioned above the gate structure. | 2015-12-03 |
20150349054 | DOUBLE/MULTIPLE FIN STRUCTURE FOR FINFET DEVICES - A method of forming double and/or multiple numbers of fins of a FinFET device using a Si/SiGe selective epitaxial growth process and the resulting device are provided. Embodiments include forming a Si pillar in an oxide layer, the Si pillar having a bottom portion and a top portion; removing the top portion of the Si pillar; forming a SiGe pillar on the bottom portion of the Si pillar; reducing the SiGe pillar; forming a first set of Si fins on opposite sides of the reduced SiGe pillar; removing the SiGe pillar; replacing the Si fins with SiGe fins; reducing the SiGe fins; forming a second set of Si fins on opposite sides of the SiGe fins; and removing the SiGe fins. | 2015-12-03 |
20150349055 | SEMICONDUCTOR DEVICE - An element isolation trench is formed in a substrate and is formed along each side of a polygon in a planar view. A first trench is formed in the substrate and extends in a direction different from that of any side of the trench. A first-conductivity type region is formed on/over apart located on the side of an end of the first trench in the substrate. Accordingly, when an impurity region that extends in a depth direction in the substrate is formed by forming the trench in the substrate and diagonally implanting an impurity into the trench, the impurity is prevented from being implanted into a side face of a groove such as a groove for element isolation and so forth impurity implantation into the side face of which is not desired. | 2015-12-03 |
20150349056 | SEMICONDUCTOR DEVICE COMPRISING TRENCH STRUCTURES - A semiconductor device includes a central portion and an edge termination portion outside the central portion. The central portion includes a transistor cell array in a semiconductor substrate. Components of transistor cells of the transistor cell array are disposed in adjacent trench structures in the semiconductor substrate. The trench structures run in a first linear direction parallel to a main surface of the semiconductor substrate. The trench structures include a plurality of concatenated trench segments in a plane parallel to the main surface in the central portion, at least one of the trench segments connecting a first point and a second point of one trench structure, the first point and the second point being arranged along the first linear direction. The trench segment comprises a portion extending in a direction different from the first direction. | 2015-12-03 |
20150349057 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor layer made of a wide bandgap semiconductor and including a gate trench; a gate insulating film formed on the gate trench; and a gate electrode embedded in the gate trench to be opposed to the semiconductor layer through the gate insulating film. The semiconductor layer includes a first conductivity type source region; a second conductivity type body region; a first conductivity type drift region; a second conductivity type first breakdown voltage holding region; a source trench passing through the first conductivity type source region and the second conductivity type body region from the front surface and reaching a drain region; and a second conductivity type second breakdown voltage region selectively formed on an edge portion of the source trench where the sidewall and the bottom wall thereof intersect with each other in a parallel region of the source trench. | 2015-12-03 |
20150349058 | SEMICONDUCTOR DEVICE - A semiconductor device includes a pillar-shaped semiconductor layer and a sidewall having a laminated structure. The laminated structure includes an insulating film and silicon, and the laminated structure is on an upper sidewall of the first pillar-shaped semiconductor layer. The silicon is electrically connected to a top of the pillar-shaped semiconductor layer. | 2015-12-03 |
20150349059 | SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF - A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a semiconductor column having a first portion comprising a first material, a second portion comprising a second material, and a third portion comprising a third material, where the second material is different than the first material and the third material. The first portion, the second portion, and the third portion have substantially equal widths. A first abrupt interface exists between a top surface of the first portion and a bottom surface of the second portion, and a second abrupt interface exists between a top surface of the second portion and a bottom surface of the third portion, in an embodiment. In an embodiment, the column forms part of a transistor where the first portions functions as a source or drain, the second portion functions as a channel, and the third portion functions as a drain or source. | 2015-12-03 |
20150349060 | SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment includes: a first diamond semiconductor layer of a first conductivity type including a main surface having a first plane orientation; a trench structure formed in the first diamond semiconductor layer; a second diamond semiconductor layer formed on the first diamond semiconductor layer in the trench structure and having a lower dopant concentration than the first diamond semiconductor layer; a third diamond semiconductor layer of a second conductivity type formed on the second diamond semiconductor layer and having a higher dopant concentration than the second diamond semiconductor layer; a first electrode electrically connected to the first diamond semiconductor layer; and a second electrode electrically connected to the third diamond semiconductor layer. | 2015-12-03 |
20150349061 | METHODS FOR FABRICATING GRAPHENE DEVICE TOPOGRAPHY AND DEVICES FORMED THEREFROM - Methods for forming graphite-based structures ( | 2015-12-03 |
20150349062 | CONFIGURATION OF PORTIONS OF A POWER DEVICE WITHIN A SILICON CARBIDE CRYSTAL - In one general aspect, an apparatus can include a silicon carbide (SiC) crystal having a top surface aligned along a plane and the SiC crystal having an off-orientation direction. The apparatus including a semiconductor device defined within the SiC crystal. The semiconductor device having an outer perimeter where the outer perimeter has a first side aligned along the off-orientation direction and a second side aligned along a direction non-parallel to the off-orientation direction. The first side of the outer perimeter of the semiconductor device having a length longer than the second side of the outer perimeter of the semiconductor device. | 2015-12-03 |
20150349063 | GROUP III NITRIDE COMPOSITE SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME, LAMINATED GROUP III NITRIDE COMPOSITE SUBSTRATE, AND GROUP III NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A group III nitride composite substrate with a diameter of 75 mm or more includes a support substrate having a thickness t | 2015-12-03 |
20150349064 | NUCLEATION AND BUFFER LAYERS FOR GROUP III-NITRIDE BASED SEMICONDUCTOR DEVICES - A semiconductor wafer includes a substrate and at least one nucleation layer overlying the substrate. The nucleation layer includes a Al | 2015-12-03 |
20150349065 | TRANSISTOR STRUCTURE INCLUDING EPITAXIAL CHANNEL LAYERS AND RAISED SOURCE/DRAIN REGIONS - The present disclosure provides an integrated circuit device including n-channel and p-channel MOSFETs. The MOSFETs include epitaxial grown raised source/drain regions and epitaxial grown channel regions. An epitaxially grown diffusion barrier layer separates the epitaxial grown channel regions from underlying deep n-wells and p-wells. The epitaxial source/drain regions allow for a low thermal budget that in combination with the diffusion barrier layer allows the deep n-wells and p-wells to be heavily doped while preserving high purity in the channel layers. | 2015-12-03 |
20150349066 | Semiconductor Device, Silicon Wafer and Silicon Ingot - A CZ silicon ingot is doped with donors and acceptors and includes an axial gradient of doping concentration of the donors and of the acceptors. An electrically active net doping concentration, which is based on a difference between the doping concentrations of the donors and acceptors varies by less than 60% for at least 40% of an axial length of the CZ silicon ingot due to partial compensation of at least 20% of the doping concentration of the donors by the acceptors. | 2015-12-03 |
20150349067 | THIN-FILM TRANSISTOR SUBSTRATE - An embodiment of the invention provides a thin-film transistor substrate, including: a substrate; a gate electrode disposed on the substrate; a gate insulating layer disposed on the substrate and covering the gate electrode; an active layer disposed on the gate insulating layer and above the gate electrode, wherein the active layer includes a metal oxide; a source electrode disposed on and electrically connecting to the active layer; a first insulating layer covering the source electrode; and a drain electrode disposed on and electrically connecting to the active layer, wherein the drain electrode includes a metal oxide layer. | 2015-12-03 |
20150349068 | CONTACT RESISTANCE OPTIMIZATION VIA EPI GROWTH ENGINEERING - A transistor contact structure and methods of making the same. The method includes forming a first semiconductor layer in a source/drain opening of a substrate, the first layer having a non-planar top surface; forming a second semiconductor layer directly on the first layer, the second layer having a defect density greater than the first layer; and forming a silicide region formed with the second layer, the silicide region having a non-planar interface with the first layer. A portion of the silicide interface may be higher than a top surface of the substrate and another portion may be below. | 2015-12-03 |
20150349069 | FINFET SEMICONDUCTOR DEVICES WITH IMPROVED SOURCE/DRAIN RESISTANCE - A FinFET device includes a plurality of spaced-apart trenches in a semiconducting substrate, the plurality of spaced-apart trenches at least partially defining a fin for the FinFET device, wherein the fin comprises a first semiconductor material. A first layer of insulating material is positioned above a bottom surface of each of the plurality of spaced-apart trenches and an etch stop layer is positioned above an upper surface of the first layer of insulating material in each of the plurality of spaced-apart trenches. A metal silicide region is positioned on at least all sidewall surfaces of the fin that extend above the upper surface of the etch stop layer. | 2015-12-03 |
20150349070 | SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. The semiconductor comprises a field effect transistor (FET) provided in a substrate, the FET including a plurality of gates, sources, and drains each extending in parallel along a longitudinal direction of the gates, the sources, and the drains; an upper electrode provided above the substrate with an insulating layer therebetween, the upper electrode having an opening where the FET is disposed, and a plurality of source extractions each connected to respective sources through via structures passing the insulating layer and to the upper electrode, the source extractions extending along the longitudinal direction. | 2015-12-03 |
20150349071 | SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF - A semiconductor arrangement and methods of formation are provided. The semiconductor arrangement includes a first contact having first contact dimensions that are relative to first gate dimensions of at least one of a first gate or a second gate, where relative refers to a specific relationship between the first contact dimensions and the first gate dimensions. The first contact is between the first gate and the second gate. The first contact having the first contact dimensions relative to the first gate dimensions has lower resistance with little to no increased capacitance, as compared to a semiconductor arrangement having first contact dimensions not in accordance with the specific relationship. The semiconductor arrangement having the lower resistance with little to no increased capacitance exhibits at least one of improved performance or reduced power requirements than a semiconductor arrangement that does not have such lower resistance with little to no increased capacitance. | 2015-12-03 |
20150349072 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR - A semiconductor electronic device structure includes a substrate having a trench disposed therein, a gate electrode disposed in the trench, and a gate dielectric layer disposed on the surface in the trench. The substrate and the gate electrode are electrically insulated from each other by the gate dielectric layer. The substrate further has a pair of doped areas. The doped areas each are vertically disposed along the two respective lateral sides of the trench. The doped areas each have a first portion and a second portion arranged atop the first portion. The first portion extends vertically to the portion of the substrate that is aligned to the gate electrode. The lateral dimension of the first portion is smaller than the lateral dimension of the second portion, and the doping concentration of the first portion is lighter than the doping concentration of the second portion. | 2015-12-03 |
20150349073 | DUAL WORK FUNCTION BURIED GATE-TYPE TRANSISTOR, METHOD FOR FORMING THE SAME, AND ELECTRONIC DEVICE INCLUDING THE SAME - A transistor includes: a source region and a drain region that are formed in a substrate to be spaced apart from each other; a trench formed in the substrate between the source region and the drain region; and a buried gate electrode inside the trench, wherein the buried gate electrode includes: a lower buried portion which includes a high work-function barrier layer including an aluminum-containing titanium nitride, and a first low-resistivity layer disposed over the high work-function barrier layer; and an upper buried portion which includes a low work-function barrier layer disposed over the lower buried portion and overlapping with the source region and the drain region, and a second low-resistivity layer disposed over the low work-function barrier layer. | 2015-12-03 |
20150349074 | ELECTRONIC DEVICE COMPRISING A SEMICONDUCTOR MEMORY UNIT - Devices and methods based on disclosed technology include, among others, an electronic device capable of improving a signal transfer characteristic and a method for fabricating the same. Specifically, an electronic device in one implementation includes a plurality of buried gates formed in a substrate, open parts formed in the substrate on both sides of the buried gate, isolation layers each formed between a sidewall of the open part and a sidewall of the buried gate, source/drain regions formed in the substrate under the respective open parts, and contact plugs buried in the respective open parts. | 2015-12-03 |
20150349075 | INTEGRATED MULTIPLE GATE LENGTH SEMICONDUCTOR DEVICE INCLUDING SELF-ALIGNED CONTACTS - A multi-channel semiconductor device includes a first and second gate channels formed in a semiconductor substrate. The first gate channel has a first length and the second gate channel has a second length greater than the first length. A gate dielectric layer is formed in the first and second gate channels. A first plurality of work function metal layers is formed on the gate dielectric layer of the first gate channel. A second plurality of work function metal layers is formed on the gate dielectric layer of the second gate channel. A barrier layer is formed on each of the first and second plurality of work function metal layers, and the gate dielectric layer. The multi-channel semiconductor device further includes metal gate stacks formed on of the barrier layer such that the barrier layer is interposed between the metal gate stacks and the gate dielectric layer. | 2015-12-03 |
20150349076 | VARIABLE LENGTH MULTI-CHANNEL REPLACEMENT METAL GATE INCLUDING SILICON HARD MASK - A method of forming a semiconductor device includes forming first and second semiconductor structures on a semiconductor substrate. The first semiconductor structure includes a first gate channel region having a first gate length, and the second semiconductor structure including a second gate channel region having a second gate length that is greater than the first gate length. The method further includes depositing a work function metal layer in each of a first gate void formed at the first gate channel region and a second gate void formed at the second gate channel region. The method further includes depositing a semiconductor masking layer on the work function metal layer, and simultaneously etching the silicon masking layer located at the first and second gate channel regions to re-expose the first and second gate voids. A low-resistive metal is deposited in the first and second gate voids to form low-resistive metal gate stacks. | 2015-12-03 |
20150349077 | DEEP GATE-ALL-AROUND SEMICONDUCTOR DEVICE HAVING GERMANIUM OR GROUP III-V ACTIVE LAYER - Deep gate-all-around semiconductor devices having germanium or group III-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack. | 2015-12-03 |
20150349078 | SEMICONDUCTOR WITH A TWO-INPUT NOR CIRCUIT - A semiconductor device includes a two-input NOR circuit including four MOS transistors arranged in a line. Each of the MOS transistors is disposed on a planar silicon layer disposed on a substrate. The drain, gate, and source of the MOS transistor are arranged in the vertical direction. The gate surrounds a silicon pillar. The planar silicon layer is constituted by a first activation region of a first conductivity type and a second activation region of a second conductivity type. The first and second activation regions are connected to each other via a silicon layer disposed on a surface of the planar silicon layer, so as to form a NOR circuit having a small area. | 2015-12-03 |
20150349079 | SEMICONDUCTOR DEVICE WITH A NAND CIRCUIT HAVING FOUR TRANSISTORS - A semiconductor device includes a two-input NAND circuit including four MOS transistors arranged in a line. Each of the MOS transistors is disposed on a planar silicon layer disposed on a substrate. The drain, gate, and source of the MOS transistor are arranged in the vertical direction. The gate surrounds a silicon pillar. The planar silicon layer is constituted by a first activation region of a first conductivity type and a second activation region of a second conductivity type. The first and second activation regions are connected to each other via a silicon layer disposed on a surface of the planar silicon layer, so as to form a NAND circuit having a small area. | 2015-12-03 |
20150349080 | FinFETs with Multiple Threshold Voltages - A device includes a substrate, a semiconductor fin over the substrate, and a gate dielectric layer on a top surface and sidewalls of the semiconductor fin. A gate electrode is spaced apart from the semiconductor fin by the gate dielectric layer. The gate electrode includes a top portion over and aligned to the semiconductor fin, and a sidewall portion on a sidewall portion of the dielectric layer. The top portion of the gate electrode has a first work function, and the sidewall portion of the gate electrode has a second work function different from the first work function. | 2015-12-03 |
20150349081 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to an embodiment includes: a semiconductor layer; a block insulating film; an organic molecular layer, which is formed between the semiconductor layer and the block insulating film, and provided with a first organic molecular film on the semiconductor layer side containing first organic molecules and a second organic molecular film on the block insulating film side containing second organic molecules, and in which the first organic molecule has a charge storing unit and the second organic molecule is an amphiphilic organic molecule; and a control gate electrode formed on the block insulating film. | 2015-12-03 |
20150349082 | SEMICONDUCTOR STRUCTURES COMPRISING ALUMINUM OXIDE - A semiconductor structure comprising aluminum oxide. The semiconductor structure comprises a dielectric material overlying a substrate. The aluminum oxide overlies the dielectric material in a first region of the structure. A second region of the structure includes a first titanium nitride portion overlying the dielectric material, magnesium over the first titanium nitride portion, and a second titanium nitride portion over the magnesium. Methods of forming the semiconductor structure including aluminum oxide are also disclosed. | 2015-12-03 |
20150349083 | METHODS OF FORMING MIS CONTACT STRUCTURES FOR SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES - One method disclosed includes, among other things, conformably depositing a layer of contact insulating material and a conductive material layer in a contact opening, forming a reduced-thickness sacrificial material layer in the contact opening so as to expose a portion, but not all, of the conductive material layer, removing portions of the conductive material layer and the layer of contact insulating material positioned above the upper surface of the reduced-thickness sacrificial material layer, removing the reduced-thickness sacrificial material layer, and forming a conductive contact in the contact opening that contacts the recessed portions of the conductive material layer and the layer of contact insulating material. | 2015-12-03 |
20150349084 | METHOD OF PRODUCING A JUNCTION FIELD-EFFECT TRANSISTOR (JFET) - The invention concerns a method for producing a field effect transistor having a trench gate comprising:—the forming ( | 2015-12-03 |
20150349085 | METHOD FOR MAKING A SEMICONDUCTOR DEVICE WITH SIDEWALL SPACERS FOR CONFINING EPITAXIAL GROWTH - A method for making a semiconductor device includes forming laterally spaced-apart semiconductor fins above a substrate. At least one dielectric layer is formed adjacent an end portion of the semiconductor fins and within the space between adjacent semiconductor fins. A pair of sidewall spacers is formed adjacent outermost semiconductor fins at the end portion of the semiconductor fins. The at least one dielectric layer and end portion of the semiconductor fins between the pair of sidewall spacers are removed. Source/drain regions are formed between the pair of sidewall spacers. | 2015-12-03 |
20150349086 | VERTICAL BJT FOR HIGH DENSITY MEMORY - Some aspects of this disclosure relate to a memory device. The memory device includes a collector region having a first conductivity type and which is coupled to a source line of the memory device. A base region is formed over the collector region and has a second conductivity type. A gate structure is coupled to the base region and acts as a shared word line for first and second neighboring memory cells of the memory device. First and second emitter regions are formed over the base region and have the first conductivity type. The first and second emitter regions are arranged on opposite sides of the gate structure. First and second contacts extend upwardly from the first and second emitter regions, respectively, and couple the first and second emitter regions to first and second data storage elements, respectively, of the first and second neighboring memory cells, respectively. | 2015-12-03 |
20150349087 | METHOD OF FORMING HIGH ELECTRON MOBILITY TRANSISTOR - A method of forming a high electron mobility transistor (HEMT) includes epitaxially growing a second III-V compound layer on a first III-V compound layer. The method further includes partially etching the second III-V compound layer to form two through holes in the second III-V compound layer. Additionally, the method includes forming a silicon feature in each of two through holes. Furthermore, the method includes depositing a metal layer on each silicon feature. Moreover, the method includes annealing the metal layer and each silicon feature to form corresponding salicide source/drain features. The method also includes forming a gate electrode over the second III-V compound layer between the salicide source/drain features. | 2015-12-03 |
20150349088 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A semiconductor structure includes a gate structure disposed on a substrate and having an outer spacer, a recess disposed in the substrate and adjacent to the gate structure, a doped epitaxial material filling up the recess, a cap layer including an undoped epitaxial material and disposed on the doped epitaxial material, a lightly doped drain disposed below the cap layer and sandwiched between the doped epitaxial material and the cap layer, and a silicide disposed on the cap layer and covering the doped epitaxial material to cover the cap layer together with the outer spacer without directly contacting the lightly doped drain. | 2015-12-03 |
20150349089 | TUCKED ACTIVE REGION WITHOUT DUMMY POLY FOR PERFORMANCE BOOST AND VARIATION REDUCTION - In one embodiment, a semiconductor device is provided that includes a semiconductor substrate including an active region and at least one trench isolation region at a perimeter of the active region, and a functional gate structure present on a portion of the active region of the semiconductor substrate. Embedded semiconductor regions are present in the active region of the semiconductor substrate on opposing sides of the portion of the active region that the functional gate structure is present on. A portion of the active region of the semiconductor substrate separates the outermost edge of the embedded semiconductor regions from the at least one isolation region. Methods of forming the aforementioned device are also provided. | 2015-12-03 |
20150349090 | Methods and Apparatus for Doped SiGe Source/Drain Stressor Deposition - A method of manufacturing a semiconductor device includes etching a recess into a substrate and epitaxially growing a source/drain region in the recess. The source/drain region includes a first undoped layer of stressor material lining the recess, a lightly doped layer of stressor material over the first undoped layer, a second undoped layer of stressor material over the lightly doped layer, and a highly doped layer of stressor material over the second undoped layer. | 2015-12-03 |
20150349091 | SEMICONDUCTOR POWER DEVICES MANUFACTURED WITH SELF-ALIGNED PROCESSES AND MORE RELIABLE ELECTRICAL CONTACTS - This invention discloses semiconductor power device that includes a plurality of top electrical terminals disposed near a top surface of a semiconductor substrate. Each and every one of the top electrical terminals comprises a terminal contact layer formed as a silicide contact layer near the top surface of the semiconductor substrate. The trench gates of the semiconductor power device are opened from the top surface of the semiconductor substrate and each and every one of the trench gates comprises the silicide layer configured as a recessed silicide contact layer disposed on top of every on of the trench gates slightly below a top surface of the semiconductor substrate surround the trench gate. | 2015-12-03 |
20150349092 | TRENCH GATE TRENCH FIELD PLATE SEMI-VERTICAL SEMI-LATERAL MOSFET - A semiconductor device has a vertical drain extended MOS transistor with deep trench structures to define a vertical drift region and at least one vertical drain contact region, separated from the vertical drift region by at least one instance of the deep trench structures. Dopants are implanted into the vertical drain contact regions and the semiconductor device is annealed so that the implanted dopants diffuse proximate to a bottom of the deep trench structures. The vertical drain contact regions make electrical contact to the proximate vertical drift region at the bottom of the intervening deep trench structure. At least one gate, body region and source region are formed above the drift region at, or proximate to, a top surface of a substrate of the semiconductor device. The deep trench structures are spaced so as to form RESURF regions for the drift region. | 2015-12-03 |
20150349093 | FINFET WITH DIELECTRIC ISOLATION AFTER GATE MODULE FOR IMPROVED SOURCE AND DRAIN REGION EPITAXIAL GROWTH - A method forming a semiconductor device that in one embodiment includes forming a gate structure on a channel region of fin structures, and forming a flowable dielectric material on a source region portion and a drain region portion of the fin structures. The flowable dielectric material is present at least between adjacent fin structures of the plurality of fin structures filling a space between the adjacent fin structures. An upper surface of the source region portion and the drain region portion of fin structures is exposed. An epitaxial semiconductor material is formed on the upper surface of the source region portion and the drain region portion of the fin structures. | 2015-12-03 |
20150349094 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - Provided are a method for fabricating a semiconductor device The method for fabricating include providing a substrate including a first region and a second region, the first region including first and second sub-regions, and the second region including third and fourth sub-regions, forming first to fourth fins on the first and second regions to protrude from the substrate, the first fin being formed on the first sub-region, the second fin being formed on the second sub-region, the third fin being formed on the third sub-region, and the fourth fin being formed on the fourth sub-region, forming first to fourth dummy gate structures to intersect the first to fourth fins, the first dummy gate structure being formed on the first fin, the second dummy gate structure being formed on the second fin, the third dummy gate structure being formed on the third fin, and the fourth dummy gate structure being formed on the fourth fin, forming a first doped region in each of the first and second fins and a second doped region in each of the third and fourth fins by doping impurities into the first to fourth fins on both sides of the first to fourth dummy gate structures by performing an ion implantation process simultaneously in the first and second regions; and removing the first doped region of the first fin and the second doped region of the third fin, or removing the first doped region of the second fin and the second doped region of the fourth fin. | 2015-12-03 |
20150349095 | METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH NONVOLATILE MEMORY DEVICES - Methods for fabricating integrated circuits are provided. An exemplary method for fabricating an integrated circuit includes forming a stack gate structure overlying a semiconductor substrate. The method forms a select gate material overlying the stack gate structure and the semiconductor substrate and having a planar surface overlying the stack gate structure. The method includes anisotropically etching the select gate material to define a select gate adjacent the stack gate structure, wherein the select gate is formed with a planar upper surface. | 2015-12-03 |
20150349096 | METHOD OF MAKING A SPLIT GATE NON-VOLATILE MEMORY (NVM) CELL - Making a non-volatile memory (NVM) structure uses a semiconductor substrate. One embodiment includes forming a select gate structure including a first dummy material on the semiconductor substrate and forming a control gate structure including a second dummy material on the semiconductor substrate, where the first dummy material is different from the second dummy material. The embodiment also includes replacing the first dummy material with metal and replacing the second dummy material with polysilicon. | 2015-12-03 |
20150349097 | Method of Manufacturing a Semiconductor Device Having a Rectifying Junction at the Side Wall of a Trench - A method for forming a field-effect semiconductor device includes: providing a wafer having a main surface and a first semiconductor layer of a first conductivity type; forming at least two trenches from the main surface partly into the first semiconductor layer so that each of the at least two trenches includes, in a vertical cross-section substantially orthogonal to the main surface, a side wall and a bottom wall, and that a semiconductor mesa is formed between the side walls of the at least two trenches; forming at least two second semiconductor regions of a second conductivity type in the first semiconductor layer so that the bottom wall of each of the at least two trenches adjoins one of the at least two second semiconductor regions; and forming a rectifying junction at the side wall of at least one of the at least two trenches. | 2015-12-03 |
20150349098 | A MANUFACTURING METHOD OF A THIN FILM TRANSISTOR AND PIXEL UNIT THEREOF - The present invention provides a method of manufacturing a thin film transistor and a pixel unit thereof, comprising: forming a metal oxide layer, a gate insulating layer, a gate metal layer and an etching barrier layer on a substrate; through the same mask, etching a part of the etching barrier layer, the gate metal layer and the gate insulating layer on the substrate, while retaining: the metal oxide layer, the gate insulating layer, the gate metal layer and the etching barrier layer in a gate region, and the part of the metal oxide layer, the gate insulating layer and the gate metal layer in source and drain regions for forming contact vias; and exposing the remaining metal oxide layer in the source region and in the drain region; depositing a passivation layer, etching and metallizing the exposed oxide in the source and drain regions to form the source and drain contact vias. | 2015-12-03 |
20150349099 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - It is an object to provide a semiconductor device including a thin film transistor with favorable electric properties and high reliability, and a method for manufacturing the semiconductor device with high productivity. In an inverted staggered (bottom gate) thin film transistor, an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, and a buffer layer formed using a metal oxide layer is provided between the semiconductor layer and a source and drain electrode layers. The metal oxide layer is intentionally provided as the buffer layer between the semiconductor layer and the source and drain electrode layers, whereby ohmic contact is obtained. | 2015-12-03 |
20150349100 | BIPOLAR TRANSISTOR - P-type second semiconductor layers each interposed between a corresponding pair of n-type first semiconductor layers reduce the apparent doping concentration in the entire collector layer without reducing the doping concentrations in the first semiconductor layers. This improves the linearity of capacitance characteristics and enables sufficient mass productivity to be achieved. Interposing each of the second semiconductor layers between the corresponding pair of the first semiconductor layers reduce the average carrier concentration over the entire collector layer, which allows a wide depletion layer to be formed inside the collector layer and, as a result, reduces base-collector capacitance. | 2015-12-03 |
20150349101 | INJECTION CONTROL IN SEMICONDUCTOR POWER DEVICES - Semiconductor power devices can be formed on substrate structure having a lightly doped semiconductor substrate of a first conductivity type or a second conductivity type opposite to the first conductivity type. A semiconductive first buffer layer of the first conductivity type formed above the substrate. A doping concentration of the first buffer layer is greater than a doping concentration of the substrate. A second buffer layer of the second conductivity type formed above the first buffer layer. An epitaxial layer of the second conductivity type formed above the second buffer layer. A doping concentration of the epitaxial layer is greater than a doping concentration of the second buffer layer. This abstract is provided to allow a searcher or reader to quickly ascertain the subject matter of the disclosure with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 2015-12-03 |
20150349102 | TI-IGBT AND FORMATION METHOD THEREOF - A TI-IGBT, comprising a first semiconductor substrate, a second semiconductor substrate, and a first doped layer; a short circuit region and a collector region disposed in parallel are formed in the first semiconductor substrate; the short circuit region and the collector region have different doping types; the second semiconductor substrate is located on the upper surface of the first semiconductor substrate, and has the same doping type with the short circuit region; the first doped layer is located between the first semiconductor substrate and the second semiconductor substrate, and covers at least the collector region; the first doped layer has the same doping type with the second semiconductor substrate, and has a doping concentration smaller than that of the second semiconductor substrate. | 2015-12-03 |
20150349103 | SEMICONDUCTOR DEVICE - A semiconductor device has mesa form first and second p-type base regions and a floating p-type region provided in a surface layer of an n−-type drift layer. The first p-type base region and floating p-type region are separated by a first trench. The second p-type base region is separated from the floating p-type region by a second trench. The first and second p-type base regions are conductively connected to an emitter electrode. The floating p-type region is in a floating state electrically isolated from the emitter electrode. A first gate electrode is provided via a first gate insulating film inside the first trench. An emitter potential second gate electrode is provided via a second gate insulating film inside the second trench. Therefore, di/dt controllability when turning on the semiconductor device can be increased. | 2015-12-03 |
20150349104 | INSULATED GATE TURN-OFF DEVICE WITH TURN-OFF TRANSISTOR - An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n− epi layer, a p-well, vertical insulated gate regions formed in the p-well, and n+ regions between the gate regions, so that vertical NPN and PNP transistors are formed. The device is formed of a matrix of cells. To turn the device on, a positive voltage is applied to the gate, referenced to the cathode. The cells further contain a vertical p-channel MOSFET, for shorting the base of the NPN transistor to its emitter, to turn the NPN transistor off when the p-channel MOSFET is turned on by a slight negative voltage applied to the gate. This allows the IGTO device to be more easily turned off while in a latch-up condition, when the device is acting like a thyristor. | 2015-12-03 |
20150349105 | SEMICONDUCTOR DEVICE AND METHOD - A semiconductor device includes a device region including a compound semiconductor material and a non-device region at least partially surrounding the device region. The semiconductor device further includes a dielectric material in the non-device region and at least one electrode in the device region. The semiconductor device further includes at least one pad electrically coupled to the at least one electrode, wherein the at least one pad is arranged on the dielectric material in the non-device region. | 2015-12-03 |
20150349106 | SEMICONDUCTOR STRUCTURE HAVING SETS OF III-V COMPOUND LAYERS AND METHOD OF FORMING THE SAME - A semiconductor structure includes a substrate; and a graded III-V layer over the substrate. The semiconductor structure further includes a p-doped gallium nitride (GaN) layer over the graded III-V layer. The semiconductor structure further includes one or more sets of GaN layers over the p-doped GaN layer. Each set of the one or more sets of GaN layers includes a lower GaN layer, wherein the lower GaN layer is undoped, unintentionally doped having N-type doping, or N-type doped. Each set of the one or more sets of GaN layers includes an upper GaN layer on the lower GaN layer, wherein the upper GaN layer is P-type doped. The semiconductor structure includes a second GaN layer over the one or more sets of GaN layers, the second GaN layer being either undoped or unintentionally doped having the N-type doping. The semiconductor structure includes an active layer over the second GaN layer. | 2015-12-03 |
20150349107 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a substrate, a channel layer, a spacer layer, a barrier layer, and an oxidized cap layer. The channel layer is disposed on or above the substrate. The spacer layer is disposed on the channel layer. The barrier layer is disposed on the spacer layer. The oxidized cap layer is disposed on the barrier layer. The oxidized cap layer is made of oxynitride. | 2015-12-03 |
20150349108 | ELECTRODE STRUCTURE FOR NITRIDE SEMICONDUCTOR DEVICE, AND NITRIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR - An electrode structure for nitride semiconductor device according to an embodiment of the invention includes a source electrode and a drain electrode provided from recesses of a nitride semiconductor multilayer structure to a surface of an insulating film so as to be in contact with the surface of the nitride semiconductor multilayer structure between the insulating film and the opening edges of the recesses. According to the structure of the ohmic electrodes, ON-state maximum electric field at ends of the source electrode and the drain electrode adjacent to the nitride semiconductor multilayer structure can be reduced so that the ON-state withstand voltage can be improved, as compared with an electrode structure in which end edge portions of ohmic electrodes are sandwiched between a nitride semiconductor multilayer structure and an insulating film. | 2015-12-03 |
20150349109 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device may include interlayer insulating layers stacked in a first direction and separated from each other, word lines formed between the interlayer insulating layers, and sacrificial insulating layers formed between the interlayer insulating layers so that the sacrificial insulating layers are arranged at layers where the word lines are formed. The semiconductor device may also include cell contact plugs each including a first pillar portion passing through at least one of the interlayer insulating layers and the sacrificial insulating layers in the first direction, and a first protruding portion protruding from a sidewall of the first pillar portion and contacting a sidewall of one of the word lines, wherein the cell contact plugs have different depths. | 2015-12-03 |
20150349110 | MOSFET HAVING DUAL-GATE CELLS WITH AN INTEGRATED CHANNEL DIODE - A semiconductor device includes MOSFET cells having a drift region of a first conductivity type. A first and second active area trench are in the drift region. A split gate uses the active trenches as field plates or includes planar gates between the active trenches including a MOS gate electrode (MOS gate) and a diode gate electrode (diode gate). A body region of the second conductivity type in the drift region abutts the active trenches. A source of the first conductivity type in the body region includes a first source portion proximate to the MOS gate and a second source portion proximate to the diode gate. A vertical drift region uses the drift region below the body region to provide a drain. A connector shorts the diode gate to the second source portion to provide an integrated channel diode. The MOS gate is electrically isolated from the first source portion. | 2015-12-03 |
20150349111 | SEMICONDUCTOR DEVICE - A semiconductor device includes a drift region of a first conductivity type, a channel forming region of a second conductivity type that is selectively provided in a first main surface of the drift region, a first main electrode region of the first conductivity type that is selectively provided in an upper part of the channel forming region, a second main electrode region of the second conductivity type that is provided in a second main surface of the drift region, and a high-concentration region of the first conductivity type that is provided in a portion of the drift region below the channel forming region so as to be separated from the channel forming region. The high-concentration region has a higher impurity concentration than the drift region and the total amount of first-conductivity-type impurities in the high-concentration region is equal to or less than 2.0×10 | 2015-12-03 |
20150349112 | TRENCH MOSFET HAVING REDUCED GATE CHARGE - A trench MOSFET device includes a semiconductor layer of a first doping type. MOS transistor cells are in a body region of a second doping type in the semiconductor layer. The transistor cells include a first cell type including a first trench providing a first gate electrode or the first gate electrode is on the semiconductor surface between the first trench and a second trench, and a first source region is formed in the body region. The first gate electrode is electrically isolated from the first source region. A second cell type has a third trench providing a second gate electrode or the second gate electrode is on the semiconductor surface between the third trench and a fourth trench, and a second source region is in the body region. An electrically conductive member directly connects the second gate electrode, first source region and second source region together. | 2015-12-03 |
20150349113 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device, includes a first semiconductor layer of a first conductivity, a second semiconductor layer of a second conductivity type, and a third semiconductor layer of the first conductivity. A first plurality of source elements are spaced from each other and a first gate electrode extends continuously between the source elements. A source electrode is electrically connected to the source elements, and a drain electrode is on the first semiconductor layer such that the first semiconductor layer is between the second semiconductor layer and the drain electrode. By employing this structure, an inactive region decreases, and an active area ratio increases. Thereby, a breakdown voltage can be maintained while an on-resistance can be reduced. | 2015-12-03 |
20150349114 | SEMICONDUCTOR DEVICE - In a semiconductor device provided with a MOSFET part and a gate pad part, the gate pad part includes: a low resistance semiconductor layer; a drift layer; a poly-silicon layer constituting a conductor layer and a gate pad electrode formed above the drift layer over the whole area of the gate pad part with a field insulation layer interposed therebetween; and a gate oscillation suppressing structure, wherein the gate oscillation suppressing structure includes a p | 2015-12-03 |
20150349115 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME - Disclosed herein is a technique for realizing a high-performance and high-reliability silicon carbide semiconductor device. A trenched MISFET with a trench formed into the drift through a p-type body layer | 2015-12-03 |