49th week of 2015 patent applcation highlights part 71 |
Patent application number | Title | Published |
20150349116 | Semiconductor Device Having an Active Trench and a Body Trench - A semiconductor substrate having a first main surface and a transistor cell includes a drift region, a body region between the drift region and the first main surface, an active trench at the first main surface extending into the drift region, a gate insulating layer at sidewalls and a bottom side of the active trench, a gate conductive layer in the active trench, a source region in the body region, and adjacent to the active trench, a body trench at the first main surface extending into the drift region, the body trench being adjacent to the body region and to the drift region, an insulating layer at sidewalls and at a bottom side of the body trench, the insulating layer being asymmetric with respect to an axis extending perpendicular to the first main surface at a center of the body trench, and a conductive layer in the body trench. | 2015-12-03 |
20150349117 | III-NITRIDE INSULATING-GATE TRANSISTORS WITH PASSIVATION - A field-effect transistor (FET) includes a plurality of semiconductor layers, a source electrode and a drain electrode contacting one of the semiconductor layers, a first dielectric layer on a portion of a top semiconductor surface between the source and drain electrodes, a first trench extending through the first dielectric layer and having a bottom located on a top surface or within one of the semiconductor layers, a second dielectric layer lining the first trench and covering a portion of the first dielectric layer, a third dielectric layer over the semiconductor layers, the first dielectric layer, and the second dielectric layer, a second trench extending through the third dielectric layer and having a bottom located in the first trench on the second dielectric layer and extending over a portion of the second dielectric, and a gate electrode filling the second trench. | 2015-12-03 |
20150349118 | VERTICAL TRANSISTOR AND METHOD TO FORM VERTICAL TRANSISTOR CONTACT NODE - A vertical transistor structure includes a substrate with a protruding structure, an offset layer covering a top surface of the protruding structure, a conductive layer disposed on the offset layer, and an interlayer disposed between the offset layer and the conductive layer to serve as a contact node. | 2015-12-03 |
20150349119 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for producing a semiconductor device includes a first step of forming a first insulating film around the fin-shaped semiconductor layer; a second step of forming a pillar-shaped semiconductor layer and a first dummy gate formed of a first polysilicon; a third step of forming a second dummy gate on sidewalls of the first dummy gate and the pillar-shaped semiconductor layer; a fourth step of forming a fifth insulating film left as a sidewall around the second dummy gate, forming a second diffusion layer in an upper portion of the fin-shaped semiconductor layer and a lower portion of the pillar-shaped semiconductor layer, and forming a metal-semiconductor compound on the second diffusion layer; a fifth step of forming a gate electrode and a gate line; and a sixth step of depositing a second gate insulating film around the pillar-shaped semiconductor layer and on the gate electrode and the gate line, removing a portion of the second gate insulating film on the gate line, depositing a second metal, etching back the second metal, removing the second gate insulating film on the pillar-shaped semiconductor layer, depositing a third metal, and etching a portion of the third metal and a portion of the second metal to form a first contact in which the second metal surrounds a sidewall of an upper portion of the pillar-shaped semiconductor layer, a second contact that connects an upper portion of the first contact and an upper portion of the pillar-shaped semiconductor layer, and a third contact made of the second metal and the third metal and formed on the gate line. | 2015-12-03 |
20150349120 | SEMICONDUCTOR DEVICE STRUCTURE - A semiconductor device structure includes a semiconductor substrate with an active region provided therein, a gate structure, a dummy gate structure and two contact regions provided in the active region for forming source and drain regions. The gate structure and the dummy gate structure are formed on the semiconductor substrate so as to partially overlie the active region, and one of the contact regions is located at one side of the dummy gate structure. The semiconductor device structure includes a contact structure contacting one of the contact regions and the dummy gate for connecting this contact region and the dummy gate to one of a Vdd rail and a Vss rail. The active region has an extension portion protruding laterally away from the active region relative to the other contact region, where the contact structure is located over the extension portion. | 2015-12-03 |
20150349121 | ASYMMETRIC STRESSOR DRAM - A stressor structure is formed within a drain region of an access transistor in a dynamic random access memory (DRAM) cell in a semiconductor-on-insulator (SOI) substrate without forming any stressor structure in a source region of the DRAM cell. The stressor structure induces a stress gradient within the body region of the access transistor, which induces a greater leakage current at the body-drain junction than at the body-source junction. The body potential of the access transistor has a stronger coupling to the drain voltage than to the source voltage. An asymmetric etch of a gate dielectric cap, application of a planarization material layer, and a non-selective etch of the planarization material layer and the gate dielectric cap can be employed to form the DRAM cell. | 2015-12-03 |
20150349122 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A method of fabricating one or more semiconductor devices includes forming a trench in a semiconductor substrate, performing a cycling process to remove contaminants from the trench, and forming an epitaxial layer on the trench. The cycling process includes sequentially supplying a first reaction gas containing germane, hydrogen chloride and hydrogen and a second reaction gas containing hydrogen chloride and hydrogen onto the semiconductor substrate. | 2015-12-03 |
20150349123 | STRAINED FinFET BY EPITAXIAL STRESSOR INDEPENDENT OF GATE PITCH - A semiconductor device is fabricated by forming a fin and a plurality of gates upon a semiconductor substrate, forming sacrificial spacers upon opposing gate sidewalls, forming a mask upon an upper surface of the fin between neighboring gates, removing the sacrificial spacers, recessing a plurality of regions of the fin to create a dummy fin and fin segments, removing the mask, and epitaxially merging the dummy fin and fin segments. The fins may be partially recessed prior to forming the sacrificial spacers. The device may include the substrate, gates, fin segments each associated with a particular gate, the dummy fin between a fin segment pair separated by the wider pitch, and merged epitaxy connecting the dummy fin and the fin segment pair. The dummy fin may serve as a filler between the fin segment pair and may add epitaxial growth planes to allow for epitaxial merging within the wider pitch. | 2015-12-03 |
20150349124 | TRANSISTOR STRUCTURE HAVING BURIED ISLAND REGIONS - A semiconductor device such as a transistor includes a source region, a drain region, a semiconductor region, at least one island region and at least one gate region. The semiconductor region is located between the source region and the drain region. The island region is located in the semiconductor region. Each of the island regions differs from the semiconductor region in one or more characteristics selected from the group including resistivity, doping type, doping concentration, strain and material composition. The gate region is located between the source region and the drain region covering at least a portion of the island regions. | 2015-12-03 |
20150349125 | FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE AND METHOD FOR FORMING THE SAME - A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure are provided. The FinFET structure includes a substrate and a fin structure extending above the substrate. The FinFET structure also includes a gate electrode formed over the fin structure, and the gate electrode has a grid-like pattern when seen from a top-view. | 2015-12-03 |
20150349126 | FIELD EFFECT TRANSISTORS HAVING A FIN - An embodiment of a transistor has a semiconductor fin, a dielectric over the semiconductor fin, a control gate over the dielectric, and source/drains in the semiconductor fin and having upper surfaces below an uppermost surface of the semiconductor fin. Another embodiment of a transistor has first and second semiconductor fins, a first source/drain region in the first semiconductor fin and extending downward from an uppermost surface of the first semiconductor fin, a second source/drain region in the second semiconductor fin and extending downward from an uppermost surface of the second semiconductor fin, a dielectric between the first and second semiconductor fins and adjacent to sidewalls of the first and second semiconductor fins, and a control gate over the dielectric and between the first and second semiconductor fins and extending to a level below upper surfaces of the first and second source/drain regions. | 2015-12-03 |
20150349127 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE - The semiconductor device includes a first layer including a first transistor, a second layer including a first insulating film over the first layer, a third layer including a second insulating film over the second layer, and a fourth layer including a second transistor over the third layer. A first conductive film electrically connects the first transistor and the second transistor to each other through an opening provided in the first insulating film. A second conductive film electrically connects the first transistor, the second transistor, and the first conductive film to one another through an opening provided in the second insulating film. A channel formation region of the first transistor includes a single crystal semiconductor. A channel formation region of the second transistor includes an oxide semiconductor. The width of a bottom surface of the second conductive film is 5 nm or less. | 2015-12-03 |
20150349128 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device including an insulator, a first conductor as a source electrode, a second conductor as a drain electrode, a third conductor as a gate electrode, and an island-shaped semiconductor is provided. The first conductor includes a first side surface, a second side surface, and a third side surface. The second conductor includes a fourth side surface. The first conductor and the second conductor are positioned to make the first side surface and the fourth side surface face each other. The first conductor includes a first corner portion between the first side surface and the second side surface and a second corner portion between the second side surface and the third side surface. The first corner portion includes a portion having a smaller radius of curvature than the second corner portion. | 2015-12-03 |
20150349129 | IMAGING ELEMENT, ELECTRONIC APPLIANCE, METHOD FOR DRIVING IMAGING DEVICE, AND METHOD FOR DRIVING ELECTRONIC APPLIANCE - An imaging element which is capable of obtaining a piece of image data by performing light exposure plural times is provided. In addition, an imaging element which is capable of obtaining image data with little noise is provided. Furthermore, an imaging device with reduced power consumption is provided. In an imaging element including a pixel, the pixel includes a photodiode, a transistor including an oxide semiconductor layer, a diode, and a charge retention portion. The polarity of an electrode of the photodiode which is connected to the transistor is the same as that of an electrode of the diode which is connected to the transistor. | 2015-12-03 |
20150349130 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE - Threshold voltage adjustment method of a semiconductor device is provided. In a semiconductor device in which at least one of transistors included in an inverter includes a semiconductor, a source electrode or a drain electrode electrically connected to the semiconductor, a gate electrode, and a charge trap layer provided between the gate electrode and the semiconductor, the potential of the gate electrode of the transistor that is higher than those of the source electrode and the drain electrode is held for a short time of 5 s or shorter, whereby electrons are trapped in the charge trap layer and the threshold voltage is increased. At this time, when the potential differences between the gate electrode and the source electrode, and the gate electrode and the drain electrode are different from each other, the threshold voltage of the transistor of the semiconductor device becomes appropriate. | 2015-12-03 |
20150349131 | SEMICONDUCTOR DEVICE - A semiconductor device which occupies a small area is provided. A semiconductor device includes a resistor. The resistor includes a transistor. The increase rate of a drain current of the transistor with a 0.1 V change in drain voltage is preferably higher than or equal to 1% when the drain voltage is higher than a difference between a gate voltage and a threshold voltage of the transistor. The semiconductor device has a function of generating a voltage based on the resistance of the resistor. | 2015-12-03 |
20150349132 | SEMICONDUCTOR DEVICE, MODULE, AND ELECTRONIC DEVICE - Provided is a semiconductor device including a first insulator, a second insulator, a first oxide semiconductor, a second oxide semiconductor, a first conductor, and a second conductor. The first oxide semiconductor is over the first insulator. The second oxide semiconductor is over the first oxide semiconductor. The first conductor includes a region in contact with a top surface of the second oxide semiconductor. The second insulator includes a region in contact with the top surface of the second oxide semiconductor. The second conductor is over the second oxide semiconductor with the second insulator therebetween. The second oxide semiconductor includes a first layer and a second layer. The first layer includes a region in contact with the first oxide semiconductor. The second layer includes a region in contact with the second insulator. The first layer has a lower proportion of oxygen vacancies than the second layer. | 2015-12-03 |
20150349133 | OXIDE SEMICONDUCTOR STACKED FILM AND SEMICONDUCTOR DEVICE - An oxide semiconductor stacked film which does not easily cause a variation in electrical characteristics of a transistor and has high stability is provided. Further, a transistor which includes the oxide semiconductor stacked film in its channel formation region and has stable electrical characteristics is provided. An oxide semiconductor stacked film includes a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer which are sequentially stacked and each of which contains indium, gallium, and zinc. The content percentage of indium in the second oxide semiconductor layer is higher than that in the first oxide semiconductor layer and the third oxide semiconductor layer, and the absorption coefficient of the oxide semiconductor stacked film, which is measured by the CPM, is lower than or equal to 3×10 | 2015-12-03 |
20150349134 | SEMICONDUCTOR DEVICE - There is provided a readily manufacturable semiconductor device including two transistors having mutually different characteristics. The semiconductor device includes a substrate, a multilayer wiring layer disposed over the substrate, a first transistor disposed in the multilayer wiring layer, and a second transistor disposed in a layer different from a layer including the first transistor disposed therein of the multilayer wiring layer, and having different characteristics from those of the first transistor. This can provide a readily manufacturable semiconductor device including two transistors having mutually different characteristics. | 2015-12-03 |
20150349135 | SEMICONDUCTOR DEVICE - A highly reliable semiconductor device is provided. The semiconductor device includes a gate electrode, a gate insulating film over the gate electrode, a semiconductor film overlapping with the gate electrode with the gate insulating film positioned therebetween, a source electrode and a drain electrode that are in contact with the semiconductor film, and an oxide film over the semiconductor film, the source electrode, and the drain electrode. An end portion of the semiconductor film is spaced from an end portion of the source electrode or the drain electrode in a region overlapping with the semiconductor film in a channel width direction. The semiconductor film and the oxide film each include a metal oxide including In, Ga, and Zn. The oxide film has an atomic ratio where the atomic percent of In is lower than the atomic percent of In in the atomic ratio of the semiconductor film. | 2015-12-03 |
20150349136 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Methods for manufacturing semiconductor devices according to embodiments of the present invention may include providing a sacrificial substrate including a wiring region and a device region, sequentially forming a sacrificial layer and a buffer layer on the sacrificial substrate, forming a thin-film transistor on the buffer layer of the device region, forming a device protection element surrounding the thin-film transistor within the device region, forming a flexible substrate on the buffer layer, and exposing a surface of the buffer layer by separating the sacrificial substrate by removing the sacrificial layer. Since typical semiconductor process technologies may be directly used, the process compatibility may be improved, and semiconductor devices having high resolution and high performance may be manufactured. Furthermore, since the thin-film transistor is protected by the device protection element, the deformation of semiconductor devices under flexibility conditions may be prevented, thereby improving the reliability of the semiconductor devices. | 2015-12-03 |
20150349137 | THIN FILM FORMING METHOD, SEMICONDUCTOR SUBSTRATE AND ELECTRONIC DEVICE PRODUCED BY EMPLOYING SAME - The present invention provides a thin film forming method. The method includes the steps of: providing a first substrate, of which a surface is covered with a thin film; forming a plurality of openings through the thin film; forming a hollow portion between the first substrate and the thin film by etching the first substrate through the openings; bringing the thin film into contact with a second substrate with a liquid interposed between the thin film and the second substrate; and heating the first substrate and/or the second substrate. In the step of heating, the liquid interposed between the thin film and the second substrate evaporates off, which results in that the thin film is separated from the first substrate and transferred onto the second substrate. | 2015-12-03 |
20150349138 | FIELD-EFFECT TRANSISTOR, DISPLAY ELEMENT, IMAGE DISPLAY DEVICE, AND SYSTEM - To provide a field-effect transistor, containing: a substrate; a protective layer; a gate insulating layer formed between the substrate and the protective layer; a source electrode and a drain electrode, which are formed to be in contact with the gate insulating layer; a semiconductor layer, which is formed at least between the source electrode and the drain electrode, and is in contact with the gate insulating layer, the source electrode, and the drain electrode; and a gate electrode, which is formed at an opposite side to the side where the semiconductor layer is provided, with the gate insulating layer being between the gate electrode and the semiconductor layer, and is in contact with the gate insulating layer, wherein the protective layer contains a metal oxide composite, which contains at least Si and alkaline earth metal. | 2015-12-03 |
20150349139 | Oxide Thin Film Transistor and Manufacturing Method Thereof, Array Substrate and Display Device - The present invention provides an oxide thin film transistor and a manufacturing method thereof, an array substrate and a display device. The oxide thin film transistor of the present invention comprises a substrate, and a gate, a gate insulation layer, an oxide semiconductor active layer, a source and a drain, which are sequentially formed on the substrate, wherein, the oxide thin film transistor further comprises a transition layer formed between the oxide semiconductor active layer and the source and between the oxide semiconductor active layer and the drain, the transition layer comprises a metal layer and a protective layer, and the protective layer is in contact with the oxide semiconductor active layer, the metal layer is arranged on the protective layer and in contact with the source and the drain, and the protective layer is made of a metal oxide. | 2015-12-03 |
20150349140 | THIN FILM TRANSISTOR, METHOD FOR FABRICATING THE SAME AND DISPLAY APPARATUS - Embodiments of the present invention provide a thin film transistor, method for fabricating the thin film transistor and display apparatus. The method includes steps of: forming an active layer pattern which has a mobility greater than a predetermined threshold from an active layer material; and performing ion implantation on the active layer pattern. The energy of a compound bond formed from the implanted ions is greater than that of a compound bond formed from ions in the active layer material, thereby reducing the chance of vacancy formation and reducing the carrier concentration. Therefore, the mobility of the active layer surface is reduced, the leakage current is reduced, the threshold voltage is adjusted to shift toward positive direction and performance of the thin film transistor is improved. | 2015-12-03 |
20150349141 | THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE, DISPLAY DEVICE - There are provided a thin film transistor and a manufacturing method thereof, an array substrate, a display device. The manufacturing method includes forming a gate electrode, a gate insulating layer, a metal oxide semiconductor active layer, a source electrode and a drain electrode on a substrate. The forming the metal oxide semiconductor active layer includes forming a zinc oxide-based binary metal oxide pattern layer on a substrate. The pattern layer includes a first pattern, a second pattern and a third pattern. Metal doping ions are implanted into the zinc oxide-based binary metal oxide pattern layer by using an ion implantation technology, so that a binary metal oxide of the third pattern is transformed into a multi-element metal oxide semiconductor, and the metal oxide semiconductor active layer is formed. | 2015-12-03 |
20150349142 | SPLIT GATE MEMORY CELL WITH IMPROVED ERASE PERFORMANCE - A semiconductor device includes a semiconductor substrate, a charge storage stack over a portion of the substrate. The charge storage stack includes a first dielectric layer, a layer of nanocrystals in contact with the first dielectric layer, a second dielectric layer over and in contact with the layer of nanocrystals, a nitride layer over and in contact with the second dielectric layer, and a third dielectric layer over the nitride layer. | 2015-12-03 |
20150349143 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An improvement is achieved in the performance of a semiconductor device including a memory element. Over a semiconductor substrate, a gate electrode for the memory element is formed via an insulating film as a gate insulating film for the memory element. The insulating film includes first, second, third, fourth, and fifth insulating films in order of being apart from the substrate. The second insulating film has a charge storing function. The band gap of each of the first and third insulating films is larger than a band gap of the second insulating film. The band gap of the fourth insulating film is smaller than the band gap of the third insulating film. The band gap of the fifth insulating film is smaller than the band gap of the fourth insulating film. | 2015-12-03 |
20150349144 | SEMICONDUCTOR DEVICE - The semiconductor device includes a p-anode region disposed on an n-drift region, and a p-diffusion region disposed so as to be in contact with the p-anode region on the n-drift region. A resistance region disposed so as to be in contact with the p-diffusion region on an n | 2015-12-03 |
20150349145 | SHINGLED SOLAR CELL MODULE - A high efficiency configuration for a solar cell module comprises solar cells arranged in a shingled manner to form super cells, which may be arranged to efficiently use the area of the solar module, reduce series resistance, and increase module efficiency. | 2015-12-03 |
20150349146 | SOLAR CELL - A semiconductor substrate of any one of a first conductivity type and a second conductivity type includes a first main surface and a second main surface. A first semiconductor layer of the first conductivity type is provided on the first main surface. A second semiconductor layer of the second conductivity type is provided on the first main surface. A first electrode is electrically connected to the first semiconductor layer. A second electrode is electrically connected to the second semiconductor layer. An insulating layer comprises silicon nitride and is arranged between the first semiconductor layer and the second semiconductor layer in an overlap region where the second semiconductor layer is provided above the first semiconductor layer. An anti-diffusion film is arranged between the insulating layer and the first semiconductor layer and is configured to prevent nitrogen from diffusing from the insulating layer into the first semiconductor layer. | 2015-12-03 |
20150349147 | Broad Band Anti-Reflection Coating for Photovoltaic Devices and Other Devices - A device having a broad-band, white incident angle range anti-reflection coating disclosed. The device includes a substrate having a first refractive index, at least one interference layer disposed on top of the substrate; and a gradient index optical layer. The gradient index optical layer has a gradient refractive index disposed on top of the at least one high index optical layer. The gradient index optical layer has a bottom refractive index at a bottom surface of the gradient index optical layer and a top refractive index at a top surface of the gradient index optical layer. The gradient refractive index of the gradient index optical layer decreases gradually from the bottom surface to the top surface. The at least one interference layer has a refractive index between the first refractive index of the substrate and the bottom refractive index of the gradient index optical layer. | 2015-12-03 |
20150349148 | AN ELECTRO-CONDUCTIVE PASTE COMPRISING A VANADIUM CONTAINING COMPOUND AND A PHOSPHOROUS CONTAINING MATERIAL IN THE PREPARATION OF ELECTRODES IN MWT SOLAR CELLS - The invention relates to an electro-conductive paste comprising both, a vanadium containing compound and a phosphorus containing material, in the preparation of electrodes in solar cells, particularly in the preparation of electrodes in MWT solar cells, particularly in the preparation of the metal wrap through, or plug, electrode in such solar cells. In particular, the invention relates to a solar cell precursor, a process for preparing a solar cell, a solar cell and a module comprising solar cells. The invention relates to a solar cell precursor at least comprising as precursor parts:
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20150349149 | AN ELECTRO-CONDUCTIVE PASTE COMPRISING ELEMENTAL PHOSPHORUS IN THE PREPARATION OF ELECTRODES IN MWT SOLAR CELLS - The invention relates to an electro-conductive paste comprising elemental phosphorus in the preparation of electrodes in solar cells, particularly in the preparation of electrodes in MWT solar cells, particularly in the preparation of the metal wrap through, or plug, electrode in such solar cells. In particular, the invention relates to a solar cell precursor, a process for preparing a solar cell, a solar cell and a module comprising solar cells. The invention relates to a solar cell precursor at least comprising as precursor parts:
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20150349150 | High Speed Photosensitive Devices and Associated Methods - High speed optoelectronic devices and associated methods are provided. In one aspect, for example, a high speed optoelectronic device can include a silicon material having an incident light surface, a first doped region and a second doped region forming a semiconductive junction in the silicon material, and a textured region coupled to the silicon material and positioned to interact with electromagnetic radiation. The optoelectronic device has a response time of from about 1 picosecond to about 5 nanoseconds and a responsivity of greater than or equal to about 0.4 A/W for electromagnetic radiation having at least one wavelength from about 800 nm to about 1200 nm. | 2015-12-03 |
20150349151 | ARRAY OF MESA PHOTODIODES WITH AN IMPROVED MTF - An array of mesa photodiodes, including a useful layer of Cd | 2015-12-03 |
20150349152 | METHOD FOR METALLIZATION OF SOLAR CELL SUBSTRATES - The present invention relates to a metallization method for solar cell substrates by electroplating wherein i) a resist is deposited onto at least one surface of a solar cell substrate and patterned, ii) a conductive seed layer is deposited onto the patterned resist and into the openings formed by the resist pattern, iii) a first metal or metal alloy is electroplated onto the conductive seed layer, and iv) those portions of the first metal or metal alloy layer deposited onto the patterned resist are removed. | 2015-12-03 |
20150349153 | SHINGLED SOLAR CELL MODULE - A high efficiency configuration for a solar cell module comprises solar cells arranged in a shingled manner to form super cells, which may be arranged to efficiently use the area of the solar module, reduce series resistance, and increase module efficiency. | 2015-12-03 |
20150349154 | ALIGNMENT FREE SOLAR CELL METALLIZATION - A solar cell can include a substrate and a semiconductor region disposed in or above the substrate. The solar cell can also include a contact finger coupled to the semiconductor region via a plurality of weld regions with at least one of the weld regions being a partial weld. | 2015-12-03 |
20150349155 | FOIL-BASED METALLIZATION OF SOLAR CELLS - A solar cell can include a semiconductor region disposed in or above a substrate. The solar cell can also include a contact finger formed over the semiconductor region, where a first weld region couples the contact finger to the semiconductor region. The contact finger can include a first relief structure. | 2015-12-03 |
20150349156 | SOLAR BATTERY CELL AND METHOD OF MANUFACTURING THE SAME - [Problem] To provide a solar battery cell such that higher conversion efficiency than ever before is achieved and conversion efficiency of its front surface and conversion efficiency of its rear surface become almost equivalent in a double-sided light-receiving type solar battery cell. | 2015-12-03 |
20150349157 | THIN FILM COMPOUND SEMICONDUCTOR SOLAR CELLS - Provided is a thin film solar cell including: a substrate on which a rear surface electrode is formed; a light absorbing layer, which is a compound semiconductor, positioned on the rear surface electrode; and a composite layer positioned on the light absorbing layer and contacting the light absorbing layer, wherein the composite layer includes: a conductive mesh; and a semiconductor material filled in at least an empty space of the conductive mesh. | 2015-12-03 |
20150349158 | METHOD OF FORMING CONTACTS FOR A BACK-CONTACT SOLAR CELL - Methods of forming contacts for solar cells are described. In one embodiment, a method includes forming a silicon layer above a substrate, forming and patterning a solid-state p-type dopant source on the silicon layer, forming an n-type dopant source layer over exposed regions of the silicon layer and over a plurality of regions of the solid-state p-type dopant source, and heating the substrate to provide a plurality of n-type doped silicon regions among a plurality of p-type doped silicon regions. | 2015-12-03 |
20150349159 | BENDABLE SOLAR CELL CAPABLE OF OPTIMIZING THICKNESS AND CONVERSION EFFICIENCY - A bendable solar cell capable of optimizing thickness and conversion efficiency, comprising: a solar cell body having a top surface, a bottom surface, and four side walls; and a layer of nanostructures located on said side walls, wherein said solar cell body has a thickness ranging from about 50 μm to about 120 μm, and said layer of nanostructures has a depth ranging from about 2 μm to 8 μm. | 2015-12-03 |
20150349160 | Backside Illuminated Photo-Sensitive Device With Gradated Buffer Layer - A photo-sensitive device includes a uniform layer, a gradated buffer layer over the uniform layer, a silicon layer over the gradated buffer layer, a photo-sensitive light-sensing region in the uniform layer and the silicon layer, a device layer on the silicon layer, and a carrier wafer bonded to the device layer. | 2015-12-03 |
20150349161 | SHINGLED SOLAR CELL MODULE - A high efficiency configuration for a solar cell module comprises solar cells arranged in a shingled manner to form super cells, which may be arranged to efficiently use the area of the solar module, reduce series resistance, and increase module efficiency. | 2015-12-03 |
20150349162 | SHINGLED SOLAR CELL MODULE - A high efficiency configuration for a solar cell module comprises solar cells arranged in a shingled manner to form super cells, which may be arranged to efficiently use the area of the solar module, reduce series resistance, and increase module efficiency. | 2015-12-03 |
20150349163 | ENCAPSULANT FILM - Embodiments of the present application relate to an encapsulant film, a method for manufacturing an encapsulant film, an optoelectronic device, and a method for manufacturing an optoelectronic device, and can provide superior adhesive force with a front substrate and a back sheet, and specifically having long-term adhesive and heat resistance properties. Also, the present application can provide the encapsulant which does not have a negative effect on parts, such as optoelectronic elements or wire electrodes encapsulated in the optoelectronic devices, and on a working environment, and which can maintain superior workability and economic feasibility in device manufacturing. | 2015-12-03 |
20150349164 | IN-CELL BYPASS DIODE - A solar cell can include a built-in bypass diode. In one embodiment, the solar cell can include an active region disposed in or above a first portion of a substrate and a bypass diode disposed in or above a second portion of the substrate. The first and second portions of the substrate can be physically separated with a groove. A metallization structure can couple the active region to the bypass diode. | 2015-12-03 |
20150349165 | SOLAR CELL WITH ABSORBER SUBSTRATE BONDED BETWEEN SUBSTRATES - A solar cell includes a first processed optically transparent (transparent) substrate and a second processed transparent substrate, wherein at least one of the first processed transparent substrate and second processed transparent substrate includes at least one electrode thereon. At least one solar absorber material substrate having a first side and a second side is between the first and second processed transparent substrates. The solar absorber material substrate is bonded by an adhesiveless bonded interface on both the first side and the second side to the first and second processed transparent substrates. | 2015-12-03 |
20150349166 | GROUNDING CLIPS AND TABS FOR MOUNTING COMPONENTS TO SOLAR MODULES - This disclosure generally relates to integrated grounding for solar modules and electrical wire management, and more specifically, to grounding clips and tabs that are integrated into solar module racking systems. | 2015-12-03 |
20150349167 | SHINGLED SOLAR CELL MODULE - A high efficiency configuration for a solar cell module comprises solar cells arranged in a shingled manner to form super cells, which may be arranged to efficiently use the area of the solar module, reduce series resistance, and increase module efficiency. | 2015-12-03 |
20150349168 | SHINGLED SOLAR CELL MODULE - A high efficiency configuration for a solar cell module comprises solar cells arranged in a shingled manner to form super cells, which may be arranged to efficiently use the area of the solar module, reduce series resistance, and increase module efficiency. | 2015-12-03 |
20150349169 | SHINGLED SOLAR CELL MODULE - A high efficiency configuration for a solar cell module comprises solar cells arranged in a shingled manner to form super cells, which may be arranged to efficiently use the area of the solar module, reduce series resistance, and increase module efficiency. | 2015-12-03 |
20150349170 | SHINGLED SOLAR CELL MODULE - A high efficiency configuration for a solar cell module comprises solar cells arranged in a shingled manner to form super cells, which may be arranged to efficiently use the area of the solar module, reduce series resistance, and increase module efficiency. | 2015-12-03 |
20150349171 | SHINGLED SOLAR CELL MODULE - A high efficiency configuration for a solar cell module comprises solar cells arranged in a shingled manner to form super cells, which may be arranged to efficiently use the area of the solar module, reduce series resistance, and increase module efficiency. | 2015-12-03 |
20150349172 | SHINGLED SOLAR CELL MODULE - A high efficiency configuration for a solar cell module comprises solar cells arranged in a shingled manner to form super cells, which may be arranged to efficiently use the area of the solar module, reduce series resistance, and increase module efficiency. | 2015-12-03 |
20150349173 | SHINGLED SOLAR CELL MODULE - A high efficiency configuration for a solar cell module comprises solar cells arranged in a shingled manner to form super cells, which may be arranged to efficiently use the area of the solar module, reduce series resistance, and increase module efficiency. | 2015-12-03 |
20150349174 | SHINGLED SOLAR CELL MODULE - A high efficiency configuration for a solar cell module comprises solar cells arranged in a shingled manner to form super cells, which may be arranged to efficiently use the area of the solar module, reduce series resistance, and increase module efficiency. | 2015-12-03 |
20150349175 | SHINGLED SOLAR CELL PANEL EMPLOYING HIDDEN TAPS - A high efficiency configuration for a solar cell module comprises solar cells arranged in a shingled manner to form super cells, which may be arranged to efficiently use the area of the solar module, reduce series resistance, and increase module efficiency | 2015-12-03 |
20150349176 | HIGH VOLTAGE SOLAR PANEL - A high voltage solar cell module comprises silicon solar cells arranged in a shingled manner to form super cells. A solar photovoltaic system may comprise two or more such high voltage solar cell modules electrically connected in parallel with each other and to an inverter. | 2015-12-03 |
20150349177 | FLUID COOLED INTEGRATED PHOTOVOLTAIC MODULE - A fluid cooled photovoltaic module in which a polymer heat exchanger transfers heat from the photovoltaic module to a circulated fluid. The photovoltaic module is maintained at a cool temperature enabling increased power output while the heat transferred to the circulated fluid can be useful for applications that require heat. A polymer heat exchanger is specifically utilized to achieve a robust design that is cost effective; high performance; easily adaptable to various photovoltaic module types and sizes; compatible with conventional photovoltaic module balance of systems; light weight; resistant to water sanitizers and other chemicals; resistant to lime-scale buildup and heat exchanger fouling; corrosion resistant; easily transported, assembled, installed, and maintained; and leverages high production manufacturing methods. | 2015-12-03 |
20150349178 | FLUID COOLED INTEGRATED PHOTOVOLTAIC MODULE - A fluid cooled photovoltaic module in which a polymer heat exchanger transfers heat from the photovoltaic module to a circulated fluid. The photovoltaic module is maintained at a cool temperature enabling increased power output while the heat transferred to the circulated fluid can be useful for applications that require heat. A polymer heat exchanger is specifically utilized to achieve a robust design that is cost effective; high performance; easily adaptable to various photovoltaic module types and sizes; compatible with conventional photovoltaic module balance of systems; light weight; resistant to water sanitizers and other chemicals; resistant to lime-scale buildup and heat exchanger fouling; corrosion resistant; easily transported, assembled, installed, and maintained; and leverages high production manufacturing methods. | 2015-12-03 |
20150349179 | SOLAR CELL UNIT - A solar cell unit, comprising a solar cell with a light receiving surface, and a transparent optical element frictionally connected to the receiving surface. The optical element having a portion of surface formed substantially convex such that sunlight striking the receiving surface is bundled by the convex receiving surface. The light receiving surface is surrounded by a shoulder-shaped ledge that has a first rim surface and a second rim surface. A first alignment mark is provided in association with the first rim surface and a second alignment mark is provided in association with the second rim surface to position the optical element in regard to the receiving surface of the solar cell via the two alignment marks. The first alignment mark being spaced apart from the second alignment mark in order to guide the incident sunlight totally or at least largely to the receiving surface. | 2015-12-03 |
20150349180 | RELATIVE DOPANT CONCENTRATION LEVELS IN SOLAR CELLS - A solar cell may include a substrate having a front side facing the sun to receive solar radiation during normal operation and a backside opposite the front side. The solar cell may further include a polysilicon layer formed over the backside of the substrate. A P-type diffusion region and an N-type diffusion region may be formed in the polysilicon layer to provide a butting PN junction. The P-type diffusion region may have a first dopant concentration level and the N-type diffusion region may have a second dopant concentration level such that the first dopant concentration level is less than the second dopant concentration level. | 2015-12-03 |
20150349181 | METHOD FOR ETCHING MULTI-LAYER EPITAXIAL MATERIAL - A single-step wet etch process is provided to isolate multijunction solar cells on semiconductor substrates, wherein the wet etch chemistry removes semiconductor materials nonselectively without a major difference in etch rate between different heteroepitaxial layers. The solar cells thus formed comprise multiple heterogeneous semiconductor layers epitaxially grown on the semiconductor substrate. | 2015-12-03 |
20150349182 | PHOTOCONDUCTIVE SWITCH - A photoconductive switch comprising a photoconductive material and first and second contacts provided on said photoconductive material, wherein said first and second contacts comprise a plurality of interdigitated tracks, the tracks of each contact being separated from the tracks of the other contact by a photoconductive gap, the tracks being curved such that the minimum photoconductive gap measured in a first direction remains substantially similar regardless of the orientation of the first direction. | 2015-12-03 |
20150349183 | MICROWAVE SIGNAL SWITCHING DEVICE, PARTICULARLY OF NANOMETRIC SIZE, AND ELECTRONIC COMPONENT INCORPORATING SUCH A DEVICE - A device for switching an electrical signal, controlled by an optical wave and having an on state and an off state, which can be inserted into a microwave transmission line, comprises a semiconductor substrate on which two conductive tracks are formed, these tracks being separated by a gap providing electrical insulation between the two tracks and each being connected to an input port and an output port, in the on state the electrical contact between the two tracks being established by illuminating the substrate in the region of the gap by means of the optical wave, the input impedance and the output impedance of said switching device being mismatched to the impedance of the transmission line in the off state and are matched to the impedance of the transmission line in the on state. | 2015-12-03 |
20150349184 | PHOTOSENSING DEVICE WITH GRAPHENE - A photosensing device with a photovoltage sensing mechanism, a graphene layer and a semiconductor layer. The graphene layer is sandwiched between the semiconductor layer and a substrate. The photovoltage sensing mechanism senses the photovoltage created by light impinging on the graphene-semiconductor heterojunction. The strength of the photovoltage is used to indicate the level of illumination of the impinging light. | 2015-12-03 |
20150349185 | PHOTOSENSING DEVICE WITH GRAPHENE - A photosensing device with a photovoltage sensing mechanism, a graphene layer and a semiconductor layer. The graphene layer is sandwiched between the semiconductor layer and a substrate. The photovoltage sensing mechanism senses the photovoltage created by light impinging on the graphene-semiconductor heterojunction. The strength of the photovoltage is used to indicate the level of illumination of the impinging light. | 2015-12-03 |
20150349186 | PHOTOTRANSISTOR WITH BODY-STRAPPED BASE - A photosensing device with a photovoltage sensing mechanism, a graphene layer and a semiconductor layer. The graphene layer is sandwiched between the semiconductor layer and a substrate. The photovoltage sensing mechanism senses the photovoltage created by light impinging on the graphene-semiconductor heterojunction. The strength of the photovoltage is used to indicate the level of illumination of the impinging light. | 2015-12-03 |
20150349187 | POWER SEMICONDUCTOR DEVICE - A semiconductor device suitable for power applications includes a thyristor epitaxial layer structure defining an anode region offset vertically from a cathode region with a plurality of intermediate regions therebetween. An anode electrode is electrically coupled to the anode region. A cathode electrode is electrically coupled to the cathode region. A switchable current path that extends vertically between the anode region and the cathode region has a conducting state and a non-conducting state. An epitaxial resistive region is electrically coupled to and extends laterally from one of the plurality of intermediate regions. An FET is provided having a channel that is electrically coupled to the epitaxial resistive region. The FET can be configured to inject (or remove) electrical carriers into (or from) the one intermediate region via the epitaxial resistive region in order to switch the switchable current path between its non-conducting state and its conducting state. | 2015-12-03 |
20150349188 | AFFECTING THE THERMOELECTRIC FIGURE OF MERIT (ZT) AND THE POWER FACTOR BY HIGH PRESSURE, HIGH TEMPERATURE SINTERING - A method for increasing the ZT of a semiconductor, involves creating a reaction cell including a semiconductor in a pressure-transmitting medium, exposing the reaction cell to elevated pressure and elevated temperature for a time sufficient to increase the ZT of the semiconductor, and recovering the semiconductor with an increased ZT. | 2015-12-03 |
20150349189 | SOLAR CELL MODULE PRODUCTION METHOD, AND SOLAR CELL MODULE ADHESIVE APPLICATION SYSTEM - A solar cell module production method involves applying an adhesive on a light-receiving surface and a rear surface of a solar cell having electrodes on the light-receiving surface and the rear surface, and positioning and attaching a wiring material on the adhesive. Specifically, the solar cell, which is positioned with the light-receiving surface facing upward, is inverted so that the rear surface is facing upward, and the adhesive is applied on the rear surface; and then the solar cell is inverted once again so that the light-receiving surface is facing upward, and the adhesive is applied to the light-receiving surface. | 2015-12-03 |
20150349190 | SHINGLED SOLAR CELL MODULE - A high efficiency configuration for a solar cell module comprises solar cells arranged in a shingled manner to form super cells, which may be arranged to efficiently use the area of the solar module, reduce series resistance, and increase module efficiency. | 2015-12-03 |
20150349191 | METHOD FOR PRODUCING A THICK CRYSTALLINE LAYER - The process wherein steps consisting in: a) implanting ionic species through a substrate with at least on its surface, a crystalline layer of Si | 2015-12-03 |
20150349192 | LIGHT DETECTION DEVICE - A method of forming a light detection device includes forming a non-porous layer on a substrate, forming a light absorption layer on the non-porous layer, the light absorption layer including pores formed in a surface thereof, forming a Schottky layer on the surface of the light absorption layer and in the pores thereof, and forming a first electrode layer on the Schottky layer. | 2015-12-03 |
20150349193 | SHINGLED SOLAR CELL MODULE - A high efficiency configuration for a solar cell module comprises solar cells arranged in a shingled manner to form super cells, which may be arranged to efficiently use the area of the solar module, reduce series resistance, and increase module efficiency. | 2015-12-03 |
20150349194 | NANOSTRUCTURE MATERIAL METHODS AND DEVICES - In one aspect, structures are provided comprising: a substrate having a first surface and a second surface; and a polymeric layer disposed on the first surface of the substrate, the polymeric layer comprising a polymer and a plurality of light-emitting nanocrystals; the polymeric layer having a patterned surface, the patterned surface having a patterned first region having a first plurality of recesses and a patterned second region having a second plurality of recesses, wherein the plurality of recesses in each region has a first periodicity in a first direction, and a second periodicity in a second direction which intersects the first direction, wherein the first periodicity of the first region is different from the first periodicity of the second region. | 2015-12-03 |
20150349195 | FLIP-CHIP LED AND FABRICATION METHOD THEREOF - A flip-chip LED and a method for forming the LED are disclosed. The method includes: providing a substrate and depositing on the substrate an epitaxial layer including, from the bottom upward, an n-type GaN layer, a multi-quantum well active layer, and a p-type GaN layer; etching the epitaxial layer to form an array of openings exposing the n-type GaN layer; forming a first metal layer on the p-type GaN layer; annealing the first metal layer to induce self-assembly thereof; etching the p-type GaN layer by using the first metal layer as a mask such that an array of holes formed therein; and depositing a second metal layer over the array of holes, the second metal layer and the first metal layer form a metal reflector layer. The design can result in an improvement in the light extraction efficiency of the LED. | 2015-12-03 |
20150349196 | NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING SAME - Disclosed herein are a nitride semiconductor light-emitting device and a method of manufacturing the same, which are capable of reducing the number of masks by introducing a three-mask process so that the processing becomes simpler and the production yield can be improved. | 2015-12-03 |
20150349197 | NITRIDE SEMICONDUCTOR LIGHT-EMITTING ELEMENT - Provided is a nitride semiconductor light-emitting element including in order a first n-type nitride semiconductor layer, a second n-type nitride semiconductor layer, an n-type electron-injection layer, a light-emitting layer, and a p-type nitride semiconductor layer, wherein the average n-type dopant concentration of the second n-type nitride semiconductor layer is 0.53 times or less as high as the average n-type dopant concentration of the first n-type nitride semiconductor layer, and the average n-type dopant concentration of the n-type electron-injection layer is 1.5 times or more as high as the average n-type dopant concentration of the second n-type nitride semiconductor layer. | 2015-12-03 |
20150349198 | SEMICONDUCTOR LIGHT EMITTING ELEMENT AND OPTICAL COHERENCE TOMOGRAPHY APPARATUS - The semiconductor light emitting element, includes a multiple quantum well active layer including a first quantum well and a second quantum well having well widths different from each other. Well layers of the first quantum well and the second quantum well are formed of In | 2015-12-03 |
20150349199 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND WAFER - According to one embodiment, a semiconductor light emitting device includes: a foundation layer, a first semiconductor layer, a light emitting part, and a second semiconductor layer. The foundation layer includes a nitride semiconductor. The foundation layer has a dislocation density not more than 5×10 | 2015-12-03 |
20150349200 | MICRO-LIGHT-EMITTING DIODE - A micro-light-emitting diode (micro-LED) includes a first type semiconductor layer, a second type semiconductor, a first current controlling layer, a first electrode, and a second electrode. The second type semiconductor layer and the first current controlling layer are joined with the first type semiconductor layer. The first current controlling layer has at least one opening therein. The first electrode is electrically coupled with the first type semiconductor layer through the opening. The second electrode is electrically coupled with the second type semiconductor layer. At least one of the first electrode and the second electrode has a light-permeable part. A vertical projection of the first current controlling layer on said one of the first electrode and the second electrode overlaps with the light-permeable part. The light-permeable part is transparent or semi-transparent. | 2015-12-03 |
20150349201 | METHOD OF MANUFACTURING LIGHT EMITTING DEVICE PACKAGE - A method of manufacturing a light emitting device package includes forming on a growth substrate a light emitting structure including a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer. First and second electrodes are formed on the light emitting structure to be connected to the first and second conductivity-type semiconductor layers, respectively. A first bonding layer is formed on the light emitting structure, and is polished A second bonding layer is formed on the polished first bonding layer, and a support substrate is bonded to the light emitting structure using the first and second bonding layers. | 2015-12-03 |
20150349202 | SEMICONDUCTOR LIGHT-EMITTING ELEMENT - A semiconductor light-emitting element includes a substrate and a semiconductor stack portion provided on the substrate and having at least a first-conductivity-type semiconductor layer, a light-emitting layer, and a second-conductivity-type semiconductor layer. The substrate has a property to allow transmission of light from the light-emitting layer, and has a hexahedral shape including a first surface on which a semiconductor stack portion is provided, a second surface located opposite to the first surface, a pair of third surfaces orthogonal to the first surface and the second surface, and a pair of fourth surfaces orthogonal to the first surface and the second surface and different from the pair of third surfaces. | 2015-12-03 |
20150349203 | NITRIDE SEMICONDUCTOR ELEMENT AND METHOD FOR MANUFACTURING THE SAME - A nitride semiconductor element includes a sapphire substrate including: a main surface extending in a c-plane of the sapphire substrate, and a plurality of projections disposed at the main surface, the plurality of projections including at least one projection having an elongated shape in a plan view; and a nitride semiconductor layer disposed on the main surface of the sapphire substrate. The at least one projection has an outer edge extending in a longitudinal direction of the elongated shape, the outer edge extending in a direction oriented at an angle in a range of −10° to +10° with respect to an a-plane of the sapphire substrate in the plan view. | 2015-12-03 |
20150349204 | EPITAXIAL DEVICES - Epitaxial growth methods and devices are described that include a textured surface on a substrate. Geometry of the textured surface provides a reduced lattice mismatch between an epitaxial material and the substrate. Devices formed by the methods described exhibit better interfacial adhesion and lower defect density than devices formed without texture. Silicon substrates are shown with gallium nitride epitaxial growth and devices such as LEDs are formed within the gallium nitride. | 2015-12-03 |
20150349205 | MICRO-LIGHT-EMITTING DIODE - A micro-light-emitting diode (micro-LED) includes a first type semiconductor layer, a second type semiconductor layer, a first edge isolation structure, a first electrode, and a second electrode. The second type semiconductor layer and the first edge isolation structure are joined with the first type semiconductor layer. The first electrode is electrically coupled with the first type semiconductor layer. At least a part of a vertical projection of an edge of the first type semiconductor layer on the first electrode overlaps with the first electrode. The first edge isolation structure is at least partially located on the part of the first type semiconductor layer. The second electrode is electrically coupled with the second type semiconductor layer. | 2015-12-03 |
20150349206 | Diode for a Printable Composition - An exemplary printable composition of a liquid or gel suspension of diodes comprises a plurality of diodes, a first solvent and/or a viscosity modifier. An exemplary diode comprises: a light emitting or absorbing region having a diameter between about 20 and 30 microns and a height between 2.5 to 7 microns; a plurality of first terminals spaced apart and coupled to the light emitting region peripherally on a first side, each first terminal of the plurality of first terminals having a height between about 0.5 to 2 microns; and one second terminal coupled centrally to a mesa region of the light emitting region on the first side, the second terminal having a height between 1 to 8 microns. | 2015-12-03 |
20150349207 | LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A light-emitting device includes a semiconductor light-emitting element, a first resin layer, a first metallic layer, a second resin layer, and a second metallic layer. The semiconductor light-emitting element includes a semiconductor stacked body and an electrode provided on one side of the semiconductor stacked body. The second resin layer is provided on the first resin layer and has a lower surface in contact with the first resin layer and an upper surface opposite to the lower surface. The second metallic layer is provided in the second resin layer and has a metallic lower surface and a metallic upper surface opposite to the metallic lower surface. The metallic upper surface is exposed from the second resin layer. The metallic upper surface of the second metallic layer is at least partially lower in height from the semiconductor stacked body than the upper surface of the second resin layer. | 2015-12-03 |
20150349208 | LIGHT EMITTING DEVICE AND METHOD FOR FABRICATING THE SAME - Provided herein is a semiconductor light emitting device capable of increasing the light extraction efficiency and a fabricating method thereof, the device including a buffer layer formed on a substrate; an n-type semiconductor layer formed on the buffer; an active layer formed on a partial area of the n-type semiconductor layer such that the n-type semiconductor layer is exposed; a p-type semiconductor layer formed on the active layer; a transparent conductive layer formed on the p-type semiconductor layer; a first mesa surface formed along a side wall of the active layer from a side wall of the transparent conductive layer; a passivation layer formed along the first mesa surface; and a metal reflectance film formed along the passivation layer such that it re-reflects escaping light, thereby re-reflecting escaping light to increase the light extraction efficiency. | 2015-12-03 |
20150349209 | LIGHT-EMITTING ELEMENT - A light-emitting element includes a semiconductor laminate including a light-emitting layer, a transparent electrode layer formed on the semiconductor laminate, the transparent electrode layer including an oxide including indium, a pad electrode formed on the transparent electrode layer so as to connect to the transparent electrode layer, and a reflective layer including aluminum. The reflective layer is formed under the pad electrode so as not to contact the transparent electrode layer. | 2015-12-03 |
20150349210 | HIGH BRIGHTNESS LIGHT EMITTING DIODE STRUCTURE AND THE MANUFACTURING METHOD THEREOF - A light-emitting diode structure comprises a first semiconductor layer; a second semiconductor layer under the first semiconductor layer; a light-emitting layer between the first semiconductor layer and the second semiconductor layer for emitting a light; a first electrical pad on the first semiconductor layer for wire bonding; a first extension connecting to the first electrical pad; and a first reflective layer covering the first extension and exposing the first electrical pad, wherein the first electrical pad and the first extension have the same thickness, and the reflectivity of the first reflective layer is higher than that of the first extension. | 2015-12-03 |
20150349211 | LED LIGHT SOURCE PACKAGING METHOD, LED LIGHT SOURCE PACKAGE STRUCTURE AND LIGHT SOURCE MODULE - A method for packaging LED light source, a package structure of LED light source and a light source module are provided. The method for packaging LED light source includes providing a substrate integrated with LED chips, where a surface of the substrate is provided with a filling layer configured to cover the LED chips; printing, on the a surface of the filling layer, phosphor patterns to cover the surface of the filling layer, where the phosphor patterns include one or more first phosphor patterns, one or more second phosphor patterns and one or more third phosphor patterns, where every two of the first, the second and the third phosphor patterns are adjacent to each other. The package structure of LED light source and the light source module have good uniformity of light-emission and low cost, and the process of the method for packaging LED light source is simple. | 2015-12-03 |
20150349212 | NANOSTRUCTURE MATERIAL METHODS AND DEVICES - In one aspect, structures are provided comprising: a substrate having a first surface and a second surface; and a polymeric layer disposed on the first surface of the substrate, the polymeric layer comprising a polymer and a plurality of light-emitting nanocrystals; the polymeric layer having a patterned surface, the patterned surface having a patterned first region having a first plurality of recesses and a patterned second region having a second plurality of recesses, wherein the plurality of recesses in each region has a first periodicity in a first direction, and a second periodicity in a second direction which intersects the first direction, wherein the first periodicity of the first region is different from the first periodicity of the second region. | 2015-12-03 |
20150349213 | RED PHOSPHOR AND LIGHT EMITTING DEVICE INCLUDING THE SAME - A red phosphor including the composition represented by the following general formula. | 2015-12-03 |
20150349214 | Optoelectronic Semiconductor Chip - An optoelectronic semiconductor chip, comprising: a semiconductor layer sequence having an active zone for generating a light radiation; and a conversion structure, comprising conversion regions for converting the generated light radiation, non-converting regions being arranged between said conversion regions. | 2015-12-03 |
20150349215 | Optoelectronic Semiconductor Chip - An optoelectronic semiconductor chip includes a number of active elements arranged at a distance from one another. A carrier is arranged transversely of the active elements. The active elements each have a main axis that extends perpendicularly to the carrier and are oriented parallel to one another. A converter material surrounds the active elements on circumferential faces. The converter material includes a conversion substance or a conversion substance and a matrix material. The active elements each have a central core region that is enclosed by at least two layers such that an active layer encloses the core region and a cover layer encloses the active layer. The core region is formed with a first semiconductor material. The active layer includes a light-emitting material. The cover layer is formed with a second semiconductor material and can have a layer thickness between 0.1 nm and 100 n. | 2015-12-03 |