49th week of 2013 patent applcation highlights part 19 |
Patent application number | Title | Published |
20130320472 | BACKSIDE ILLUMINATION CMOS IMAGE SENSOR AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a backside illumination image sensor includes forming an epitaxial layer on a silicon (Si) substrate, and forming an inter-metal dielectric (IMD) on the epitaxial layer. The method includes forming a trench in one side region of the epitaxial layer, forming an insulating layer at a side wall and bottom of the trench, forming a color filter and microlens on the IMD, bonding a support wafer onto the IMD with the color filter and microlens formed therein, and/or removing the Si substrate. | 2013-12-05 |
20130320473 | SOLID-STATE IMAGING DEVICE, PRODUCTION METHOD OF THE SAME, AND IMAGING APPARATUS - A solid-state imaging device in which a pixel circuit formed on the first surface side of a semiconductor substrate is shared by a plurality of light reception regions and second surface side of the semiconductor substrate is the light incident side of the light reception regions. The second surface side regions of the light reception regions are arranged at approximately even intervals and the first surface side regions of the light reception regions e are arranged at uneven intervals. Respective second surface side regions and first surface side regions are joined in the semiconductor substrate so that the light reception regions extend from the second surface side to the first surface side of the semiconductor substrate. | 2013-12-05 |
20130320474 | PHOTO DETECTOR DEVICE, PHOTO SENSOR AND SPECTRUM SENSOR - A photodetector device includes: a first semiconductor region of a first conductivity type electrically connected to a first external electrode: a second semiconductor region of a second conductivity type formed on the first semiconductor region; a third semiconductor region of the first conductivity type formed on the second semiconductor region; and a plurality of fourth semiconductor regions of the second conductivity type formed on the second semiconductor region, each of the plurality of fourth semiconductor regions being surrounded by the third semiconductor region, including a second conductivity type impurity having a concentration higher than a concentration of the second semiconductor region, and electrically connected to a second external electrode. | 2013-12-05 |
20130320475 | SEMICONDUCTOR APPARATUS, METHOD OF MANUFACTURING SEMICONDUCTOR APPARATUS, METHOD OF DESIGNING SEMICONDUCTOR APPARATUS, AND ELECTRONIC APPARATUS - A semiconductor device including a first material layer adjacent to a second material layer, a first via passing through the first material layer and extending into the second material layer, and a second via extending into the first material layer, where along a common cross section parallel to an interface between the two material layers, the first via has a cross section larger than that of the second via. | 2013-12-05 |
20130320476 | Miniaturized Implantable Sensor Platform Having Multiple Devices and Sub-Chips - An implantable, miniaturized platform and a method for fabricating the platform is provided, where the e platform includes a top cover plate and a bottom substrate, top cover plate including an epitaxial, Si-encased substrate and is configured to include monolithically grown devices and device contact pads, the Si-encased substrate cover plate including a gold perimeter fence deposited on its Si covered outer rim and wherein the bottom substrate is constructed of Si and includes a plurality of partial-Si-vias (PSVs), electronic integrated circuits, device pads, pad interconnects and a gold perimeter fence, wherein the device pads are aligned with a respective device contact pad on the top cover plate and includes gold bumps having a predetermined height, the top cover plate and the bottom substrate being flip-chip bonded to provide a perimeter seal and to ensure electrical connectivity between the plurality of internal devices and at least one external component. | 2013-12-05 |
20130320477 | METHOD OF ETCHING OF SOI SUBSTRATE, AND BACK-ILLUMINATED PHOTOELECTRIC CONVERSION MODULE ON SOI SUBSTRATE AND PROCESS OF MANUFACTURE THEREOF - A method of etching capable of rapidly and flatly performing wet etching on a Si substrate using fluonitric acid represented by HF(a)HNO | 2013-12-05 |
20130320478 | System and Method for Processing a Backside Illuminated Photodiode - System and method for processing a semiconductor device surface to reduce dark current and white pixel anomalies. An embodiment comprises a method applied to a semiconductor or photodiode device surface adjacent to a photosensitive region, and opposite a side having circuit structures for the device. A doped layer may optionally be created at a depth of less than about 10 nanometers below the surface of the substrate and may be doped with a boron concentration between about 1 | 2013-12-05 |
20130320479 | IMAGE SENSOR, IMAGE PROCESSING SYSTEM INCLUDING THE IMAGE SENSOR, AND METHOD OF MANUFACTURING THE IMAGE SENSOR - An image sensor includes a photodetector formed in an epitaxial layer, and trench isolations each formed in a direction from a back side of the epitaxial layer to a front side of the epitaxial layer. Each of the trench isolations is filled with at least one insulator, and the insulator is a negative charge material. | 2013-12-05 |
20130320480 | METHODS AND STRUCTURES FOR REDUCING HEAT EXPOSURE OF THERMALLY SENSITIVE SEMICONDUCTOR DEVICES - A semiconductor device comprises an integrated circuit (IC) die having a top side and a back side. The circuit substrate includes a heat source circuit, a heat sensitive circuit, a package substrate coupled to the top side of the circuit substrate, and a plurality of thermally conductive through-silicon vias (TSVs) formed from the back side of the circuit substrate to near but not through the top side of the circuit substrate. | 2013-12-05 |
20130320481 | High Density Pyroelectric Thin Film Infrared Sensor Array and Method of Manufacture Thereof - A method of manufacturing a thermal sensor array comprises: (a) providing a first wafer comprising an integrated circuit; (b) providing a second wafer comprising a carrier substrate, a thermally sensitive layer, a first electrode and a second electrode; (c) applying a polymer to a bonding surface of at least one of the first wafer and the second wafer; (d) contacting the first wafer and the second wafer for a period of time and at a temperature and pressure sufficient to create a bond; (e) removing the carrier substrate; and (f) patterning and etching the thermally sensitive layer, the first electrode and the second electrode to create an array of pixels, wherein the first wafer and the second wafer are bonded without the need for fine alignment of the wafers. | 2013-12-05 |
20130320482 | High-Voltage Monolithic Schottky Device Structure - A semiconductor device includes a pillar formed on a substrate of the same conductivity type. The pillar has a vertical thickness that extends from a top surface down to the substrate. The pillar extends in first and second lateral directions in a loop shape. First and second dielectric regions are disposed on opposite lateral sides of the pillar, respectively. First and second conductive field plates are respectively disposed in the first and second dielectric regions. A metal layer is disposed on the top surface of the pillar, the metal layer forming a Schottky diode with respect to the pillar. When the substrate is raised to a high-voltage potential with respect to both the metal layer and the first and second field plates, the first and second field plates functioning capacitively to deplete the pillar of charge, thereby supporting the high-voltage potential along the vertical thickness of the pillar. | 2013-12-05 |
20130320483 | SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATES WITH ULTRA-THIN SOI LAYERS AND BURIED OXIDES - Semiconductor-on-insulator (SOI) substrates including a buried oxide (BOX) layer having a thickness of less than 300 Å are provided. The (SOI) substrates having the thin BOX layer are provided using a method including a step in which oxygen ions are implanted at high substrate temperatures (greater than 600° C.), and at a low implant energy (less than 40 keV). An anneal step in an oxidizing atmosphere follows the implant step and is performed at a temperature less than 1250° C. The anneal step in oxygen containing atmosphere converts the region containing implanted oxygen atoms formed by the implant step into a BOX having a thickness of less than 300 Å. In some instances, the top semiconductor layer of the SOI substrate has a thickness of less than 300 Å. | 2013-12-05 |
20130320484 | SEMICONDUCTOR DEVICE FORMATION - An apparatus of and method for making a semiconductor structure having a shallow trench isolation (STI) trench with a substantially v-shaped profile, that is the distance between top portions is greater than the distance between bottom portions of shallow trench isolation (STI) structure sidewalls adjacent to the trench, provides for substantially seamless and substantially void-free gate structures. The semiconductor structures are formed by implanting an implantation species into the sidewalls, which allows for the top portions of the sidewalls to be etched away at a greater rate than that of the bottom portions, resulting in the substantially v-shaped profile. And the substantially v-shaped profile allows for subsequent device layers to more easily and smoothly fill in the v-shaped trenches, due to a wider opening toward the tops of the trenches. | 2013-12-05 |
20130320485 | SEMICONDUCTOR DEVICE - An SOI or PSOI device including a device structure having a plurality of doped semiconductor regions. One or more of the doped semiconductor regions is in electrical communication with one or more electrical terminals. The device further includes an insulator layer located between a bottom surface of the device structure and a handle wafer. The device has an insulator trench structure located between a side surface of the device structure and a lateral semiconductor region located laterally with respect to the device structure. The insulator layer and the insulator trench structure are configured to insulate the device structure from the handle wafer and the lateral semiconductor region, and the insulator trench structure includes a plurality of insulator trenches. | 2013-12-05 |
20130320486 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device. The semiconductor device includes a conductive pattern disposed on a semiconductor substrate. First and second conductive lines disposed on the conductive pattern and located at the same level as each other, are provided. An isolation pattern is disposed between the first and second conductive lines. A first vertical structure passing through the first conductive line and conductive pattern is provided. A second vertical structure passing through the second conductive line and conductive patterns is provided. An auxiliary pattern passing through the conductive pattern and in contact with the isolation pattern is provided. | 2013-12-05 |
20130320487 | Semiconductor Device with Trench Structures - A semiconductor body of a semiconductor device includes a doped layer of a first conductivity type and one or more doped zones of a second conductivity type. The one or more doped zones are formed between the doped layer and the first surface of a semiconductor body. Trench structures extend from one of the first and the second opposing surface into the semiconductor body. The trench structures are arranged between portions of the semiconductor body which are electrically connected to each other. The trench structures may be arranged for mitigating mechanical stress, locally controlling charge carrier mobility, locally controlling a charge carrier recombination rate and/or shaping buried diffusion zones. | 2013-12-05 |
20130320488 | SYSTEM AND METHOD FOR FORMING ALUMINUM FUSE FOR COMPATIBILITY WITH COPPER BEOL INTERCONNECT SCHEME - A semiconductor fuse device and a method of fabricating the fuse device including a last metal interconnect layer including at least two discrete metal conductors, an inter-level dielectric layer deposited over the last metal interconnect layer and the at least two discrete metal conductors, a thin wire aluminum fuse connecting the at least two discrete metal conductors, and a fuse opening above the aluminum fuse. | 2013-12-05 |
20130320489 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a fuse pattern disposed over a semiconductor substrate, an epoxy mold compound (EMC) layer disposed over the fuse pattern, a first package substrate disposed over the EMC layer, an insulating film disposed over the first package substrate, and a second package substrate disposed over the insulating film. To the first package substrate, a Vss voltage or a negative voltage lower than the Vss voltage is applied to prevent impurities from migrating to the fuse pattern. | 2013-12-05 |
20130320490 | INDUCTIVE ELEMENT WITH INTERRUPTER REGION AND METHOD FOR FORMING - A semiconductor device structure a semiconductor substrate having a first conductivity type and a top surface. A plurality of first doped regions is at a first depth below the top surface arranged in a checkerboard fashion. The first doped regions are of a second conductivity type. A dielectric layer is over the top surface. An inductive element is over the dielectric layer, wherein the inductive element is over the first doped regions. | 2013-12-05 |
20130320491 | Semiconductor Device Having Features to Prevent Reverse Engineering - It is desirable to design and manufacture electronic chips that are resistant to modern reverse engineering techniques. Disclosed is a method and device that allows for the design of chips that are difficult to reverse engineer using modern teardown techniques. The disclosed device uses devices having the same geometry but different voltage levels to create different logic devices. Alternatively, the disclosed uses devices having different geometries and the same operating characteristics. Also disclosed is a method of designing a chip using these devices. | 2013-12-05 |
20130320492 | SEMICONDUCTOR SUBSTRATE AND METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE - Disclosed herein is a substrate including: a base substrate; an insulating layer formed on an upper portion of the base substrate; a circuit layer formed in a form in which it is buried in the insulating layer; at least one electrode formed on upper portions of the circuit layer and the insulating layer and having a prominence and depression formed at a side thereof; and a dielectric layer formed in a form in which it surrounds the side of the electrode. | 2013-12-05 |
20130320493 | CAPACITOR FOR INTERPOSERS AND METHODS OF MANUFACTURE THEREOF - Capacitor designs for substrates, such as interposers, and methods of manufacture thereof are disclosed. A through via is formed in the interposer, and a capacitor is formed between a lower level metallization layer and a higher level metallization layer. The capacitor may be, for example, a planar capacitor with dual capacitor dielectric layers. | 2013-12-05 |
20130320494 | METAL FINGER CAPACITORS WITH HYBRID METAL FINGER ORIENTATIONS IN STACK WITH UNIDIRECTIONAL METAL LAYERS - A semiconductor die having a plurality of metal layers, including a set of metal layers having a preferred direction for minimum feature size. The set of metal layers are such that adjacent metal layers have preferred directions orthogonal to one another. Finger capacitors formed in the set of metal layers are such that a finger capacitor formed in one metal layer has a finger direction parallel to the preferred direction of that metal layer. In bidirectional metal layers, capacitor fingers may be in either direction. | 2013-12-05 |
20130320495 | Integration of Non-Noble DRAM Electrode - A method for forming a capacitor stack is described. In some embodiments of the present invention, a first electrode structure is comprised of multiple materials. A first material is formed above the substrate. A portion of the first material is etched. A second material is formed above the first material. A portion of the second material is etched. Optionally, the first electrode structure receives an anneal treatment. A dielectric material is formed above the first electrode structure. Optionally, the dielectric material receives an anneal treatment. A second electrode material is formed above the dielectric material. Typically, the capacitor stack receives an anneal treatment. | 2013-12-05 |
20130320496 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a die pad comprised of a metal, and having at least one cutout portion in its peripheral edge portion, and a protruding portion formed by the cutout portion so as to protrude laterally from the peripheral edge portion; an inner lead having at its end a bonding pad that is placed in the cutout portion with an interval between the bonding pad and the die pad; a semiconductor chip held on the die pad so that a center position of the semiconductor chip is located on the protruding portion side with respect to a center position of the die pad; and a wire configured to electrically connect the semiconductor chip to the bonding pad. | 2013-12-05 |
20130320497 | ON-CHIP RESISTOR - An integrated circuit (IC) is disclosed. The IC includes a substrate with a resistor region and a resistor body disposed on the resistor region. A plurality of first resistor contact strips and a plurality of second resistor contact strips are disposed on the resistor body along a first direction. Two adjacent first and second resistor contact strips are separated by a respective one of contact strip spaces. The IC includes a plurality of first terminals and a plurality of second terminals. Each of the first terminals is coupled to a respective one of the first resistor contact strips while each of the second terminals is coupled to a respective one of the second resistor contact strips. A set of the first terminal and the second terminal forms first and second terminals of an on-chip resistor. | 2013-12-05 |
20130320498 | LOW VOLTAGE PROTECTION DEVICES FOR PRECISION TRANSCEIVERS AND METHODS OF FORMING THE SAME - A bi-directional protection device includes a bi-directional NPN bipolar transistor including an emitter/collector formed from a first n-well region, a base formed from a p-well region, and a collector/emitter formed from a second n-well region. P-type active regions are formed in the first and second n-well regions to form a PNPNP structure, which is isolated from the substrate using dual-tub isolation consisting of an n-type tub and a p-type tub. The dual-tub isolation prevents induced latch-up during integrated circuit powered stress conditions by preventing the wells associated with the PNPNP structure from injecting carriers into the substrate. The size, spacing, and doping concentrations of active regions and wells associated with the PNPNP structure are selected to provide fine-tuned control of the trigger and holding voltage characteristics to enable the bi-directional protection device to be implemented in high voltage applications using low voltage precision interface signaling. | 2013-12-05 |
20130320499 | SEMICONDUCTOR DEVICE - By configuring an ESD protection element of an NPN transistor ( | 2013-12-05 |
20130320500 | A bipolar semiconductor component with a fully depletable channel zone - A bipolar semiconductor component, in particular a diode, comprising an anode structure which controls its emitter efficiency in a manner dependent on the current density in such a way that the emitter efficiency is low at small current densities and sufficiently high at large current densities, and an optional cathode structure, which can inject additional holes during commutation, and production methods therefor. | 2013-12-05 |
20130320501 | VARACTORS INCLUDING INTERCONNECT LAYERS - In an embodiment of the present invention is provided a varactor comprising a substrate, a plurality of bottom electrodes positioned on a surface of the substrate separated to form a gap therein, a tunable dielectric material positioned on the surface of the substrate and within the gap, the tunable dielectric at least partially overlaying the plurality of electrodes, and a top electrode in contact with the tunable dielectric. | 2013-12-05 |
20130320502 | SEMICONDUCTOR PROCESSING METHOD AND SEMICONDUCTOR STRUCTURE - A semiconductor processing method that can generate a hole with different diameters, comprising: providing first material and second material different from the first material; and utilizing a etching process to etch the first material and the second material to form a hole through the first material and the second material; wherein the etching process has different etching rates for the first material and the second material such that the hole have different diameters. A semiconductor structure corresponding to the above-mentioned method is also disclosed. | 2013-12-05 |
20130320503 | METHODS AND DEVICES FOR FABRICATING AND ASSEMBLING PRINTABLE SEMICONDUCTOR ELEMENTS - The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations. | 2013-12-05 |
20130320504 | SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS HAVING THROUGH SILICON VIAS - A semiconductor integrated circuit apparatus includes a semiconductor substrate, a plurality of through-silicon vias (TSVs) formed in the semiconductor substrate, and an impedance path blocking unit located between the plurality of TSVs. | 2013-12-05 |
20130320505 | SEMICONDUCTOR REFLOW PROCESSING FOR HIGH ASPECT RATIO FILL - A method for at least partially filling a feature on a workpiece includes obtaining a workpiece including a feature having a high aspect ratio in the range of about 10 to about 80, depositing a first conformal conductive layer in the feature, and thermally treating the workpiece to reflow the first conformal conductive layer in the feature. | 2013-12-05 |
20130320506 | BACK-SIDE CONTACT FORMATION - In one embodiment, a semiconductor is provided comprising a substrate and a plurality of wiring layers and dielectric layers formed on the substrate, the wiring layers implementing a circuit. The dielectric layers separate adjacent ones of the plurality of wiring layers. A first passivation layer is formed on the plurality of wiring layers. A first contact pad is formed in the passivation layer and electrically coupled to the circuit. A wire is formed on the passivation layer and connected to the contact pad. A through silicon via (TSV) is formed through the substrate, the plurality of wiring and dielectric layers, and the passivation layer. The TSV is electrically connected to the wire formed on the passivation layer. The TSV is electrically isolated from the wiring layers except for the connection provided by the metal wire formed on the passivation layer. | 2013-12-05 |
20130320507 | SEMICONDUCTOR DEVICE HAVING PLURAL PATTERNS EXTENDING IN THE SAME DIRECTION - A photomask has a mask blank and a light shielding film formed on the mask blank. The light shielding film includes a plurality of opening traces extending in a first direction. An end of a first opening trace in the first direction and an end of a second opening trace in the first direction are in different positions in the first direction. The second opening trace adjoins the first opening trace. | 2013-12-05 |
20130320508 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes: forming a first electrode on a first semiconductor substrate; coating the semiconductor substrate with an insulating material having a first viscosity at a first temperature, having a second viscosity lower than the first viscosity at a second temperature higher than the first temperature, and having a third viscosity higher than the second viscosity at a third temperature higher than the second temperature; and forming a first insulating film by curing the insulating material. In this method, the forming the first insulating film includes: bringing the insulating material to the second viscosity by heating the insulating material under a first condition; and bringing the insulating material to the third viscosity by heating the insulating material under a second condition. The first condition and the second condition are different in their temperature rising rate. | 2013-12-05 |
20130320509 | MOISTURE BARRIER COATINGS - A moisture barrier coating for protecting a substrate from moisture, comprises an inorganic layer disposed over the substrate, the inorganic layer comprising an oxide or nitride of an element selected from the group consisting of silicon, aluminum, titanium, zirconium, hafnium and combinations thereof; and an organic silicon-containing layer disposed over the inorganic layer. | 2013-12-05 |
20130320510 | DURABLE, HEAT-RESISTANT MULTI-LAYER COATINGS AND COATED ARTICLES - An article having a surface treated to provide a protective coating structure in accordance with the following method: vapor depositing a first layer on a substrate, wherein said first layer is a metal oxide adhesion layer selected from the group consisting of an oxide of a Group IIIA metal element, a Group IVB metal element, a Group VB metal element, and combinations thereof; vapor depositing a second layer upon said first layer, wherein said second layer includes a silicon-containing layer selected from the group consisting of silicon oxide, silicon nitride, and silicon oxynitride; and vapor depositing a third layer upon said second layer, wherein said third layer is a functional organic-comprising layer, wherein said functional organic-comprising layer is a SAM. | 2013-12-05 |
20130320511 | SEMICONDUCTOR DEVICE - A semiconductor device including a p or p+ doped portion and an n or n+ doped portion separated from the p or p+ doped portion by a semiconductor drift portion. The device further includes at least one termination portion provided adjacent to the drift portion. The at least one termination portion comprises a Super Junction structure. | 2013-12-05 |
20130320512 | Semiconductor Device and Method of Manufacturing a Semiconductor Device - A method of manufacturing a semiconductor device includes forming a trench in a semiconductor body. The method further includes doping a part of the semiconductor body via sidewalls of the trench by plasma doping. | 2013-12-05 |
20130320513 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package is provided, including: a substrate having at least a conductive pad; a semiconductor element disposed on the substrate; a conductive adhesive formed on top and side surfaces of the semiconductor element and extending to the conductive pad; and an electronic element disposed on the conductive adhesive. The conductive adhesive and the conductive pad form a shielding structure so as to prevent electromagnetic interference from occurring between the semiconductor element and the electronic element. | 2013-12-05 |
20130320514 | Package-in-Package for High Heat Dissipation Having Leadframes and Wire Bonds - A semiconductor system ( | 2013-12-05 |
20130320515 | SYSTEM, METHOD AND APPARATUS FOR LEADLESS SURFACE MOUNTED SEMICONDUCTOR PACKAGE - A packaged semiconductor device may include a termination surface having terminations configured as leadless interconnects to be surface mounted to a printed circuit board. A first flange has a first surface and a second surface. The first surface provides a first one of the terminations, and the second surface is opposite to the first surface. A second flange also has a first surface and a second surface, with the first surface providing a second one of the terminations, and the second surface is opposite to the first surface. A die is mounted to the second surface of the first flange with a material having a melting point in excess of 240° C. An electrical interconnect extends between the die and the second surface of the second flange opposite the termination surface, such that the electrical interconnect, first flange and second flange are substantially housed within a body. | 2013-12-05 |
20130320516 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - Disclosed herein are a semiconductor package and a method of manufacturing the same, the semiconductor package including: a molding member having a cavity formed therein; a device mounted in the cavity; an insulating member formed inside the cavity and on and/or beneath the molding member and the device; a circuit layer formed on the insulating member, and including vias and connection pads electrically connected with the device; a solder resist layer formed on the circuit layer, and having openings exposing upper portions of the connection pads; and solder balls formed in the openings. | 2013-12-05 |
20130320517 | LIDDED INTEGRATED CIRCUIT PACKAGE - A lid comprising a heat conductive substrate and a native silicon oxide layer connected to said substrate by at least one intermediate layer; a lidded integrated circuit package; and a method of providing a heat path through an integrated circuit package comprising providing a substrate with an exterior layer of native silicon oxide and interfacing the layer of native silicon oxide with a layer of thermal interface material. | 2013-12-05 |
20130320518 | WAFER-LEVEL PACKAGE AND METHOD OF MANUFACTURING THE SAME - A wafer-level package and a method of manufacturing the same. The wafer-level package includes a first semiconductor chip on an upper side of which an active surface facing downward is disposed, a redistribution formed on the active surface of the first semiconductor chip, a second semiconductor chip disposed on the redistribution using a flip-chip bonding (FCP) technique, a copper (Cu) post and a first solder ball sequentially disposed on the redistribution, a molding member formed on the active surface of the first semiconductor chip to expose a bottom surface of the first solder ball and an inactive surface of the second semiconductor chip, and a second solder ball disposed on the first solder ball and electrically connected to an external apparatus. | 2013-12-05 |
20130320519 | Semiconductor Device and Method of Backgrinding and Singulation of Semiconductor Wafer while Reducing Kerf Shifting and Protecting Wafer Surfaces - A semiconductor device has a semiconductor wafer with an interconnect structure formed over a first surface of the wafer. A trench is formed in a non-active area of the semiconductor wafer from the first surface partially through the semiconductor wafer. A protective coating is formed over the first surface and into the trench. A lamination tape is applied over the protective coating. A portion of a second surface of the semiconductor wafer is removed by backgrinding or wafer thinning to expose the protecting coating in the trench. A die attach film is applied over the second surface of the semiconductor wafer. A cut or modified region is formed in the die attach film under the trench using a laser. The semiconductor wafer is expanded to separate the cut or modified region of the die attach film and singulate the semiconductor wafer. | 2013-12-05 |
20130320520 | CHEMICALLY ALTERED CARBOSILANES FOR PORE SEALING APPLICATIONS - A method including forming a dielectric material including a surface porosity on a circuit substrate including a plurality of devices; chemically modifying a portion of the surface of the dielectric material with a first reactant; reacting the chemically modified portion of the surface with a molecule that, once reacted, will be thermally stable; and forming a film including the molecule. An apparatus including a circuit substrate including a plurality of devices; a plurality of interconnect lines disposed in a plurality of layers coupled to the plurality of devices; and a plurality of dielectric layers disposed between the plurality of interconnect lines, wherein at least one of the dielectric layers comprises a porous material surface relative to the plurality of devices and the surface comprises a pore obstructing material. | 2013-12-05 |
20130320521 | RELEASABLE BURIED LAYER FOR 3-D FABRICATION AND METHODS OF MANUFACTURING - A releasable buried layer for 3-D fabrication and methods of manufacturing is disclosed. The method includes forming an interposer structure which includes forming a carbon rich dielectric releasable layer over a wafer. The method further includes forming back end of the line (BEOL) layers over the carbon rich dielectric layer, including wiring layers and solder bumps. The method further includes bonding the solder bumps to a substrate using flip chip processes. The flip chip processes comprises reflowing the solder bumps and rapidly cooling down the solder bumps which releases the carbon rich dielectric releasable layer from the wafer. | 2013-12-05 |
20130320522 | Re-distribution Layer Via Structure and Method of Making Same - An embodiment is a semiconductor device comprising a contact pad over a substrate, wherein the contact pad is disposed over an integrated circuit on the substrate and a first passivation layer over the contact pad. A first via in the first passivation layer, wherein the first via has more than four sides, and wherein the first via extends to the contact pad. | 2013-12-05 |
20130320523 | Semiconductor Device and Method of Reflow Soldering for Conductive Column Structure in Flip Chip Package - A semiconductor device comprises a substrate and a semiconductor die. Bumps are formed over the substrate or a first surface of the semiconductor die. Conductive columns devoid of solder are formed over the substrate or the first surface of the semiconductor die. The semiconductor die is disposed over the substrate. A collet including a first cavity and a second cavity formed in a surface of the first cavity is mounted over the semiconductor die with a second surface of the semiconductor die opposite the first surface disposed within the first cavity. The bumps are reflowed. A force is applied to the collet to hold the bumps to the conductive columns while reflowing the bumps to make electrical connection to the conductive columns. The collet is removed. An underfill material is deposited between the semiconductor die and substrate. An encapsulant is deposited over the semiconductor die and substrate. | 2013-12-05 |
20130320524 | Design Scheme for Connector Site Spacing and Resulting Structures - A system and method for preventing cracks in a passivation layer is provided. In an embodiment a contact pad has a first diameter and an opening through the passivation layer has a second diameter, wherein the first diameter is greater than the second diameter by a first distance of about 10 μm. In another embodiment, an underbump metallization is formed through the opening, and the underbump metallization has a third diameter that is greater than the first diameter by a second distance of about 5 μm. In yet another embodiment, a sum of the first distance and the second distance is greater than about 15 μm. | 2013-12-05 |
20130320525 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SUBSTRATE AND METHOD OF MANUFACTURE THEREOF - An integrated circuit packaging system and method of manufacture thereof includes: a substrate having a top insulation layer and a top conductive layer; an inter-react layer on the substrate; an integrated circuit die on the substrate; a package body on the inter-react layer and the integrated circuit die; and a top solder bump on the top conductive layer, the top solder bump in a 3D via formed through the package body, the inter-react layer, and the top insulation layer for exposing the top conductive layer in the 3D via. | 2013-12-05 |
20130320526 | SEMICONDUCTOR CONSTRUCT AND MANUFACTURING METHOD THEREOF AS WELL AS SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor construct includes a semiconductor substrate and connection pads provided on the semiconductor substrate. Some of the connection pads are connected to a common wiring and at least one of the remaining of the connection pads are connected to a wiring. The construct also includes a first columnar electrode provided to be connected to the common wiring and a second columnar electrode provided to be connected to a connection pad portion of the wiring. | 2013-12-05 |
20130320527 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device includes a semiconductor chip, and a terminal connected with the semiconductor chip. The terminal has a first surface and a second surface spaced from each other in a thickness direction. The semiconductor device also includes a sealing resin covering the semiconductor chip and the terminal. The sealing resin is so configured that the first surface of the terminal is exposed from the sealing resin. The terminal is formed with an opening to be filled with the sealing resin. | 2013-12-05 |
20130320528 | COAXIAL SOLDER BUMP SUPPORT STRUCTURE - A solder bump support structure and method of manufacturing thereof is provided. The solder bump support structure includes an inter-level dielectric (ILD) layer formed over a silicon substrate. The ILD layer has a plurality of conductive vias. The structure further includes a first insulation layer formed on the ILD layer. The solder bump support structure further includes a pedestal member formed on the ILD layer which includes a conductive material formed above the plurality of conductive vias in the ILD layer coaxially surrounded by a second insulation layer. The second insulation layer is thicker than the first insulation layer. The structure further includes a capping under bump metal (UBM) layer formed over, and in electrical contact with, the conductive material and formed over at least a portion of the second insulation layer of the pedestal member. | 2013-12-05 |
20130320529 | REACTIVE BONDING OF A FLIP CHIP PACKAGE - An array of bonding pads including a set of reactive materials is provided on a first substrate. The set of reactive materials is selected to be capable of ignition by magnetic heating induced by time-dependent magnetic field. The magnetic heating can be eddy current heating, hysteresis heating, and/or heating by magnetic relaxation processes. An array of solder balls on a second substrate is brought to contact with the array of bonding pads. A reaction is initiated in the set of magnetic materials by an applied magnetic field. Rapid release of heat during a resulting reaction of the set of reactive materials to form a reacted material melts the solder balls and provides boding between the first substrate and the second substrate. Since the magnetic heating can be localized, the heating and warpage of the substrate can be minimized during the bonding process. | 2013-12-05 |
20130320530 | SEMICONDUCTOR DEVICE WITH REDISTRIBUTED CONTACTS - A surface mount semiconductor device is assembled by positioning an array of semiconductor dies with an array of metallic ground plane members between and beside the semiconductor dies. The arrays of dies and ground plane members are encapsulated in a molding compound. A redistribution layer is formed on the arrays of dies and ground plane members. The redistribution layer has an array of sets of redistribution conductors within a layer of insulating material. The redistribution conductors interconnect electrical contacts of the dies with external electrical contact elements of the device. As multiple devices are formed at the same time, adjacent devices are separated (singulated) by cutting along saw streets between the dies. The molding compound is interposed between tie bars of the ground plane members and the insulating material of the redistribution layer in the saw streets, and at the side surfaces of the singulated devices. | 2013-12-05 |
20130320531 | Stacked Integrated Chips and Methods of Fabrication Thereof - Structure and methods of forming stacked semiconductor chips are described. In one embodiment, a method of forming a semiconductor chip includes forming an opening for a through substrate via from a top surface of a first substrate. The sidewalls of the opening are lined with an insulating liner and the opened filled with a conductive fill material. The first substrate is etched from an opposite bottom surface to form a protrusion, the protrusion being covered with the insulating liner. A resist layer is deposited around the protrusion to expose a portion of the insulating liner. The exposed insulating liner is etched to form a sidewall spacer along the protrusion. | 2013-12-05 |
20130320532 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package which includes: a carrier substrate; a semiconductor substrate having an upper surface and a lower surface, disposed overlying the carrier substrate; a device region or sensing region located on the upper surface of the semiconductor substrate; a conducting pad located on the upper surface of the semiconductor substrate; a conducting layer electrically connected to the conducting pad and extending from the upper surface of the semiconductor substrate to a sidewall of the semiconductor substrate; and an insulating layer located between the conducting layer and the semiconductor substrate. | 2013-12-05 |
20130320533 | 3D SYSTEM-LEVEL PACKAGING METHODS AND STRUCTURES - A 3D system-level packaging method includes providing a packaging substrate having a first functional surface and a second surface with wiring arrangement within the packaging substrate and between the first functional surface and the second surface. The method also includes forming at least one flip package layer on the first functional surface of the packaging substrate and forming at least one wiring and package layer on the flip package layer. The flip package layer is formed by subsequently forming a flip mounting layer, an underfill, a sealant layer, and a wiring layer; and the wiring and package layer is formed by subsequently forming a straight mounting layer, a sealant layer, and a wiring layer. Further, the method includes planting connection balls on the second functional surface of the packaging substrate. | 2013-12-05 |
20130320534 | SYSTEM-LEVEL PACKAGING METHODS AND STRUCTURES - A system-level packaging method includes providing a packaging substrate having a first functional surface and a second surface with wiring arrangement within the packaging substrate and between the first functional surface and the second surface. The method also includes forming at least two package layers on the first functional surface of the packaging substrate, wherein each package layer is formed by subsequently forming a mounting layer, a sealant layer, and a wiring layer. Further, the method includes forming a top sealant layer and planting connection balls on the second functional surface of the packaging substrate. | 2013-12-05 |
20130320535 | THREE-DIMENSIONAL SYSTEM-LEVEL PACKAGING METHODS AND STRUCTURES - A 3D system-level packaging method includes providing a packaging substrate, forming a glue layer on the substrate, and attaching a first chip layer at an opposite side of a functional surface of the first chip layer on the packaging substrate through the glue layer. The method also includes forming a first sealant layer on the packaging substrate at a same side attached with the first chip layer and exposing bonding pads of the first chip layer. The method also includes forming first vias in the first sealant layer, forming first vertical metal wiring in the first vias, and forming a first horizontal wiring layer on the sealant layer interconnecting the first chip layer and the first vertical metal wiring. Further, the method includes forming a plurality of package layers on the first sealant layer, and each of the plurality of package layers includes a chip layer, a sealant layer covering the chip layer, and vertical metal wiring and a horizontal wiring layer interconnecting adjacent package layers. | 2013-12-05 |
20130320536 | INTEGRATED CIRCUIT INCLUDING WIRE STRUCTURE, RELATED METHOD AND DESIGN STRUCTURE - An integrated circuit (IC), design structure, and a method of making the same. In one embodiment, the IC includes: a substrate; a dielectric layer disposed on the substrate; a set of wire components disposed on the dielectric layer, the set of wire components including a first wire component disposed proximate a second wire component; a bond pad disposed on the first wire component, the bond pad including an exposed portion; a passivation layer disposed on the dielectric layer about a portion of the bond pad and the set of wire components, the passivation layer defining a wire structure via connected to the second wire component; and a wire structure disposed on the passivation layer proximate the bond pad and connected to the second wire component through the wire structure via. | 2013-12-05 |
20130320537 | THROUGH SILICON VIA (TSV) STRUCTURE AND PROCESS THEREOF - A through silicon via structure is located in a recess of a substrate. The through silicon via structure includes a barrier layer, a buffer layer and a conductive layer. The barrier layer covers a surface of the recess. The buffer layer covers the barrier layer. The conductive layer is located on the buffer layer and fills the recess, wherein the contact surface between the conductive layer and the buffer layer is smoother than the contact surface between the buffer layer and the barrier layer. Moreover, a through silicon via process forming said through silicon via structure is also provided. | 2013-12-05 |
20130320538 | Integrated Circuit Substrates Comprising Through-Substrate Vias And Methods Of Forming Through-Substrate Vias - A method of forming a through-substrate via includes forming a through-substrate via opening at least partially through a substrate from one of opposing sides of the substrate. A first material is deposited to line and narrow the through-substrate via opening. The first material is etched to widen at least an elevationally outermost portion of the narrowed through-substrate via opening on the one side. After the etching, a conductive second material is deposited to fill the widened through-substrate via opening. Additional implementations are disclosed. Integrated circuit substrates are disclosed independent of method of manufacture. | 2013-12-05 |
20130320539 | Method and Apparatus for Back End of Line Semiconductor Device Processing - Methods and apparatus are disclosed for the back end of line process for fabrication of integrated circuits (ICs). The inter-metal dielectric (IMD) layer between two metal layers may comprise an etching stop layer over a metal layer, a low-k dielectric layer over the etching stop layer, a dielectric hard mask layer over the low-k dielectric layer, an nitrogen free anti-reflection layer (NFARL) over the dielectric hard mask layer, and a metal-hard-mask (MHM) layer of a thickness in a range from about 180 Å to about 360 Å over the NFARL. The MHM layer thickness is optimized at the range from about 180 Å to about 360 Å to reduce the Cu pits while avoiding the photo overlay shifting issue. | 2013-12-05 |
20130320540 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a substrate, a conductive material, and a material layer. The substrate includes a through hole. The conductive material fills the through hole. The material layer is formed in the conductive material, wherein an electrical resistance of the conductive material is lower than an electrical resistance of the material layer. | 2013-12-05 |
20130320541 | SEMICONDUCTOR DEVICE CONTACT STRUCTURES - Semiconductor contact structures extend through a dielectric material and provide contact to multiple different subjacent materials including a silicide material and a non-silicide material such as doped silicon. The contact structures includes a lower composite layer formed using a multi-step ionized metal plasma (IMP) deposition operation. A lower IMP film is formed at a high AC bias power followed by the formation of an upper IMP film at a lower AC bias power. The composite layer may be formed of titanium. A further layer is formed as a liner over the composite layer and the liner layer may advantageously be formed using CVD and may be TiN. A conductive plug material such as tungsten or copper fills the contact openings. | 2013-12-05 |
20130320542 | Method of fabricating a self-aligned buried bit line for a vertical channel dram - A method of fabricating a self-aligned buried bit line in a structure which makes up a portion of a vertical channel DRAM. The materials and processes used enable self-alignment of elements of the buried bit line during the fabrication process. In addition, the materials and processes used enable for formation of individual DRAM cells which have a buried bit line width which is 16 nm or less. | 2013-12-05 |
20130320543 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - A semiconductor device is manufactured by forming, on an insulating base material, a first support element having a side face that extends from a surface of the insulating base material, forming a coating of amorphous silicon on the side face of the first support element, filling an aperture disposed between the first support element and a second support element that extends from a surface of the insulating base material with an insulating film, planarizing the insulating film to expose an exposed portion of the coating and a surface of the first support element, and siliciding the amorphous silicon of the coating to form an interconnect. | 2013-12-05 |
20130320544 | CORROSION/ETCHING PROTECTION IN INTEGRATION CIRCUIT FABRICATIONS - A method of producing reduced corrosion interconnect structures and structures thereby formed. A method of producing microelectronic interconnects having reduced corrosion begins with a damascene structure having a first dielectric and a first interconnect. A metal oxide layer is deposited selectively to metal or nonselective over the damascene structure and then thermally treated. The treatment converts the metal oxide over the first dielectric to a metal silicate while the metal oxide over the first interconnect remains as a self-aligned protective layer. When a subsequent dielectric stack is formed and patterned, the protective layer acts as an etch stop, oxidation barrier and ion bombardment protector. The protective layer is then removed from the patterned opening and a second interconnect formed. In a preferred embodiment the metal oxide is a manganese oxide and the metal silicate is a MnSiCOH, the interconnects are substantially copper and the dielectric contains ultra low-k. | 2013-12-05 |
20130320545 | HYBRID COPPER INTERCONNECT STRUCTURE AND METHOD OF FABRICATING SAME - A hybrid interconnect structure containing copper regions that have different impurities levels within a same opening is provided. In one embodiment, the interconnect structure includes a patterned dielectric material having at least one opening located therein. A dual material liner is located at least on sidewalls of the patterned dielectric material within the at least one opening. The structure further includes a first copper region having a first impurity level located within a bottom region of the at least one opening and a second copper region having a second impurity level located within a top region of the at least one opening and atop the first copper region. In accordance with the present disclosure, the first impurity level of the first copper region is different from the second impurity level of the second copper region. | 2013-12-05 |
20130320546 | DUAL-METAL SELF-ALIGNED WIRES AND VIAS - Disclosed is a semiconductor structure which includes a semiconductor substrate and a wiring layer on the semiconductor substrate. The wiring layer includes a plurality of fin-like structures comprising a first metal; a first layer of a second metal on each of the plurality of fin-like structures wherein the first metal is different from the second metal, the first layer of the second metal having a height less than each of the plurality of fin-like structures; and an interlayer dielectric (ILD) covering the plurality of fin-like structures and the first layer of the second metal except for exposed edges of the plurality of fin-like structures at predetermined locations, and at locations other than the predetermined locations, the height of the plurality of fin-like structures has been reduced so as to be covered by the ILD. | 2013-12-05 |
20130320547 | ENABLING PACKAGE-ON-PACKAGE (POP) PAD SURFACE FINISHES ON BUMPLESS BUILD-UP LAYER (BBUL) PACKAGE - A bumpless build-up layer (BBUL) integrated circuit package and method of manufacturing are presented. In some embodiments, the package-on-package (PoP) pads of the BBUL integrated circuit package has a surface finish that can be palladium, nickel-palladium, nickel-gold, nickel-palladium-gold, or palladium-nickel-palladium-gold. In some embodiments, the PoP pad surface finish can be formed using either an electroless or electrolytic process. | 2013-12-05 |
20130320548 | INTEGRATED CIRCUIT DIE ASSEMBLY WITH HEAT SPREADER - A packaged semiconductor device comprises a package substrate comprising a first package substrate contact and a second package substrate contact, and a semiconductor die over the package substrate. The semiconductor device further includes electrical connections between signal contact pads of the die and the package substrate, and a heat spreader that comprises a first heat spreader portion which is electrically connected to a first signal contact pad and the first package substrate contact and provides an electrical conduction path and a thermal conduction path. A second heat spreader portion provides an electrical conduction path between a second signal contact pad and the second package substrate contact and a thermal conduction path between the die and package substrate. An insulating layer is positioned between the first and second heat spreader portions. | 2013-12-05 |
20130320549 | SEMICONDUCTOR DEVICE WITH AIR GAP AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming, over a substrate, a plurality of first conductive structures which are separated from one another; forming multi-layered dielectric patterns including a first dielectric layer which covers upper ends and both sidewalls of the first conductive structures; removing portions of the first dielectric layer starting from lower end portions of the first conductive structures to define air gaps, and forming second conductive structures which are filled between the first conductive structures. | 2013-12-05 |
20130320550 | SEMICONDUCTOR DEVICE WITH AIR GAP AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming a plurality of bit line structures over a substrate, forming multiple layers of spacer layers with a capping layer interposed therebetween over the bit line structures, exposing a surface of the substrate by selectively etching the spacer layers, forming air gaps and capping spacers for covering upper portions of the air gaps by selectively etching the capping layer, and forming storage node contact plugs between the bit line structures. | 2013-12-05 |
20130320551 | DISCRETE SEMICONDUCTOR DEVICE PACKAGE AND MANUFACTURING METHOD - Disclosed is a discrete semiconductor device package ( | 2013-12-05 |
20130320552 | INTEGRATED CIRCUIT FABRICATION - A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width. | 2013-12-05 |
20130320553 | NOVEL BEAD FOR 2.5D/3D CHIP PACKAGING APPLICATION - An integrated circuit package having a multilayer interposer has one or more metal wiring beads provided in the interposer, each of the one or more metal wiring beads has a convoluted wiring pattern that is formed in one of the multiple layers of wiring structures in the interposer, and two terminal end segments connected to the power lines in the integrated circuit package, wherein the one or more metal wiring beads operate as power noise filters. | 2013-12-05 |
20130320554 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF - A semiconductor device includes a substrate having a top surface. A semiconductor circuit defines a circuit area on the top surface of the substrate. An interconnect is spaced apart from the circuit area and extends from the top surface into the substrate. The interconnect includes a sidewall formed of an electrically insulating material. An opening is provided in the sidewall. | 2013-12-05 |
20130320555 | EDA TOOL AND METHOD, AND INTEGRATED CIRCUIT FORMED BY THE METHOD - A method comprises: accessing data representing a layout of a layer of an integrated circuit (IC) comprising a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks for multi-patterning a single layer of a semiconductor substrate, where N is greater than one. For each set of N parallel polygons in the layout closer to each other than a minimum separation for patterning with a single photomask, at least N−1 stitches are inserted in each polygon within that set to divide each polygon into at least N parts, such that adjacent parts of different polygons are assigned to different photomasks from each other. Data representing assignment of each of the parts in each set to respective photomasks are stored in a non-transitory, computer readable storage medium that is accessible for use in a process to fabricate the N photomasks. | 2013-12-05 |
20130320556 | Three Dimensional Integrated Circuit Structures and Hybrid Bonding Methods for Semiconductor Wafers - Three dimensional integrated circuit (3DIC) structures and hybrid bonding methods for semiconductor wafers are disclosed. A 3DIC structure includes a first semiconductor device having first conductive pads disposed within a first insulating material on a top surface thereof, the first conductive pads having a first recess on a top surface thereof. The 3DIC structure includes a second semiconductor device having second conductive pads disposed within a second insulating material on a top surface thereof coupled to the first semiconductor device, the second conductive pads having a second recess on a top surface thereof. A sealing layer is disposed between the first conductive pads and the second conductive pads in the first recess and the second recess. The sealing layer bonds the first conductive pads to the second conductive pads. The first insulating material is bonded to the second insulating material. | 2013-12-05 |
20130320557 | SEMICONDUCTOR PACKAGE HAVING RELIABLE ELECTRICAL CONNECTION AND ASSEMBLING METHOD - A semiconductor package includes a printed circuit board, a chip, a protection frame, and a covering layer. The chip is mounted on the printed circuit board and is electrically connected to the printed circuit board through a number of first bonding wires. The protection frame includes a sidewall surrounding the chip and the bonding wires and defines a number of through holes passing through an inner surface and an outer surface of the sidewall. The protection frame is filled with adhesive. The adhesive adheres to the inner surface and covers the chip and the boding wires. The covering layer is coated on the outer surface and covers the through holes. | 2013-12-05 |
20130320558 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for forming a semiconductor device includes forming a sealing insulation film over a semiconductor substrate including a device isolation film and an active region, forming a bit line contact plug that protrudes from an upper part of the sealing insulation film and is coupled to the active region, forming a spacer over a sidewall of the protruded bit line contact plug, and forming a bit line coupled to an upper part of the bit line contact plug. | 2013-12-05 |
20130320559 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package including: a first semiconductor substrate; a second semiconductor substrate disposed on the first semiconductor substrate, wherein the second semiconductor substrate includes a lower semiconductor layer, an upper semiconductor layer, and an insulating layer located between the lower semiconductor layer and the upper semiconductor layer, and a portion of the lower semiconductor layer electrically contacts with at least a pad on the first semiconductor substrate; a signal conducting structure disposed on a lower surface of the first semiconductor substrate, wherein the signal conducting structure is electrically connected to a signal pad on the first semiconductor substrate; and a conducting layer disposed on the upper semiconductor layer of the second semiconductor substrate and electrically contacted with the portion of the lower semiconductor layer electrically contacting with the at least one pad on the first semiconductor substrate. | 2013-12-05 |
20130320560 | DISTRIBUTED ON-CHIP DECOUPLING APPARATUS AND METHOD USING PACKAGE INTERCONNECT - An integrated circuit device is disclosed. The integrated circuit device includes a semiconductor die fabricated by a front-end semiconductor process and having oppositely disposed planar surfaces. The semiconductor die is formed with semiconductor devices, power supply circuitry coupled to the semiconductor devices, decoupling capacitance circuitry, and through-vias. The through-vias include a first group of vias coupled to the power supply circuitry and a second group of vias coupled to the decoupling capacitance circuitry. Conductors are formed in a first metal layer disposed on the semiconductor die in accordance with a back-end semiconductor process. The conductors are configured to couple to the first and second groups of through-vias to establish conductive paths from the power supply circuitry to the decoupling capacitance circuitry. | 2013-12-05 |
20130320561 | PLUG VIA STACKED STRUCTURE, STACKED SUBSTRATE HAVING VIA STACKED STRUCTURE AND MANUFACTURING METHOD THEREOF - Disclosed herein is a plug via stacked structure including: a through hole plating layer plated on a through hole inner wall and around top and bottom of a through hole at thickness t; a via plug filled in an inner space of the through hole plating layer; a circuit pattern formed over the top and bottom of the through hole plating layer and the via plug and making a thickness t′ formed on the through hole plating layer thicker than a thickness t; and a stacked conductive via filled in a via hole formed on the top of the through hole and formed at thickness α from a top of the circuit pattern, wherein T≦t″+α is satisfied, T represents a sum of the thicknesses t and t′ and t″ is a thickness of a portion of the circuit pattern formed on the via plug. | 2013-12-05 |
20130320562 | SEMICONDUCTOR DEVICE - The present invention aims to relax stress induced by through-silicon via formed on semiconductor substrate in order to prevent property fluctuation of a transistor. A semiconductor device includes a semiconductor substrate, a through-silicon via formed in semiconductor substrate, an insulating film formed between the semiconductor substrate and the through-silicon via, and a transistor formed on the semiconductor substrate so as to be apart from the through-silicon via with a predetermined distance. The insulating film does not exist on a region close to a surface of the semiconductor substrate between the semiconductor substrate and the through-silicon via. A gap is formed to be surrounded by the semiconductor substrate, the through silicon via, and the insulating film under the region close to the surface of the semiconductor substrate. | 2013-12-05 |
20130320563 | Three dimensional memory structure - A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 microns in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques. | 2013-12-05 |
20130320564 | AVD HARDMASK FOR DAMASCENE PATTERNING - A method including forming a dielectric layer on a contact point of an integrated circuit structure; forming a hardmask including a dielectric material on a surface of the dielectric layer; and forming at least one via in the dielectric layer to the contact point using the hardmask as a pattern. An apparatus including a circuit substrate including at least one active layer including a contact point; a dielectric layer on the at least one active layer; a hardmask including a dielectric material having a least one opening therein for an interconnect material; and an interconnect material in the at least one opening of the hardmask and through the dielectric layer to the contact point. | 2013-12-05 |
20130320565 | Interposer Die for Semiconductor Packaging - According to one exemplary implementation, a method includes lithographically forming a plurality of reticle images on a semiconductor wafer. The method further includes singulating the semiconductor wafer into an interposer die such that the interposer die includes at least a portion of a first reticle image and at least a portion of a second reticle image from the plurality of reticle images. The first reticle image and the second reticle image can be produced from a single reticle. The method can further include electrically connecting a first active die to a second active die through the interposer die. The method can also include electrically connecting the first active die to a package substrate through the interposer die. | 2013-12-05 |
20130320566 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SUBSTRATE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; mounting a stack substrate over the base substrate with an inter-substrate connector directly on the stack substrate and the base substrate, the inter-substrate connector having an inter-substrate connector pitch; mounting an integrated circuit over the stack substrate, the integrated circuit having an internal connector directly on the stack substrate; and attaching an external connector directly on the base substrate, the external connector having an external connector pitch greater than the inter-substrate connector pitch. | 2013-12-05 |
20130320567 | BATCH PROCESS FOR THREE-DIMENSIONAL INTEGRATION - A chip package is described which includes a first chip having a first surface and first sides having a first side-wall angle, and a second chip having a second surface and second sides having a second side-wall angle, which faces and is mechanically coupled to the first chip. The chip package is fabricated using a batch process, and the chips in the chip package were singulated from their respective wafers after the chip package is assembled. This is accomplished by etching the first and second side-wall angles and thinning the wafer thicknesses prior to assembling the chip package. For example, the first and/or the second side walls can be fabricated using wet etching or dry etching. Therefore, the first and/or the second side-wall angles may be other than vertical or approximately vertical. | 2013-12-05 |
20130320568 | SEMICONDUCTOR PACKAGE AND STACKED SEMICONDUCTOR PACKAGE - A semiconductor package includes a printed wiring board and a semiconductor chip that has a first signal terminal and a second signal terminal and is mounted on the printed wiring board. The printed wiring board has a first land and a second land for solder joining, which are formed on a surface layer thereof. Further, the printed wiring board has a first wiring for electrically connecting the first signal terminal of the semiconductor chip and the first land, and a second wiring for electrically connecting the second signal terminal of the semiconductor chip and the second land. The second wiring is formed so that the wiring length thereof is larger than that of the first wiring. The second land is formed so that the surface area thereof is larger than that of the first land. This reduces difference in transmission line characteristics due to the difference in wiring length. | 2013-12-05 |
20130320569 | STACKED SEMICONDUCTOR DEVICE - A first semiconductor package which is located on an upper side includes a first printed wiring board and an encapsulation resin for encapsulating a first semiconductor chip. A second semiconductor package which is located on a lower side includes a second printed wiring board. The first printed wiring board includes first lands and a first solder resist having first openings for exposing the first lands. The second printed wiring board includes second lands opposed to the first lands, respectively, and a second solder resist having second openings for exposing the second lands and opposed to the first openings, respectively. The first lands and the second lands are solder joined to each other through the first openings and the second openings, respectively. The opening area of the first opening is set to be smaller than the opening area of the second opening. This improves joint reliability. | 2013-12-05 |
20130320570 | ELECTRONIC DEVICE FOR POWER APPLICATIONS - An electronic device for power applications and configured for being mounted on a printed circuit board is disclosed. The electronic device includes a semiconductor chip integrating a power component, and a package. The package comprises an insulating body embedding the semiconductor chip, and exposed electrodes for electrically connecting conductive terminals of the semiconductor chip to external circuitry in the printed circuit board. The electronic device is further configured to be fastened to a heatsink with a back surface of the insulating body in contact with a main surface of the heatsink for removing heat produced by the electronic device during the operation thereof. The insulating body lacks of a fixing portion in which a hole for receiving an insertable fastener element for the fastening of the electronic device to the heatsink is located. | 2013-12-05 |
20130320571 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Of three chips ( | 2013-12-05 |